FEATURES
SN54ABT16244. . . WD PACKAGE
SN74ABT16244A. . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1
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24
48
47
46
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44
43
42
41
40
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38
37
36
35
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33
32
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29
28
27
26
25
1OE
1Y1
1Y2
GND
1Y3
1Y4
V
CC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
V
CC
4Y1
4Y2
GND
4Y3
4Y4
4OE
2OE
1A1
1A2
GND
1A3
1A4
V
CC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
V
CC
4A1
4A2
GND
4A3
4A4
3OE
• Members of the Texas Instruments
Widebus™ Family
• State-of-the-Art EPIC-IIB™ BiCMOS Design
Significantly Reduces Power Dissipation
• Latch-Up Performance Exceeds 500 mA Per
JESD 70
• Typical V
at V
CC
• Distributed V
Minimizes High-Speed Switching Noise
• Flow-Through Architecture Optimizes PCB
Layout
• High-Drive Outputs (–32-mA IOH, 64-mA IOL)
• Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
(Output Ground Bounce) <1 V
OLP
= 5 V, T
= 25 ° C
A
and GND Pin Configuration
CC
SN54ABT16244, SN74ABT16244A
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS073H – SEPTEMBER 1991 – REVISED AUGUST 2005
DESCRIPTION
The SN54ABT16244 and SN74ABT16244A are 16-bit
buffers and line drivers designed specifically to
improve both the performance and density of 3-state
memory address drivers, clock drivers, and
bus-oriented receivers and transmitters. These
devices can be used as four 4-bit buffers, two 8-bit
buffers, or one 16-bit buffer. These devices provide
true outputs and symmetrical OE (active-low
output-enable) inputs.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16244 is characterized for operation over the full military temperature range of –55 ° C to 125 ° C.
The SN74ABT16244A is characterized for operation from –40 ° C to 85 ° C.
Widebus, EPIC-IIB are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FUNCTION TABLE
(EACH BUFFER)
INPUTS
OE A
L H H
L L L
H X Z
through a pullup
CC
OUTPUT
Y
Copyright © 1991–2005, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are
tested unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
47
1A1
46
1A2
44
1A3
43
1A4
1Y1
2
1Y2
3
1Y3
5
1Y4
6
41
2A1
40
2A2
38
2A3
37
2A4
2Y1
8
2Y2
9
2Y3
11
2Y4
12
36
3A1
35
3A2
33
3A3
32
3A4
3Y1
13
3Y2
14
3Y3
16
3Y4
17
30
4A1
29
4A2
27
4A3
26
4A4
4Y1
19
4Y2
20
4Y3
22
4Y4
23
EN1
1
EN4
24
1OE
2OE
3OE
4OE
EN2
48
EN3
25
(1) This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
1
1
1
1
1
2
3
4
SN54ABT16244, SN74ABT16244A
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS073H – SEPTEMBER 1991 – REVISED AUGUST 2005
LOGIC SYMBOL
(1)
2
1OE
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
1
47
46
44
43
2
3
5
6
2OE
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
48
41
40
38
37
8
9
11
12
3OE
3A1
3A2
3A3
3A4
3Y1
3Y2
3Y3
3Y4
25
36
35
33
32
13
14
16
17
4OE
4A1
4A2
4A3
4A4
4Y1
4Y2
4Y3
4Y4
24
30
29
27
26
19
20
22
23
LOGIC DIAGRAM (POSITIVE LOGIC)
SN54ABT16244, SN74ABT16244A
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS073H – SEPTEMBER 1991 – REVISED AUGUST 2005
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
V
V
V
I
I
I
θ
T
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD 51.
Supply voltage range –0.5 7 V
CC
Input voltage range
I
Voltage range applied to any output in the high or power-off state –0.5 5.5 V
O
Current into any output in the low state mA
O
Input clamp current VI< 0 –18 mA
IK
Output clamp current VO< 0 –50 mA
OK
Package thermal impedance
JA
Storage temperature range –65 150 ° C
stg
(2)
SN54ABT16244 96
(3)
SN74ABT16244A 128
DGG package 89
DGV package 93 ° C/W
DL package 94
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability
MIN MAX UNIT
–0.5 7 V
3
SN54ABT16244, SN74ABT16244A
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS073H – SEPTEMBER 1991 – REVISED AUGUST 2005
Recommended Operating Conditions
V
V
V
V
I
OH
I
OL
∆ t/ ∆ v Input transition rise or fall rate Outputs enabled 10 10 ns/V
T
(1) All unused inputs of the device must be held at V
Supply voltage 4.5 5.5 4.5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 V
I
High-level output current –24 –32 mA
Low-level output current 48 64 mA
Operating free-air temperature –55 125 –40 85 ° C
A
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS UNIT
V
IK
V
OH
V
OL
V
hys
I
I
I
OZH
I
OZL
I
off
I
CEX
(5)
I
O
I
CC
Data One input at 3.4 V,
inputs Other inputs at
(6)
∆ I
CC
Control V
inputs Other inputs at V
C
i
C
o
(1) Characteristics for TA= 25 ° C apply to the SN74ABT16244A only.
(2) All typical values are at V
(3) On products compliant to MIL-PRF-38535, this parameter does not apply.
(4) This data-sheet limit may vary among suppliers.
(5) Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
(6) This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
V
= 4.5 V, II= –18 mA –1.2 –1.2 –1.2 V
CC
V
= 4.5 V, IOH= –3 mA 2.5 2.5 2.5
CC
V
= 5 V, IOH= –3 mA 3 3 3
CC
V
= 4.5 V
CC
V
= 4.5 V V
CC
V
= 5.5 V, VI= V
CC
V
= 5.5 V, VO= 2.7 V 10
CC
V
= 5.5 V, VO= 0.5 V –10
CC
V
= 0, VIor VO≤ 5.5 V ± 100 ± 100 µ A
CC
V
= 5.5 V,
CC
VO= 5.5 V
V
= 5.5 V, VO= 2.5 V –50 –100 –180 –50 –180 –50 –180 mA
CC
V
= 5.5 V,
CC
IO= 0, Outputs low 32 32 32 mA
VI= V
V
V
or GND
CC
= 5.5 V, Outputs enabled 0.05 1.5 0.05
CC
or GND
CC
= 5.5 V, One input at 3.4 V,
CC
IOH= –24 mA 2 2
IOH= –32 mA 2
IOL= 48 mA 0.55 0.55
IOL= 64 mA 0.55
or GND ± 1 ± 1 ± 1 µ A
CC
Outputs high 50 50 50 µ A
Outputs high 3 2 3
Outputs disabled 3 2 3
Outputs disabled 0.05 1 0.05
or GND
CC
VI= 2.5 V or 0.5 V 3 pF
VO= 2.5 V or 0.5 V 6 pF
= 5 V.
CC
(1)
SN54ABT16244 SN74ABT16244A
MIN MAX MIN MAX
CC
or GND to ensure proper device operation. Refer to the TI application report,
CC
TA= 25 ° C
MIN TYP
(3)
(1)
(2)
SN54ABT16244 SN74ABT16244A
MAX MIN MAX MIN MAX
(3)
100 mV
(4)
(4)
10 10
–10 –10
0.05 1.5 0.05
CC
0 V
2
0.55
or GND.
UNIT
V
CC
V
(4)
µ A
(4)
µ A
mA
4