TEXAS INSTRUMENTS SN54165 Technical data

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The SN54165 and SN74165 devices are obsolete and are no longer supplied

SN54165, SN54LS165A, SN74165, SN74LS165A

PARALLEL-LOAD 8-BIT SHIFT REGISTERS

SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002

Complementary Outputs

Direct Overriding Load (Data) Inputs

Gated Clock Inputs

Parallel-to-Serial Data Conversion

TYPE

’165 26 MHz 210 mW ’LS165A 35 MHz 90 mW

TYPICAL MAXIMUM

CLOCK FREQUENCY

TYPICAL

POWER DISSIPATION

description

The ’165 and ’LS165A are 8-bit serial shift registers that shift the data in the direction of Q toward QH when clocked. Parallel-in access to each stage is made available by eight individual, direct data inputs that are enabled by a low level at the shift/load (SH/LD also feature gated clock (CLK) inputs and complementary outputs from the eighth bit. All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design.

Clocking is accomplished through a two-input positive-NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with SH/LD other clock input. Clock inhibit (CLK INH) should be changed to the high level only while CLK is high. Parallel loading is inhibited as long as SH/LD is high. Data at the parallel inputs are loaded directly into the register while SH/LD independently of the levels of CLK, CLK INH, or serial (SER) inputs.

) input. These registers

high enables the

is low,

SN54165, SN54LS165A ...J OR W PACKAGE

SN74165 ...N PACKAGE

SN74LS165A . . . D, N, OR NS PACKAGE

SH/LD

CLK

GND

(TOP VIEW)

1 2

6 7

16 15 14 13 12 11 10

CLK INH D C B A SER Q

SN54LS165A . . . FK PACKAGE

E F

G H

NC – No internal connection

(TOP VIEW)

SH/LD

GND

CLK

3212019

4 5 6 7 8

910111213

CLK INH

18 17 16 15 14

SER

D C NC B A

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

SN54165, SN54LS165A, SN74165, SN74LS165A

0°C to 70°C

SOIC

LS165A

CDIP

55°C to 125°C

PARALLEL-LOAD 8-BIT SHIFT REGISTERS

SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002

ORDERING INFORMATION

–

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

SH/LD

CLK INH CLK SER

L X X X a...h a b h H LLX XQ H L ↑ HXH Q H L ↑ LXL Q H H X X X Q

PACKAGE

PDIP – N Tube SN74LS165AN SN74LS165AN

–

SOP – NS Tape and reel SN74LS165ANSR 74LS165A

–

CFP – W Tube SNJ54LS165AW SNJ54LS165AW LCCC – FK Tube SNJ54LS165AFK SNJ54LS165AFK

INPUTS

†

Tube SN74LS165AD Tape and reel SN74LS165ADR

Tube SN54LS165AJ SN54LS165AJ Tube SNJ54LS165AJ SNJ54LS165AJ

FUNCTION TABLE

PARALLEL

ORDERABLE

PART NUMBER

A...H

The SN54165 and SN74165 devices are obsolete and are no longer supplied

TOP-SIDE MARKING

INTERNAL

OUTPUTS

OUTPUT

B0 An An B0

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

The SN54165 and SN74165 devices are obsolete and are no longer supplied

schematics of inputs and outputs

SN54165, SN54LS165A, SN74165, SN74LS165A

PARALLEL-LOAD 8-BIT SHIFT REGISTERS

SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002

’165

EQUIVALENT OF EACH INPUT

Input

Other Inputs: Req = 6 kΩ NOM

EQUIVALENT OF PARALLEL

INPUTS AND SERIAL INPUT

24 kΩ NOM

SH/LD: Req = 3 kΩ NOM

EQUIVALENT OF ALL

OTHER INPUTS

’LS165A

TYPICAL OF BOTH OUTPUTS

100 Ω NOM

Output

TYPICAL OF BOTH OUTPUTS

120 Ω NOM

Input

CLK, CLK INH: Req = 10 kΩ NOM

SH/LD

: Req = 13 kΩ NOM

Output

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54165, SN54LS165A, SN74165, SN74LS165A

PARALLEL-LOAD 8-BIT SHIFT REGISTERS

SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002

logic diagram (positive logic)

The SN54165 and SN74165 devices are obsolete and are no longer supplied

ABCDEF

SH/LD

CLK

SER

CLK INH

Pin numbers shown are for D, J, N, NS, and W packages.

11 12 13 14 3 4 5 6

S 1D

1D R

typical shift, load, and inhibit sequences

CLK

CLK INH

SER

1D R

S 1D

Data

Inputs

Output Q

SH/LD

Load

Serial ShiftInhibit

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT

The SN54165 and SN74165 devices are obsolete and are no longer supplied

SN54165, SN54LS165A, SN74165, SN74LS165A

PARALLEL-LOAD 8-BIT SHIFT REGISTERS

SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage, V Input voltage, V

(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

: SN54165, SN74165 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

SN54LS165A, SN74LS165A 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interemitter voltage (see Note 2) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance θ

(see Note 3): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Voltage values, except interemitter voltage, are with respect to network ground terminal.

2. This is the voltage between two emitters of a multiple-emitter transistor. This rating applies for the ’165 to the SH/LD conjunction with the CLK INH input.

3. The package thermal impedance is calculated in accordance with JESD 51-7.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

input in

recommended operating conditions

SN54165 SN74165

MIN NOM MAX MIN NOM MAX

clock

w(clock)

w(load)

Supply voltage 4.5 5 5.5 4.75 5 5.25 V High-level output current –800 –800 Low-level output current 16 16 mA Clock frequency 0 20 0 20 MHz Width of clock input pulse 25 25 ns Width of load input pulse 15 15 ns Clock-enable setup time (see Figure 1) 30 30 ns Parallel input setup time (see Figure 1) 10 10 ns Serial input setup time (see Figure 1) 20 20 ns Shift setup time (see Figure 1) 45 45 ns Hold time at any input 0 0 ns Operating free-air temperature –55 125 0 70 °C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54165, SN54LS165A, SN74165, SN74LS165A

PARAMETER

TEST CONDITIONS

†

UNIT

IIHHigh-level input current

MAX

2.4 V

IILLow-level input current

MAX

0.4 V

Any

15 pF, R

400 W

CLK

Any

15 pF, R

400 W

15 pF, R

400 W

15 pF, R

400 W

PARALLEL-LOAD 8-BIT SHIFT REGISTERS

SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

High-level input voltage 2 2 V

Low-level input voltage 0.8 0.8 V

Input clamp voltage VCC = MIN, II = –12 mA –1.5 –1.5 V

High-level output voltage

Low-level output voltage

Input current at maximum input voltage VCC = MAX, VI = 5.5 V 1 1 mA

Short-circuit output current

Supply current VCC = MAX, See Note 4 42 63 42 63 mA

NOTE 4: With the outputs open, CLK INH and CLK at 4.5 V, and a clock pulse applied to SH/LD, ICC is measured first with the parallel inputs

†

For conditions shown as MIN or MAX, use the appropriate values specified under recommended operating conditions.

‡

All typical values are at VCC = 5 V, TA = 25°C.

Not more than one output should be shorted at a time.

at 4.5 V, then with the parallel inputs grounded.

SH/LD Other inputs SH/LD Other inputs

VCC = MIN, VIL = 0.8 V,

VCC = MAX –20 –55 –18 –55 mA

VIH = 2 V, IOH = –800 mA

VIH = 2 V, IOL = 16 mA

The SN54165 and SN74165 devices are obsolete and are no longer supplied

SN54165 SN74165

MIN TYP‡MAX MIN TYP‡MAX

2.4 3.4 2.4 3.4 V

0.2 0.4 0.2 0.4 V

80 80 40 40

–3.2 –3.2 –1.6 –1.6

SN54165 and SN74165 switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)

PARAMETER

f t t t t t t

t t

= maximum clock frequency, t

max

max PLH PHL PLH PHL PLH PHL

PLH PHL

FROM

(INPUT)

= propagation delay time, low-to-high-level output, t

PLH

(OUTPUT)

TEST CONDITIONS MIN TYP MAX

20 26 MHz

= propagation delay time, high-to-low-level output

PHL

21 31 27 40 16 24 21 31 11 17 24 36

18 27 18 27

UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT

Width of clock input pulse (see Figure 2)

Width of load input pulse

PARAMETER

TEST CONDITIONS

†

UNIT

MIN

2 V

MAX

The SN54165 and SN74165 devices are obsolete and are no longer supplied

recommended operating conditions

clock

w(clock)

w(load)

Supply voltage 4.5 5 5.5 4.75 5 5.25 V High-level input voltage 2 2 V Low-level input voltage 0.7 0.8 V High-level output current –0.4 –0.4 mA Low-level output current 4 8 mA Clock frequency 0 25 0 25 MHz

Clock-enable setup time (see Figure 2) 30 30 ns Parallel input setup time (see Figure 2) 10 10 ns Serial input setup time (see Figure 2) 20 20 ns Shift setup time (see Figure 2) 45 45 ns Hold time at any input 0 0 ns Operating free-air temperature –55 125 0 70 °C

SN54165, SN54LS165A, SN74165, SN74LS165A

PARALLEL-LOAD 8-BIT SHIFT REGISTERS

SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002

SN54LS165A SN74LS165A

MIN NOM MAX MIN NOM MAX

Clock high 15 15 Clock low 25 25 Clock high 25 25 Clock low 17 17

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

SN54LS165A SN74LS165A

MIN TYP‡MAX MIN TYP‡MAX

NOTE 4. With the outputs open, CLK INH and CLK at 4.5 V, and a clock pulse applied to SH/LD, ICC is measured first with the parallel inputs

†

For conditions shown as MIN or MAX, use the appropriate values specified under recommended operating conditions.

‡

All typical values are at VCC = 5 V, TA = 25°C.

Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.

VCC = MIN, II = –18 mA –1.5 –1.5 V VCC = MIN, VIH = 2 V, VIL = MAX, IOH = –0.4 mA 2.5 3.5 2.7 3.5 V

VCC = MAX, VI = 7 V 0.1 0.1 mA VCC = MAX, VI = 2.7 V 20 20 µA VCC = MAX, VI = 0.4 V –0.4 –0.4 mA VCC = MAX –20 –100 –20 –100 mA VCC = MAX, See Note 4 18 30 18 30 mA

at 4.5 V, then with the parallel inputs grounded.

IOL = 4 mA 0.25 0.4 0.25 0.4 IOL = 8 mA 0.35 0.5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54165, SN54LS165A, SN74165, SN74LS165A

Any

2 k

W, C

15 pF

CLK

Any

2 k

W, C

15 pF

2 k

W, C

15 pF

2 k

W, C

15 pF

PARALLEL-LOAD 8-BIT SHIFT REGISTERS

SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002

SN54LS165A and SN74LS165A switching characteristics, VCC = 5 V, TA = 25°C (see Figure 2)

PARAMETER

f t t t t t t

t t

†

= maximum clock frequency, t

max

†

max PLH PHL PLH PHL PLH PHL

PLH PHL

FROM

(INPUT)

= propagation delay time, low-to-high-level output, t

PLH

(OUTPUT)

The SN54165 and SN74165 devices are obsolete and are no longer supplied

TEST CONDITIONS MIN TYP MAX

25 35 MHz

PHL

= propagation delay time, high-to-low-level output

21 35 26 35 14 25 16 25 13 25 24 30

19 30 17 25

UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

The SN54165 and SN74165 devices are obsolete and are no longer supplied

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

(see Note A)

Test

Point

(see Note B)

SN54165, SN54LS165A, SN74165, SN74LS165A

PARALLEL-LOAD 8-BIT SHIFT REGISTERS

SERIES 54/74 DEVICES

From Output

Under Test

(see Note A)

Test Point

SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002

From Output

Under Test

(see Note A)

Test

Point

(see Note B)

1 kΩ

FOR 2-STATE TOTEM-POLE OUTPUTS

High-Level

Low-Level

In-Phase

(see Note D)

Out-of-Phase

(see Note D)

NOTES: A. CL includes probe and jig capacitance.

LOAD CIRCUIT

Pulse

Input

PLH

Output

PHL

Output

PROPAGATION DELAY TIMES

B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for t E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series

54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices. F. The outputs are measured one at a time with one input transition per measurement.

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

1.5 V 1.5 V

VOLTAGE WAVEFORMS

, t

PLH

PHL

PLH

, t

FOR OPEN-COLLECTOR OUTPUTS

PHZ

LOAD CIRCUIT

3 V

0 V

, and t

PLZ

Timing

Input

Data

Input

Output

Control

(low-level

enabling)

PZL

Waveform 1

(see Notes C

and D)

PZH

Waveform 2

(see Notes C

and D)

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

; S1 is open and S2 is closed for t

LOAD CIRCUIT

FOR 3-STATE OUTPUTS

1.5 V

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.5 V 1.5 V

1.5 V

VOLTAGE WAVEFORMS

; S1 is closed and S2 is open for t

PZH

3 V

0 V

3 V

0 V

3 V

0 V

PLZ

≈1.5 V VOL + 0.5 V

PHZ

VOH – 0.5 V ≈1.5 V

PZL

Figure 1. Load Circuits and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54165, SN54LS165A, SN74165, SN74LS165A

PARALLEL-LOAD 8-BIT SHIFT REGISTERS

SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002

PARAMETER MEASUREMENT INFORMATION

SERIES 54LS/74LS DEVICES

From Output

Under Test

(see Note A)

Test

Point

(see Note B)

From Output

Under Test

(see Note A)

The SN54165 and SN74165 devices are obsolete and are no longer supplied

Test Point

From Output

Under Test

(see Note A)

Test

Point

(see Note B)

5 kΩ

FOR 2-STATE TOTEM-POLE OUTPUTS

High-Level

Low-Level

In-Phase

(see Note D)

Out-of-Phase

(see Note D)

NOTES: A. CL includes probe and jig capacitance.

LOAD CIRCUIT

Pulse

Input

PLH

Output

PHL

Output

PROPAGATION DELAY TIMES

B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for t E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.

F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns.

G. The outputs are measured one at a time with one input transition per measurement.

1.3 V 1.3 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

1.3 V 1.3 V

VOLTAGE WAVEFORMS

, t

PLH

PHL

PLH

, t

FOR OPEN-COLLECTOR OUTPUTS

PHZ

LOAD CIRCUIT

3 V

0 V

, and t

PLZ

Timing

Input

Data

Input

Output

Control

(low-level

enabling)

PZL

Waveform 1

(see Notes C

and D)

PZH

Waveform 2

(see Notes C

and D)

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

; S1 is open and S2 is closed for t

FOR 3-STATE OUTPUTS

1.3 V

1.3 V 1.3 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.3 V 1.3 V

1.3 V

VOLTAGE WAVEFORMS

; S1 is closed and S2 is open for t

PZH

LOAD CIRCUIT

3 V

0 V

3 V

0 V

PLZ

PHZ

3 V

0 V

≈1.5 V VOL + 0.5 V

VOH – 0.5 V ≈1.5 V

PZL

Figure 2. Load Circuits and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

26-Sep-2005

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

5962-7700601VEA ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC 5962-7700601VFA ACTIVE CFP W 16 1 TBD Call TI Level-NC-NC-NC

7700601EA ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC

7700601FA ACTIVE CFP W 16 1 TBD Call TI Level-NC-NC-NC JM38510/30608B2A ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC JM38510/30608BEA ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC JM38510/30608BFA ACTIVE CFP W 16 1 TBD Call TI Level-NC-NC-NC

SN54LS165AJ ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC

SN74165N OBSOLETE PDIP N 16 TBD Call TI Call TI

SN74LS165AD ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br)

SN74LS165ADE4 ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br)

SN74LS165ADR ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br)

SN74LS165ADRE4 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br)

SN74LS165AJ OBSOLETE CDIP J 16 TBD Call TI Call TI

SN74LS165AN ACTIVE PDIP N 16 25 Pb-Free

SN74LS165AN3 OBSOLETE PDIP N 16 TBD Call TI Call TI

SN74LS165ANSR ACTIVE SO NS 16 2000 Green (RoHS &

no Sb/Br)

SN74LS165ANSRG4 ACTIVE SO NS 16 2000 Green (RoHS &

no Sb/Br)

SNJ54LS165AFK ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC

SNJ54LS165AJ ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC

SNJ54LS165AW ACTIVE CFP W 16 1 TBD Call TI Level-NC-NC-NC

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-NC-NC-NC

CU NIPDAU Level-1-260C-UNLIM

(3)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

26-Sep-2005

Addendum-Page 2

IMPORTANT NOTICE

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty . Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.

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TEXAS INSTRUMENTS SN54165 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual