TEXAS INSTRUMENTS SN54165 Technical data
.
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The SN54165 and SN74165 devices
are obsolete and are no longer supplied
SN54165, SN54LS165A, SN74165, SN74LS165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002
D
Complementary Outputs
D
Direct Overriding Load (Data) Inputs
D
Gated Clock Inputs
D
Parallel-to-Serial Data Conversion
TYPE
’165 26 MHz 210 mW
’LS165A 35 MHz 90 mW
TYPICAL MAXIMUM
CLOCK FREQUENCY
TYPICAL
POWER DISSIPATION
description
The ’165 and ’LS165A are 8-bit serial shift
registers that shift the data in the direction of Q
toward QH when clocked. Parallel-in access to
each stage is made available by eight individual,
direct data inputs that are enabled by a low level
at the shift/load (SH/LD
also feature gated clock (CLK) inputs and
complementary outputs from the eighth bit. All
inputs are diode-clamped to minimize
transmission-line effects, thereby simplifying
system design.
Clocking is accomplished through a two-input
positive-NOR gate, permitting one input to be
used as a clock-inhibit function. Holding either of
the clock inputs high inhibits clocking, and holding
either clock input low with SH/LD
other clock input. Clock inhibit (CLK INH) should
be changed to the high level only while CLK is
high. Parallel loading is inhibited as long as SH/LD
is high. Data at the parallel inputs are loaded
directly into the register while SH/LD
independently of the levels of CLK, CLK INH, or
serial (SER) inputs.
) input. These registers
high enables the
is low,
SN54165, SN54LS165A ...J OR W PACKAGE
SN74165 ...N PACKAGE
SN74LS165A . . . D, N, OR NS PACKAGE
SH/LD
CLK
Q
GND
(TOP VIEW)
1
2
E
3
F
4
G
5
H
6
7
H
8
16
15
14
13
12
11
10
9
V
CC
CLK INH
D
C
B
A
SER
Q
H
A
SN54LS165A . . . FK PACKAGE
E
F
NC
G
H
NC – No internal connection
(TOP VIEW)
SH/LD
NC
NC
GND
V
Q
CLK
3212019
4
5
6
7
8
910111213
H
Q
CC
CLK INH
18
17
16
15
14
H
SER
D
C
NC
B
A
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
SN54165, SN54LS165A, SN74165, SN74LS165A
0°C to 70°C
SOIC
D
LS165A
CDIP
J
55°C to 125°C
.
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002
ORDERING INFORMATION
T
A
–
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
SH/LD
CLK INH CLK SER
L X X X a...h a b h
H LLX XQ
H L ↑ HXH Q
H L ↑ LXL Q
H H X X X Q
PACKAGE
PDIP – N Tube SN74LS165AN SN74LS165AN
–
SOP – NS Tape and reel SN74LS165ANSR 74LS165A
–
CFP – W Tube SNJ54LS165AW SNJ54LS165AW
LCCC – FK Tube SNJ54LS165AFK SNJ54LS165AFK
INPUTS
†
Tube SN74LS165AD
Tape and reel SN74LS165ADR
Tube SN54LS165AJ SN54LS165AJ
Tube SNJ54LS165AJ SNJ54LS165AJ
FUNCTION TABLE
PARALLEL
ORDERABLE
PART NUMBER
A...H
The SN54165 and SN74165 devices
are obsolete and are no longer supplied
TOP-SIDE
MARKING
INTERNAL
OUTPUTS
Q
A
Q
A0
Q
A0
OUTPUT
Q
Q
B
B0
An
An
B0
H
Q
H0
Q
Gn
Q
Gn
Q
H0
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
.
The SN54165 and SN74165 devices
are obsolete and are no longer supplied
schematics of inputs and outputs
SN54165, SN54LS165A, SN74165, SN74LS165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002
’165
EQUIVALENT OF EACH INPUT
V
CC
Input
Other Inputs: Req = 6 kΩ NOM
EQUIVALENT OF PARALLEL
INPUTS AND SERIAL INPUT
V
CC
24 kΩ NOM
R
eq
SH/LD: Req = 3 kΩ NOM
EQUIVALENT OF ALL
OTHER INPUTS
’LS165A
R
eq
TYPICAL OF BOTH OUTPUTS
V
CC
100 Ω NOM
Output
TYPICAL OF BOTH OUTPUTS
120 Ω NOM
V
CC
Input
Input
CLK, CLK INH: Req = 10 kΩ NOM
SH/LD
: Req = 13 kΩ NOM
Output
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54165, SN54LS165A, SN74165, SN74LS165A
G
.
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002
logic diagram (positive logic)
The SN54165 and SN74165 devices
are obsolete and are no longer supplied
ABCDEF
1
SH/LD
CLK
SER
15
2
10
CLK INH
Pin numbers shown are for D, J, N, NS, and W packages.
11 12 13 14 3 4 5 6
S
1D
R
C1
S
C1
Q
A
1D
R
Q
typical shift, load, and inhibit sequences
CLK
CLK INH
SER
L
H
S
C1
B
1D
R
S
C1
Q
C
1D
R
S
C1
Q
D
1D
R
S
C1
Q
E
1D
R
S
C1
Q
F
1D
R
Q
G
S
1D
R
C1
9
Q
H
7
Q
H
Data
Inputs
Output Q
Output Q
SH/LD
A
B
C
D
E
F
G
H
H
H
Load
H
L
H
L
H
L
H
H
L
H
H
L
L
H
L
H
L
Serial ShiftInhibit
H
L
H
L
H
L
H
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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