TEXAS INSTRUMENTS SN5414 Technical data

PDIP

N

7414

0°C to 70°C

SOIC

D

LS14

CDIP

J

CFP

W

查询5962-9665801Q2A供应商

SN5414, SN54LS14,

SN7414, SN74LS14

HEX SCHMITT-TRIGGER INVERTERS

SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002

D

Operation From Very Slow Edges

D

Improved Line-Receiving Characteristics

D

High Noise Immunity

description

Each circuit functions as an inverter, but because of the Schmitt action, it has different input threshold levels for positive-going (V negative-going (V

These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean, jitter-free output signals.

) signals.

T–

T+

) and

SN5414, SN54LS14 ...J OR W PACKAGE

SN7414 . . . D, N, OR NS PACKAGE

SN74LS14 . . . D, DB, OR N PACKAGE

SN54LS14 . . . FK PACKAGE

2A

NC

2Y

NC

3A

(TOP VIEW)

1A

1

1Y

2

2A

3

2Y

4

3A

5

3Y

6

GND

7

(TOP VIEW)

1Y1ANC

3212019

4 5 6 7 8

910111213

14 13 12 11 10

V

CC

6A 6Y 5A 5Y 4A

9

4Y

8

CC

6A

V

6Y

18

NC

17

5A

16

NC

15

5Y

14

4Y

NC

4A

3Y

GND

NC – No internal connection

ORDERING INFORMA TION

T

A

SOP – NS Tape and reel SN7414NSR SN7414 SSOP – DB Tape and reel SN74LS14DBR LS14

–55°C to 125°C

LCCC – FK Tube SNJ54LS14FK SNJ54LS14FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

PACKAGE

–

†

Tube SN7414N SN7414N Tube SN74LS14N SN74LS14N Tube SN7414D Tape and reel SN7414DR Tube SN74LS14D Tape and reel SN74LS14DR

Tube SN5414J SN5414J Tube SNJ5414J SNJ5414J Tube SN54LS14J SN54LS14J Tube SNJ54LS14J SNJ54LS14J Tube SNJ5414W SNJ5414W Tube SNJ54LS14W SNJ54LS14W

ORDERABLE

PART NUMBER

TOP-SIDE MARKING

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2002, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

1

SN5414, SN54LS14, SN7414, SN74LS14 HEX SCHMITT-TRIGGER INVERTERS

SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002

logic diagram (positive logic)

1

1A

3

2A

5

3A

9

4A

11

5A

13

6A

Y = A

Pin numbers shown are for the D, DB, J, N, NS, and W packages.

10

12

2

1Y

4

2Y

6

3Y

8

4Y

5Y

6Y

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

schematic

SN5414, SN54LS14,

SN7414, SN74LS14

HEX SCHMITT-TRIGGER INVERTERS

SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002

Input A

20 kΩ

Input A

6 kΩ

’14

’LS14

100 Ω

V

CC

Output Y

GND

V

CC

Output Y

Resistor values shown are nominal.

GND

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN5414, SN54LS14,

UNIT

‡

TEST CONDITIONS

SN7414, SN74LS14 HEX SCHMITT-TRIGGER INVERTERS

SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage, V

(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

†

Input voltage: ’14 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

’LS14 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

(see Note 2):D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperaturerange, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Voltage values are with respect to network ground terminal.

2. The package termal impedance is calculated in accordance with JESD 51-7

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions

SN5414 SN7414

MIN NOM MAX MIN NOM MAX

V I I T

OH OL

Supply voltage 4.5 5 5.5 4.75 5 5.25 V

CC

High-level output current –0.8 –0.8 mA Low-level output current 16 16 mA Operating free-air temperature –55 125 0 70 °C

A

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

SN5414

PARAMETER

V

T+

V

T–

Hysteresis (VT+ – VT–)

V

IK

V

OH

V

OL

I

T+

I

T–

I

IH

I

IL

¶

I

OS

I

CCH

I

CCL

‡

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

§

All typical values are at VCC = 5 V, TA = 25°C.

¶

Not more than one output should be shorted at a time.

VCC = 5 V 1.5 1.7 2 V VCC = 5 V 0.6 0.9 1.1 V

VCC = 5 V 0.4 0.8 V VCC = MIN, II = –12 mA –1.5 V

VCC = MIN, VI = 0.6 V, IOH = –0.8 mA 2.4 3.4 V VCC = MIN, VI = 2 V, IOL = 16 mA 0.2 0.4 V VCC = 5 V, VI = V VCC = 5 V, VI = V VCC = MAX, VI = 5.5 V 1 mA VCC = MAX, VIH = 2.4 V 40 µA VCC = MAX, VIL = 0.4 V –0.8 –1.2 mA VCC = MAX –18 –55 mA VCC = MAX 22 36 mA VCC = MAX 39 60 mA

TEST CONDITIONS

T+ T–

SN7414

MIN TYP§MAX

–0.43 mA –0.56 mA

UNIT

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER

(INPUT)

(OUTPUT)

TEST CONDITIONS

UNIT

MIN

TYP

MAX

A

Y

R

L

400 Ω

C

L

F

ns

UNIT

PARAMETER

TEST CONDITIONS

†

UNIT

VOLV

MIN

V

1.9 V

V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

A

Y

R

L

C

L

F

ns

SN5414, SN54LS14,

SN7414, SN74LS14

HEX SCHMITT-TRIGGER INVERTERS

SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002

switching characteristics, VCC = 5 V, T

PARAMETER

t

PLH

t

PHL

FROM

= 25°C (see Figure 1)

A

TO

TEST CONDITIONS

=

SN5414 SN7414

= 15

p

,

15 22 15 22

UNIT

recommended operating conditions

SN54LS14 SN74LS14

MIN NOM MAX MIN NOM MAX

V I I T

OH OL

Supply voltage 4.5 5 5.5 4.75 5 5.25 V

CC

High-level output current –0.4 –0.4 mA Low-level output current 4 8 mA Operating free-air temperature –55 125 0 70 °C

A

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

SN54LS14 SN74LS14

MIN TYP‡MAX MIN TYP‡MAX

V

T+

V

T–

Hysteresis (VT+ – VT–)

V

IK

V

OH

I

T+

I

T–

I

IH

I

IL

§

I

OS

I

CCH

I

CCL

†

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

‡

All typical values are at VCC = 5 V, TA = 25°C.

§

Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.

VCC = 5 V 1.4 1.6 1.9 1.4 1.6 1.9 V VCC = 5 V 0.5 0.8 1 0.5 0.8 1 V

VCC = 5 V 0.4 0.8 0.4 0.8 V VCC = MIN, II = –18 mA –1.5 –1.5 V

VCC = MIN, VI = 0.5 V, IOH = –0.4 mA 2.5 3.4 2.7 3.4 V

,

=

CC

VCC = 5 V, VI = V VCC = 5 V, VI = V VCC = MAX, VI = 7 V 0.1 0.1 mA VCC = MAX, VIH = 2.7 V 20 20 µA VCC = MAX, VIL = 0.4 V –0.4 –0.4 mA VCC = MAX –20 –100 –20 –100 mA VCC = MAX 8.6 16 8.6 16 mA VCC = MAX 12 21 12 21 mA

= –

I

T+ T–

IOL= 4 mA 0.25 0.4 0.25 0.4 IOL = 8 mA 0.35 0.5

–0.14 –0.14 mA –0.18 –0.18 mA

switching characteristics, VCC = 5 V, TA = 25°C (see Figure 2)

FROM TO

(INPUT) (OUTPUT)

t

PLH

t

PHL

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

= 2 kΩ,

= 15

p

15 22 15 22

5

SN5414, SN54LS14, SN7414, SN74LS14 HEX SCHMITT-TRIGGER INVERTERS

SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002

PARAMETER MEASUREMENT INFORMATION

SERIES 54/74 DEVICES

From Output

Under Test

(see Note A)

Test

Point

C

L

V

CC

R

L

(see Note B)

From Output

Under Test

(see Note A)

V

CC

V

CC

R

L

Test Point

C

L

From Output

Under Test

(see Note A)

Test

R

Point

C

L

S1

(see Note B)

1 kΩ

S2

FOR 2-STATE TOTEM-POLE OUTPUTS

High-Level

Low-Level

In-Phase

(see Note D)

Out-of-Phase

(see Note D)

NOTES: A. CL includes probe and jig capacitance.

LOAD CIRCUIT

Pulse

Input

t

PLH

Output

t

PHL

Output

PROPAGATION DELAY TIMES

B. All diodes are 1N3064 or equivalent.

C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

D. S1 and S2 are closed for t

E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series

54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices.

F. The outputs are measured one at a time with one input transition per measurement.

1.5 V 1.5 V

t

w

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

1.5 V 1.5 V

VOLTAGE WAVEFORMS

, t

PLH

PHL

t

PHL

t

PLH

, t

FOR OPEN-COLLECTOR OUTPUTS

PHZ

LOAD CIRCUIT

3 V

0 V

V

OH

V

OL

V

OH

V

OL

, and t

PLZ

Timing

Input

Data

Input

Output

Control

(low-level

enabling)

t

PZL

Waveform 1

(see Notes C

and D)

t

PZH

Waveform 2

(see Notes C

and D)

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

; S1 is open and S2 is closed for t

FOR 3-STATE OUTPUTS

1.5 V

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.5 V 1.5 V

1.5 V

VOLTAGE WAVEFORMS

; S1 is closed and S2 is open for t

PZH

LOAD CIRCUIT

3 V

0 V

t

h

3 V

0 V

t

PLZ

V

t

PHZ

V

3 V

0 V

≈1.5 V VOL + 0.5 V

OL

OH

VOH – 0.5 V ≈1.5 V

PZL

.

Figure 1. Load Circuits and Voltage Waveforms

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

From Output

Under Test

(see Note A)

Test

Point

C

L

HEX SCHMITT-TRIGGER INVERTERS

SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002

PARAMETER MEASUREMENT INFORMATION

SERIES 54LS/74LS DEVICES

V

CC

V

CC

R

L

R

(see Note B)

From Output

Under Test

(see Note A)

C

L

Test Point

V

CC

From Output

Under Test

(see Note A)

SN5414, SN54LS14,

SN7414, SN74LS14

Test

R

Point

C

L

5 kΩ

S1

(see Note B)

S2

FOR 2-STATE TOTEM-POLE OUTPUTS

High-Level

Low-Level

In-Phase

(see Note D)

Out-of-Phase

(see Note D)

NOTES: A. CL includes probe and jig capacitance.

LOAD CIRCUIT

Pulse

Input

t

PLH

Output

t

PHL

Output

PROPAGATION DELAY TIMES

B. All diodes are 1N3064 or equivalent.

C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

D. S1 and S2 are closed for t

E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns.

G. The outputs are measured one at a time with one input transition per measurement.

1.3 V 1.3 V

t

w

1.3 V 1.3 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

1.3 V 1.3 V

VOLTAGE WAVEFORMS

, t

PLH

PHL

t

PHL

t

PLH

, t

FOR OPEN-COLLECTOR OUTPUTS

PHZ

LOAD CIRCUIT

3 V

0 V

V

OH

V

OL

V

OH

V

OL

, and t

PLZ

Timing

Input

Data

Input

Output

Control

(low-level

enabling)

t

PZL

Waveform 1

(see Notes C

and D)

t

PZH

Waveform 2

(see Notes C

and D)

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

; S1 is open and S2 is closed for t

FOR 3-STATE OUTPUTS

1.3 V

t

su

1.3 V 1.3 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.3 V 1.3 V

1.3 V

VOLTAGE WAVEFORMS

; S1 is closed and S2 is open for t

PZH

LOAD CIRCUIT

3 V

0 V

t

h

3 V

0 V

t

PLZ

V

t

PHZ

V

3 V

0 V

≈1.5 V VOL + 0.5 V

OL

OH

VOH – 0.5 V ≈1.5 V

PZL

.

Figure 2. Load Circuits and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7