Texas Instruments SN10KHT5578DW, SN10KHT5578DWR, SN10KHT5578NT Datasheet
SN10KHT5578
OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE
EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE
SDZS014A – APRIL 1990 – REVISED JANUARY 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
10KH Compatible
D
TTL Clock and ECL Control Inputs
D
Noninverting Outputs
D
Flow-Through Architecture Optimizes PCB
Layout
D
Center Pin VCC, VEE, and GND Configurations
Minimize High-Speed Switching Noise
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015
D
Package Options Include Plastic Small-Outline
(DW) Package and Standard Plastic (NT) DIPs
description
This octal TTL-to-ECL translator is designed to
provide efficient translation between a TTL signal
environment and a 10KH ECL signal environment. This device is designed specifically to
improve the performance and density of
TTL-to-ECL CPU/bus-oriented functions such as
memory address drivers, clock drivers, and
bus-oriented receivers and transmitters.
The eight flip-flops of the ’5578 are edge-triggered D-type flip-flops. On the positive transition of the clock, the
Q outputs are set to the logic levels that were set up at the D inputs.
The output-control input OE
does not affect the internal operations of the flip-flops. Old data can be retained
or new data can be entered while the outputs are off.
The SN10KHT5578 is characterized for operation from 0°C to 75°C.
FUNCTION TABLE
INPUTS
OUTPUT
OE CLK D
(ECL)
Q
L ↑ L L
L ↑ H H
L L X Q
0
H X X L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
1Q
2Q
3Q
4Q
GND
GND
GND
GND
5Q
6Q
7Q
8Q
1D
2D
3D
4D
OE
(ECL)
V
CC
V
EE
CLK(TTL)
5D
6D
7D
8D
DW OR NT PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1999, Texas Instruments Incorporated
SN10KHT5578
OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE
EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE
SDZS014A – APRIL 1990 – REVISED JANUARY 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
1D
CLK
2D
3D
4D
5D
6D
7D
8D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
17
20
24
23
22
21
16
15
14
13 12
11
10
9
4
3
2
1
1D
C1
TTL/ECL
TTL/ECL
EN
OE
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1D
CLK
2D
3D
4D
5D
6D
7D
8D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
20
17
24
23
22
21
16
15
14
13
12
11
10
9
4
3
2
1
OE
TTL/ECL
TTL/ECL
TTL/ECL
TTL/ECL
TTL/ECL
TTL/ECL
TTL/ECL
TTL/ECL
TTL/ECL
C1
1D
C1
1D
1D
1D
1D
1D
1D
C1
C1
C1
C1
C1
C1
1D
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