Texas Instruments SMJ4C1024-10FQ, SMJ4C1024-10HJ, SMJ4C1024-10HK, SMJ4C1024-10HL, SMJ4C1024-10JD Datasheet

’4C1024-80 80 ns 20 ns 40 ns 150 ns ’4C1024-10 100 ns 25 ns 45 ns 190 ns ’4C1024-12 120 ns 30 ns 55 ns 220 ns ’4C1024-15 150 ns 40 ns 70 ns 260 ns

Enhanced Page-Mode Operation for Faster

a(C)ta(CA)

)(t

CAC

) (tAA) CYCLE

Memory Access – Higher Data Bandwidth Than

Conventional Page Mode Parts

– Random Single-Bit Access Within a Row

With a Column Address

One of TI’s CMOS Megabit Dynamic Random-Access Memory (DRAM) Family Including SMJ44C256 — 256K × 4 Enhanced Page Mode

CAS-Before-RAS (CBR) Refresh

Long Refresh Period

512-Cycle Refresh in 8 ms (Max)

3-State Unlatched Output

Low Power Dissipation

All Inputs/Outputs and Clocks Are TTL-Compatible

Packaging Offered: – 20/26-Pin J-Leaded Ceramic Surface

Mount Package (HJ Suffix)

– 18-Pin 300-Mil Ceramic Dual-In-Line

Package (JD Suffix) – 20-Pin Ceramic Flatpack (HK Suffix) – 20/26-Terminal Leadless Ceramic

Surface Mount Package (FQ/HL Suffixes) – 20-Pin Ceramic Zig-Zag In-Line Package

(SV Suffix)

Operating Temperature Range

– 55°C to 125°C

WRITE

HJ PACKAGE

(TOP VIEW)

1 2

RAS

A0 A1 A2 A3

3 4 5

6 7 8 9 10

RAS

A0 A1 A2 A3

FQ/HL PACKAGES

(TOP VIEW)

RAS

A0 A1 A2 A3

20 19

Q CAS

17 16

HK PACKAGE

(TOP VIEW)

1 2 3 4 5 6 7 8 9 10

Q CAS NC A9

A8 A7 A6 A5 A4

RAS

20 19 18 17 16 15 14 13 12 11

TF A0 A1 A2 A3

RAS

A0 A2

A5 A7

JD PACKAGE

(TOP VIEW)

SV PACKAGE

(SIDE VIEW)

1 3 5 7 9 11 13 15 17 19

2 4 6

8 10 12 14 16 18 20

Q D

Q CAS NC A9 A8 A7 A6 A5 A4

CAS V

W TF NC A1 A3 A4 A6 A8

Q CAS A9 A8 A7 A6 A5 A4

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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SMJ4C1024 1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY

SGMS023E – DECEMBER 1988 – REVISED MARCH 1996

PIN NOMENCLATURE

A0–A9 Address Inputs CAS D Data In NC No Internal Connection Q Data Out RAS TF Test Function V

description

The SMJ4C1024 is a 1048576-bit DRAM organized as 1048576 words of one bit each. It employs technology for high performance, reliability, and low power at a low cost.

Column Address Strobe

Row Address Strobe

5-V Supply Ground Write Enable

This device features maximum RAS

access times of 80 ns, 100 ns, 120 ns, and 150 ns. Maximum power

dissipation is as low as 305 mW operating and 16.5 mW standby on 150-ns devices.

peaks are typIcally 140 mA and a –1 V input voltage undershoot can be tolerated, minimizing system noise.

All inputs and outputs, including clocks, are compatible with series 54 TTL. All addresses and data-in lines are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.

The SMJ4C1024 is offered in an 18-pin ceramic dual-in-line package (JD suffix), a 20 /26-terminal leadless ceramic carrier package (FQ/HL suffixes), a 20/26-pin J-leaded carrier package (HJ suffix), a 20-pin flatpack (HK suffix), and a 20-pin ceramic zig-zag in-line package (SV suffix). They are characterized for operation from – 55°C to 125°C.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SMJ4C1024

1048576 BY 1-BIT

DYNAMIC RANDOM-ACCESS MEMORY

SGMS023E – DECEMBER 1988 – REVISED MARCH 1996

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std. 91-1984 and IEC Publication 617-12. The pin numbers shown are for the 18-pin JD package.

†

RAM 1024K × 1

1 048 575

23C22

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9

RAS

CAS

5 6 7 8 10 11 12 13 14 15

2 1

20D10/21D0

20D19/21D9

C20 [ROW] G23 [REFRESH ROW] 24 [PWR DWN]

C21 [COL] G24

23,21D 24 A, 22D

A∇ Q

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SMJ4C1024 1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY

SGMS023E – DECEMBER 1988 – REVISED MARCH 1996

functional block diagram

Row

Address

Buffers

(10)

RAS CAS W

Timing and Control

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9

256K

Array

Column

Address

Buffers

(10)

256K

Array

Row

Decode

Sense Amplifiers

Column Decode

Sense Amplifiers

Row

Decode

256K

Array

256K

Array

I/O

Buffers

1 of 8

Selection

Data In

Reg.

Data

Out Reg.

operation

enhanced page mode

Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. The time for row-address setup and hold and for address multiplexing is eliminated. The maximum number of columns that can be accessed is determined by the maximum RAS CAS

page-cycle time used. With minimum CAS page-cycle time, all 1 024 columns specified by column

addresses A0 through A9 can be accessed without intervening RAS

cycles.

Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling edge of RAS

. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS latches the column addresses. This feature lets the SMJ4C1024 operate at a higher data bandwidth than conventional page-mode parts, since data retrieval begins as soon as the column address is valid rather than when CAS

goes low. This performance improvement is referred to as enhanced page mode. A valid column address can be presented immediately after the row-address hold time has been satisfied, usually well in advance of the falling edge of CAS low) if t

maximum (access time from column address) has been satisfied. If the column addresses for the

a(CA)

next page cycle are valid at the same time CAS later occurrence of t

a(CA)

or t

. In this case, data is obtained after t

goes high, access time for the next cycle is determined by the

(access time from rising edge of CAS).

a(CP)

maximum (access time from CAS

a(C)

address (A0–A9)

low time and the

Twenty address bits are required to decode one of 1048576 storage cell locations. Ten row-address bits are set up on inputs A0 through A9 and latched onto the chip by RAS pins A0 through A9 and latched onto the chip by CAS

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. All addresses must be stable on or before the falling edges

. The ten column-address bits are set up on

address (A0–A9) (continued)

SMJ4C1024

1048576 BY 1-BIT

DYNAMIC RANDOM-ACCESS MEMORY

SGMS023E – DECEMBER 1988 – REVISED MARCH 1996

of RAS decoder. CAS

and CAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row

is used as a chip select to activate the output buffer as well as to latch the address bits into the

column-address buffer.

write enable (W

The read or write mode is selected through W

)

. A logic high on the W input selects the read mode and a logic low selects the write mode. The write-enable pin can be driven from standard TTL circuits without a pullup resistor. The data input is disabled when the read mode is selected. When W

goes low prior to CAS (early write),

data out remains in the high-impedance state for the entire cycle, permitting common input/output operation.

data in (D)

Data-in is written during a write or a read-modify-write cycle. Depending on the mode of operation, the falling edge of CAS and the data is strobed in by CAS read-modify-write cycle, CAS

or W strobes data into the on-chip latch. In an early-write cycle, W is brought low prior to CAS,

with setup and hold times referenced to this signal. In a delayed-write or a

is already low, and the data is strobed in by W with setup and hold times

referenced to this signal.

data out (Q)

The 3-state output buffers provide direct TTL compatibility (no pullup resistor required) with a fanout of two series 54 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS from CAS becomes valid after the access time has elapsed and remains valid while CAS

is brought low. In a read cycle, the output becomes valid after the access time t

low (t

) begins with the negative transition of CAS as long as t

a(C)

a(R)

and t

are satisfied. The output

a(CA)

is low; when CAS goes high, the

. The access time

a(C)

output returns to a high-impedance state. In a delayed-write or read-modify-write cycle, the output follows the sequence for the read cycle.

refresh

A refresh operation must be performed at least once every 8 ms to retain data. This can be achieved by strobing each of the 512 rows (A0–A8). A normal read or write cycle refreshes all bits in each selected row. A RAS operation can be used by holding CAS in the high-impedance state. Externally generated addresses must be used for a RAS

at the high (inactive) level, conserving power as the output buffer remains

-only refresh. Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only refresh cycle.

CAS

-before-RAS (CBR) refresh

CBR refresh is used by bringing CAS RAS

falls (parameter t

d(RLCH)R

low earlier than RAS (see parameter t

d(CLRL)R

) and holding it low after

). For successive CBR refresh cycles, CAS can remain low while cycling RAS. The external address is ignored and the refresh address is generated internally. The external address is also ignored during the hidden refresh cycles.

power up

T o achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is required after full V

level is achieved.

test function (TF) pin

During normal device operation, TF must be disconnected or biased at a voltage ≤ V

-only

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SMJ4C1024 1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY

SGMS023E – DECEMBER 1988 – REVISED MARCH 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Voltage range on any pin (see Note 1) – 1 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range on V Short-circuit output current, I

– 1 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power dissipation 1 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to VSS.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

– 55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage 4.5 5 5.5 V

High-level input voltage 2.4 6.5 V

Low-level input voltage (see Note 2) –1 0.8 V

Minimum operating free-air temperature – 55

Maximum operating case temperature 125

NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.

°C °C

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SMJ4C1024

PARAMETER

UNIT

PARAMETER

UNIT

PARAMETER

UNIT

1048576 BY 1-BIT

DYNAMIC RANDOM-ACCESS MEMORY

SGMS023E – DECEMBER 1988 – REVISED MARCH 1996

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

’4C1024-80 ’4C1024-10 ’4C1024-12 ’4C1024-15

MIN MAX MIN MAX MIN MAX MIN MAX

± 10 ± 10 ± 10 ± 10 µA

3 3 3 3 mA

70 65 55 50 mA

50 45 35 30 mA

CC1

CC2

CC3

CC4

High-level output voltage

Low-level output voltage

Input current (leakage)

Output current (leakage)

Read- or write-cycle current

Standby current

Average refresh current (RAS

only or

CBR) Average page

current

TEST

CONDITIONS

IOH = – 5 mA 2.4 2.4 2.4 2.4 V

IOL = 4.2 mA 0.4 0.4 0.4 0.4 V VCC = 5.5 V, VI = 0 V to 6.5 V,

All other pins = 0 V to V VCC = 5.5 V, VO = 0 V to VCC,

high

CAS

VCC = 5.5 V, Minimum cycle 75 70 60 55 mA

After one memory cycle, RAS

and CAS high,

VIH = 2.4 V VCC = 5.5 V, Minimum cycle,

cycling,

RAS

high (RAS only),

CAS

low after CAS low (CBR)

RAS VCC = 5.5 V, tPC = minimum,

low, CAS cycling

RAS

capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 3)

HL/JD/FQ HJ HK SV

MIN MAX MIN MAX MIN MAX MIN MAX

i(A)

i(D)

i(RC)

i(W)

NOTE 3: Capacitance is sampled only at initial design and after any major change. Samples are tested at 0 V and 25°C with a 1-MHz signal

Input capacitance, address inputs 6 7 8 9 pF Input capacitance, data input 5 5 6 7 pF Input capacitance, strobe inputs 7 7 8 8 pF Input capacitance, write-enable input 7 7 7 7 pF Output capacitance 7 9 10 8 pF

applied to the pin under test. All other pins are open.

switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Figure 1)

’4C1024-80 ’4C1024-10 ’4C1024-12 ’4C1024-15

MIN MAX MIN MAX MIN MAX MIN MAX

20 25 30 40 ns 40 45 55 70 ns 80 100 120 150 ns 40 40 60 75 ns

20 25 30 35 ns

a(C)

a(CA)

a(R)

a(CP)

dis(CH)

NOTE 4: t

ALT.

SYMBOL

Access time from CAS low t Access time from column address t Access time from RAS low t Access time from column precharge t Output disable time after CAS high

(see Note 4)

is specified when the output is no longer driven. The output is disabled by bringing CAS high.

dis(CH)

CAC

AA RAC CPA

OFF

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SMJ4C1024

UNIT

1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY

SGMS023E – DECEMBER 1988 – REVISED MARCH 1996

timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 5)

ALT.

SYMBOL

c(rd)

c(W)

c(rdW)

c(P)

c(PM)

w(CH)

w(CL)

w(RH)

w(RL)

w(RL)P

w(WL)

su(CA)

su(RA)

su(D)

su(rd)

su(WCL)

su(WCH)

su(WRH)

h(CA)

h(RA)

NOTES: 5. Timing measurements in this table are referenced to VIL max and VIH min.

Cycle time, read (see Note 6)

Cycle time, write t Cycle time,

read-write/read-modify-write Cycle time, page-mode read

or write (see Note 7) Cycle time, page-mode

read-modify-write Pulse duration, CAS high t Pulse duration, CAS low

(see Note 8) Pulse duration, RAS high

(precharge) Pulse duration, nonpage

mode, RAS (see Note 9)

Pulse duration, page mode, RAS

Pulse duration, write t Setup time, column address

before CAS Setup time, row address

before RAS Setup time, data

(see Note 10) Setup time, read before CAS

low Setup time, W low before

CAS Setup time, W low before

RAS Hold time, column address

after CAS Hold time, row address after

RAS

6. All cycle times assume tt = 5 ns.

7. To assure t

8. In a read-modify-write cycle, t

9. In a read-modify-write cycle, t

10. Referenced to the later of CAS

11. Early write operation only

low

low (see Note 9)

low

low (see Note 11)

high

low

min, t

c(P)

su(CA)

should be ≥ t

RWC

PRWC

CAS

RAS

RASP

ASC

ASR

RCS

WCS

CWL

RWL

CAH

RAH

d(CLWL) d(RLWL)

or W in write operations

’4C1024-80 ’4C1024-10 ’4C1024-12 ’4C1024-15 MIN MAX MIN MAX MIN MAX MIN MAX

150 190 220 260 ns 150 190 220 260 ns 175 220 265 315 ns

50 55 65 80 ns

75 85 110 135 ns 10 10 15 25 ns 20 10000 25 10000 30 10000 40 10000 ns

60 80 90 100 ns

80 10000 100 10000 120 10000 150 10000 ns

80 100000 100 100000 120 100000 150 100000 ns 15 15 20 25 ns

0 3 3 3 ns

0 0 0 0 ns

20 25 30 40 ns

15 20 20 25 ns

12 15 15 20 ns

w(CH)

and t and t

su(WCH) su(WRH)

must be observed. must be observed.

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SMJ4C1024

UNIT

1048576 BY 1-BIT

DYNAMIC RANDOM-ACCESS MEMORY

SGMS023E – DECEMBER 1988 – REVISED MARCH 1996

timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 5) (continued)

ALT.

SYMBOL

h(RLCA)

h(D)

h(RLD)

h(CHrd)

h(RHrd)

h(CLW)

h(RLW)

d(RLCH)

d(CHRL)

d(CLRH)

d(CLWL)

d(RLCL)

d(RLCA)

d(CARH)

d(CACH)

d(RLWL)

d(CAWL)

d(RLCH)R

d(CLRL)R

d(RHCL)R

NOTES: 5. Timing measurements in this table are referenced to VIL max and VIH min.

Hold time, column address after RAS

low (see Note 12) Hold time, data (see Note 10) t Hold time, data after RAS low

(see Note 12) Hold time, read after CAS high

(see Note 13) Hold time, read after RAS high

(see Note 13) Hold time, write after CAS low

(see Note 11) Hold time, write after RAS low

(see Note 12) Delay time, RAS low to CAS high t Delay time, CAS high to RAS low t Delay time, CAS low to RAS high t Delay time, CAS low to W low

(see Note 14) Delay time, RAS low to CAS low

(see Note 15) Delay time, RAS low to column

address (see Note 15) Delay time, column address to RAS

high Delay time, column address to CAS

high Delay time, RAS low to W low

(see Note 14) Delay time, column address to W

low (see Note 14) Delay time, RAS low to CAS high

(see Note 16) Delay time, CAS low to RAS low

(see Note 16) Delay time, RAS high to CAS low t Refresh time interval t Transition time (see Note 17) — — — — — ns

10. Referenced to the later of CAS

11. Early-write operation only

12. The minimum value is measured when t

13. Either t

14. Read-modify-write operation only

15. Maximum value specified only to assure access time.

16. CBR refresh only

17. Transition times (rise and fall) for RAS

h(RHrd)

or t

h(CHrd)

or W in write operations.

must be satisfied for a read cycle.

AR DH

DHR

RCH

RRH

WCH

WCR

CSH CRP RSH

CWD

RCD

RAD

RAL

CAL

RWD

AWD

CHR

CSR RPC

REF

d(RLCL)

and CAS are to be minimum of 3 ns and a maximum of 50 ns.

’4C1024-80 ’4C1024-10 ’4C1024-12 ’4C1024-15

MIN MAX MIN MAX MIN MAX MIN MAX

60 70 80 100 ns 15 20 25 30 ns 60 70 85 110 ns

0 0 0 0 ns

10 10 10 10 ns

15 20 25 30 ns

60 70 85 100 ns 80 100 120 150 ns

0 0 0 0 ns

20 25 30 40 ns 20 25 40 50 ns

22 60 28 75 28 90 33 110 ns

17 40 20 55 20 65 25 80 ns

40 45 55 70 ns

80 100 130 160 ns

40 45 65 80 ns

20 25 25 30 ns

10 10 10 15 ns

0 0 0 0 ns

8 8 8 8 ms

is set t

d(RLCL)

min as a reference.

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+ 18 hidden pages