Texas Instruments SMJ320C15-25FJM, SMJ320C15-25JDM Datasheet

TMS320C1x

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JUL Y 1991

• Performance Up to 8.77 MIPs

• All TMS320C1x Devices are Object Code

Compatible

• 144/256-Word On-Chip Data RAM

• 1.5K/4K/8K-Word On-Chip Program ROM

• 4K-Word On-Chip Program EPROM

(TMS320E14/P14/E15/P15/E17/P17)

• One-T ime Programmable (OTP)

Versions Available (TMS320P14/P15/P17)

• EPROM Code Protection for Copyright

Security

• 4K / 64K-Word Total External Memory at

Full Speed

• 32-Bit ALU/Accumulator

• 16 × 16-Bit Multiplier With a 32-Bit Product

• 0 to 16-Bit Barrel Shifter

• Eight Input/Output Channels

• Dual-Channel Serial Port

• Simple Memory and I/O Interface

• Commercial and Military Versions A vailable

• Operating Free-Air Temperature

. . . 0°C to 70°C

• Packaging: DIP, PLCC, Quad Flatpack, and

CER-QUAD

• CMOS Technology:

Device

— TMS320C10 200-ns. . . . . . . . . . . . . . . . . . .

— TMS320C10-14 280-ns. . . . . . . . . . . . . . . .

— TMS320C10-25 160-ns. . . . . . . . . . . . . . . .

— TMS320C14 160-ns. . . . . . . . . . . . . . . . . . .

— TMS320E14 160-ns. . . . . . . . . . . . . . . . . . .

— TMS320P14 160-ns. . . . . . . . . . . . . . . . . . .

— TMS320C15 200-ns. . . . . . . . . . . . . . . . . . .

— TMS320C15-25 160-ns. . . . . . . . . . . . . . . .

— TMS320E15 200-ns. . . . . . . . . . . . . . . . . . .

— TMS320E15-25 160-ns. . . . . . . . . . . . . . . .

— TMS320LC15 250-ns. . . . . . . . . . . . . . . . . .

— TMS320P15 200-ns. . . . . . . . . . . . . . . . . . .

— TMS320C16 114-ns. . . . . . . . . . . . . . . . . . .

— TMS320C17 200-ns. . . . . . . . . . . . . . . . . . .

— TMS320E17 200-ns. . . . . . . . . . . . . . . . . . .

— TMS320LC17 278-ns. . . . . . . . . . . . . . . . . .

— TMS320P17 200-ns. . . . . . . . . . . . . . . . . . .

Cycle Time

• 5-V and 3.3-V Versions Available

(TMS320LC15/LC17)

introduction

The TMS32010 digital signal processor (DSP), introduced in 1983, was the first DSP in the TMS320 family . From it has evolved this TMS320C1x generation of 16-bit DSPs. All ′C1x DSPs are object code compatible with the TMS32010 DSP. The ′C1x DSPs combine the flexibility of a high-speed controller with the numerical capability of an array processor, thereby offering an inexpensive alternative to multichip bit-slice processors. The highly paralleled architecture and efficient instruction set provide speed and flexibility to produce a CMOS microprocessor generation capable of executing up to 8.77 MIPS (million instructions per second) (′C16). These ′C1x devices utilize a modified Harvard architecture to optimize speed and flexibility , implementing functions in hardware that other processors implement through microcode or software.

The ′C1x generation’s powerful instruction set, inherent flexibility, high-speed number-handling capabilities, reduced power consumption, and innovative architecture have made these cost-effective DSPs the ideal solution for many telecommunications, computer, commercial, industrial, and military applications.

This data sheet provides detailed design documentation for the ′C1x DSPs. It facilitates the selection of devices best suited for various user applications by providing specifications and special features for each ′C1x DSP.

This data sheet is arranged as follows: introduction, quick reference table of device parameters and packages, summary overview of each device, architecture overview, and the ′C1x device instruction set summary. These are followed by data sheets for each ′C1x device providing available package styles, terminal function tables, block diagrams, and electrical and timing parameters. An index is provided to facilitate data sheet usage.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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TMS320C1x DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987– REVISED JULY 1991

T able 1 provides an overview of ′C1x processors with comparisons of memory , I/O, cycle timing, military support, and package types. For specific availability, contact the nearest TI Field Sales Office.

Table 1. TMS320C1x Device Overview

DEVICE

TMS320C10 (2) 144 1.5K — 4K — 8 × 16 200 40 44 — TMS320C10-14 144 1.5K — 4K — 8 × 16 280 40 44 — TMS320C10-25 144 1.5K — 4K — 8 × 16 160 40 44 — TMS320C14 (3) 256 4K — 4K 1 7 × 16 (4) 160 — 68 — TMS320E14 (3) 256 — 4K 4K 1 7 × 16 (4) 160 — — 68 CER TMS320P14 TMS320C15 (3) 256 4K — 4K — 8 × 16 200 40 44 — TMS320C15-25 256 4K — 4K — 8 × 16 160 40 44 — TMS320E15 (3) 256 — 4K 4K — 8 × 16 200 40 — 44 CER TMS320E15-25 256 — 4K 4K — 8 × 16 160 40 — 44 CER TMS320LC15 256 4K — 4K — 8 × 16 250 40 44 — TMS320P15 TMS320C16 256 8K — 64K — 8 × 16 114 — — 64 QFP TMS320C17 256 4K — — 2 6 ×16 (5) 200 40 44 — TMS320E17 (5) 256 — 4K — 2 6 × 16 (5) 200 40 — 44 CER TMS320LC17 (5) 256 4K — — 2 6 × 16 (5) 278 40 44 — TMS320P17 (5)

†

One-time programmable (OTP) device is in a windowless plastic package and cannot be erased.

NOTES: 1. DIP = dual in-line package. PLCC = plastic-leaded chip carrier. CER = ceramic-leaded chip carrier. QFP = plastic quad flat pack.

†

2. Military version available.

3. Military versions planned; contact nearest TI Field Sales Office for availability .

4. On-chip 16-bit I/O, four capture inputs, and six compare outputs are available.

5. On-chip 16-bit coprocessor interface is optional by pin selection.

RAM ROM EPROM PROG. SERIAL PARALLEL (ns) DIP PLCC CER-QUAD

256 — 4K 4K 1 7 × 16 (4) 160 — 68 —

256 — 4K 4K — 8 × 16 200 40 44 —

†

256 — 4K — 2 6 × 16 (5) 200 40 44

MEMORY I/O CYCLE PACKAGE (1)

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TMS320C1x

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JUL Y 1991

description

TMS320C10

The ′C10 provides the core CPU used in all other ′C1x devices. Its microprocessor operates at 5 MIPS. It provides a parallel I/O of 8 × 16 bits. Three versions with cycle times of 160, 200, and 280 ns are available as illustrated in Table 1. The ′C10 versions are offered in plastic 40-pin DIP or a 44-lead PLCC packages.

TMS320C14/E14/P14

The ′C14/E14/P14 devices, using the ′C10 core CPU, offer expanded on-chip RAM, and ROM or EPROM (′E14/P14), 16 pins of bit selectable parallel I/O, an I/O mapped asynchronous serial port, four 16-bit timers, and external/internal interrupts. The ′C14 devices can provide for microcomputer/microprocessor operating modes. Three versions with cycle times of 160-ns are available as illustrated in Table 1. These devices are offered in 68-pin plastic PLCC or ceramic CER-QUAD packages.

TMS320C15/E15/P15

The ′C15/E15/P15 devices are a version of the ′C10, offering expanded on-chip RAM, and ROM or EPROM (′E15/P15). The ′P15 is a one-time programmable (OTP), windowless EPROM version. These devices can operate in the microcomputer or microprocessor modes. Five versions are available with cycle times of 160 to 200 ns (see Table 1). These devices are offered in 40-pin DIP, 44-pin PLCC, or 44-pin ceramic packages.

TMS320LC15

The ′LC15 is a low-power version of the ′C15, utilizing a V requirement reduction over the typical 5-V ′C1x device. It operates at a cycle time of 250 ns. The device is offered in 40-pin DIP or 44-lead PLCC packages.

of only 3.3-V . This feature results in a 2.3: 1 power

TMS320C16

The ′C16 offers on-chip RAM of 256-words, an expanded program memory of 64K-words, and a fast instruction cycle time of 114 ns (8.77 MIPS). It is offered in a 64-pin quad flat-pack package.

TMS320C17/E17/P17

The ′C17/E17/P17 versions consist of five major functional units: the ′C15 microcomputer, a system control register, a full-duplex dual channel serial port, µ-law/A-law companding hardware, and a coprocessor port. The dual-channel serial port is capable of full-duplex serial communication and offers direct interface to two combo-codecs. The hardware companding logic can operate in either µ-law or A-law format with either sign-magnitude or twos complement numbers in either serial or parallel modes. The coprocessor port allows the ′C17/E17/P17 to act as a slave microcomputer or as a master to a peripheral microcomputer .

The ′P17 utilizes a one-time programmable (OTP) windowless EPROM version of the ′E17.

TMS320LC17

The ′LC17 is a low-power version of the ′C17, utilizing a V

2.3: 1 power requirement reduction over the typical 5-V ′C1x device. It operates at a cycle time of 278 ns.

of only 3.3-V. This feature results in a

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TMS320C1x DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987– REVISED JULY 1991

TMS320C10/C15/LC15/P15

N/JD Packages

A1/PA1 A0/PA0 MC/MP

INT

CLKOUT

X2/CLKIN

BIO

D8 D9

D10

D11 D12 D13 D14 D15

D7 D6

TCLK/CLKR

TCLK2/CLKX

CLKOUT

NMI

/MC/MP

CLKIN

9876543216867666564636261 10 11

REN

INT

18 19

21 22

WDT

23 24

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

(Top View)

TMS320C14/E14/P14

FN/FZ Packages

CMP0

CMP1

A10

A11

IOP15

IOP14

IOP13

A2/PA2 A3 A4 A5 A6 A7 A8 MEN DEN WE V

A9 A10 A11 D0 D1 D2 D3 D4 D5

(Top View)

CC2VSS2

CMP2

CMP3

CC1VSS1

IOP12

D15

CAP0

D14

CAP1

IOP11

TMS320C17/E17/LC17/P17

PA1/RBLE PA0/HI/LO

EXINT

CLKOUT

X2/CLKIN

D8/LD8

D9/LD9 D10/Ld10 D11/LD11

D12/LD12 D13/LD13 D14/LD14 D15/LD15

D7/LD7

D6/LD6

AMP4/CAP2/FSR

IOP10

CMP5/CAP3/FSX

D13

D12

IOP9

IOP8

CLKOUT

X2/CLKIN

N/JD Packages

(Top View)

1 2

4 5 6

7 8

BIO

11 12 13 14 15 16 17 18 19 20

IOP0

IOP1

IOP2

IOP3

IOP4

IOP5

RXD/DATA

TXD/CLK

D10

IOP6

IOP7

D11

BIO

SS D8 D9

D10

D11

D12

PA2/TBLF

FSR

FSX

DX1

DX0

SCLK

DR1

DEN 31 30 29 28 27 26 25 24 23 22 21

/RD WE/WR V

DR0 XF MC/PM D0/LD0 D1/LD1 D2/LD2 D3/LD3 D4/LD4 D5/LD5

TMS320C17/E17 FN/FZ Packages

(Top View)

PAO/HI/LO

PA1/RBLE

D7/LD7

D14/LD14

D15/LD15

PA2/TBLF

44 43 42 41 40

123456

D6/LD6

D5/LD5

EXINTRSMC

7 8 9 10 11 12 13 14 15 16 17

18 19 20 21 22 23 24 25 26 27 28

D13/LD13

FSR

FSXFRDX1

D4/LD4

D3/LD3

X2/CLKIN

CLKOUT

39 38 37 36 35 34 33 32 31 30 29

D2/LD2

D1/LD1

TMS320C10/C15/E15/LC15/P15

FN/FZ Packages

(Top View)

INTRSMC/MP

CLKOUT

BIO

D10

D11

D12

8 9 10 11 12

D8 D9

14 15 16 17

18 19 20 21 22 23 24 25 26 27 28

D13

TMS320C16 PG Package

(Top View)

BIO

INT

MC/MP

64636261605958575655545352

4 5

9 10

D15

D14

D13

D12

D11

D10

20212223242526272829303132

D8D7D6D5D4D3D2NCD1

DX0 SCLK DR1

/RD

DEN WE/WR V

DR0 XF MC/PM D0/LD0 V

D14

A0/PA0

D15

DDDDDD

VVV

A1/PA1

A2/PA2A3A4A5A6

44 43 42 41 40

123456

D7D6D5

MEN

IOEN

MWE

IOWE

A15

MEN

DEN

A10

A11

NC A0/PA0

A1/PA1

A2/PA2

47 46

A3 A4

45 44

A6 V

A10

A11

A12

36 35

A13

A14

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TMS320C1x

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JUL Y 1991

architecture

The ′C1x DSPs use a modified Harvard architecture for speed and flexibility. In a strict Harvard architecture, program and data memory lie in two separate spaces, permitting a full overlap of instruction fetch and one-cycle execution. The ′C1x DSPs modification allows transfers between program and data spaces, thereby increasing the flexibility of the device. This modification permits coefficients stored in program memory to be read into the RAM, eliminating the need for a separate coefficient ROM.

32-bit accumulator

All ′C1x devices contain a 32-bit ALU and accumulator for support of double-precision, twos-complement arithmetic. The ALU is a general-purpose arithmetic unit that operates on 16-bit words taken from the data RAM or derived from immediate instructions. In addition to the usual arithmetic instructions, the ALU can perform Boolean operations, providing the bit manipulation ability required of a high-speed controller. The accumulator stores the output from the ALU and is often an input to the ALU. It operates with a 32-bit word length. The accumulator is divided into a high-order word (bits 31 through 16) and a low-order word (bits 15 through 0). Instructions are provided for storing the high- and low-order accumulator words in memory.

shifters

Two shifters are available for manipulating data. The ALU barrel shifter performs a left-shift of 0 to 16 places on data memory words loaded into the ALU. This shifter extends the high-order bit of the data word and zero-fills the low-order bits for twos-complement arithmetic. The accumulator parallel shifter performs a left-shift of 0, 1 or 4 places on the entire accumulator and places the resulting high-order accumulator bits into data RAM. Both shifters are useful for scaling and bit extraction.

16 × 16-bit parallel multiplier

The multiplier performs a 16 × 16-bit twos-complement multiplication with a 32-bit result in a single instruction cycle. The multiplier consists of three units: the T Register, P Register, and a multiplier array. The 16-bit T Register stores the multiplicand, and the P Register stores the 32-bit product. Multiplier values either come from the data memory or are derived immediately from the MPYK (multiply immediate) instruction word. The fast on-chip multiplier allows the device to perform fundamental operations such as convolution, correlation, and filtering.

data and program memory

Since the ′C1x devices use a Harvard type architecture, data and program memory reside in two separate spaces. These DSP devices have 144-or 256-words of on-chip data RAM and 1.5K- to 8K-words of on-chip program ROM. On-chip program EPROM of 4K-words is provided in the ′E14/E15/E17 devices. An on-chip one-time programmable 4K-word EPROM is provided in the ′P14/P15/P17 devices. The EPROM cell utilizes standard PROM programmers and is programmed identically to a 64K CMOS EPROM (TMS27C64). (Reference Table 1.)

program memory expansion

All ′C1x devices except the ′C17/E17/LC17/P17 devices are capable of executing from off-chip external memory at full speed for those applications requiring external program memory space. This allows for external RAM-based systems to provide multiple functionality. The ′C17/E17/LC17/P17 devices provide no external memory expansion. (Reference Table 1.)

microcomputer/microprocessor operating modes

All devices except the ′x17 offer two modes of operation defined by the state of the MC/MP microcomputer mode (MC/MP = 1) or the microprocessor mode (MC/MP = 0 ). In the microcomputer mode, on-chip ROM is mapped into the program memory space. In the microprocessor mode, all words of progam memory are external.

pin: the

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TMS320C1x DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987– REVISED JULY 1991

interrupts and subroutines

All devices except the ′C16 contain a four-level stack for saving the contents of the program counter during interrupts and subroutine calls. Because of the larger 64K program space, the ′C16’s hardware stack has been increased to eight levels. Instructions are available for saving the device’s complete context. PUSH and POP instructions permit a level of nesting restricted only by the amount of available RAM. The interrupts used in these devices are maskable.

input/output

The 16-bit parallel data bus can be utilized to perform I/O functions in two cycles. The I/O ports are addressed by the three LSBs on the address lines. In addition, a polling input for bit test and jump operations (BIO an interrupt pin (INT) have been incorporated for multitasking. The bit selectable I/O of the ′C14 is suitable for microcontroller applications.

serial port (TMS320C17/E17)

Two of the I/O ports on the ′C17/E17 are dedicated to the serial port and companding hardware. I/O port 0 is dedicated to control register 0, which controls the serial port, interrupts, and companding hardware. I/O port 1 accesses control register 1, as well as both serial port channels, and companding hardware. The six remaining I/O ports are available for external parallel interfaces.

serial port (TMS320C14/E14)

The ′C14/E14 devices include one I/O-mapped serial port that operates asynchronously. I/O-mapped control registers are used to configure port parameters such as inter-processor communication protocols and baud rate.

) and

companding hardware (TMS320C17/E17)

On-chip hardware enables the ′C17/E17 to compand (COMpress/exP AND) data in either µ-law or A-law format. The companding logic operation is configured via the system control register. Data may be companded in either serial mode for operation on serial port data (converting between linear and logarithmic PCM) or a parallel mode for computation inside the device. The ′C17/E17 allows the hardware companding logic to operate with either sign-magnitude or twos-complement numbers.

coprocessor port (TMS320C17/E17)

The coprocessor port on the ′C17/E17 provides a direct connection to most microcomputers and microprocessors. The port is accessed through I/O port 5 using IN and OUT instructions. The coprocessor interface allows the device to act as a peripheral (slave) microcomputer to a microprocessor, or as a master to a peripheral microcomputer. In the microcomputer mode, the 16 data lines are used for the 6 parallel 16-bit I/O ports. In the coprocessor mode, the 16-bit parallel port is reconfigured to operate as a 16-bit latched bus interface. For peripheral transfer, an 8-bit or 16-bit length of the coprocessor port can be selected.

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TMS320C1x

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JUL Y 1991

instruction set

A comprehensive instruction set supports both numeric-intensive operations, such as signal processing, and general-purpose operations, such as high-speed control. All of the ′C1x devices are object-code compatible and use the same 60 instructions. The instruction set consists primarily of single-cycle single-word instructions, permitting execution rates of more than six million instructions per second. Only infrequently used branch and I/O instructions are multicycle. Instructions that shift data as part of an arithmetic operation execute in a single cycle and are useful for scaling data in parallel with other operations.

NOTE

The BIO pin on other ′C1x devices is not available for use in the ′C14/E14/P14. An attempt to execute the BIOZ (Branch on BIO

Three main addressing modes are available with the instruction set: direct, indirect, and immediate addressing.

direct addressing

In direct addressing, seven bits of the instruction word concatenated with the 1-bit data page pointer form the data memory address. This implements a paging scheme in which the first page contains 128 words, and the second page contains up to 128 words.

indirect addressing

Indirect addressing forms the data memory address from the least-significant eight bits of one of the two auxiliary registers, AR0-AR1. The Auxiliary Register Pointer (ARP) selects the current auxiliary register. The auxiliary registers can be automatically incremented or decremented and the ARP changed in parallel with the execution of any indirect instruction to permit single-cycle manipulation of data tables. Indirect addressing can be used with all instructions requiring data operands, except for the immediate operand instructions.

low) instruction will result in a two cycle NOP action.

immediate addressing

Immediate instructions derive data from part of the instruction word rather than from the data RAM. Some useful immediate instructions are multiply immediate (MPYK), load accumulator immediate (LACK), and load auxiliary register immediate (LARK).

instruction set summary

T able 2 lists the symbols and abbreviations used in T able 3, the instruction set summary . T able 3 contains a short description and the opcode for each ′C1x instruction. The summary is arranged according to function and alphabetized within each functional group.

Table 2. Instruction Symbols

SYMBOL MEANING

ACC Accumulator D Data memory address field M Addressing mode bit K Immediate operand field PA 3-bit port address field R 1-bit operand field specifying auxiliary register S 4-bit left-shift code X 3-bit accumulator left-shift field

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TMS320C1x DIGITAL SIGNAL PROCESSORS

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Table 3. TMS320C1x Instruction Set Summary

ACCUMULATOR INSTRUCTIONS

MNEMONIC DESCRIPTION INSTRUCTION REGISTER

ABS Absolute value of accumulator 1 1 0 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 ADD Add to accumulator with shift 1 1 0 000 M ADDH Add to high-order accumulator bits 1 1 0 1100000M ADDS Add to accumulator with no sign extension 1 1 0 1100001M AND AND with accumulator 1 1 0 1111001M LAC Load accumulator with shift 1 1 0 010 M LACK Load accumulator immediate 1 1 0 1111110 OR OR with accumulator 1 1 0 1111010M SACH Store high-order accumulator bits with shift 1 1 0 1011 M SACL Store low-order accumulator bits 1 1 0 1010000M SUB Subtract from accumulator with shift 1 1 0 001 M SUBC Conditional subtract (for divide) 1 1 0 1100100M SUBH Subtract from high-order accumulator bits 1 1 0 1100010M SUBS Subtract from accumulator with no sign extension 1 1 0 1100011M XOR Exclusive OR with accumulator 1 1 0 1111000M ZAC Zero accumulator 1 1 0 111111110001001 ZALH Zero accumulator and load high-order bits 1 1 0 1100101M ZALS Zero accumulator and load low-order bits with no sign extension 1 1 0 1100110M

AUXILIARY REGISTER AND DATA PAGE POINTER INSTRUCTIONS

MNEMONIC DESCRIPTION INSTRUCTION REGISTER

LAR Load auxiliary register 1 1 0 0 1 1 1 0 0 R M LARK Load auxiliary register immediate 1 1 0 111000R LARP Load auxiliary register pointer immediate 1 1 0 11010001000000K LDP Load data memory page pointer 1 1 0 1101111M LDPK Load data memory page pointer immediate 1 1 0 11011100000000K MAR Modify auxiliary register and pointer 1 1 0 1101000M SAR Store auxiliary register 1 1 0 0 1 1 0 0 0 R M

NO.

CYCLES

NO.

CYCLES

NO.

WORDS

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NO.

WORDS

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OPCODE

D D

D D D K D D

D D D D D D

D D

D K

D D

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TMS320C1x

DIGITAL SIGNAL PROCESSORS

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Table 3. TMS320C1x Instruction Set Summary (continued)

BRANCH INSTRUCTIONS

MNEMONIC DESCRIPTION INSTRUCTION REGISTER

B Branch unconditionally 2 2

BANZ Branch on auxiliary register not zero 2 2

BGEZ Branch if accumulator

BGZ Branch if accumulator > 0 2 2

BIOZ Branch on BIO

BLEZ Branch if accumulator

BLZ Branch if accumulator < 0 2 2

BNZ Branch if accumulator ≠ 022

BV Branch on overflow 2 2

BZ Branch if accumulator = 0 2 2

CALA Call subroutine from accumulator

CALL Call subroutine immediately 2 2

RET Return from subroutine or interrupt routine

MNEMONIC DESCRIPTION INSTRUCTION REGISTER

APAC Add P register to accumulator 1 1 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 LT Load T Register 1 1 0 1101010M LTA LTA combines LT and APAC into one instruction 1 1 0 1101100M LTD LTD combines LT, APAC, and DMOV into one instruction 1 1 0 1101011M MPY Multiply with T register, store product in P register 1 1 0 1101101M

MPYK

PAC Load accumulator from P register 1 1 0 111111110001110 SPAC Subtract P register from accumulator 1 1 0 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0

†

This instruction is a NOP on the ′320C14/E14/P14.

Multiply T register with immediate operand; store product in P register

≥ 022

†

= 0

≤ 0 2 2

T REGISTER, P REGISTER, AND MULTIPLY INSTRUCTIONS

NO.

CYCLES

2 1 0 111111110001100

2 1 0 111111110001101

NO.

CYCLES

1 1 1 00

NO.

WORDS

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 000 1 111010000000000 0 000 1 111110100000000 0 000 1 111110000000000 0 000 1 111011000000000 0 000 1 111101100000000 0 000 1 111101000000000 0 000 1 111111000000000 0 000 1 111010100000000 0 000 1 111111100000000 0 000

1 111100000000000 0 000

NO.

WORDS

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OPCODE

BRANCH ADDRESS

OPCODE

D D D D

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TMS320C1x DIGITAL SIGNAL PROCESSORS

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Table 3. TMS320C1x Instruction Set Summary (concluded)

CONTROL INSTRUCTIONS

MNEMONIC DESCRIPTION INSTRUCTION REGISTER

DINT Disable interrupt 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 EINT Enable interrupt 1 1 0 111111110000010 LST Load status register 1 1 0 1111011M NOP No operation 1 1 0 111111110000000 POP POP stack to accumulator 2 1 0 111111110011101 PUSH PUSH stack from accumulator 2 1 0 111111110011100 ROVM Reset overflow mode 1 1 0 111111110001010 SOVM Set overflow mode 1 1 0 111111110001011 SST Store status register 1 1 0 1111100M

I/O AND DATA MEMORY OPERATIONS

MNEMONIC DESCRIPTION INSTRUCTION REGISTER

DMOV Copy contents of data memory location into next higher location 1 1 0 1 1 0 1 0 0 1 M IN Input data from port 2 1 0 1000 M OUT Output data to port 2 1 0 1001 M TBLR Table read from program memory to data RAM 3 1 0 1100111M TBLW Table write from data RAM to program memory 3 1 0 1 1 1 1 1 0 1 M

NO.

CYCLES

NO.

CYCLES

NO.

WORDS

NO.

WORDS

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OPCODE

D D DPA D

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C10, TMS320C10-14, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JUL Y 1991

Key Features: TMS320C10

• Instruction Cycle Timing

— 160-ns (TMS320C10-25) — 200-ns (TMS32010) — 280-ns (TMS320C10-14)

• 144 Words of On-Chip Data RAM

• 1.5K Words On-Chip Program ROM

• External Memory Expansion up to 4K

Words at Full Speed

• 16 × 16-Bit Multiplier With 32-Bit Product

• 0 to 16-Bit Barrel Shifter

• On-Chip Clock Oscillator

• Device Packaging:

— 40-Pin DIP — 44-Lead PLCC

• Single 5-V Supply

• Operating Free-Air Temperature Range

...0°C to 70°C

Interrupt

+5 V GND

144-Word RAM

Data (16)

1.5K-Word ROM

32-Bit ALU/ACC

Multiplier

Address (12)

Shifters

A1/PA1 A0/PA0

MC/MP

INT

CLKOUT

X2/CLKIN

BIO

D8 D9

D10

D11 D12 D13 D14 D15

D7 D6

TMS320C10

N/JD Package

19 20

A2/PA2 A3 A4 A5 A6 A7 A8 MEN DEN WE V

A9 A10 A11 D0 D1 D2 D3 D4 D5

CLKOUT

X2/CLKIN

BIO

D9 D10 D11 D12

INTRSMC/MP

7 8 9 10 11 12 13 14 15 16 17

18 19 20

TMS320C10

FN/FZ Package

(Top View)(Top View)

A0/PA0

A1/PA1

123456

21 22 23 24 25 26

D13

D7D6D5D4D3

D14

D15

A2/PA2A3A4A5A6

44 43 42 41 40

27 28

39 38 37 36 35 34 33 32 31 30 29

A7 A8 MEN DEN WE V

A9 A10 A11 D0 D1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C10, TMS320C10-14, TMS320C10-25 DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987– REVISED JULY 1991

TERMINAL FUNCTIONS

NAME I/O

A11-A0/PA2-PA0 BIO CLKOUT D15-D0 DEN INT MC/MP MEN NC RS V

WE X1 X2/CLKIN

†

Input/Output/High-impedance state.

†

External address bus. I/O port address multiplexed over PA2-PA0.

External polling input

System clock output, 1/4 crystal/CLKIN frequency

I/O

16-bit parallel data bus

Data enable for device input data on D15-D0

External interrupt input

Memory mode select pin. High selects microcomputer mode. Low selects microprocessor mode.

Memory enable indicates that D15-D0 will accept external memory instruction.

No connection

Reset for initializing the device

+ 5 V supply

Ground

Write enable for device output data on D15-D0

Crystal output for internal oscillator

Crystal input internal oscillator or external system clock input

DEFINITION

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functional block diagram

DEN

MEN

BIO

MC/MP

INT

A11-A0/

PA2-PA0

Controller

MUX

TMS320C10, TMS320C10-14, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JUL Y 1991

X2/CLKINCLKOUT

Program Bus

12 LSB

MUX

PC (12) 12

Stack 4 × 12

Program Bus

Instruction

Program ROM/EPROM (1.5K Words)

Address

MUX

D15-D0

ARP

Legend:

ACC = Accumulator ALU = Arithmetic Logic Unit ARP = Auxiliary Register Pointer AR0 = Auxiliary Register 0 AR1 = Auxiliary Register 1 DP = Data Page Pointer P = P Register PC = Program Counter T = T Register

AR0 (16) AR1 (16)

MUX 8

Address

Data RAM

(144 Words)

Data

16 16

Data Bus

Shifter

(0–16)

Shifter (0,1,4)

ALU (32)

ACC (32)

T(16)

Multiplier

P(32)

MUX

Data Bus

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C10, TMS320C10-14, TMS320C10-25 DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987– REVISED JULY 1991

electrical specifications

This section contains the electrical specifications for all speed versions of the ′C10 Digital Signal Processors, including test parameter measurement information.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range VCC (see Note 6) –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous power dissipation 0.5 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature: L suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A suffix – 40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature –55

†

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .

NOTE 6: All voltage values are with respect to V

SS.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage 4.5 5 5.25 V

Supply voltage 0 V

High-level input voltage

Low-level input voltage

High-level output current, all outputs –300 µA

Low-level output current 2 mA

Operating free-air temperature

CLKIN 3 V All remaining inputs 2 V MC/MP 0.6 V All remaining inputs 0.8 V

L suffix 0 70 °C A suffix – 40 85 °C

C to 150 °C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C10, TMS320C10-14, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JUL Y 1991

electrical characteristics over specified temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

High-level output voltage

Low-level output voltage IOL = MAX 0.3 0.5 V

Off-state output current

Input current

Input capacitance

o Output capacitance

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

Values derived from characterization data and not tested.

NOTE 7: This voltage specification is included for interface to HC logic. However, note that all of the other timing parameters defined in this data

sheet are specified for TTL logic levels and will differ for HC logic levels.

Data bus 25 All others 15 Data bus 25 All others 10

IOH = MAX 2.4 3 IOH = 20 µA (see Note 7) VCC– 0.4

VCC = MAX

VCC = VSS to V

f = 1 MHz, all other pins 0 V

VO = 2.4 V 20 VO = 0.4 V –20 All inputs except CLKIN ±20

CLKIN ±50

†

MAX UNIT

‡

‡ ‡ ‡ ‡

µA

INTERNAL CLOCK OPTION

X1 X2/CLKIN

Crystal

C1 C2

Figure 1. Internal Clock Option

PARAMETER MEASUREMENT INFORMATION

2.15 V

RL = 825 Ω

From Output

Under Test

Figure 2. Test Load Circuit

Test Point

CL = 100 pF

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C10, TMS320C10-25 DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987– REVISED JULY 1991

electrical characteristics over specified temperature range (unless otherwise noted)

PARAMETER

‡

Supply current

†

All typical values are at TA = 70°C and are used for thermal resistance calculations.

‡

ICC characteristics are inversely proportional to temperature. For ICC dependence on temperature, frequency, and loading.

TMS320C10 f = 20.5 MHz, VCC = 5.5 V, TA = – 40°C to 85°C 33 55 TMS320C10-25 f = 25.6 MHz, VCC = 5.5 V TA = – 0°C to 70°C 40 65

CLOCK CHARACTERISTICS AND TIMING

The ′C10/C10-25 can use either its internal oscillator or an external frequency source for a clock.

internal clock option

The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 1). The frequency of CLKOUT is one-fourth the crystal fundamental frequency. The crystal should be fundamental mode, and parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW , and should be specified at a load capacitance of 20 pF.

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

Crystal frequency, f

C1, C2 TA = – 40°C to 85°C 10 pF

TMS320C10 TA = – 40°C to 85°C 6.7 20.5 TMS320C10-25 TA = 0°C to 70°C 6.7 25.6

TEST CONDITIONS

(SEE FIGURE 2)

MIN TYP†MAX UNIT

MHz

external clock option

An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left unconnected. The external frequency injected must conform to the specifications listed in the table below.

switching characteristics over recommended operating conditions

PARAMETER UNITTEST CONDITIONS

c(C)

r(C)

f(C)

w(CL)

w(CH)

d(MCC)

c(C)

Values derived from characterization data and not tested.

CLKOUT cycle time CLKOUT rise time 10 CLKOUT fall time 8 Pulse duration, CLKOUT low 92 Pulse duration, CLKOUT high 90 Delay time, CLKIN↑ to CLKOUT↓ 25

is the cycle time of CLKOUT, i.e., 4t

RL = 825 Ω, CL = 100 pF

(see Figure 2)

(4 times CLKIN cycle time if an external oscillator is used).

c(MC)

MIN NOM MAX MIN NOM MAX

TMS320C10 TMS320C10-25

195.12 200 156.25 160 ns ¶

¶ ¶ ¶

25 50

72 70

¶ ¶

timing requirements over recommended operating conditions

TMS320C10 TMS320C10-25

MIN NOM MAX MIN NOM MAX

c(MC)

r(MC)

f(MC)

w(MCP)

w(MCL)

w(MCH)

Values derived from characterization data and not tested.

Master clock cycle time 48.78 50 150 39.06 40 150 Rise time, master clock input 5 Fall time, master clock input 5 Pulse duration, master clock 0.4t Pulse duration, master clock low 20 Pulse duration, master clock high 20

c(MC)

¶ ¶

0.6t

¶ ¶

10 10

c(MC)

¶ ¶

0.45t

c(MC)

0.55t ¶

10 10

c(MC)

ns ns ns ns

UNIT

ns ns ns

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JUL Y 1991

MEMORY AND PERIPHERAL INTERFACE TIMING

switching characteristics over recommended operating conditions

PARAMETER

d10

h(A-WMD)

su(A-MD)

†

Values derived from characterization data and not tested.

NOTE 8: For interfacing I/O devices, see Figure 3.

Delay time, CLKOUT↓ to address bus valid

Delay time, CLKOUT↓ to MEN

↓

Delay time, CLKOUT↓ to MEN

↑

Delay time, CLKOUT↓ to DEN

↓

Delay time, CLKOUT↓ to DEN

↑

Delay time, CLKOUT↓ to WE↓ 1/2t Delay time, CLKOUT↓ to WE↑ –10 Delay time, CLKOUT↓ to data

bus OUT valid Time after CLKOUT↓ that data

bus starts to be driven Time after CLKOUT↓that data

bus stops being driven Data bus OUT valid after

CLKOUT↓ Address hold time after WE↑,

MEN

↑, or DEN↑ (see Note 8)

Address bus setup time prior to MEN

↓ or DEN↓

CONDITIONS

RL = 825 Ω

CL = 100 pF,

(see Figure 2)

TEST

1/4t

TMS320C10 TMS320C10-25

MIN TYP MAX MIN TYP MAX

†

–5†1/4t

c(C)

†

–10

†1

–5

c(C)

†

–10

–5†1/2t

c(C)

†

–5

c(C)

–10 1/4t

c(C)

†

–10

–45 1/4t

c(C)

1/4t

/4t

c(C)

50 10

+15 1/4t

c(C)

15 –10

+15 1/4t

c(C)

15 –10

+ 15 1/2t

c(C)

15 –10

+ 65 1/4t

c(C)

+ 40

TMS320C10, TMS320C10-25

UNIT

†

–5†1/4t

c(C)

†

–5†1/4t

c(C)

†

–5

c(C)

†

1/4t

†

–10

†

–5

c(C)

–10 ns

c(C)

†

–35 ns

c(C)

1/2t

1/4t

40 ns

c(C)

12 ns

c(C)

12 ns

c(C)

12 ns

+ 52

c(C)

+ 40

c(C)

+ 12 ns

†

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C10, TMS320C10-25 DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987– REVISED JULY 1991

timing requirements over recommended operating conditions

TEST CONDITION

NOTE 9: Data may be removed from the data bus upon MEN↑ or DEN↑ preceding CLKOUT↓.

Setup time, data bus valid prior to CLKOUT↓ 50 40 ns

su(D)

Hold time, data bus held valid after CLKOUT↓

h(D)

(see Note 9)

RL = 825 Ω, CL = 100 pF

(see Figure 2)

SUGGESTED I/O DECODE CIRCUIT

The circuit shown in Figure 3 is a design example for interfacing I/O devices to the ′C10/C10-25. This circuit decodes the address for output operations using the OUT instruction. The same circuit can be used to decode input and output operations if the inverter (’ALS04) is replaced with a NAND gate and both DEN and WE are connected. Inputs and outputs can be decoded at the same port provided the output of the decoder (’AS137) is gated with the appropriate signal (DEN be increased when the circuit shown in Figure 3 is repeated to support IN instructions with DEN connected rather than WE.

The table write (TBL W) function requires a dif ferent circuit. A detailed discussion of an example circuit for this function is described in the application report, “Interfacing External Memory to the TMS32010”, published in the book,

Digital Signal Processing Applications with the TMS320 Famil

or WE) to select read or write (using an ’ALS32). Access times can

TMS320C10 TMS320C10-25

MIN NOM MAX MIN NOM MAX

0 0 ns

y (SPRA012A).

UNIT

TMS320C10 74AS137

PA0

PA1

PA2

74ALS04

Figure 3. I/O Decode Circuit

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

15 14 13 12 11 10 9 7

I/O Device

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C10, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JUL Y 1991

RESET (RS) TIMING

switching characteristics over recommended operating conditions

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

d11

dis(R)

†

Values derived from characterization data and not tested.

Delay time, DEN↑, WE↑, and MEN↑ from RS 1/2t Data bus disable time after RS

timing requirements over recommended operating conditions

PARAMETER

su(R)

w(R)

NOTE 10: RS can occur anytime during a clock cycle. Time given is minimum to ensure synchronous operation.

Reset (RS) setup time prior to CLKOUT (see Note 10) 50 40 ns RS pulse duration 5t

INTERRUPT (INT) TIMING

RL 825 Ω,

CL = 100 pF,

(see Figure 2)

TMS320C10 TMS320C10-25

MIN NOM MAX MIN NOM MAX

c(C)

1/4t

+50† ns

c(C)

+50

c(C)

†

UNIT

timing requirements over recommended operating conditions

TMS320C10 TMS320C10-25

MIN NOM MAX MIN NOM MAX

f(INT)

w(INT)

su(INT)

Fall time, INT 15 15 ns Pulse duration, INT t Setup time, INT↓ before CLKOUT↓ 50 40 ns

c(C)

IO (BIO) TIMING

timing requirements over recommended operating conditions

TMS320C10 TMS320C10-25

MIN NOM MAX MIN NOM MAX

f(IO)

w(IO)

su(IO)

Fall time, BIO 15 15 ns Pulse duration, BIO t Setup time, BIO↓ before CLKOUT↓ 50 40 ns

c(C)

UNIT

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C10-14 DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987– REVISED JULY 1991

electrical characteristics over specified temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

‡

Supply current

†

All typical values are at TA = 70°C and are used for thermal resistance calculations.

‡

ICC characteristics are inversely proportional to temperature; i.e., ICC decreases approximately linearly with temperature.

f = 14.4, MHz, VCC = 5.5 V, TA = 0°C to 70°C 28 65 mA

CLOCK CHARACTERISTICS AND TIMING

The TMS320C10-14 can use either its internal oscillator or an external frequency source for a clock.

internal clock option

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

Crystal frequency, f C1, C2 TA = 0°C to 70°C 10 pF

TA = 0°C to 70°C 6.7 14.4 MHz

†

MAX UNIT

external clock option

switching characteristics over recommended operating conditions

TEST CONDITIONS MIN NOM MAX UNIT

c(C)

r(C)

f(C)

w(CL)

w(CH)

d(MCC)

§t

c(C)

Values derived from characterization data and not tested.

CLKOUT cycle time CLKOUT rise time 10 ns CLKOUT fall time 8 ns Pulse duration, CLKOUT low 131 ns

Pulse duration, CLKOUT high 129 ns Delay time, CLKIN↑ to CLKOUT↓ 25

is the cycle time of CLKOUT, i.e., 4t

RL = 825 Ω,

CL = 100 pF,

(see Figure 2)

(4 times CLKIN cycle time if an external oscillator is used).

c(MC)

277.78 ns

timing requirements over recommended operating conditions

MIN NOM MAX UNIT

c(MC)

r(MC)

f(MC)

w(MCP)

w(MCL)

w(MCH)

Values derived from characterization data and not tested.

Master clock cycle time 69.5 150 ns Rise time, master clock input 5 Fall time, master clock input 5 Pulse duration, master clock 0.4t Pulse duration, master clock low, t Pulse duration, master clock high, t

= 50 ns 20

c(MC)

= 50 ns 20

c(MC)

0.6t

c(MC)

¶ ¶

ns ns ns

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JUL Y 1991

MEMORY AND PERIPHERAL INTERFACE TIMING

switching characteristics over recommended operating conditions

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

d10

h(A-WMD)

su(A-MD)

†

Values derived from characterization data and not tested.

NOTE 8: For interfacing I/O devices, see Figure 3.

Delay time, CLKOUT↓ to address bus valid 10 Delay time, CLKOUT↓ to MEN↓ 1/4t Delay time, CLKOUT↓ to MEN↑ –10 Delay time, CLKOUT↓ to DEN↓ 1/4t Delay time, CLKOUT↓ to DEN↑ –10 Delay time, CLKOUT↓ to WE↓ 1/2t Delay time, CLKOUT↓ to WE↑ –10 Delay time, CLKOUT↓ to data bus OUT valid 1/4t Time after CLKOUT↓ that data bus starts to be driven 1/4t Time after CLKOUT↓that data bus stops being driven 1/4t Data bus OUT valid after CLKOUT↓ 1/4t Address hold time after WE↑, MEN↑, or DEN↑

(see Note 8) Address bus setup time prior to MEN↓ or DEN↓ 1/4t

RL = 825 Ω,

CL = 100 pF

(see Figure 2)

TMS320C10-14

†

– 5

c(C)

†

†1

– 5

c(C)

†

– 5

c(C)

†

– 5

c(C)

– 10 ns

c(C)

†

–10

– 45 ns

c(C)

1/4t

/4t

1/2t

c(C)

50 ns

15 ns

+15 ns

+ 65 ns

+ 40†ns

timing requirements over recommended operating conditions

TEST CONDITIONS MIN NOM MAX UNIT

su(D)

h(D)

NOTE 9: Data may be removed from the data bus upon MEN↑ or DEN↑ preceding CLKOUT↓.

Setup time, data bus valid prior to CLKOUT↓ 50 ns Hold time, data bus held valid after CLKOUT↓ (see Note 9) 0 ns

RL = 825 Ω, CL = 100 pF

(see Figure 2)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C10-14 DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987– REVISED JULY 1991

RESET (RS) TIMING

switching characteristics over recommended operating conditions

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

d11

dis(R)

†

Values were derived from characterization data and not tested.

Delay time, DEN↑, WE↑, and MEN↑ from RS 1/2t Data bus disable time after RS

timing requirements over recommended operating conditions

su(R)

w(R)

NOTE 10: RS can occur anytime during a clock cycle. Time given is minimum to ensure synchronous operation.

Reset (RS) setup time prior to CLKOUT (see Note 10) 50 ns RS pulse duration 5t

INTERRUPT (INT) TIMING

timing requirements over recommended operating conditions

f(INT)

w(INT)

su(INT)

Fall time, INT 15 ns Pulse duration, INT t Setup time, INT↓ before CLKOUT↓ 50 ns

RL = 825 Ω,

CL = 100 pF

(see Figure 2)

MIN NOM MAX UNIT

c(C)

MIN NOM MAX UNIT

c(C)

1/4t

c(C) c(C)

+ 50 + 50

†

IO (BIO) TIMING

timing requirements over recommended operating conditions

f(IO)

w(IO)

su(IO)

Fall time, BIO 15 ns Pulse duration, BIO t Setup time, BIO↓ before CLKOUT↓ 50 ns

MIN NOM MAX UNIT

c(C)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C10, TMS320C10-14, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JUL Y 1991

TIMING DIAGRAMS

Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2 volts, unless otherwise noted.

clock timing

†

d(MCC)

and t

X2/CLKIN

CLKOUT

w(MCP)

r(MC)

c(MC)

w(MCL)

f(MC)

d(MCC)

f(C)

†

w(CL)

are referenced to an intermediate level of 1.5 V on the CLKIN waveform.

w(MCH)

c(C)

w(MCP)

r(C)

†

w(CH)

memory read timing

CLKOUT

MEN

A11-A0

D15-D0

c(C)

su(A-MD)

Address Bus Valid

su(D)

Instruction Valid

h(A-WMD)

h(D)

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TMS320C10, TMS320C10-14, TMS320C10-25 DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987– REVISED JULY 1991

TBLR instruction timing

CLKOUT

MEN

A11-A0

D15-D0

Legend:

1. TBLR Instruction Prefetch 7. Address Bus V alid

2. Dummy Prefetch 8. Address Bus Valid

3. Data Fetch 9. Instruction Valid

4. Next Instruction Prefetch 10. Instruction Valid

5. Address Bus Valid 11. Data Input Valid

6. Address Bus Valid 12. Instruction Valid

12 3 4

5678

9101112

su(D)

h(D)

TBLW instruction timing

CLKOUT

MEN

A11-A0

D15-D0

Legend:

1. TBLW Instruction Prefetch 7. Address Bus Valid

2. Dummy Prefetch 8. Instruction Valid

3. Next Instruction Prefetch 9. Instruction Valid

4. Address Bus Valid 10. Data Output Valid

5. Address Bus Valid 11. Instruction Valid

6. Address Bus Valid

12 3

4567

891011

d10

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

IN instruction timing

CLKOUT

TMS320C10, TMS320C10-14, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JUL Y 1991

MEN

A11-A0

DEN

D15-D0

Legend:

1. IN Instruction Prefetch 5. Address Bus Valid

2. Next Instruction Prefetch 6. Instruction Valid

3. Address Bus Valid 7. Data Input Valid

4. Peripheral Address Valid 8. Instruction Valid

345

678

OUT instruction timing

CLKOUT

MEN

su(A-MD)

su(D)

h(D)

A11-A0

D15-D0

Legend:

1. OUT Instruction Prefetch 5. Address Bus Valid

2. Next Instruction Prefetch 6. Instruction Valid

3. Address Bus Valid 7. Data Output Valid

4. Peripheral Address Valid 8. Instruction Valid

34 5

678

d10

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TMS320C10, TMS320C10-14, TMS320C10-25 DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987– REVISED JULY 1991

reset timing

CLKOUT

su(R)

w(R)

DEN

MEN

D15-D0

MEN

(see Note E)

dis(R)

Data

Out

d11

Data Shown Relative to WE

su(R)

Data In From

PC ADDR 0

Data In From

PC ADDR PC+1

AB = Address Bus

Address

Bus

NOTES: A. RS forces DEN, WE, and MEN high and places data bus D0 through D15 in a high-impedance state. AB outputs (and program count-

er) are synchronously cleared to zero after the next complete CLK cycle from RS

B. RS

must be maintained for a minimum of five clock cycles. C. Resumption of normal program will commence after one complete CLK cycle from RS D. Due to the synchronization action on RS

cycle.

E. Diagram shown is for definition purpose only . DEN

F. During a write cycle, RS

AB = PC AB = PC+1

, time to execute the function can vary dependent upon when RS↑ or RS↓ occur in the CLK

, WE, and MEN are mutually exclusive.

may produce an invalid write address.

AB = PC = 0

↓.

↑.

AB = PC+1

interrupt timing

CLKOUT

su(INT)

INT

f(INT)

w(INT)

BIO timing

CLKOUT

BIO

su(IO)

f(IO)

w(IO)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C10, TMS320C10-14, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JUL Y 1991

TYPICAL POWER VS. FREQUENCY GRAPHS

- Supply Current - mAI CC

1.2 4 8 12 16 20 24 28

VCC = 5.5 V

VCC = 5.0 V

VCC = 4.5 V

fx - Crystal Frequency - MHz

(a) – 40°C to 85°C Temperature Range

TA = – 40°C

TA = 85°C

TA = – 40°C

TA = 85°C

TA = – 40°C TA = 85°C

With Load

- Supply Current - mA CC

1.2 4 8 12 16 20 24 28

(b) Voltage = 5 V; Temperature = 25°C

Without Load

fx - Crystal Frequency - MHz

Figure 4. Typical CMOS ICC vs Frequency

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C14, TMS320E14, TMS320P14 DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987– REVISED JULY 1991

Key Features: TMS320C14/E14/P14

• 160-ns Instruction Cycle

• 256 Words of On-Chip Data RAM

• 4K Words of On-Chip Program ROM

(TMS320C14)

• 4K Words of On-Chip Program EPROM

(TMS320E14/P14)

• One-Time Programmable (OTP) Windowless

EPROM Version Available (′320P14)

• EPROM Code Protection for Copyright Security

• External Memory Expansion up to 4K-Words

at Full Speed (Microprocessor Mode)

• 16 × 16-Bit Multipler With 32-Bit Product

• 0 to 16-Bit Barrel Shifter

• Seven Input and Seven Output External Ports

• Bit Selectable I/O Port (16 Pins)

• 16-Bit Bidirectional Data Bus With Greater than

50-Mbps Transfer Rate

• Asynchronous Serial Port

• 15 Internal/External Interrupts

• Event Manager With Capture Inputs and

Compare Outputs

• Four Independent Timers [Watchdog,

General Purpose (2), Serial Port]

• Four-Level Hardware Stack

• Packaging: 68-Pin PLCC (FN Suffix)

or CLCC (FZ Suffix)

• Single 5-V Supply

• Operating Free-Air Temperature

...0°C to 70°C

Interrupt

TCLK/CLKR

TCLK2/CLKX

REN

INT

CLKOUT

/MC/MP

NMI

WDT

CLKIN

+5 V GND

256-Word RAM

8K-Word ROM/

EPROM

32-Bit ALU/ACC

Multiplier

Shifters

TMS320C14, TMS320E14/P14

FN/FZ Packages

(Top View)

CC2VSS2

CMP3

CAP0

CMP0

CMP1

A10

A11

9876543216867666564636261 10 11

14 15 16 17 18 19

21 22 23 24

27 28 2930 31 32 33 34 35 3637 38 39 40 41 42 43

IOP15

IOP14

IOP13

IOP12

CC1

CMP2

D15

SS1

D14

CAP1

IOP11

Address (12)

CMP5/CAP3/FSX

AMP4/CAP2/FSR

D13

D12

IOP9

IOP10

IOP8

Data (16)

IOP0

IOP1

IOP2

IOP3

IOP4

IOP5

RXD/DATA

TXD/CLK

D10

IOP6

IOP7

D11

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C14, TMS320E14, TMS320P14

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JUL Y 1991

introduction

The ′C14/E14/P14 are 16/32-bit single-chip digital signal processing (DSP) microcontrollers that combine the high performance of a DSP with on-chip peripherals. With a 160-ns instruction cycle, these devices are capable of executing up to 6.4 million instructions per second (MIPS). The ′C14/E14/P14 DSPs are ideal for applications such as automotive control systems, computer peripherals, industrial controls, and military command/control system applications.

Control-specific on-chip peripherals include: An event manager with 6 channel PWM D/A/, 6-bit I/O pins, an asynchronous serial port, four 16-bit timers, and internal/external interrupts.

With 4K-words of on-chip ROM, the ′C14 is a mask programmable device. Code is provided by the customer, and TI incorporates the customer’s code into the photomask. It is offered in a 68-pin plastic chip carrier package (FN suffix), rated for operation from 0°C to 70°C.

The ′E14 is provided with a 4K-word on-chip EPROM. This EPROM version is excellent for prototyping and for customized applications. It is programmable with standard EPROM programmers. It is offered in a 68-pin (windowed) cerquad package (FZ suffix), rated for operation from 0°C to 70°C.

The ′P14 features a one-time programmable 4K-word on-chip EPROM. The ′P14 is provided in an unprogrammed state and is programmed as if it were a blank ′E14. It is offered in a low-cost, volume-production-oriented, 68-pin plastic leaded chip carrier (PLCC) package (FN suffix), rated for operation from 0°C to 70°C.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C14, TMS320E14, TMS320P14 DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987– REVISED JULY 1991

Each device can execute programs form either internal (MC/MP=0) or external program memory (MC/MP=1). For proprietary code security, the ′E14 and ′P14 incorporate an EPROM protect bit (RBIT). If this bit is

programmed, the device’s internal program memory cannot be accessed by any external means.

TERMINAL FUNCTIONS

PIN DESCRIPTION

NAME NO.

A11 A10 A9 A8 A7 A6 A5 A4 A3 A2/PA2 A1/PA1 A0/PA0

D15 MSB D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB

INT 18 I External interrupt input. The interrupt signal is generated by a high-to-low transition on this pin. NMI/MC/MP 22 I Non-maskable interrupt. When this pin is brought low, the device is interrupted irrespective of the

5 6

9 12 13 14 20 21 25 26 27 28

35 36 39 40 43 46 49 50 57 58 59 60 61 62 63 64

†

I/O/Z

O/Z Program memory address bus A11 (MSB) through A0 (LSB) and port addresses P A2 (MSB) through

I/O/Z Parallel data bus D15 (MSB) through D0 (LSB). The data bus is always in the high-impedance state

PA0 (LSB). Addresses A11 through A0 are always active and never go to high impedance except during reset. During execution of the IN and OUT instructions, pins 26, 27, and 28 carry the port addresses. Pins A3 through A11 are held high when port accesses are made on pins PA0 through PA2.

except when WE

state of the INTM bit in status register ST.

is active (low). The data bus is also active when internal peripherals are written to.

INTERRUPT AND MISCELLANEOUS SIGNALS

ADDRESS/DATA BUSES

Microcomputer/microprocessor select. This pin is also sampled when RS

internal program memory is selected. If low during reset, external memory will be selected. WE 15 O Write enable. When active low, WE indicates that device will output data on the bus. REN 16 O Read enable. When active low, REN indicates that device will accept data from the bus. RS 17 I Reset. When this pin is low, the device is reset and PC is set to zero.

Continued next page. †

Input/Output/High-impedance state.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

is low. If high during reset,

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