Texas instruments SM320F28335-HT Data Manual

SM320F28335-HT

Digital Signal Controller (DSC)

Data Manual

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Literature Number: SPRS682

December 2010

SM320F28335-HT

SPRS682–DECEMBER 2010

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Contents

1 SM320F28335 DSC ............................................................................................................. 10

1.1 Features .................................................................................................................... 10

1.2 SUPPORTS EXTREME TEMPERATURE APPLICATIONS ......................................................... 11

2 Introduction ...................................................................................................................... 12

2.1 Pin Assignments ........................................................................................................... 13

2.2 Signal Descriptions ........................................................................................................ 18

3 Functional Overview .......................................................................................................... 26

3.1 Memory Maps .............................................................................................................. 27

3.2 Brief Descriptions .......................................................................................................... 31

3.2.1 C28x CPU ....................................................................................................... 31

3.2.2 Memory Bus (Harvard Bus Architecture) .................................................................... 31

3.2.3 Peripheral Bus .................................................................................................. 31

3.2.4 Real-Time JTAG and Analysis ................................................................................ 32

3.2.5 External Interface (XINTF) .................................................................................... 32

3.2.6 Flash ............................................................................................................. 32

3.2.7 M0, M1 SARAMs ............................................................................................... 32

3.2.8 L0, L1, L2, L3, L4, L5, L6, L7 SARAMs ..................................................................... 32

3.2.9 Boot ROM ....................................................................................................... 33

3.2.10 Security .......................................................................................................... 33

3.2.11 Peripheral Interrupt Expansion (PIE) Block ................................................................. 34

3.2.12 External Interrupts (XINT1-XINT7, XNMI) ................................................................... 35

3.2.13 Oscillator and PLL .............................................................................................. 35

3.2.14 Watchdog ........................................................................................................ 35

3.2.15 Peripheral Clocking ............................................................................................. 35

3.2.16 Low-Power Modes .............................................................................................. 35

3.2.17 Peripheral Frames 0, 1, 2, 3 (PFn) ........................................................................... 36

3.2.18 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 36

3.2.19 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 36

3.2.20 Control Peripherals ............................................................................................. 37

3.2.21 Serial Port Peripherals ......................................................................................... 37

3.3 Register Map ............................................................................................................... 38

3.4 Device Emulation Registers .............................................................................................. 39

3.5 Interrupts .................................................................................................................... 40

3.5.1 External Interrupts .............................................................................................. 44

3.6 System Control ............................................................................................................ 44

3.6.1 OSC and PLL Block ............................................................................................ 46

3.6.1.1 External Reference Oscillator Clock Option .................................................... 47

3.6.1.2 PLL-Based Clock Module ......................................................................... 47

3.6.1.3 Loss of Input Clock ................................................................................ 49

3.6.2 Watchdog Block ................................................................................................. 49

3.7 Low-Power Modes Block ................................................................................................. 50

4 Peripherals ....................................................................................................................... 51

4.1 DMA Overview ............................................................................................................. 51

4.2 32-Bit CPU-Timers 0/1/2 ................................................................................................. 53

4.3 Enhanced PWM Modules (ePWM1/2/3/4/5/6) ......................................................................... 55

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4.4 High-Resolution PWM (HRPWM) ....................................................................................... 59

4.5 Enhanced CAP Modules (eCAP1/2/3/4/5/6) ........................................................................... 59

4.6 Enhanced QEP Modules (eQEP1/2) .................................................................................... 62

4.7 Analog-to-Digital Converter (ADC) Module ............................................................................ 64

4.7.1 ADC Connections if the ADC Is Not Used .................................................................. 67

4.7.2 ADC Registers .................................................................................................. 67

4.7.3 ADC Calibration ................................................................................................. 68

4.8 Multichannel Buffered Serial Port (McBSP) Module .................................................................. 69

4.9 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B) .................................... 72

4.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C) .......................................... 77

4.11 Serial Peripheral Interface (SPI) Module (SPI-A) ..................................................................... 80

4.12 Inter-Integrated Circuit (I2C) ............................................................................................. 83

4.13 GPIO MUX ................................................................................................................. 84

4.14 External Interface (XINTF) ............................................................................................... 91

SPRS682–DECEMBER 2010

5 Device Support ................................................................................................................. 93

6 Electrical Specifications ..................................................................................................... 93

6.1 Absolute Maximum Ratings .............................................................................................. 93

6.2 Recommended Operating Conditions .................................................................................. 95

6.3 Electrical Characteristics ................................................................................................. 95

6.4 Current Consumption ..................................................................................................... 96

6.4.1 Reducing Current Consumption .............................................................................. 98

6.4.2 Current Consumption Graphs ................................................................................. 99

6.4.3 Thermal Design Considerations ............................................................................. 100

6.5 Emulator Connection Without Signal Buffering for the DSP ....................................................... 100

6.6 Timing Parameter Symbology .......................................................................................... 102

6.6.1 General Notes on Timing Parameters ...................................................................... 102

6.6.2 Test Load Circuit .............................................................................................. 102

6.6.3 Device Clock Table ........................................................................................... 102

6.7 Clock Requirements and Characteristics ............................................................................. 104

6.8 Power Sequencing ....................................................................................................... 105

6.8.1 Power Management and Supervisory Circuit Solutions .................................................. 105

6.9 General-Purpose Input/Output (GPIO) ................................................................................ 108

6.9.1 GPIO - Output Timing ........................................................................................ 108

6.9.2 GPIO - Input Timing .......................................................................................... 109

6.9.3 Sampling Window Width for Input Signals ................................................................. 110

6.9.4 Low-Power Mode Wakeup Timing .......................................................................... 111

6.10 Enhanced Control Peripherals ......................................................................................... 115

6.10.1 Enhanced Pulse Width Modulator (ePWM) Timing ....................................................... 115

6.10.2 Trip-Zone Input Timing ....................................................................................... 115

6.11 External Interrupt Timing ................................................................................................ 117

6.12 I2C Electrical Specification and Timing ............................................................................... 118

6.13 Serial Peripheral Interface (SPI) Timing .............................................................................. 118

6.13.1 Master Mode Timing .......................................................................................... 118

6.13.2 SPI Slave Mode Timing ...................................................................................... 122

6.14 External Interface (XINTF) Timing ..................................................................................... 125

6.14.1 USEREADY = 0 ............................................................................................... 125

6.14.2 Synchronous Mode (USEREADY = 1, READYMODE = 0) ............................................. 126

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SPRS682–DECEMBER 2010

6.14.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1) ............................................ 126

6.14.4 XINTF Signal Alignment to XCLKOUT ..................................................................... 128

6.14.5 External Interface Read Timing ............................................................................. 129

6.14.6 External Interface Write Timing ............................................................................. 130

6.14.7 External Interface Ready-on-Read Timing With One External Wait State ............................ 132

6.14.8 External Interface Ready-on-Write Timing With One External Wait State ............................. 135

6.14.9 XHOLD and XHOLDA Timing ............................................................................... 138

6.15 On-Chip Analog-to-Digital Converter .................................................................................. 141

6.15.1 ADC Power-Up Control Bit Timing .......................................................................... 142

6.15.2 Definitions ...................................................................................................... 143

6.15.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0) ............................................ 144

6.15.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) .......................................... 145

6.15.5 Detailed Descriptions ......................................................................................... 146

6.16 Multichannel Buffered Serial Port (McBSP) Timing ................................................................. 147

6.16.1 McBSP Transmit and Receive Timing ...................................................................... 147

6.16.2 McBSP as SPI Master or Slave Timing .................................................................... 149

6.17 Flash Timing .............................................................................................................. 153

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7 Thermal/Mechanical Data .................................................................................................. 155

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SPRS682–DECEMBER 2010

List of Figures

2-1 181-Pin GB........................................................................................................................ 13

3-1 Functional Block Diagram ...................................................................................................... 26

3-2 Memory Map ...................................................................................................................... 28

3-3 External and PIE Interrupt Sources............................................................................................ 41

3-4 External Interrupts................................................................................................................ 41

3-5 Multiplexing of Interrupts Using the PIE Block ............................................................................... 42

3-6 Clock and Reset Domains ...................................................................................................... 45

3-7 OSC and PLL Block Diagram................................................................................................... 46

3-8 Using a 3.3-V External Oscillator............................................................................................... 47

3-9 Using a 1.9-V External Oscillator............................................................................................... 47

3-10 Using the Internal Oscillator .................................................................................................... 47

3-11 Watchdog Module................................................................................................................ 49

4-1 DMA Functional Block Diagram ................................................................................................ 52

4-2 CPU-Timers....................................................................................................................... 53

4-3 CPU-Timer Interrupt Signals and Output Signal ............................................................................. 53

4-4 Multiple PWM Modules .......................................................................................................... 55

4-5 ePWM Submodules Showing Critical Internal Signal Interconnections................................................... 58

4-6 eCAP Functional Block Diagram ............................................................................................... 61

4-7 eQEP Functional Block Diagram............................................................................................... 62

4-8 Block Diagram of the ADC Module ............................................................................................ 65

4-9 ADC Pin Connections With Internal Reference .............................................................................. 66

4-10 ADC Pin Connections With External Reference ............................................................................. 67

4-11 McBSP Module .................................................................................................................. 70

4-12 eCAN Block Diagram and Interface Circuit ................................................................................... 73

4-13 eCAN-A Memory Map ........................................................................................................... 74

4-14 eCAN-B Memory Map ........................................................................................................... 75

4-15 Serial Communications Interface (SCI) Module Block Diagram............................................................ 79

4-16 SPI Module Block Diagram (Slave Mode) .................................................................................... 82

4-17 I2C Peripheral Module Interfaces .............................................................................................. 83

4-18 GPIO MUX Block Diagram...................................................................................................... 85

4-19 Qualification Using Sampling Window......................................................................................... 90

4-20 External Interface Block Diagram .............................................................................................. 91

4-21 Typical 16-bit Data Bus XINTF Connections ................................................................................. 92

4-22 Typical 32-bit Data Bus XINTF Connections ................................................................................. 92

6-1 SM320F28335 Operating Life Derating Chart................................................................................ 94

6-2 Typical Operational Current Versus Frequency for T 6-3 Typical Operational Current Versus Frequency for T

6-4 Emulator Connection Without Signal Buffering for the DSP .............................................................. 101

6-5 3.3-V Test Load Circuit......................................................................................................... 102

6-6 Clock Timing..................................................................................................................... 105

6-7 Power-on Reset................................................................................................................. 106

6-8 Warm Reset ..................................................................................................................... 107

6-9 Example of Effect of Writing Into PLLCR Register ......................................................................... 108

6-10 General-Purpose Output Timing.............................................................................................. 109

6-11 Sampling Mode ................................................................................................................. 109

6-12 General-Purpose Input Timing................................................................................................ 110

6-13 IDLE Entry and Exit Timing.................................................................................................... 111

= 25°C ........................................................... 100

= 210°C.......................................................... 100

SM320F28335-HT

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6-14 STANDBY Entry and Exit Timing Diagram.................................................................................. 112

6-15 HALT Wake-Up Using GPIOn................................................................................................. 114

6-16 PWM Hi-Z Characteristics..................................................................................................... 115

6-17 ADCSOCAO or ADCSOCBO Timing ........................................................................................ 117

6-18 External Interrupt Timing....................................................................................................... 117

6-19 SPI Master Mode External Timing (Clock Phase = 0) ..................................................................... 120

6-20 SPI Master Mode External Timing (Clock Phase = 1) ..................................................................... 122

6-21 SPI Slave Mode External Timing (Clock Phase = 0)....................................................................... 124

6-22 SPI Slave Mode External Timing (Clock Phase = 1)....................................................................... 125

6-23 Relationship Between XTIMCLK and SYSCLKOUT ....................................................................... 128

6-24 Example Read Access......................................................................................................... 130

6-25 Example Write Access......................................................................................................... 131

6-26 Example Read With Synchronous XREADY Access ...................................................................... 133

6-27 Example Read With Asynchronous XREADY Access..................................................................... 134

6-28 Write With Synchronous XREADY Access.................................................................................. 136

6-29 Write With Asynchronous XREADY Access ................................................................................ 137

6-30 External Interface Hold Waveform............................................................................................ 139

6-31 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK).................................................. 140

6-32 ADC Power-Up Control Bit Timing ........................................................................................... 142

6-33 ADC Analog Input Impedance Model ........................................................................................ 143

6-34 Sequential Sampling Mode (Single-Channel) Timing...................................................................... 144

6-35 Simultaneous Sampling Mode Timing ....................................................................................... 145

6-36 McBSP Receive Timing........................................................................................................ 149

6-37 McBSP Transmit Timing....................................................................................................... 149

6-38 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0................................................... 150

6-39 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0................................................... 151

6-40 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1................................................... 152

6-41 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1................................................... 153

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List of Tables

2-1 Hardware Features .............................................................................................................. 12

2-2 Pin Out Information .............................................................................................................. 13

2-3 Signal Descriptions............................................................................................................... 18

3-1 Addresses of Flash Sectors .................................................................................................... 29

3-2 Handling Security Code Locations............................................................................................. 29

3-3 Wait-states ........................................................................................................................ 30

3-4 Boot Mode Selection............................................................................................................. 33

3-5 Peripheral Frame 0 Registers .................................................................................................. 38

3-6 Peripheral Frame 1 Registers .................................................................................................. 38

3-7 Peripheral Frame 2 Registers .................................................................................................. 39

3-8 Peripheral Frame 3 Registers .................................................................................................. 39

3-9 Device Emulation Registers..................................................................................................... 39

3-10 PIE Peripheral Interrupts ....................................................................................................... 42

3-11 PIE Configuration and Control Registers...................................................................................... 43

3-12 External Interrupt Registers..................................................................................................... 44

3-13 PLL, Clocking, Watchdog, and Low-Power Mode Registers ............................................................... 46

3-14 PLLCR Bit Descriptions ......................................................................................................... 48

3-15 CLKIN Divide Options ........................................................................................................... 48

3-16 Possible PLL Configuration Modes ............................................................................................ 48

3-17 Low-Power Modes ............................................................................................................... 50

4-1 CPU-Timers 0, 1, 2 Configuration and Control Registers................................................................... 54

4-2 ePWM Control and Status Registers (default configuration in PF1)....................................................... 56

4-3 ePWM Control and Status Registers (remapped configuration in PF3 - DMA accessible)............................. 57

4-4 eCAP Control and Status Registers ........................................................................................... 61

4-5 eQEP Control and Status Registers ........................................................................................... 63

4-6 ADC Registers ................................................................................................................... 67

4-7 McBSP Register Summary...................................................................................................... 71

4-8 3.3-V eCAN Transceivers ...................................................................................................... 73

4-9 CAN Register Map .............................................................................................................. 76

4-10 SCI-A Registers .................................................................................................................. 78

4-11 SCI-B Registers .................................................................................................................. 78

4-12 SCI-C Registers ................................................................................................................. 78

4-13 SPI-A Registers................................................................................................................... 81

4-14 I2C-A Registers................................................................................................................... 84

4-15 GPIO Registers .................................................................................................................. 86

4-16 GPIO-A Mux Peripheral Selection Matrix .................................................................................... 87

4-17 GPIO-B Mux Peripheral Selection Matrix .................................................................................... 88

4-18 GPIO-C Mux Peripheral Selection Matrix .................................................................................... 89

4-19 XINTF Configuration and Control Register Mapping ........................................................................ 92

6-1 Current Consumption by Power Supply Pins................................................................................. 96

6-2 Typical Current Consumption by Various Peripherals (at 150 MHz) ..................................................... 98

6-3 Clocking Nomenclature for T 6-4 Clocking Nomenclature for T

6-5 Input Clock Frequency ......................................................................................................... 104

6-6 XCLKIN Timing Requirements - PLL Enabled ............................................................................. 104

6-7 XCLKIN Timing Requirements - PLL Disabled ............................................................................. 104

6-8 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ...................................................... 104

= -55°C to 125°C (150-MHz Devices) ................................................... 103

= 210°C (100-MHz Devices) .............................................................. 103

SM320F28335-HT

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6-9 Power Management and Supervisory Circuit Solutions ................................................................... 105

6-10 Reset (XRS) Timing Requirements .......................................................................................... 107

6-11 General-Purpose Output Switching Characteristics........................................................................ 108

6-12 General-Purpose Input Timing Requirements .............................................................................. 109

6-13 IDLE Mode Timing Requirements ........................................................................................... 111

6-14 IDLE Mode Switching Characteristics ....................................................................................... 111

6-15 STANDBY Mode Timing Requirements ..................................................................................... 111

6-16 STANDBY Mode Switching Characteristics ................................................................................ 112

6-17 HALT Mode Timing Requirements ........................................................................................... 113

6-18 HALT Mode Switching Characteristics ...................................................................................... 113

6-19 ePWM Timing Requirements ................................................................................................. 115

6-20 ePWM Switching Characteristics ............................................................................................ 115

6-21 Trip-Zone input Timing Requirements ....................................................................................... 115

6-22 High Resolution PWM Characteristics at SYSCLKOUT = (60 - 120 MHz).............................................. 116

6-23 Enhanced Capture (eCAP) Timing Requirement .......................................................................... 116

6-24 eCAP Switching Characteristics ............................................................................................. 116

6-25 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements .................................................. 116

6-26 eQEP Switching Characteristics ............................................................................................. 116

6-27 External ADC Start-of-Conversion Switching Characteristics............................................................. 117

6-28 External Interrupt Timing Requirements .................................................................................... 117

6-29 External Interrupt Switching Characteristics ................................................................................ 117

6-30 I2C Timing ...................................................................................................................... 118

6-31 SPI Master Mode External Timing (Clock Phase = 0) .................................................................... 119

6-32 SPI Master Mode External Timing (Clock Phase = 1) .................................................................... 121

6-33 SPI Slave Mode External Timing (Clock Phase = 0) ...................................................................... 122

6-34 SPI Slave Mode External Timing (Clock Phase = 1) ...................................................................... 124

6-35 Relationship Between Parameters Configured in XTIMING and Duration of Pulse ................................... 125

6-36 XINTF Clock Configurations................................................................................................... 128

6-37 External Interface Read Timing Requirements ............................................................................. 129

6-38 External Interface Read Switching Characteristics......................................................................... 129

6-39 External Interface Write Switching Characteristics......................................................................... 130

6-40 External Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)................................... 132

6-41 External Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... 132

6-42 Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... 132

6-43 Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)....................................... 132

6-44 External Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) ................................... 135

6-45 Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ....................................... 135

6-46 Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ...................................... 135

6-47 XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) ...................................................... 138

6-48 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) ................................................. 139

6-49 ADC Electrical Characteristics (over recommended operating conditions) ............................................ 141

6-50 ADC Power-Up Delays......................................................................................................... 142

6-51 Typical Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK) .............................. 142

6-52 Sequential Sampling Mode Timing ........................................................................................... 144

6-53 Simultaneous Sampling Mode Timing ....................................................................................... 145

6-54 McBSP Timing Requirements ................................................................................................ 147

6-55 McBSP Switching Characteristics ........................................................................................... 147

6-56 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) ................................ 149

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6-57 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)............................ 149

6-58 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) ................................ 150

6-59 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)............................ 150

6-60 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) ................................ 151

6-61 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)............................ 151

6-62 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) ................................ 152

6-63 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) ........................... 152

6-64 Flash Endurance for A and S Temperature Material ...................................................................... 153

6-65 Flash Endurance for Q Temperature Material .............................................................................. 153

6-66 Flash Parameters at 150-MHz SYSCLKOUT............................................................................... 153

6-67 Flash/OTP Access Timing..................................................................................................... 153

6-68 Minimum Required Flash/OTP Wait-States at Different Frequencies ................................................... 154

7-1 Thermal Model of 181-Pin GB ................................................................................................ 155

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Digital Signal Controller (DSC)

1 SM320F28335 DSC

1.1 Features

• High-Performance Static CMOS Technology – Up to 150 MHz for TC= -55°C to 125°C

and Up to 100 MHZ for TC= 210°C

– 1.9-V Core, 3.3-V I/O Design

• High-Performance 32-Bit CPU – IEEE-754 Single-Precision Floating-Point

Unit (FPU) ) – 16 x 16 and 32 x 32 MAC Operations – 16 x 16 Dual MAC – Harvard Bus Architecture – Fast Interrupt Response and Processing – Unified Memory Programming Model – Code-Efficient (in C/C++ and Assembly)

• Six Channel DMA Controller (for ADC, McBSP, ePWM, XINTF, and SARAM)

• 16-bit or 32-bit External Interface (XINTF) – Over 2M x 16 Address Reach

• On-Chip Memory – 256K x 16 Flash, 34K x 16 SARAM – 1K x 16 OTP ROM

• Boot ROM (8K x 16) – With Software Boot Modes (via SCI, SPI,

CAN, I2C, McBSP, XINTF, and Parallel I/O)

– Standard Math Tables

• Clock and System Control – Dynamic PLL Ratio Changes Supported – On-Chip Oscillator – Watchdog Timer Module

• GPIO0 to GPIO63 Pins Can Be Connected to One of the Eight External Core Interrupts

• Peripheral Interrupt Expansion (PIE) Block That Supports All 58 Peripheral Interrupts

• 128-Bit Security Key/Lock – Protects Flash/OTP/RAM Blocks – Prevents Firmware Reverse Engineering

• Enhanced Control Peripherals – Up to 18 PWM Outputs – Up to 6 HRPWM Outputs With 150 ps MEP Boundary Scan Architecture

Resolution – Up to 6 Event Capture Inputs – Up to 2 Quadrature Encoder Interfaces – Up to 8 32-bit/Nine 16-bit Timers

• Three 32-Bit CPU Timers

• Serial Port Peripherals – Up to 2 CAN Modules – Up to 3 SCI (UART) Modules – Up to 2 McBSP Modules (Configurable as

SPI) – One SPI Module – One Inter-Integrated-Circuit (I2C) Bus

• 12-Bit ADC, 16 Channels – 80-ns Conversion Rate – 2 x 8 Channel Input Multiplexer – Two Sample-and-Hold – Single/Simultaneous Conversions – Internal or External Reference

• Up to 88 Individually Programmable, Multiplexed GPIO Pins With Input Filtering

• JTAG Boundary Scan Support

• Advanced Emulation Features – Analysis and Breakpoint Functions – Real-Time Debug via Hardware

• Development Support Includes – ANSI C/C++ Compiler/Assembler/Linker – Code Composer Studio™ IDE – DSP/BIOS™ – Digital Motor Control and Digital Power

Software Libraries

• Low-Power Modes and Power Savings – IDLE, STANDBY, HALT Modes Supported – Disable Individual Peripheral Clocks

• Package Option – Ceramic Pin Grid Array (GB)

• Temperature Range: – –55°C to 210°C

(1) IEEE Standard 1149.1-1990 Standard Test Access Port and

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(1)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Code Composer Studio, DSP/BIOS are trademarks of Texas Instruments.

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1.2 SUPPORTS EXTREME TEMPERATURE APPLICATIONS

• Controlled Baseline

• One Assembly/Test Site

• One Fabrication Site

• Available in Extreme (–55°C/210°C) Temperature Range

• Extended Product Life Cycle

• Extended Product-Change Notification

• Product Traceability

• Texas Instruments high temperature products utilize highly optimized silicon (die) solutions with design and process enhancements to maximize performance over extended temperatures.

(2) Custom temperature ranges available

(2)

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2 Introduction

The SM320F28335 is a highly integrated, high-performance solution for demanding control applications. Throughout this document, the device is abbreviated as F28335. Table 2-1 provides a summary of

features.

Table 2-1. Hardware Features

FEATURE TYPE

Instruction cycle

Floating-point Unit – Yes

3.3-V on-chip flash (16-bit word) – 256K Single-access RAM (SARAM) (16-bit word) – 34K One-time programmable (OTP) ROM

(16-bit word) Code security for on-chip flash/SARAM/OTP blocks – Yes Boot ROM (8K X16) – Yes 16/32-bit External Interface (XINTF) 1 Yes 6-channel Direct Memory Access (DMA) 0 Yes PWM outputs 0 ePWM1/2/3/4/5/6 HRPWM channels 0 ePWM1A/2A/3A/4A/5A/6A 32-bit Capture inputs or auxiliary PWM outputs 0 6 32-bit QEP channels (four inputs/channel) 0 2 Watchdog timer – Yes

12-Bit ADC MSPS 2 12.5

32-Bit CPU timers – 3 Multichannel Buffered Serial Port (McBSP)/SPI 1 2 Serial Peripheral Interface (SPI) 0 1 Serial Communications Interface (SCI) 0 3 Enhanced Controller Area Network (eCAN) 0 2 Inter-Integrated Circuit (I2C) 0 1 General Purpose I/O pins (shared) – 88 External interrupts – 8 Packaging 181-pin GB – Yes Temperature range –55°C to 210°C – Yes

(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor

differences between devices that do not affect the basic functionality of the module.

TC= -55°C to 125°C – 6.66 ns TC= 210°C – 10 ns

No. of channels 16

Conversion time 80 ns

(1)

– 1K

F28335 (150 MHz)

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15141311 128 96 7 10

K J

542 3

G F

D C

0.100 (2,54) TYP

1.400 (35,56) TYP

Bottom View

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2.1 Pin Assignments

The 181-pin ceramic pin grid array (CPGA) terminal assignments are shown in Figure 2-1. Table 2-2 gives the pin out information and Table 2-3 describes the function(s) of each pin.

SPRS682–DECEMBER 2010

Figure 2-1. 181-Pin GB

Table 2-2. Pin Out Information

PIN FUNCTION

A1 NC

M1 ADCINA0

L1 ADCINA1 K1 ADCINA2 J1 ADCINA3 P2 ADCINA4 N2 ADCINA5

M2 ADCINA6

L2 ADCINA7 M6 ADCINB0 M7 ADCINB1

R2 ADCINB2

R3 ADCINB3

R4 ADCINB4

R5 ADCINB5

R6 ADCINB6

R7 ADCINB7

N1 ADCLO

P3 ADCREFIN

P4 ADCREFM

P5 ADCREFP

P6 ADCRESEXT

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Table 2-2. Pin Out Information (continued)

R11 EMU0 R12 EMU1

F1 GPIO0/EPWM1A G1 GPIO1/EPWM1B/ECAP6/MFSRB

E4 GPIO10/EPWM6A/CANRXB/ADCSOCBO

F4 GPIO11/EPWM6B/SCIRXDB/ECAP4 G4 GPIO12/TZ1/CANTXB/MDXB

J4 GPIO13/TZ2/CANRXB/MDRB

K4 GPIO14/TX3/XHOLD/SCITXDB/MCLKXB

L4 GPIO15/TZ4/XHOLDA/SCIRXDB/MFSXB M4 GPIO16//SPISIMOA/CANTXB/TZ5

J3 GPIO17/SPIOMIA/CANRXB/TZ6

N7 GPIO18/SPICLKA/SCITXDB/CANRXA M8 GPIO19/SPISTEA/SCIRXDB/CANTXA

H1 GPIO2/EPWM2A M9 GPIO20/EQEP1A/MDXA/CANTXB

M10 GPIO21/EQEP1B/MDRA/CANRXB M11 GPIO22/EQEP1S/MCLKXA/SCITXDB

L8 GPIO23/EQEP1I/MFSXA/SCIRXDB

M12 GPIO24/ECAP1/EQEP2A.MDXB

N8 GPIO25/ECAP2/EQEP2B/MDRB

N11 GPIO26/ECAP3/EQEP2I/MCLKXB N12 GPIO27/ECAP4/EQEP2S/MFSX

A9 GPIO28/SCIRXDA/XZCS6

C1 GPIO29/SCITXDA/XA19

E2 GPIO3/EPWM2B/ECAP5/MCLKRB

B1 GPIO30/CANRXA/XA18

A2 GPIO31/CANTXA/XA17

N13 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO

P8 GPIO33/SCLA/EPWMSYNCO/ADCSOCBO

B13 GPIO34/ECAP1/XREADY C11 GPIO35/SCITXDA/XR/1 B10 GPIO36/SCIRXDA/XZCS0

C9 GPIO37/ECAP2/XZCS7

A13 GPIO38/nXWEO

A3 GPIO39/XA16

F2 GPIO4/EPWM3A

D8 GPIO40/XA0/XWE1

D7 GPIO41/XA1

D6 GPIO42/XA2

D4 GPIO43/XA3

C8 GPIO44/XA4

C7 GPIO45/XA5

C4 GPIO46/XA6

C3 GPIO47/XA7

R14 GPIO48/ECAP5/XD31 P15 GPIO49/ECAP6/XD30

G2 GPIO5/EPWM3B/MFSRA/ECAP1

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Table 2-2. Pin Out Information (continued)

N15 GPIO50/EQEP1A/XD29 M15 GPIO51/EQEP1B/XD28

J15 GPIO52/EQEP1S/XD27 H15 GPIO53/EQEP1I/XD26 N14 GPIO54/SPISIMOA/XD25 M14 GPIO55/SPISOMIA/XD24

L14 GPIO56/SPICLKA/XD23 K14 GPIO57/SPISTEA/XD22

J14 GPIO58/MCLKRA/XD21 H12 GPIO59/MFSRA/XD20

H2 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO H11 GPIO60/MCLKRB/XD19 G12 GPIO61/MFSRB/XD18

F12 GPIO62/SCIRXDC/XD17 E12 GPIO63/SCITXDC/XD16 D12 GPIO64/XD15 G13 GPIO65/XD14 D13 GPIO66/XD13

F14 GPIO67/XD12 E14 GPIO68/XD11 D14 GPIO69/XD10

F3 GPIO7/EPWM4B/MCLKRA/ECAP2

G15 GPIO70/XD9

F15 GPIO71/XD8 E15 GPIO72/XD7 D15 GPIO73/XD6 C15 GPIO74/XD5 B15 GPIO75/XD4 D11 GPIO76/XD3 D10 GPIO77/XD2

D9 GPIO78/XD1

A14 GPIO79/XD0

G3 GPIO8/EPWM5A/CANTXB/ADCSOCAO

B8 GPIO80/XA8 B7 GPIO81/XA9 B6 GPIO82/XA10 B3 GPIO83/XA11 B2 GPIO84/XA12 A6 GPIO85/XA13 A5 GPIO86/XA14 A4 GPIO87/XA15 H3 GPIO9/EPWM5B/SCITXDB/ECAP3

R13 TCK

P9 TDI P10 TDO P14 TEST1

R8 TEST2 P12 TMS

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Table 2-2. Pin Out Information (continued)

P11 TRSTn A11 VDD B14 VDD

B4 VDD

B9 VDD

D5 VDD

E1 VDD

E3 VDD

F13 VDD

H14 VDD

H5 VDD

J12 VDD

K3 VDD

N6 VDD

M3 VDD1A18

N4 VDD2A18 R10 VDD3VFL

K2 VDDA2

M5 VDDAIO

A8 VDDIO B12 VDDIO

C6 VDDIO

D2 VDDIO G14 VDDIO K15 VDDIO

L12 VDDIO N10 VDDIO A10 VSS

A7 VSS

B11 VSS

B5 VSS C12 VSS C13 VSS C14 VSS

C2 VSS

C5 VSS

D1 VSS

D3 VSS E13 VSS

E8 VSS H13 VSS

H4 VSS K12 VSS

L13 VSS L15 VSS

L3 VSS

N5 VSS

N9 VSS

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Table 2-2. Pin Out Information (continued)

R9 VSS

N3 VSS1AGND

P7 VSS2AGND

J2 VSSA2

P1 VSSAIO K13 X1 M13 X2

J13 XCLKIN A12 XCLKOUT C10 XRD P13 XRSn A15 NC

R1 NC

R15 NC

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2.2 Signal Descriptions

Table 2-3 describes the signals. The GPIO function (shown in Italics) is the default at reset. The peripheral

signals that are listed under them are alternate functions. Some peripheral functions may not be available in all devices. See Table 2-1 for details. Inputs are not 5-V tolerant. All pins capable of producing an XINTF output function have a drive strength of 8 mA (typical). This is true even if the pin is not configured for XINTF functionality. All other pins have a drive strength of 4-mA drive typical (unless otherwise indicated). All GPIO pins are I/O/Z and have an internal pullup, which can be selectively enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on GPIO0-GPIO11 pins are not enabled at reset. The pullups on GPIO12-GPIO34 are enabled upon reset.

Table 2-3. Signal Descriptions

NAME DESCRIPTION

JTAG

JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored.

TRST

TCK JTAG test clock with internal pullup (I, ↑) TMS

TDI

TDO

EMU0

EMU1

DD3VFL

TEST1 Test Pin. Reserved for TI. Must be left unconnected. (I/O) TEST2 Test Pin. Reserved for TI. Must be left unconnected. (I/O)

XCLKOUT XINTCNF2 register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting

XCLKIN tied to GND. If a crystal/resonator is used (or if an external 1.9-V oscillator is used to feed clock to X1 pin), this pin

NOTE: TRST is an active high test pin and must be maintained low at all times during normal device operation. An external pulldown resistor is recommended on this pin. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application. (I, ↓)

JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. (I, ↑)

JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. (I, ↑)

JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)

Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode. (I/O/Z, 8 mA drive ↑) NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application.

Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode. (I/O/Z, 8 mA drive ↑) NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application.

FLASH

3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times.

CLOCK

Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or onefourth the frequency of SYSCLKOUT. This is controlled by bits 18:16 (XTIMCLK) and bit 2 (CLKMODE) in the

XINTCNF2[CLKOFF] to 1. Unlike other GPIO pins, the XCLKOUT pin is not placed in high-impedance state during a reset. (O/Z, 8 mA drive).

External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this case, the X1 pin must be must be tied to GND. (I)

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Table 2-3. Signal Descriptions (continued)

NAME DESCRIPTION

Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a ceramic resonator may be

connected across X1 and X2. The X1 pin is referenced to the 1.9-V core digital power supply. A 1.9-V external oscillator may be connected to the X1 pin. In this case, the XCLKIN pin must be connected to ground. If a 3.3-V external oscillator is used with the XCLKIN pin, X1 must be tied to GND. (I)

Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected across X1 and X2. If X2 is not used it must be left unconnected. (O)

RESET

Device Reset (in) and Watchdog Reset (out). Device reset. XRS causes the device to terminate execution. The PC will point to the address contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the location pointed to by the PC. This

XRS pin is driven low by the DSC when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the

watchdog reset duration of 512 OSCCLK cycles. (I/OD, ↑) The output buffer of this pin is an open-drain with an internal pullup. It is recommended that this pin be driven by an open-drain device.

ADC SIGNALS

ADCINA7 ADC Group A, Channel 7 input (I) ADCINA6 ADC Group A, Channel 6 input (I) ADCINA5 ADC Group A, Channel 5 input (I) ADCINA4 ADC Group A, Channel 4 input (I) ADCINA3 ADC Group A, Channel 3 input (I) ADCINA2 ADC Group A, Channel 2 input (I) ADCINA1 ADC Group A, Channel 1 input (I) ADCINA0 ADC Group A, Channel 0 input (I) ADCINB7 ADC Group B, Channel 7 input (I) ADCINB6 ADC Group B, Channel 6 input (I) ADCINB5 ADC Group B, Channel 5 input (I) ADCINB4 ADC Group B, Channel 4 input (I) ADCINB3 ADC Group B, Channel 3 input (I) ADCINB2 ADC Group B, Channel 2 input (I) ADCINB1 ADC Group B, Channel 1 input (I) ADCINB0 ADC Group B, Channel 0 input (I) ADCLO Low Reference (connect to analog ground) (I) ADCRESEXT ADC External Current Bias Resistor. Connect a 22-kΩ resistor to analog ground. ADCREFIN External reference input (I)

ADCREFP

ADCREFM

Internal Reference Positive Output. Requires a low ESR (50 mΩ - 1.5 Ω) ceramic bypass capacitor of 2.2 mF to analog ground. (O)

Internal Reference Medium Output. Requires a low ESR (50 mΩ - 1.5 Ω) ceramic bypass capacitor of 2.2 mF to analog ground. (O)

CPU AND I/O POWER PINS

DDA2

SSA2

DDAIO

SSAIO

DD1A18

SS1AGND

DD2A18

SS2AGND

DDIO

ADC Analog Power Pin ADC Analog Ground Pin ADC Analog I/O Power Pin ADC Analog I/O Ground Pin ADC Analog Power Pin ADC Analog Ground Pin ADC Analog Power Pin ADC Analog Ground Pin CPU and Logic Digital Power Pin Digital I/O Power Pin Digital Ground Pin

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Table 2-3. Signal Descriptions (continued)

NAME DESCRIPTION

GPIOA AND PERIPHERAL SIGNALS

GPIO0 General purpose input/output 0 (I/O/Z) EPWM1A Enhanced PWM1 Output A and HRPWM channel (O)

- -

- GPIO1 General purpose input/output 1 (I/O/Z)

EPWM1B Enhanced PWM1 Output B (O) ECAP6 Enhanced Capture 6 input/output (I/O) MFSRB McBSP-B receive frame synch (I/O)

GPIO2 General purpose input/output 2 (I/O/Z) EPWM2A Enhanced PWM2 Output A and HRPWM channel (O)

- -

- GPIO3 General purpose input/output 3 (I/O/Z)

EPWM2B Enhanced PWM2 Output B (O) ECAP5 Enhanced Capture 5 input/output (I/O) MCLKRB McBSP-B receive clock (I/O)

GPIO4 General purpose input/output 4 (I/O/Z) EPWM3A Enhanced PWM3 output A and HRPWM channel (O)

- -

- GPIO5 General purpose input/output 5 (I/O/Z)

EPWM3B Enhanced PWM3 output B (O) MFSRA McBSP-A receive frame synch (I/O) ECAP1 Enhanced Capture input/output 1 (I/O)

GPIO6 General purpose input/output 6 (I/O/Z) EPWM4A Enhanced PWM4 output A and HRPWM channel (O) EPWMSYNCI External ePWM sync pulse input (I) EPWMSYNCO External ePWM sync pulse output (O)

GPIO7 General purpose input/output 7 (I/O/Z) EPWM4B Enhanced PWM4 output B (O) MCLKRA McBSP-A receive clock (I/O) ECAP2 Enhanced capture input/output 2 (I/O)

GPIO8 General Purpose Input/Output 8 (I/O/Z) EPWM5A Enhanced PWM5 output A and HRPWM channel (O) CANTXB Enhanced CAN-B transmit (O) ADCSOCAO ADC start-of-conversion A (O)

GPIO9 General purpose input/output 9 (I/O/Z) EPWM5B Enhanced PWM5 output B (O) SCITXDB SCI-B transmit data(O) ECAP3 Enhanced capture input/output 3 (I/O)

GPIO10 General purpose input/output 10 (I/O/Z) EPWM6A Enhanced PWM6 output A and HRPWM channel (O) CANRXB Enhanced CAN-B receive (I) ADCSOCBO ADC start-of-conversion B (O)

GPIO11 General purpose input/output 11 (I/O/Z) EPWM6B Enhanced PWM6 output B (O) SCIRXDB SCI-B receive data (I) ECAP4 Enhanced CAP Input/Output 4 (I/O)

GPIO12 General purpose input/output 12 (I/O/Z) TZ1 Trip Zone input 1 (I) CANTXB Enhanced CAN-B transmit (O) MDXB McBSP-B transmit serial data (O)

GPIO13 General purpose input/output 13 (I/O/Z) TZ2 Trip Zone input 2 (I) CANRXB Enhanced CAN-B receive (I) MDRB McBSP-B receive serial data (I)

GPIO14 General purpose input/output 14 (I/O/Z)

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Table 2-3. Signal Descriptions (continued)

NAME DESCRIPTION

Trip Zone input 3/External Hold Request. XHOLD, when active (low), requests the external interface (XINTF) to release the external bus and place all buses and strobes into a high-impedance state. To prevent this from

TZ3/XHOLD

SCITXDB SCI-B Transmit (I) MCLKXB McBSP-B transmit clock (I/O)

GPIO15 General purpose input/output 15 (I/O/Z)

TZ4/XHOLDA output, then XHOLDA function is chosen. XHOLDA is driven active (low) when the XINTF has granted an XHOLD

SCIRXDB SCI-B receive (I) MFSXB McBSP-B transmit frame synch (I/O)

GPIO16 General purpose input/output 16 (I/O/Z) SPISIMOA SPI slave in, master out (I/O) CANTXB Enhanced CAN-B transmit (O) TZ5 Trip Zone input 5 (I)

GPIO17 General purpose input/output 17 (I/O/Z) SPISOMIA SPI-A slave out, master in (I/O) CANRXB Enhanced CAN-B receive (I) TZ6 Trip zone input 6 (I)

GPIO18 General purpose input/output 18 (I/O/Z) SPICLKA SPI-A clock input/output (I/O) SCITXDB SCI-B transmit (O) CANRXA Enhanced CAN-A receive (I)

GPIO19 General purpose input/output 19 (I/O/Z) SPISTEA SPI-A slave transmit enable input/output (I/O) SCIRXDB SCI-B receive (I) CANTXA Enhanced CAN-A transmit (O)

GPIO20 General purpose input/output 20 (I/O/Z) EQEP1A Enhanced QEP1 input A (I) MDXA McBSP-A transmit serial data (O) CANTXB Enhanced CAN-B transmit (O)

GPIO21 General purpose input/output 21 (I/O/Z) EQEP1B Enhanced QEP1 input B (I) MDRA McBSP-A receive serial data (I) CANRXB Enhanced CAN-B receive (I)

GPIO22 General purpose input/output 22 (I/O/Z) EQEP1S Enhanced QEP1 strobe (I/O) MCLKXA McBSP-A transmit clock (I/O) SCITXDB SCI-B transmit (O)

GPIO23 General purpose input/output 23 (I/O/Z) EQEP1I Enhanced QEP1 index (I/O) MFSXA McBSP-A transmit frame synch (I/O) SCIRXDB SCI-B receive (I)

GPIO24 General purpose input/output 24 (I/O/Z) ECAP1 Enhanced capture 1 (I/O) EQEP2A Enhanced QEP2 input A (I) MDXB McBSP-B transmit serial data (O)

GPIO25 General purpose input/output 25 (I/O/Z) ECAP2 Enhanced capture 2 (I/O) EQEP2B Enhanced QEP2 input B (I) MDRB McBSP-B receive serial data (I)

GPIO26 General purpose input/output 26 (I/O/Z) ECAP3 Enhanced capture 3 (I/O) EQEP2I Enhanced QEP2 index (I/O) MCLKXB McBSP-B transmit clock (I/O)

happening when TZ3 signal goes active, disable this function by writing XINTCNF2[HOLD] = 1. If this is not done, the XINTF bus will go into high impedance anytime TZ3 goes low. On the ePWM side, TZn signals are ignored by default, unless they are enabled by the code. The XINTF will release the bus when any current access is complete and there are no pending accesses on the XINTF. (I)

Trip Zone input 4/External Hold Acknowledge. The pin function for this option is based on the direction chosen in the GPADIR register. If the pin is configured as an input, then TZ4 function is chosen. If the pin is configured as an

request. All XINTF buses and strobe signals will be in a high-impedance state. XHOLDA is released when the XHOLD signal is released. External devices should only drive the external bus when XHOLDA is active (low). (I/0)

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Table 2-3. Signal Descriptions (continued)

NAME DESCRIPTION

GPIO27 General purpose input/output 27 (I/O/Z) ECAP4 Enhanced capture 4 (I/O) EQEP2S Enhanced QEP2 strobe (I/O) MFSXB McBSP-B transmit frame synch (I/O)

GPIO28 General purpose input/output 28 (I/O/Z) SCIRXDA SCI receive data (I) XZCS6 External Interface zone 6 chip select (O)

GPIO29 General purpose input/output 29. (I/O/Z) SCITXDA SCI transmit data (O) XA19 External Interface Address Line 19 (O)

GPIO30 General purpose input/output 30 (I/O/Z) CANRXA Enhanced CAN-A receive (I) XA18 External Interface Address Line 18 (O)

GPIO31 General purpose input/output 31 (I/O/Z) CANTXA Enhanced CAN-A transmit (O) XA17 External Interface Address Line 17 (O)

GPIO32 General purpose input/output 32 (I/O/Z) SDAA I2C data open-drain bidirectional port (I/OD) EPWMSYNCI Enhanced PWM external sync pulse input (I) ADCSOCAO ADC start-of-conversion A (O)

GPIO33 General-Purpose Input/Output 33 (I/O/Z) SCLA I2C clock open-drain bidirectional port (I/OD) EPWMSYNCO Enhanced PWM external synch pulse output (O) ADCSOCBO ADC start-of-conversion B (O)

GPIO34 General-Purpose Input/Output 34 (I/O/Z) ECAP1 Enhanced Capture input/output 1 (I/O) XREADY External Interface Ready signal

GPIO35 General-Purpose Input/Output 35 (I/O/Z) SCITXDA SCI-A transmit data (O) XR/W External Interface read, not write strobe

GPIO36 General-Purpose Input/Output 36 (I/O/Z) SCIRXDA SCI receive data (I) XZCS0 External Interface zone 0 chip select (O)

GPIO37 General-Purpose Input/Output 37 (I/O/Z) ECAP2 Enhanced Capture input/output 2 (I/O) XZCS7 External Interface zone 7 chip select (O)

GPIO38 General-Purpose Input/Output 38 (I/O/Z)

- XWE0 External Interface Write Enable 0 (O)

GPIO39 General-Purpose Input/Output 39 (I/O/Z)

- XA16 External Interface Address Line 16 (O)

GPIO40 General-Purpose Input/Output 40 (I/O/Z)

- XA0/XWE1 External Interface Address Line 0/External Interface Write Enable 1 (O)

GPIO41 General-Purpose Input/Output 41 (I/O/Z)

- XA1 External Interface Address Line 1 (O)

GPIO42 General-Purpose Input/Output 42 (I/O/Z)

- XA2 External Interface Address Line 2 (O)

GPIO43 General-Purpose Input/Output 43 (I/O/Z)

- XA3 External Interface Address Line 3 (O)

GPIO44 General-Purpose Input/Output 44 (I/O/Z)

- XA4 External Interface Address Line 4 (O)

GPIO45 General-Purpose Input/Output 45 (I/O/Z)

- XA5 External Interface Address Line 5 (O)

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Table 2-3. Signal Descriptions (continued)

NAME DESCRIPTION

GPIO46 General-Purpose Input/Output 46 (I/O/Z)

- XA6 External Interface Address Line 6 (O)

GPIO47 General-Purpose Input/Output 47 (I/O/Z)

- XA7 External Interface Address Line 7 (O)

GPIO48 General-Purpose Input/Output 48 (I/O/Z) ECAP5 Enhanced Capture input/output 5 (I/O) XD31 External Interface Data Line 31 (O)

GPIO49 General-Purpose Input/Output 49 (I/O/Z) ECAP6 Enhanced Capture input/output 6 (I/O) XD30 External Interface Data Line 30 (O)

GPIO50 General-Purpose Input/Output 50 (I/O/Z) EQEP1A Enhanced QEP 1input A (I) XD29 External Interface Data Line 29 (O)

GPIO51 General-Purpose Input/Output 51 (I/O/Z) EQEP1B Enhanced QEP 1input B (I) XD28 External Interface Data Line 28 (O)

GPIO52 General-Purpose Input/Output 52 (I/O/Z) EQEP1S Enhanced QEP 1Strobe (I/O) XD27 External Interface Data Line 27 (O)

GPIO53 General-Purpose Input/Output 53 (I/O/Z) EQEP1I Enhanced CAP1 lndex (I/O) XD26 External Interface Data Line 26 (O)

GPIO54 General-Purpose Input/Output 54 (I/O/Z) SPISIMOA SPI-A slave in, master out (I/O) XD25 External Interface Data Line 25 (O)

GPIO55 General-Purpose Input/Output 55 (I/O/Z) SPISOMIA SPI-A slave out, master in (I/O) XD24 External Interface Data Line 24 (O)

GPIO56 General-Purpose Input/Output 56 (I/O/Z) SPICLKA SPI-A clock (I/O) XD23 External Interface Data Line 23 (O)

GPIO57 General-Purpose Input/Output 57 (I/O/Z) SPISTEA SPI-A slave transmit enable (I/O) XD22 External Interface Data Line 22 (O)

GPIO58 General-Purpose Input/Output 58 (I/O/Z) MCLKRA McBSP-A receive clock (I/O) XD21 External Interface Data Line 21 (O)

GPIO59 General-Purpose Input/Output 59 (I/O/Z) MFSRA McBSP-A receive frame synch (I/O) XD20 External Interface Data Line 20 (O)

GPIO60 General-Purpose Input/Output 60 (I/O/Z) MCLKRB McBSP-B receive clock (I/O) XD19 External Interface Data Line 19 (O)

GPIO61 General-Purpose Input/Output 61 (I/O/Z) MFSRB McBSP-B receive frame synch (I/O) XD18 External Interface Data Line 18 (O)

GPIO62 General-Purpose Input/Output 62 (I/O/Z) SCIRXDC SCI-C receive data (I) XD17 External Interface Data Line 17 (O)

GPIO63 General-Purpose Input/Output 63 (I/O/Z) SCITXDC SCI-C transmit data (O) XD16 External Interface Data Line 16 (O)

GPIO64 General-Purpose Input/Output 64 (I/O/Z)

- XD15 External Interface Data Line 15 (O)

GPIO65 General-Purpose Input/Output 65 (I/O/Z)

- XD14 External Interface Data Line 14 (O)

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Table 2-3. Signal Descriptions (continued)

NAME DESCRIPTION

GPIO66 General-Purpose Input/Output 66 (I/O/Z)

- XD13 External Interface Data Line 13 (O)

GPIO67 General-Purpose Input/Output 67 (I/O/Z)

- XD12 External Interface Data Line 12 (O)

GPIO68 General-Purpose Input/Output 68 (I/O/Z)

- XD11 External Interface Data Line 11 (O)

GPIO69 General-Purpose Input/Output 69 (I/O/Z)

- XD10 External Interface Data Line 10 (O)

GPIO70 General-Purpose Input/Output 70 (I/O/Z)

- XD9 External Interface Data Line 9 (O)

GPIO71 General-Purpose Input/Output 71 (I/O/Z)

- XD8 External Interface Data Line 8 (O)

GPIO72 General-Purpose Input/Output 72 (I/O/Z)

- XD7 External Interface Data Line 7 (O)

GPIO73 General-Purpose Input/Output 73 (I/O/Z)

- XD6 External Interface Data Line 6 (O)

GPIO74 General-Purpose Input/Output 74 (I/O/Z)

- XD5 External Interface Data Line 5 (O)

GPIO75 General-Purpose Input/Output 75 (I/O/Z)

- XD4 External Interface Data Line 4 (O)

GPIO76 General-Purpose Input/Output 76 (I/O/Z)

- XD3 External Interface Data Line 3 (O)

GPIO77 General-Purpose Input/Output 77 (I/O/Z)

- XD2 External Interface Data Line 2 (O)

GPIO78 General-Purpose Input/Output 78 (I/O/Z)

- XD1 External Interface Data Line 1 (O)

GPIO79 General-Purpose Input/Output 79 (I/O/Z)

- XD0 External Interface Data Line 0 (O)

GPIO80 General-Purpose Input/Output 80 (I/O/Z)

- XA8 External Interface Address Line 8 (O)

GPIO81 General-Purpose Input/Output 81 (I/O/Z)

- XA9 External Interface Address Line 9 (O)

GPIO82 General-Purpose Input/Output 82 (I/O/Z)

- XA10 External Interface Address Line 10 (O)

GPIO83 General-Purpose Input/Output 83 (I/O/Z)

- XA11 External Interface Address Line 11 (O)

GPIO84

XA12

GPIO85 General-Purpose Input/Output 85 (I/O/Z)

- XA13 External Interface Address Line 13 (O)

General-Purpose Input/Output 84 (I/O/Z) External Interface Address Line 12 (O)

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(1)

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Table 2-3. Signal Descriptions (continued)

NAME DESCRIPTION

GPIO86 General-Purpose Input/Output 86 (I/O/Z)

- XA14 External Interface Address Line 14 (O)

GPIO87 General-Purpose Input/Output 87 (I/O/Z)

- XA15 External Interface Address Line 15 (O)

XRD External Interface Read Enable

SPRS682–DECEMBER 2010

(1)

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L0SARAM4Kx16 (0-Wait,DualMap)

L1SARAM4Kx16 (0-Wait,DualMap)

L2SARAM4Kx16 (0-Wait,DualMap)

L3SARAM4Kx16 (0-Wait,DualMap)

M0SARAM1Kx16

(0-Wait)

M1SARAM1Kx16

(0-Wait)

L4SARAM4Kx16

(0-WData,1-WProg)

L5SARAM4Kx16

(0-WData,1-WProg)

L6SARAM4Kx16

(0-WData,1-WProg)

L7SARAM4Kx16

(0-WData,1-WProg)

MemoryBus

BootROM

8Kx16

Code

Security

Module

DMA Bus

PSWD

OTP 1Kx16

Flash 256Kx16 8Sectors

Pump

Flash

Wrapper

TEST1

TEST2

XINTF

XA0/XWE1

XWE0

XZCS6

XZCS7

XZCS0

XR/W

XREADY

XHOLD

XHOLDA

XD31:0

XA19:1

GPIO

MUX

MemoryBus

XCLKOUT

XRD

GPIO

MUX

88GPIOs

8ExternalInterrupts

88GPIOs

12-Bit

ADC

2-S/H

A7:0

B7:0

CPUTimer0

CPUTimer1

CPUTimer2

OSC,

PLL,

LPM,

DMA 6Ch

PIE

(Interrupts)

32-bitCPU (150MHZ@1.9V) (100MHz@1.8V)

EMU1

EMU0

TRST

TDO

TMS

TDI

TCK

XRS

XCLKIN

FPU

REFIN

DMA Bus

MemoryBus

FIFO

(16Levels)

SCI-A/B/C

FIFO

(16Levels)

SPI-A

FIFO

(16Levels)

I2C

16-bitperipheralbus

SPISOMIx

SPISIMOx

SPICLKx

SPISTEx

SCIRXDx

SCITXDx

SDAx

SCLx

McBSP-A/B

MRXx

MDXx

MCLKXx

MCLKRx

MFSXx

MFSRx

32-bitperipheralbus

(DMA accessible)

EPWM-1/../6

HRPWM-1/../6

ECAP-1/../6

EQEP-1/2

EPWMxA

EPWMxB

ESYNCI

ESYNCO

TZx

ECAPx

EQEPxA

EQEPxB

EQEPxI

EQEPxS

CAN-A/B

(32-mbox)

CANRXx

CANTXx

32-bitperipheralbus

GPIOMUX

88GPIOs

XINTF

Securezone

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SPRS682–DECEMBER 2010

3 Functional Overview

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Figure 3-1. Functional Block Diagram

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3.1 Memory Maps

In Figure 3-2 the following applies:

• Memory blocks are not to scale.

• Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps are restricted to data memory only. A user program cannot access these memory maps in program space.

• Protected means the order of "Write followed by Read" operations is preserved rather than the pipeline order.

• Certain memory ranges are EALLOW protected against spurious writes after configuration.

• Locations 0x38 0080 - 0x38 008F contain the ADC calibration routine. It is not programmable by the user.

• If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for this.

SPRS682–DECEMBER 2010

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Block

Start Address

0x000000

M0Vector-RAM(32x32)

(EnableifVMAP =0)

DataSpace

ProgSpace

M0SARAM(1Kx16)

M1SARAM(1Kx16)

PeripheralFrame0

0x000040

0x000400

0x000800

PIEVector-RAM

(256x16) (Enabledif VMAP =1,

ENPIE=1)

PeripheralFrame0

Reserved

L0SARAM(4Kx16,SecureZoneDualMapped)

PeripheralFrame1

(Protected)

Reserved

PeripheralFrame2

(Protected)

L1SARAM(4Kx16,SecureZoneDualMapped)

FLASH(256Kx16,SecureZone)

Reserved

BootROM(8Kx16)

BROMVector-ROM(32x32)

(EnableifVMAP =1,ENPIE=0)

0x000D00

0x000E00

0x002000

0x006000

0x007000

0x008000

0x009000

0x010000

0x300000

0x3FC000

0x3FE000

0x3FFFC0

DataSpace

ProgSpace

Reserved

On-ChipMemory ExternalMemoryXINTF

Onlyoneofthesevectormaps-M0vector,PIEvector,BROMvector-shouldbeenabledatatime.

LEGEND:

L2SARAM(4Kx16,SecureZone,DualMapped)

L3SARAM(4Kx16,SecureZone,DualMapped)

L4SARAM(4Kx16,DMA Accessible)

L5SARAM(4Kx16,DMA Accessible)

L6SARAM(4Kx16,DMA Accessible)

L7SARAM(4Kx16,DMA Accessible)

0x00 A000

0x00B000

0x00C000

0x00D000

0x00E000

0x00F000

Reserved

XINTFZone0(4Kx16, )XZCS0

(Protected)DMA Accessible

0x004000

0x005000

Low64K

(24x/240xEquivalentDataSpace)

High64K

(24x/240xEquivalent

ProgramSpace)

0x005000

PeripheralFrame3

(Protected)DMA Accessible

128-bitPassword

0x33FFF8

0x340000

L0SARAM(4Kx16,SecureZoneDualMapped)

UserOTP (1Kx16,SecureZone)

0x3F8000

Reserved

0x380400

L1SARAM(4Kx16,SecureZoneDualMapped)

0x3F9000

L2SARAM(4Kx16,SecureZoneDualMapped)

0x3F A000

L3SARAM(4Kx16,SecureZoneDualMapped)

0x3FB000

0x380800

Reserved

XINTFZone6(1Mx16, )(DMA Accessible)XZCS6

0x100000

0x200000

0x300000

XINTFZone7(1Mx16, )XZCS7 (DMA Accessible)

ADCCalibrationData

0x380080

Reserved

0x380090

SM320F28335-HT

SPRS682–DECEMBER 2010

Figure 3-2. Memory Map

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SPRS682–DECEMBER 2010

Table 3-1. Addresses of Flash Sectors

ADDRESS RANGE PROGRAM AND DATA SPACE

0x30 0000 - 0x30 7FFF Sector H (32K x 16) 0x30 8000 - 0x30 FFFF Sector G (32K x 16) 0x31 0000 - 0x31 7FFF Sector F (32K x 16) 0x31 8000 - 0x31 FFFF Sector E (32K x 16) 0x32 0000 - 0x32 7FFF Sector D (32K x 16) 0x32 8000 - 0x32 FFFF Sector C (32K x 16) 0x33 0000 - 0x33 7FFF Sector B (32K x 16) 0x33 8000 - 0x33 FF7F Sector A (32K x 16)

0x33 FF80 - 0x33 FFF5

0x33 FFF6 - 0x33 FFF7

0x33 FFF8 - 0x33 FFFF

Program to 0x0000 when using the

Code Security Module

Boot-to-Flash Entry Point

(program branch instruction here)

Security Password

(128-Bit) (Do Not Program to all zeros)

NOTE

• When the code-security passwords are programmed, all addresses between 0x33FF80 and 0x33FFF5 cannot be used as program code or data. These locations must be programmed to 0x0000.

• If the code security feature is not used, addresses 0x33FF80 through 0x33FFEF may be used for code or data. Addresses 0x33FFF0 – 0x33FFF5 are reserved for data and should not contain program code. .

Table 3-2 shows how to handle these memory locations.

Table 3-2. Handling Security Code Locations

ADDRESS FLASH

Code security enabled Code security disabled

0x33FF80 - 0x33FFEF Application code and data 0x33FFF0 - 0x33FFF5 Reserved for data only

Fill with 0x0000

Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 are grouped together to enable these blocks to be write/read peripheral block protected. The protected mode ensures that all accesses to these blocks happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different memory locations, will appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral applications where the user expected the write to occur first (as written). The C28x CPU supports a block protection mode where a region of memory can be protected so as to make sure that operations occur as written (the penalty is extra cycles are added to align the operations). This mode is programmable and by default, it will protect the selected zones.

The wait-states for the various spaces in the memory map area are listed in Table 3-3.

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Table 3-3. Wait-states

Area Wait-States (CPU) Wait-States (DMA)

M0 and M1 SARAMs 0-wait Fixed

Peripheral Frame 0 0-wait (writes) 0-wait (reads)

1-wait (reads)

Peripheral Frame 3 0-wait (writes) 0-wait (writes) Assumes no conflicts between CPU and DMA.

2-wait (reads) 1-wait (reads)

Peripheral Frame 1 0-wait (writes) Cycles can be extended by peripheral generated ready.

2-wait (reads) Consecutive writes to the CAN will experience a 1-cycle

Peripheral Frame 2 0-wait (writes) Fixed. Cycles cannot be extended by the peripheral.

2-wait (reads) L0 SARAM 0-wait data and Assumes no CPU conflicts L1 SARAM L2 SARAM L3 SARAM L4 SARAM 0-wait data (read) 0-wait data (write) Assumes no conflicts between CPU and DMA. L5 SARAM 0-wait data (write) 0-wait data (read) L6 SARAM 1-wait program (read) L7 SARAM 1-wait program (write)

XINTF Programmable Programmable Programmed via the XTIMING registers or extendable via

OTP Programmable Programmed via the Flash registers.

FLASH Programmable Programmed via the Flash registers.

FLASH Password 16-wait fixed Wait states of password locations are fixed.

Boot-ROM 1-wait 0-wait speed is not possible.

(1) The DMA has a base of 4 cycles/word.

program

0-wait minimum writes 0-wait minimum writes 0-wait minimum for writes assumes write buffer enabled and

with write buffer with write buffer enabled not full.

enabled Assumes no conflicts between CPU and DMA. When DMA and

1-wait minimum 1-wait is minimum number of wait states allowed. 1-wait-state

1-wait Paged min 0-wait minimum for paged access is not allowed

1-wait Random min

Random ≥ Paged

(1)

Comments

pipeline hit.

external XREADY signal to meet system timing requirements. 1-wait is minimum wait states allowed on external waveforms

for both reads and writes on XINTF.

CPU attempt simultaneous conflict, 1-cycle delay is added for arbitration.

operation is possible at a reduced CPU frequency.

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