Texas instruments SM320F28335-HT Data Manual

SM320F28335-HT

Digital Signal Controller (DSC)

Data Manual

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Literature Number: SPRS682

December 2010

SM320F28335-HT

SPRS682–DECEMBER 2010

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Contents

1 SM320F28335 DSC ............................................................................................................. 10

1.1 Features .................................................................................................................... 10

1.2 SUPPORTS EXTREME TEMPERATURE APPLICATIONS ......................................................... 11

2 Introduction ...................................................................................................................... 12

2.1 Pin Assignments ........................................................................................................... 13

2.2 Signal Descriptions ........................................................................................................ 18

3 Functional Overview .......................................................................................................... 26

3.1 Memory Maps .............................................................................................................. 27

3.2 Brief Descriptions .......................................................................................................... 31

3.2.1 C28x CPU ....................................................................................................... 31

3.2.2 Memory Bus (Harvard Bus Architecture) .................................................................... 31

3.2.3 Peripheral Bus .................................................................................................. 31

3.2.4 Real-Time JTAG and Analysis ................................................................................ 32

3.2.5 External Interface (XINTF) .................................................................................... 32

3.2.6 Flash ............................................................................................................. 32

3.2.7 M0, M1 SARAMs ............................................................................................... 32

3.2.8 L0, L1, L2, L3, L4, L5, L6, L7 SARAMs ..................................................................... 32

3.2.9 Boot ROM ....................................................................................................... 33

3.2.10 Security .......................................................................................................... 33

3.2.11 Peripheral Interrupt Expansion (PIE) Block ................................................................. 34

3.2.12 External Interrupts (XINT1-XINT7, XNMI) ................................................................... 35

3.2.13 Oscillator and PLL .............................................................................................. 35

3.2.14 Watchdog ........................................................................................................ 35

3.2.15 Peripheral Clocking ............................................................................................. 35

3.2.16 Low-Power Modes .............................................................................................. 35

3.2.17 Peripheral Frames 0, 1, 2, 3 (PFn) ........................................................................... 36

3.2.18 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 36

3.2.19 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 36

3.2.20 Control Peripherals ............................................................................................. 37

3.2.21 Serial Port Peripherals ......................................................................................... 37

3.3 Register Map ............................................................................................................... 38

3.4 Device Emulation Registers .............................................................................................. 39

3.5 Interrupts .................................................................................................................... 40

3.5.1 External Interrupts .............................................................................................. 44

3.6 System Control ............................................................................................................ 44

3.6.1 OSC and PLL Block ............................................................................................ 46

3.6.1.1 External Reference Oscillator Clock Option .................................................... 47

3.6.1.2 PLL-Based Clock Module ......................................................................... 47

3.6.1.3 Loss of Input Clock ................................................................................ 49

3.6.2 Watchdog Block ................................................................................................. 49

3.7 Low-Power Modes Block ................................................................................................. 50

4 Peripherals ....................................................................................................................... 51

4.1 DMA Overview ............................................................................................................. 51

4.2 32-Bit CPU-Timers 0/1/2 ................................................................................................. 53

4.3 Enhanced PWM Modules (ePWM1/2/3/4/5/6) ......................................................................... 55

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4.4 High-Resolution PWM (HRPWM) ....................................................................................... 59

4.5 Enhanced CAP Modules (eCAP1/2/3/4/5/6) ........................................................................... 59

4.6 Enhanced QEP Modules (eQEP1/2) .................................................................................... 62

4.7 Analog-to-Digital Converter (ADC) Module ............................................................................ 64

4.7.1 ADC Connections if the ADC Is Not Used .................................................................. 67

4.7.2 ADC Registers .................................................................................................. 67

4.7.3 ADC Calibration ................................................................................................. 68

4.8 Multichannel Buffered Serial Port (McBSP) Module .................................................................. 69

4.9 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B) .................................... 72

4.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C) .......................................... 77

4.11 Serial Peripheral Interface (SPI) Module (SPI-A) ..................................................................... 80

4.12 Inter-Integrated Circuit (I2C) ............................................................................................. 83

4.13 GPIO MUX ................................................................................................................. 84

4.14 External Interface (XINTF) ............................................................................................... 91

SPRS682–DECEMBER 2010

5 Device Support ................................................................................................................. 93

6 Electrical Specifications ..................................................................................................... 93

6.1 Absolute Maximum Ratings .............................................................................................. 93

6.2 Recommended Operating Conditions .................................................................................. 95

6.3 Electrical Characteristics ................................................................................................. 95

6.4 Current Consumption ..................................................................................................... 96

6.4.1 Reducing Current Consumption .............................................................................. 98

6.4.2 Current Consumption Graphs ................................................................................. 99

6.4.3 Thermal Design Considerations ............................................................................. 100

6.5 Emulator Connection Without Signal Buffering for the DSP ....................................................... 100

6.6 Timing Parameter Symbology .......................................................................................... 102

6.6.1 General Notes on Timing Parameters ...................................................................... 102

6.6.2 Test Load Circuit .............................................................................................. 102

6.6.3 Device Clock Table ........................................................................................... 102

6.7 Clock Requirements and Characteristics ............................................................................. 104

6.8 Power Sequencing ....................................................................................................... 105

6.8.1 Power Management and Supervisory Circuit Solutions .................................................. 105

6.9 General-Purpose Input/Output (GPIO) ................................................................................ 108

6.9.1 GPIO - Output Timing ........................................................................................ 108

6.9.2 GPIO - Input Timing .......................................................................................... 109

6.9.3 Sampling Window Width for Input Signals ................................................................. 110

6.9.4 Low-Power Mode Wakeup Timing .......................................................................... 111

6.10 Enhanced Control Peripherals ......................................................................................... 115

6.10.1 Enhanced Pulse Width Modulator (ePWM) Timing ....................................................... 115

6.10.2 Trip-Zone Input Timing ....................................................................................... 115

6.11 External Interrupt Timing ................................................................................................ 117

6.12 I2C Electrical Specification and Timing ............................................................................... 118

6.13 Serial Peripheral Interface (SPI) Timing .............................................................................. 118

6.13.1 Master Mode Timing .......................................................................................... 118

6.13.2 SPI Slave Mode Timing ...................................................................................... 122

6.14 External Interface (XINTF) Timing ..................................................................................... 125

6.14.1 USEREADY = 0 ............................................................................................... 125

6.14.2 Synchronous Mode (USEREADY = 1, READYMODE = 0) ............................................. 126

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SPRS682–DECEMBER 2010

6.14.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1) ............................................ 126

6.14.4 XINTF Signal Alignment to XCLKOUT ..................................................................... 128

6.14.5 External Interface Read Timing ............................................................................. 129

6.14.6 External Interface Write Timing ............................................................................. 130

6.14.7 External Interface Ready-on-Read Timing With One External Wait State ............................ 132

6.14.8 External Interface Ready-on-Write Timing With One External Wait State ............................. 135

6.14.9 XHOLD and XHOLDA Timing ............................................................................... 138

6.15 On-Chip Analog-to-Digital Converter .................................................................................. 141

6.15.1 ADC Power-Up Control Bit Timing .......................................................................... 142

6.15.2 Definitions ...................................................................................................... 143

6.15.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0) ............................................ 144

6.15.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) .......................................... 145

6.15.5 Detailed Descriptions ......................................................................................... 146

6.16 Multichannel Buffered Serial Port (McBSP) Timing ................................................................. 147

6.16.1 McBSP Transmit and Receive Timing ...................................................................... 147

6.16.2 McBSP as SPI Master or Slave Timing .................................................................... 149

6.17 Flash Timing .............................................................................................................. 153

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7 Thermal/Mechanical Data .................................................................................................. 155

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SPRS682–DECEMBER 2010

List of Figures

2-1 181-Pin GB........................................................................................................................ 13

3-1 Functional Block Diagram ...................................................................................................... 26

3-2 Memory Map ...................................................................................................................... 28

3-3 External and PIE Interrupt Sources............................................................................................ 41

3-4 External Interrupts................................................................................................................ 41

3-5 Multiplexing of Interrupts Using the PIE Block ............................................................................... 42

3-6 Clock and Reset Domains ...................................................................................................... 45

3-7 OSC and PLL Block Diagram................................................................................................... 46

3-8 Using a 3.3-V External Oscillator............................................................................................... 47

3-9 Using a 1.9-V External Oscillator............................................................................................... 47

3-10 Using the Internal Oscillator .................................................................................................... 47

3-11 Watchdog Module................................................................................................................ 49

4-1 DMA Functional Block Diagram ................................................................................................ 52

4-2 CPU-Timers....................................................................................................................... 53

4-3 CPU-Timer Interrupt Signals and Output Signal ............................................................................. 53

4-4 Multiple PWM Modules .......................................................................................................... 55

4-5 ePWM Submodules Showing Critical Internal Signal Interconnections................................................... 58

4-6 eCAP Functional Block Diagram ............................................................................................... 61

4-7 eQEP Functional Block Diagram............................................................................................... 62

4-8 Block Diagram of the ADC Module ............................................................................................ 65

4-9 ADC Pin Connections With Internal Reference .............................................................................. 66

4-10 ADC Pin Connections With External Reference ............................................................................. 67

4-11 McBSP Module .................................................................................................................. 70

4-12 eCAN Block Diagram and Interface Circuit ................................................................................... 73

4-13 eCAN-A Memory Map ........................................................................................................... 74

4-14 eCAN-B Memory Map ........................................................................................................... 75

4-15 Serial Communications Interface (SCI) Module Block Diagram............................................................ 79

4-16 SPI Module Block Diagram (Slave Mode) .................................................................................... 82

4-17 I2C Peripheral Module Interfaces .............................................................................................. 83

4-18 GPIO MUX Block Diagram...................................................................................................... 85

4-19 Qualification Using Sampling Window......................................................................................... 90

4-20 External Interface Block Diagram .............................................................................................. 91

4-21 Typical 16-bit Data Bus XINTF Connections ................................................................................. 92

4-22 Typical 32-bit Data Bus XINTF Connections ................................................................................. 92

6-1 SM320F28335 Operating Life Derating Chart................................................................................ 94

6-2 Typical Operational Current Versus Frequency for T 6-3 Typical Operational Current Versus Frequency for T

6-4 Emulator Connection Without Signal Buffering for the DSP .............................................................. 101

6-5 3.3-V Test Load Circuit......................................................................................................... 102

6-6 Clock Timing..................................................................................................................... 105

6-7 Power-on Reset................................................................................................................. 106

6-8 Warm Reset ..................................................................................................................... 107

6-9 Example of Effect of Writing Into PLLCR Register ......................................................................... 108

6-10 General-Purpose Output Timing.............................................................................................. 109

6-11 Sampling Mode ................................................................................................................. 109

6-12 General-Purpose Input Timing................................................................................................ 110

6-13 IDLE Entry and Exit Timing.................................................................................................... 111

= 25°C ........................................................... 100

= 210°C.......................................................... 100

SM320F28335-HT

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6-14 STANDBY Entry and Exit Timing Diagram.................................................................................. 112

6-15 HALT Wake-Up Using GPIOn................................................................................................. 114

6-16 PWM Hi-Z Characteristics..................................................................................................... 115

6-17 ADCSOCAO or ADCSOCBO Timing ........................................................................................ 117

6-18 External Interrupt Timing....................................................................................................... 117

6-19 SPI Master Mode External Timing (Clock Phase = 0) ..................................................................... 120

6-20 SPI Master Mode External Timing (Clock Phase = 1) ..................................................................... 122

6-21 SPI Slave Mode External Timing (Clock Phase = 0)....................................................................... 124

6-22 SPI Slave Mode External Timing (Clock Phase = 1)....................................................................... 125

6-23 Relationship Between XTIMCLK and SYSCLKOUT ....................................................................... 128

6-24 Example Read Access......................................................................................................... 130

6-25 Example Write Access......................................................................................................... 131

6-26 Example Read With Synchronous XREADY Access ...................................................................... 133

6-27 Example Read With Asynchronous XREADY Access..................................................................... 134

6-28 Write With Synchronous XREADY Access.................................................................................. 136

6-29 Write With Asynchronous XREADY Access ................................................................................ 137

6-30 External Interface Hold Waveform............................................................................................ 139

6-31 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK).................................................. 140

6-32 ADC Power-Up Control Bit Timing ........................................................................................... 142

6-33 ADC Analog Input Impedance Model ........................................................................................ 143

6-34 Sequential Sampling Mode (Single-Channel) Timing...................................................................... 144

6-35 Simultaneous Sampling Mode Timing ....................................................................................... 145

6-36 McBSP Receive Timing........................................................................................................ 149

6-37 McBSP Transmit Timing....................................................................................................... 149

6-38 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0................................................... 150

6-39 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0................................................... 151

6-40 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1................................................... 152

6-41 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1................................................... 153

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List of Tables

2-1 Hardware Features .............................................................................................................. 12

2-2 Pin Out Information .............................................................................................................. 13

2-3 Signal Descriptions............................................................................................................... 18

3-1 Addresses of Flash Sectors .................................................................................................... 29

3-2 Handling Security Code Locations............................................................................................. 29

3-3 Wait-states ........................................................................................................................ 30

3-4 Boot Mode Selection............................................................................................................. 33

3-5 Peripheral Frame 0 Registers .................................................................................................. 38

3-6 Peripheral Frame 1 Registers .................................................................................................. 38

3-7 Peripheral Frame 2 Registers .................................................................................................. 39

3-8 Peripheral Frame 3 Registers .................................................................................................. 39

3-9 Device Emulation Registers..................................................................................................... 39

3-10 PIE Peripheral Interrupts ....................................................................................................... 42

3-11 PIE Configuration and Control Registers...................................................................................... 43

3-12 External Interrupt Registers..................................................................................................... 44

3-13 PLL, Clocking, Watchdog, and Low-Power Mode Registers ............................................................... 46

3-14 PLLCR Bit Descriptions ......................................................................................................... 48

3-15 CLKIN Divide Options ........................................................................................................... 48

3-16 Possible PLL Configuration Modes ............................................................................................ 48

3-17 Low-Power Modes ............................................................................................................... 50

4-1 CPU-Timers 0, 1, 2 Configuration and Control Registers................................................................... 54

4-2 ePWM Control and Status Registers (default configuration in PF1)....................................................... 56

4-3 ePWM Control and Status Registers (remapped configuration in PF3 - DMA accessible)............................. 57

4-4 eCAP Control and Status Registers ........................................................................................... 61

4-5 eQEP Control and Status Registers ........................................................................................... 63

4-6 ADC Registers ................................................................................................................... 67

4-7 McBSP Register Summary...................................................................................................... 71

4-8 3.3-V eCAN Transceivers ...................................................................................................... 73

4-9 CAN Register Map .............................................................................................................. 76

4-10 SCI-A Registers .................................................................................................................. 78

4-11 SCI-B Registers .................................................................................................................. 78

4-12 SCI-C Registers ................................................................................................................. 78

4-13 SPI-A Registers................................................................................................................... 81

4-14 I2C-A Registers................................................................................................................... 84

4-15 GPIO Registers .................................................................................................................. 86

4-16 GPIO-A Mux Peripheral Selection Matrix .................................................................................... 87

4-17 GPIO-B Mux Peripheral Selection Matrix .................................................................................... 88

4-18 GPIO-C Mux Peripheral Selection Matrix .................................................................................... 89

4-19 XINTF Configuration and Control Register Mapping ........................................................................ 92

6-1 Current Consumption by Power Supply Pins................................................................................. 96

6-2 Typical Current Consumption by Various Peripherals (at 150 MHz) ..................................................... 98

6-3 Clocking Nomenclature for T 6-4 Clocking Nomenclature for T

6-5 Input Clock Frequency ......................................................................................................... 104

6-6 XCLKIN Timing Requirements - PLL Enabled ............................................................................. 104

6-7 XCLKIN Timing Requirements - PLL Disabled ............................................................................. 104

6-8 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ...................................................... 104

= -55°C to 125°C (150-MHz Devices) ................................................... 103

= 210°C (100-MHz Devices) .............................................................. 103

SM320F28335-HT

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6-9 Power Management and Supervisory Circuit Solutions ................................................................... 105

6-10 Reset (XRS) Timing Requirements .......................................................................................... 107

6-11 General-Purpose Output Switching Characteristics........................................................................ 108

6-12 General-Purpose Input Timing Requirements .............................................................................. 109

6-13 IDLE Mode Timing Requirements ........................................................................................... 111

6-14 IDLE Mode Switching Characteristics ....................................................................................... 111

6-15 STANDBY Mode Timing Requirements ..................................................................................... 111

6-16 STANDBY Mode Switching Characteristics ................................................................................ 112

6-17 HALT Mode Timing Requirements ........................................................................................... 113

6-18 HALT Mode Switching Characteristics ...................................................................................... 113

6-19 ePWM Timing Requirements ................................................................................................. 115

6-20 ePWM Switching Characteristics ............................................................................................ 115

6-21 Trip-Zone input Timing Requirements ....................................................................................... 115

6-22 High Resolution PWM Characteristics at SYSCLKOUT = (60 - 120 MHz).............................................. 116

6-23 Enhanced Capture (eCAP) Timing Requirement .......................................................................... 116

6-24 eCAP Switching Characteristics ............................................................................................. 116

6-25 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements .................................................. 116

6-26 eQEP Switching Characteristics ............................................................................................. 116

6-27 External ADC Start-of-Conversion Switching Characteristics............................................................. 117

6-28 External Interrupt Timing Requirements .................................................................................... 117

6-29 External Interrupt Switching Characteristics ................................................................................ 117

6-30 I2C Timing ...................................................................................................................... 118

6-31 SPI Master Mode External Timing (Clock Phase = 0) .................................................................... 119

6-32 SPI Master Mode External Timing (Clock Phase = 1) .................................................................... 121

6-33 SPI Slave Mode External Timing (Clock Phase = 0) ...................................................................... 122

6-34 SPI Slave Mode External Timing (Clock Phase = 1) ...................................................................... 124

6-35 Relationship Between Parameters Configured in XTIMING and Duration of Pulse ................................... 125

6-36 XINTF Clock Configurations................................................................................................... 128

6-37 External Interface Read Timing Requirements ............................................................................. 129

6-38 External Interface Read Switching Characteristics......................................................................... 129

6-39 External Interface Write Switching Characteristics......................................................................... 130

6-40 External Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)................................... 132

6-41 External Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... 132

6-42 Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... 132

6-43 Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)....................................... 132

6-44 External Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) ................................... 135

6-45 Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ....................................... 135

6-46 Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ...................................... 135

6-47 XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) ...................................................... 138

6-48 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) ................................................. 139

6-49 ADC Electrical Characteristics (over recommended operating conditions) ............................................ 141

6-50 ADC Power-Up Delays......................................................................................................... 142

6-51 Typical Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK) .............................. 142

6-52 Sequential Sampling Mode Timing ........................................................................................... 144

6-53 Simultaneous Sampling Mode Timing ....................................................................................... 145

6-54 McBSP Timing Requirements ................................................................................................ 147

6-55 McBSP Switching Characteristics ........................................................................................... 147

6-56 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) ................................ 149

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6-57 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)............................ 149

6-58 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) ................................ 150

6-59 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)............................ 150

6-60 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) ................................ 151

6-61 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)............................ 151

6-62 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) ................................ 152

6-63 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) ........................... 152

6-64 Flash Endurance for A and S Temperature Material ...................................................................... 153

6-65 Flash Endurance for Q Temperature Material .............................................................................. 153

6-66 Flash Parameters at 150-MHz SYSCLKOUT............................................................................... 153

6-67 Flash/OTP Access Timing..................................................................................................... 153

6-68 Minimum Required Flash/OTP Wait-States at Different Frequencies ................................................... 154

7-1 Thermal Model of 181-Pin GB ................................................................................................ 155

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Digital Signal Controller (DSC)

1 SM320F28335 DSC

1.1 Features

• High-Performance Static CMOS Technology – Up to 150 MHz for TC= -55°C to 125°C

and Up to 100 MHZ for TC= 210°C

– 1.9-V Core, 3.3-V I/O Design

• High-Performance 32-Bit CPU – IEEE-754 Single-Precision Floating-Point

Unit (FPU) ) – 16 x 16 and 32 x 32 MAC Operations – 16 x 16 Dual MAC – Harvard Bus Architecture – Fast Interrupt Response and Processing – Unified Memory Programming Model – Code-Efficient (in C/C++ and Assembly)

• Six Channel DMA Controller (for ADC, McBSP, ePWM, XINTF, and SARAM)

• 16-bit or 32-bit External Interface (XINTF) – Over 2M x 16 Address Reach

• On-Chip Memory – 256K x 16 Flash, 34K x 16 SARAM – 1K x 16 OTP ROM

• Boot ROM (8K x 16) – With Software Boot Modes (via SCI, SPI,

CAN, I2C, McBSP, XINTF, and Parallel I/O)

– Standard Math Tables

• Clock and System Control – Dynamic PLL Ratio Changes Supported – On-Chip Oscillator – Watchdog Timer Module

• GPIO0 to GPIO63 Pins Can Be Connected to One of the Eight External Core Interrupts

• Peripheral Interrupt Expansion (PIE) Block That Supports All 58 Peripheral Interrupts

• 128-Bit Security Key/Lock – Protects Flash/OTP/RAM Blocks – Prevents Firmware Reverse Engineering

• Enhanced Control Peripherals – Up to 18 PWM Outputs – Up to 6 HRPWM Outputs With 150 ps MEP Boundary Scan Architecture

Resolution – Up to 6 Event Capture Inputs – Up to 2 Quadrature Encoder Interfaces – Up to 8 32-bit/Nine 16-bit Timers

• Three 32-Bit CPU Timers

• Serial Port Peripherals – Up to 2 CAN Modules – Up to 3 SCI (UART) Modules – Up to 2 McBSP Modules (Configurable as

SPI) – One SPI Module – One Inter-Integrated-Circuit (I2C) Bus

• 12-Bit ADC, 16 Channels – 80-ns Conversion Rate – 2 x 8 Channel Input Multiplexer – Two Sample-and-Hold – Single/Simultaneous Conversions – Internal or External Reference

• Up to 88 Individually Programmable, Multiplexed GPIO Pins With Input Filtering

• JTAG Boundary Scan Support

• Advanced Emulation Features – Analysis and Breakpoint Functions – Real-Time Debug via Hardware

• Development Support Includes – ANSI C/C++ Compiler/Assembler/Linker – Code Composer Studio™ IDE – DSP/BIOS™ – Digital Motor Control and Digital Power

Software Libraries

• Low-Power Modes and Power Savings – IDLE, STANDBY, HALT Modes Supported – Disable Individual Peripheral Clocks

• Package Option – Ceramic Pin Grid Array (GB)

• Temperature Range: – –55°C to 210°C

(1) IEEE Standard 1149.1-1990 Standard Test Access Port and

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(1)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Code Composer Studio, DSP/BIOS are trademarks of Texas Instruments.

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1.2 SUPPORTS EXTREME TEMPERATURE APPLICATIONS

• Controlled Baseline

• One Assembly/Test Site

• One Fabrication Site

• Available in Extreme (–55°C/210°C) Temperature Range

• Extended Product Life Cycle

• Extended Product-Change Notification

• Product Traceability

• Texas Instruments high temperature products utilize highly optimized silicon (die) solutions with design and process enhancements to maximize performance over extended temperatures.

(2) Custom temperature ranges available

(2)

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2 Introduction

The SM320F28335 is a highly integrated, high-performance solution for demanding control applications. Throughout this document, the device is abbreviated as F28335. Table 2-1 provides a summary of

features.

Table 2-1. Hardware Features

FEATURE TYPE

Instruction cycle

Floating-point Unit – Yes

3.3-V on-chip flash (16-bit word) – 256K Single-access RAM (SARAM) (16-bit word) – 34K One-time programmable (OTP) ROM

(16-bit word) Code security for on-chip flash/SARAM/OTP blocks – Yes Boot ROM (8K X16) – Yes 16/32-bit External Interface (XINTF) 1 Yes 6-channel Direct Memory Access (DMA) 0 Yes PWM outputs 0 ePWM1/2/3/4/5/6 HRPWM channels 0 ePWM1A/2A/3A/4A/5A/6A 32-bit Capture inputs or auxiliary PWM outputs 0 6 32-bit QEP channels (four inputs/channel) 0 2 Watchdog timer – Yes

12-Bit ADC MSPS 2 12.5

32-Bit CPU timers – 3 Multichannel Buffered Serial Port (McBSP)/SPI 1 2 Serial Peripheral Interface (SPI) 0 1 Serial Communications Interface (SCI) 0 3 Enhanced Controller Area Network (eCAN) 0 2 Inter-Integrated Circuit (I2C) 0 1 General Purpose I/O pins (shared) – 88 External interrupts – 8 Packaging 181-pin GB – Yes Temperature range –55°C to 210°C – Yes

(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor

differences between devices that do not affect the basic functionality of the module.

TC= -55°C to 125°C – 6.66 ns TC= 210°C – 10 ns

No. of channels 16

Conversion time 80 ns

(1)

– 1K

F28335 (150 MHz)

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15141311 128 96 7 10

K J

542 3

G F

D C

0.100 (2,54) TYP

1.400 (35,56) TYP

Bottom View

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2.1 Pin Assignments

The 181-pin ceramic pin grid array (CPGA) terminal assignments are shown in Figure 2-1. Table 2-2 gives the pin out information and Table 2-3 describes the function(s) of each pin.

SPRS682–DECEMBER 2010

Figure 2-1. 181-Pin GB

Table 2-2. Pin Out Information

PIN FUNCTION

A1 NC

M1 ADCINA0

L1 ADCINA1 K1 ADCINA2 J1 ADCINA3 P2 ADCINA4 N2 ADCINA5

M2 ADCINA6

L2 ADCINA7 M6 ADCINB0 M7 ADCINB1

R2 ADCINB2

R3 ADCINB3

R4 ADCINB4

R5 ADCINB5

R6 ADCINB6

R7 ADCINB7

N1 ADCLO

P3 ADCREFIN

P4 ADCREFM

P5 ADCREFP

P6 ADCRESEXT

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Table 2-2. Pin Out Information (continued)

R11 EMU0 R12 EMU1

F1 GPIO0/EPWM1A G1 GPIO1/EPWM1B/ECAP6/MFSRB

E4 GPIO10/EPWM6A/CANRXB/ADCSOCBO

F4 GPIO11/EPWM6B/SCIRXDB/ECAP4 G4 GPIO12/TZ1/CANTXB/MDXB

J4 GPIO13/TZ2/CANRXB/MDRB

K4 GPIO14/TX3/XHOLD/SCITXDB/MCLKXB

L4 GPIO15/TZ4/XHOLDA/SCIRXDB/MFSXB M4 GPIO16//SPISIMOA/CANTXB/TZ5

J3 GPIO17/SPIOMIA/CANRXB/TZ6

N7 GPIO18/SPICLKA/SCITXDB/CANRXA M8 GPIO19/SPISTEA/SCIRXDB/CANTXA

H1 GPIO2/EPWM2A M9 GPIO20/EQEP1A/MDXA/CANTXB

M10 GPIO21/EQEP1B/MDRA/CANRXB M11 GPIO22/EQEP1S/MCLKXA/SCITXDB

L8 GPIO23/EQEP1I/MFSXA/SCIRXDB

M12 GPIO24/ECAP1/EQEP2A.MDXB

N8 GPIO25/ECAP2/EQEP2B/MDRB

N11 GPIO26/ECAP3/EQEP2I/MCLKXB N12 GPIO27/ECAP4/EQEP2S/MFSX

A9 GPIO28/SCIRXDA/XZCS6

C1 GPIO29/SCITXDA/XA19

E2 GPIO3/EPWM2B/ECAP5/MCLKRB

B1 GPIO30/CANRXA/XA18

A2 GPIO31/CANTXA/XA17

N13 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO

P8 GPIO33/SCLA/EPWMSYNCO/ADCSOCBO

B13 GPIO34/ECAP1/XREADY C11 GPIO35/SCITXDA/XR/1 B10 GPIO36/SCIRXDA/XZCS0

C9 GPIO37/ECAP2/XZCS7

A13 GPIO38/nXWEO

A3 GPIO39/XA16

F2 GPIO4/EPWM3A

D8 GPIO40/XA0/XWE1

D7 GPIO41/XA1

D6 GPIO42/XA2

D4 GPIO43/XA3

C8 GPIO44/XA4

C7 GPIO45/XA5

C4 GPIO46/XA6

C3 GPIO47/XA7

R14 GPIO48/ECAP5/XD31 P15 GPIO49/ECAP6/XD30

G2 GPIO5/EPWM3B/MFSRA/ECAP1

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Table 2-2. Pin Out Information (continued)

N15 GPIO50/EQEP1A/XD29 M15 GPIO51/EQEP1B/XD28

J15 GPIO52/EQEP1S/XD27 H15 GPIO53/EQEP1I/XD26 N14 GPIO54/SPISIMOA/XD25 M14 GPIO55/SPISOMIA/XD24

L14 GPIO56/SPICLKA/XD23 K14 GPIO57/SPISTEA/XD22

J14 GPIO58/MCLKRA/XD21 H12 GPIO59/MFSRA/XD20

H2 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO H11 GPIO60/MCLKRB/XD19 G12 GPIO61/MFSRB/XD18

F12 GPIO62/SCIRXDC/XD17 E12 GPIO63/SCITXDC/XD16 D12 GPIO64/XD15 G13 GPIO65/XD14 D13 GPIO66/XD13

F14 GPIO67/XD12 E14 GPIO68/XD11 D14 GPIO69/XD10

F3 GPIO7/EPWM4B/MCLKRA/ECAP2

G15 GPIO70/XD9

F15 GPIO71/XD8 E15 GPIO72/XD7 D15 GPIO73/XD6 C15 GPIO74/XD5 B15 GPIO75/XD4 D11 GPIO76/XD3 D10 GPIO77/XD2

D9 GPIO78/XD1

A14 GPIO79/XD0

G3 GPIO8/EPWM5A/CANTXB/ADCSOCAO

B8 GPIO80/XA8 B7 GPIO81/XA9 B6 GPIO82/XA10 B3 GPIO83/XA11 B2 GPIO84/XA12 A6 GPIO85/XA13 A5 GPIO86/XA14 A4 GPIO87/XA15 H3 GPIO9/EPWM5B/SCITXDB/ECAP3

R13 TCK

P9 TDI P10 TDO P14 TEST1

R8 TEST2 P12 TMS

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Table 2-2. Pin Out Information (continued)

P11 TRSTn A11 VDD B14 VDD

B4 VDD

B9 VDD

D5 VDD

E1 VDD

E3 VDD

F13 VDD

H14 VDD

H5 VDD

J12 VDD

K3 VDD

N6 VDD

M3 VDD1A18

N4 VDD2A18 R10 VDD3VFL

K2 VDDA2

M5 VDDAIO

A8 VDDIO B12 VDDIO

C6 VDDIO

D2 VDDIO G14 VDDIO K15 VDDIO

L12 VDDIO N10 VDDIO A10 VSS

A7 VSS

B11 VSS

B5 VSS C12 VSS C13 VSS C14 VSS

C2 VSS

C5 VSS

D1 VSS

D3 VSS E13 VSS

E8 VSS H13 VSS

H4 VSS K12 VSS

L13 VSS L15 VSS

L3 VSS

N5 VSS

N9 VSS

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Table 2-2. Pin Out Information (continued)

R9 VSS

N3 VSS1AGND

P7 VSS2AGND

J2 VSSA2

P1 VSSAIO K13 X1 M13 X2

J13 XCLKIN A12 XCLKOUT C10 XRD P13 XRSn A15 NC

R1 NC

R15 NC

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2.2 Signal Descriptions

Table 2-3 describes the signals. The GPIO function (shown in Italics) is the default at reset. The peripheral

signals that are listed under them are alternate functions. Some peripheral functions may not be available in all devices. See Table 2-1 for details. Inputs are not 5-V tolerant. All pins capable of producing an XINTF output function have a drive strength of 8 mA (typical). This is true even if the pin is not configured for XINTF functionality. All other pins have a drive strength of 4-mA drive typical (unless otherwise indicated). All GPIO pins are I/O/Z and have an internal pullup, which can be selectively enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on GPIO0-GPIO11 pins are not enabled at reset. The pullups on GPIO12-GPIO34 are enabled upon reset.

Table 2-3. Signal Descriptions

NAME DESCRIPTION

JTAG

JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored.

TRST

TCK JTAG test clock with internal pullup (I, ↑) TMS

TDI

TDO

EMU0

EMU1

DD3VFL

TEST1 Test Pin. Reserved for TI. Must be left unconnected. (I/O) TEST2 Test Pin. Reserved for TI. Must be left unconnected. (I/O)

XCLKOUT XINTCNF2 register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting

XCLKIN tied to GND. If a crystal/resonator is used (or if an external 1.9-V oscillator is used to feed clock to X1 pin), this pin

NOTE: TRST is an active high test pin and must be maintained low at all times during normal device operation. An external pulldown resistor is recommended on this pin. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application. (I, ↓)

JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. (I, ↑)

JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. (I, ↑)

JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)

Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode. (I/O/Z, 8 mA drive ↑) NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application.

Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode. (I/O/Z, 8 mA drive ↑) NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application.

FLASH

3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times.

CLOCK

Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or onefourth the frequency of SYSCLKOUT. This is controlled by bits 18:16 (XTIMCLK) and bit 2 (CLKMODE) in the

XINTCNF2[CLKOFF] to 1. Unlike other GPIO pins, the XCLKOUT pin is not placed in high-impedance state during a reset. (O/Z, 8 mA drive).

External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this case, the X1 pin must be must be tied to GND. (I)

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Table 2-3. Signal Descriptions (continued)

NAME DESCRIPTION

Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a ceramic resonator may be

connected across X1 and X2. The X1 pin is referenced to the 1.9-V core digital power supply. A 1.9-V external oscillator may be connected to the X1 pin. In this case, the XCLKIN pin must be connected to ground. If a 3.3-V external oscillator is used with the XCLKIN pin, X1 must be tied to GND. (I)

Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected across X1 and X2. If X2 is not used it must be left unconnected. (O)

RESET

Device Reset (in) and Watchdog Reset (out). Device reset. XRS causes the device to terminate execution. The PC will point to the address contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the location pointed to by the PC. This

XRS pin is driven low by the DSC when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the

watchdog reset duration of 512 OSCCLK cycles. (I/OD, ↑) The output buffer of this pin is an open-drain with an internal pullup. It is recommended that this pin be driven by an open-drain device.

ADC SIGNALS

ADCINA7 ADC Group A, Channel 7 input (I) ADCINA6 ADC Group A, Channel 6 input (I) ADCINA5 ADC Group A, Channel 5 input (I) ADCINA4 ADC Group A, Channel 4 input (I) ADCINA3 ADC Group A, Channel 3 input (I) ADCINA2 ADC Group A, Channel 2 input (I) ADCINA1 ADC Group A, Channel 1 input (I) ADCINA0 ADC Group A, Channel 0 input (I) ADCINB7 ADC Group B, Channel 7 input (I) ADCINB6 ADC Group B, Channel 6 input (I) ADCINB5 ADC Group B, Channel 5 input (I) ADCINB4 ADC Group B, Channel 4 input (I) ADCINB3 ADC Group B, Channel 3 input (I) ADCINB2 ADC Group B, Channel 2 input (I) ADCINB1 ADC Group B, Channel 1 input (I) ADCINB0 ADC Group B, Channel 0 input (I) ADCLO Low Reference (connect to analog ground) (I) ADCRESEXT ADC External Current Bias Resistor. Connect a 22-kΩ resistor to analog ground. ADCREFIN External reference input (I)

ADCREFP

ADCREFM

Internal Reference Positive Output. Requires a low ESR (50 mΩ - 1.5 Ω) ceramic bypass capacitor of 2.2 mF to analog ground. (O)

Internal Reference Medium Output. Requires a low ESR (50 mΩ - 1.5 Ω) ceramic bypass capacitor of 2.2 mF to analog ground. (O)

CPU AND I/O POWER PINS

DDA2

SSA2

DDAIO

SSAIO

DD1A18

SS1AGND

DD2A18

SS2AGND

DDIO

ADC Analog Power Pin ADC Analog Ground Pin ADC Analog I/O Power Pin ADC Analog I/O Ground Pin ADC Analog Power Pin ADC Analog Ground Pin ADC Analog Power Pin ADC Analog Ground Pin CPU and Logic Digital Power Pin Digital I/O Power Pin Digital Ground Pin

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Table 2-3. Signal Descriptions (continued)

NAME DESCRIPTION

GPIOA AND PERIPHERAL SIGNALS

GPIO0 General purpose input/output 0 (I/O/Z) EPWM1A Enhanced PWM1 Output A and HRPWM channel (O)

- -

- GPIO1 General purpose input/output 1 (I/O/Z)

EPWM1B Enhanced PWM1 Output B (O) ECAP6 Enhanced Capture 6 input/output (I/O) MFSRB McBSP-B receive frame synch (I/O)

GPIO2 General purpose input/output 2 (I/O/Z) EPWM2A Enhanced PWM2 Output A and HRPWM channel (O)

- -

- GPIO3 General purpose input/output 3 (I/O/Z)

EPWM2B Enhanced PWM2 Output B (O) ECAP5 Enhanced Capture 5 input/output (I/O) MCLKRB McBSP-B receive clock (I/O)

GPIO4 General purpose input/output 4 (I/O/Z) EPWM3A Enhanced PWM3 output A and HRPWM channel (O)

- -

- GPIO5 General purpose input/output 5 (I/O/Z)

EPWM3B Enhanced PWM3 output B (O) MFSRA McBSP-A receive frame synch (I/O) ECAP1 Enhanced Capture input/output 1 (I/O)

GPIO6 General purpose input/output 6 (I/O/Z) EPWM4A Enhanced PWM4 output A and HRPWM channel (O) EPWMSYNCI External ePWM sync pulse input (I) EPWMSYNCO External ePWM sync pulse output (O)

GPIO7 General purpose input/output 7 (I/O/Z) EPWM4B Enhanced PWM4 output B (O) MCLKRA McBSP-A receive clock (I/O) ECAP2 Enhanced capture input/output 2 (I/O)

GPIO8 General Purpose Input/Output 8 (I/O/Z) EPWM5A Enhanced PWM5 output A and HRPWM channel (O) CANTXB Enhanced CAN-B transmit (O) ADCSOCAO ADC start-of-conversion A (O)

GPIO9 General purpose input/output 9 (I/O/Z) EPWM5B Enhanced PWM5 output B (O) SCITXDB SCI-B transmit data(O) ECAP3 Enhanced capture input/output 3 (I/O)

GPIO10 General purpose input/output 10 (I/O/Z) EPWM6A Enhanced PWM6 output A and HRPWM channel (O) CANRXB Enhanced CAN-B receive (I) ADCSOCBO ADC start-of-conversion B (O)

GPIO11 General purpose input/output 11 (I/O/Z) EPWM6B Enhanced PWM6 output B (O) SCIRXDB SCI-B receive data (I) ECAP4 Enhanced CAP Input/Output 4 (I/O)

GPIO12 General purpose input/output 12 (I/O/Z) TZ1 Trip Zone input 1 (I) CANTXB Enhanced CAN-B transmit (O) MDXB McBSP-B transmit serial data (O)

GPIO13 General purpose input/output 13 (I/O/Z) TZ2 Trip Zone input 2 (I) CANRXB Enhanced CAN-B receive (I) MDRB McBSP-B receive serial data (I)

GPIO14 General purpose input/output 14 (I/O/Z)

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Table 2-3. Signal Descriptions (continued)

NAME DESCRIPTION

Trip Zone input 3/External Hold Request. XHOLD, when active (low), requests the external interface (XINTF) to release the external bus and place all buses and strobes into a high-impedance state. To prevent this from

TZ3/XHOLD

SCITXDB SCI-B Transmit (I) MCLKXB McBSP-B transmit clock (I/O)

GPIO15 General purpose input/output 15 (I/O/Z)

TZ4/XHOLDA output, then XHOLDA function is chosen. XHOLDA is driven active (low) when the XINTF has granted an XHOLD

SCIRXDB SCI-B receive (I) MFSXB McBSP-B transmit frame synch (I/O)

GPIO16 General purpose input/output 16 (I/O/Z) SPISIMOA SPI slave in, master out (I/O) CANTXB Enhanced CAN-B transmit (O) TZ5 Trip Zone input 5 (I)

GPIO17 General purpose input/output 17 (I/O/Z) SPISOMIA SPI-A slave out, master in (I/O) CANRXB Enhanced CAN-B receive (I) TZ6 Trip zone input 6 (I)

GPIO18 General purpose input/output 18 (I/O/Z) SPICLKA SPI-A clock input/output (I/O) SCITXDB SCI-B transmit (O) CANRXA Enhanced CAN-A receive (I)

GPIO19 General purpose input/output 19 (I/O/Z) SPISTEA SPI-A slave transmit enable input/output (I/O) SCIRXDB SCI-B receive (I) CANTXA Enhanced CAN-A transmit (O)

GPIO20 General purpose input/output 20 (I/O/Z) EQEP1A Enhanced QEP1 input A (I) MDXA McBSP-A transmit serial data (O) CANTXB Enhanced CAN-B transmit (O)

GPIO21 General purpose input/output 21 (I/O/Z) EQEP1B Enhanced QEP1 input B (I) MDRA McBSP-A receive serial data (I) CANRXB Enhanced CAN-B receive (I)

GPIO22 General purpose input/output 22 (I/O/Z) EQEP1S Enhanced QEP1 strobe (I/O) MCLKXA McBSP-A transmit clock (I/O) SCITXDB SCI-B transmit (O)

GPIO23 General purpose input/output 23 (I/O/Z) EQEP1I Enhanced QEP1 index (I/O) MFSXA McBSP-A transmit frame synch (I/O) SCIRXDB SCI-B receive (I)

GPIO24 General purpose input/output 24 (I/O/Z) ECAP1 Enhanced capture 1 (I/O) EQEP2A Enhanced QEP2 input A (I) MDXB McBSP-B transmit serial data (O)

GPIO25 General purpose input/output 25 (I/O/Z) ECAP2 Enhanced capture 2 (I/O) EQEP2B Enhanced QEP2 input B (I) MDRB McBSP-B receive serial data (I)

GPIO26 General purpose input/output 26 (I/O/Z) ECAP3 Enhanced capture 3 (I/O) EQEP2I Enhanced QEP2 index (I/O) MCLKXB McBSP-B transmit clock (I/O)

happening when TZ3 signal goes active, disable this function by writing XINTCNF2[HOLD] = 1. If this is not done, the XINTF bus will go into high impedance anytime TZ3 goes low. On the ePWM side, TZn signals are ignored by default, unless they are enabled by the code. The XINTF will release the bus when any current access is complete and there are no pending accesses on the XINTF. (I)

Trip Zone input 4/External Hold Acknowledge. The pin function for this option is based on the direction chosen in the GPADIR register. If the pin is configured as an input, then TZ4 function is chosen. If the pin is configured as an

request. All XINTF buses and strobe signals will be in a high-impedance state. XHOLDA is released when the XHOLD signal is released. External devices should only drive the external bus when XHOLDA is active (low). (I/0)

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Table 2-3. Signal Descriptions (continued)

NAME DESCRIPTION

GPIO27 General purpose input/output 27 (I/O/Z) ECAP4 Enhanced capture 4 (I/O) EQEP2S Enhanced QEP2 strobe (I/O) MFSXB McBSP-B transmit frame synch (I/O)

GPIO28 General purpose input/output 28 (I/O/Z) SCIRXDA SCI receive data (I) XZCS6 External Interface zone 6 chip select (O)

GPIO29 General purpose input/output 29. (I/O/Z) SCITXDA SCI transmit data (O) XA19 External Interface Address Line 19 (O)

GPIO30 General purpose input/output 30 (I/O/Z) CANRXA Enhanced CAN-A receive (I) XA18 External Interface Address Line 18 (O)

GPIO31 General purpose input/output 31 (I/O/Z) CANTXA Enhanced CAN-A transmit (O) XA17 External Interface Address Line 17 (O)

GPIO32 General purpose input/output 32 (I/O/Z) SDAA I2C data open-drain bidirectional port (I/OD) EPWMSYNCI Enhanced PWM external sync pulse input (I) ADCSOCAO ADC start-of-conversion A (O)

GPIO33 General-Purpose Input/Output 33 (I/O/Z) SCLA I2C clock open-drain bidirectional port (I/OD) EPWMSYNCO Enhanced PWM external synch pulse output (O) ADCSOCBO ADC start-of-conversion B (O)

GPIO34 General-Purpose Input/Output 34 (I/O/Z) ECAP1 Enhanced Capture input/output 1 (I/O) XREADY External Interface Ready signal

GPIO35 General-Purpose Input/Output 35 (I/O/Z) SCITXDA SCI-A transmit data (O) XR/W External Interface read, not write strobe

GPIO36 General-Purpose Input/Output 36 (I/O/Z) SCIRXDA SCI receive data (I) XZCS0 External Interface zone 0 chip select (O)

GPIO37 General-Purpose Input/Output 37 (I/O/Z) ECAP2 Enhanced Capture input/output 2 (I/O) XZCS7 External Interface zone 7 chip select (O)

GPIO38 General-Purpose Input/Output 38 (I/O/Z)

- XWE0 External Interface Write Enable 0 (O)

GPIO39 General-Purpose Input/Output 39 (I/O/Z)

- XA16 External Interface Address Line 16 (O)

GPIO40 General-Purpose Input/Output 40 (I/O/Z)

- XA0/XWE1 External Interface Address Line 0/External Interface Write Enable 1 (O)

GPIO41 General-Purpose Input/Output 41 (I/O/Z)

- XA1 External Interface Address Line 1 (O)

GPIO42 General-Purpose Input/Output 42 (I/O/Z)

- XA2 External Interface Address Line 2 (O)

GPIO43 General-Purpose Input/Output 43 (I/O/Z)

- XA3 External Interface Address Line 3 (O)

GPIO44 General-Purpose Input/Output 44 (I/O/Z)

- XA4 External Interface Address Line 4 (O)

GPIO45 General-Purpose Input/Output 45 (I/O/Z)

- XA5 External Interface Address Line 5 (O)

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Table 2-3. Signal Descriptions (continued)

NAME DESCRIPTION

GPIO46 General-Purpose Input/Output 46 (I/O/Z)

- XA6 External Interface Address Line 6 (O)

GPIO47 General-Purpose Input/Output 47 (I/O/Z)

- XA7 External Interface Address Line 7 (O)

GPIO48 General-Purpose Input/Output 48 (I/O/Z) ECAP5 Enhanced Capture input/output 5 (I/O) XD31 External Interface Data Line 31 (O)

GPIO49 General-Purpose Input/Output 49 (I/O/Z) ECAP6 Enhanced Capture input/output 6 (I/O) XD30 External Interface Data Line 30 (O)

GPIO50 General-Purpose Input/Output 50 (I/O/Z) EQEP1A Enhanced QEP 1input A (I) XD29 External Interface Data Line 29 (O)

GPIO51 General-Purpose Input/Output 51 (I/O/Z) EQEP1B Enhanced QEP 1input B (I) XD28 External Interface Data Line 28 (O)

GPIO52 General-Purpose Input/Output 52 (I/O/Z) EQEP1S Enhanced QEP 1Strobe (I/O) XD27 External Interface Data Line 27 (O)

GPIO53 General-Purpose Input/Output 53 (I/O/Z) EQEP1I Enhanced CAP1 lndex (I/O) XD26 External Interface Data Line 26 (O)

GPIO54 General-Purpose Input/Output 54 (I/O/Z) SPISIMOA SPI-A slave in, master out (I/O) XD25 External Interface Data Line 25 (O)

GPIO55 General-Purpose Input/Output 55 (I/O/Z) SPISOMIA SPI-A slave out, master in (I/O) XD24 External Interface Data Line 24 (O)

GPIO56 General-Purpose Input/Output 56 (I/O/Z) SPICLKA SPI-A clock (I/O) XD23 External Interface Data Line 23 (O)

GPIO57 General-Purpose Input/Output 57 (I/O/Z) SPISTEA SPI-A slave transmit enable (I/O) XD22 External Interface Data Line 22 (O)

GPIO58 General-Purpose Input/Output 58 (I/O/Z) MCLKRA McBSP-A receive clock (I/O) XD21 External Interface Data Line 21 (O)

GPIO59 General-Purpose Input/Output 59 (I/O/Z) MFSRA McBSP-A receive frame synch (I/O) XD20 External Interface Data Line 20 (O)

GPIO60 General-Purpose Input/Output 60 (I/O/Z) MCLKRB McBSP-B receive clock (I/O) XD19 External Interface Data Line 19 (O)

GPIO61 General-Purpose Input/Output 61 (I/O/Z) MFSRB McBSP-B receive frame synch (I/O) XD18 External Interface Data Line 18 (O)

GPIO62 General-Purpose Input/Output 62 (I/O/Z) SCIRXDC SCI-C receive data (I) XD17 External Interface Data Line 17 (O)

GPIO63 General-Purpose Input/Output 63 (I/O/Z) SCITXDC SCI-C transmit data (O) XD16 External Interface Data Line 16 (O)

GPIO64 General-Purpose Input/Output 64 (I/O/Z)

- XD15 External Interface Data Line 15 (O)

GPIO65 General-Purpose Input/Output 65 (I/O/Z)

- XD14 External Interface Data Line 14 (O)

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Table 2-3. Signal Descriptions (continued)

NAME DESCRIPTION

GPIO66 General-Purpose Input/Output 66 (I/O/Z)

- XD13 External Interface Data Line 13 (O)

GPIO67 General-Purpose Input/Output 67 (I/O/Z)

- XD12 External Interface Data Line 12 (O)

GPIO68 General-Purpose Input/Output 68 (I/O/Z)

- XD11 External Interface Data Line 11 (O)

GPIO69 General-Purpose Input/Output 69 (I/O/Z)

- XD10 External Interface Data Line 10 (O)

GPIO70 General-Purpose Input/Output 70 (I/O/Z)

- XD9 External Interface Data Line 9 (O)

GPIO71 General-Purpose Input/Output 71 (I/O/Z)

- XD8 External Interface Data Line 8 (O)

GPIO72 General-Purpose Input/Output 72 (I/O/Z)

- XD7 External Interface Data Line 7 (O)

GPIO73 General-Purpose Input/Output 73 (I/O/Z)

- XD6 External Interface Data Line 6 (O)

GPIO74 General-Purpose Input/Output 74 (I/O/Z)

- XD5 External Interface Data Line 5 (O)

GPIO75 General-Purpose Input/Output 75 (I/O/Z)

- XD4 External Interface Data Line 4 (O)

GPIO76 General-Purpose Input/Output 76 (I/O/Z)

- XD3 External Interface Data Line 3 (O)

GPIO77 General-Purpose Input/Output 77 (I/O/Z)

- XD2 External Interface Data Line 2 (O)

GPIO78 General-Purpose Input/Output 78 (I/O/Z)

- XD1 External Interface Data Line 1 (O)

GPIO79 General-Purpose Input/Output 79 (I/O/Z)

- XD0 External Interface Data Line 0 (O)

GPIO80 General-Purpose Input/Output 80 (I/O/Z)

- XA8 External Interface Address Line 8 (O)

GPIO81 General-Purpose Input/Output 81 (I/O/Z)

- XA9 External Interface Address Line 9 (O)

GPIO82 General-Purpose Input/Output 82 (I/O/Z)

- XA10 External Interface Address Line 10 (O)

GPIO83 General-Purpose Input/Output 83 (I/O/Z)

- XA11 External Interface Address Line 11 (O)

GPIO84

XA12

GPIO85 General-Purpose Input/Output 85 (I/O/Z)

- XA13 External Interface Address Line 13 (O)

General-Purpose Input/Output 84 (I/O/Z) External Interface Address Line 12 (O)

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(1)

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Table 2-3. Signal Descriptions (continued)

NAME DESCRIPTION

GPIO86 General-Purpose Input/Output 86 (I/O/Z)

- XA14 External Interface Address Line 14 (O)

GPIO87 General-Purpose Input/Output 87 (I/O/Z)

- XA15 External Interface Address Line 15 (O)

XRD External Interface Read Enable

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(1)

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L0SARAM4Kx16 (0-Wait,DualMap)

L1SARAM4Kx16 (0-Wait,DualMap)

L2SARAM4Kx16 (0-Wait,DualMap)

L3SARAM4Kx16 (0-Wait,DualMap)

M0SARAM1Kx16

(0-Wait)

M1SARAM1Kx16

(0-Wait)

L4SARAM4Kx16

(0-WData,1-WProg)

L5SARAM4Kx16

(0-WData,1-WProg)

L6SARAM4Kx16

(0-WData,1-WProg)

L7SARAM4Kx16

(0-WData,1-WProg)

MemoryBus

BootROM

8Kx16

Code

Security

Module

DMA Bus

PSWD

OTP 1Kx16

Flash 256Kx16 8Sectors

Pump

Flash

Wrapper

TEST1

TEST2

XINTF

XA0/XWE1

XWE0

XZCS6

XZCS7

XZCS0

XR/W

XREADY

XHOLD

XHOLDA

XD31:0

XA19:1

GPIO

MUX

MemoryBus

XCLKOUT

XRD

GPIO

MUX

88GPIOs

8ExternalInterrupts

88GPIOs

12-Bit

ADC

2-S/H

A7:0

B7:0

CPUTimer0

CPUTimer1

CPUTimer2

OSC,

PLL,

LPM,

DMA 6Ch

PIE

(Interrupts)

32-bitCPU (150MHZ@1.9V) (100MHz@1.8V)

EMU1

EMU0

TRST

TDO

TMS

TDI

TCK

XRS

XCLKIN

FPU

REFIN

DMA Bus

MemoryBus

FIFO

(16Levels)

SCI-A/B/C

FIFO

(16Levels)

SPI-A

FIFO

(16Levels)

I2C

16-bitperipheralbus

SPISOMIx

SPISIMOx

SPICLKx

SPISTEx

SCIRXDx

SCITXDx

SDAx

SCLx

McBSP-A/B

MRXx

MDXx

MCLKXx

MCLKRx

MFSXx

MFSRx

32-bitperipheralbus

(DMA accessible)

EPWM-1/../6

HRPWM-1/../6

ECAP-1/../6

EQEP-1/2

EPWMxA

EPWMxB

ESYNCI

ESYNCO

TZx

ECAPx

EQEPxA

EQEPxB

EQEPxI

EQEPxS

CAN-A/B

(32-mbox)

CANRXx

CANTXx

32-bitperipheralbus

GPIOMUX

88GPIOs

XINTF

Securezone

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3 Functional Overview

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Figure 3-1. Functional Block Diagram

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3.1 Memory Maps

In Figure 3-2 the following applies:

• Memory blocks are not to scale.

• Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps are restricted to data memory only. A user program cannot access these memory maps in program space.

• Protected means the order of "Write followed by Read" operations is preserved rather than the pipeline order.

• Certain memory ranges are EALLOW protected against spurious writes after configuration.

• Locations 0x38 0080 - 0x38 008F contain the ADC calibration routine. It is not programmable by the user.

• If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for this.

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Block

Start Address

0x000000

M0Vector-RAM(32x32)

(EnableifVMAP =0)

DataSpace

ProgSpace

M0SARAM(1Kx16)

M1SARAM(1Kx16)

PeripheralFrame0

0x000040

0x000400

0x000800

PIEVector-RAM

(256x16) (Enabledif VMAP =1,

ENPIE=1)

PeripheralFrame0

Reserved

L0SARAM(4Kx16,SecureZoneDualMapped)

PeripheralFrame1

(Protected)

Reserved

PeripheralFrame2

(Protected)

L1SARAM(4Kx16,SecureZoneDualMapped)

FLASH(256Kx16,SecureZone)

Reserved

BootROM(8Kx16)

BROMVector-ROM(32x32)

(EnableifVMAP =1,ENPIE=0)

0x000D00

0x000E00

0x002000

0x006000

0x007000

0x008000

0x009000

0x010000

0x300000

0x3FC000

0x3FE000

0x3FFFC0

DataSpace

ProgSpace

Reserved

On-ChipMemory ExternalMemoryXINTF

Onlyoneofthesevectormaps-M0vector,PIEvector,BROMvector-shouldbeenabledatatime.

LEGEND:

L2SARAM(4Kx16,SecureZone,DualMapped)

L3SARAM(4Kx16,SecureZone,DualMapped)

L4SARAM(4Kx16,DMA Accessible)

L5SARAM(4Kx16,DMA Accessible)

L6SARAM(4Kx16,DMA Accessible)

L7SARAM(4Kx16,DMA Accessible)

0x00 A000

0x00B000

0x00C000

0x00D000

0x00E000

0x00F000

Reserved

XINTFZone0(4Kx16, )XZCS0

(Protected)DMA Accessible

0x004000

0x005000

Low64K

(24x/240xEquivalentDataSpace)

High64K

(24x/240xEquivalent

ProgramSpace)

0x005000

PeripheralFrame3

(Protected)DMA Accessible

128-bitPassword

0x33FFF8

0x340000

L0SARAM(4Kx16,SecureZoneDualMapped)

UserOTP (1Kx16,SecureZone)

0x3F8000

Reserved

0x380400

L1SARAM(4Kx16,SecureZoneDualMapped)

0x3F9000

L2SARAM(4Kx16,SecureZoneDualMapped)

0x3F A000

L3SARAM(4Kx16,SecureZoneDualMapped)

0x3FB000

0x380800

Reserved

XINTFZone6(1Mx16, )(DMA Accessible)XZCS6

0x100000

0x200000

0x300000

XINTFZone7(1Mx16, )XZCS7 (DMA Accessible)

ADCCalibrationData

0x380080

Reserved

0x380090

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Figure 3-2. Memory Map

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Table 3-1. Addresses of Flash Sectors

ADDRESS RANGE PROGRAM AND DATA SPACE

0x30 0000 - 0x30 7FFF Sector H (32K x 16) 0x30 8000 - 0x30 FFFF Sector G (32K x 16) 0x31 0000 - 0x31 7FFF Sector F (32K x 16) 0x31 8000 - 0x31 FFFF Sector E (32K x 16) 0x32 0000 - 0x32 7FFF Sector D (32K x 16) 0x32 8000 - 0x32 FFFF Sector C (32K x 16) 0x33 0000 - 0x33 7FFF Sector B (32K x 16) 0x33 8000 - 0x33 FF7F Sector A (32K x 16)

0x33 FF80 - 0x33 FFF5

0x33 FFF6 - 0x33 FFF7

0x33 FFF8 - 0x33 FFFF

Program to 0x0000 when using the

Code Security Module

Boot-to-Flash Entry Point

(program branch instruction here)

Security Password

(128-Bit) (Do Not Program to all zeros)

NOTE

• When the code-security passwords are programmed, all addresses between 0x33FF80 and 0x33FFF5 cannot be used as program code or data. These locations must be programmed to 0x0000.

• If the code security feature is not used, addresses 0x33FF80 through 0x33FFEF may be used for code or data. Addresses 0x33FFF0 – 0x33FFF5 are reserved for data and should not contain program code. .

Table 3-2 shows how to handle these memory locations.

Table 3-2. Handling Security Code Locations

ADDRESS FLASH

Code security enabled Code security disabled

0x33FF80 - 0x33FFEF Application code and data 0x33FFF0 - 0x33FFF5 Reserved for data only

Fill with 0x0000

Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 are grouped together to enable these blocks to be write/read peripheral block protected. The protected mode ensures that all accesses to these blocks happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different memory locations, will appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral applications where the user expected the write to occur first (as written). The C28x CPU supports a block protection mode where a region of memory can be protected so as to make sure that operations occur as written (the penalty is extra cycles are added to align the operations). This mode is programmable and by default, it will protect the selected zones.

The wait-states for the various spaces in the memory map area are listed in Table 3-3.

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Table 3-3. Wait-states

Area Wait-States (CPU) Wait-States (DMA)

M0 and M1 SARAMs 0-wait Fixed

Peripheral Frame 0 0-wait (writes) 0-wait (reads)

1-wait (reads)

Peripheral Frame 3 0-wait (writes) 0-wait (writes) Assumes no conflicts between CPU and DMA.

2-wait (reads) 1-wait (reads)

Peripheral Frame 1 0-wait (writes) Cycles can be extended by peripheral generated ready.

2-wait (reads) Consecutive writes to the CAN will experience a 1-cycle

Peripheral Frame 2 0-wait (writes) Fixed. Cycles cannot be extended by the peripheral.

2-wait (reads) L0 SARAM 0-wait data and Assumes no CPU conflicts L1 SARAM L2 SARAM L3 SARAM L4 SARAM 0-wait data (read) 0-wait data (write) Assumes no conflicts between CPU and DMA. L5 SARAM 0-wait data (write) 0-wait data (read) L6 SARAM 1-wait program (read) L7 SARAM 1-wait program (write)

XINTF Programmable Programmable Programmed via the XTIMING registers or extendable via

OTP Programmable Programmed via the Flash registers.

FLASH Programmable Programmed via the Flash registers.

FLASH Password 16-wait fixed Wait states of password locations are fixed.

Boot-ROM 1-wait 0-wait speed is not possible.

(1) The DMA has a base of 4 cycles/word.

program

0-wait minimum writes 0-wait minimum writes 0-wait minimum for writes assumes write buffer enabled and

with write buffer with write buffer enabled not full.

enabled Assumes no conflicts between CPU and DMA. When DMA and

1-wait minimum 1-wait is minimum number of wait states allowed. 1-wait-state

1-wait Paged min 0-wait minimum for paged access is not allowed

1-wait Random min

Random ≥ Paged

(1)

Comments

pipeline hit.

external XREADY signal to meet system timing requirements. 1-wait is minimum wait states allowed on external waveforms

for both reads and writes on XINTF.

CPU attempt simultaneous conflict, 1-cycle delay is added for arbitration.

operation is possible at a reduced CPU frequency.

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3.2 Brief Descriptions

3.2.1 C28x CPU

The C28x+FPU based controllers have the same 32-bit fixed-point architecture as TI's existing C28x DSCs, but also include a single-precision (32-bit) IEEE 754 floating-point unit (FPU). It is a very efficient C/C++ engine, enabling users to develop their system control software in a high-level language. It also enables math algorithms to be developed using C/C++. The device is as efficient in DSP math tasks as it is in system control tasks that typically are handled by microcontroller devices. This efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC 64-bit processing capabilities enable the controller to handle higher numerical resolution problems efficiently. Add to this the fast interrupt response with automatic context save of critical registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency. The device has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables it to execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional operations further improve performance.

3.2.2 Memory Bus (Harvard Bus Architecture)

As with many DSC type devices, multiple busses are used to move data between the memories and peripherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and memories attached to the memory bus will prioritize memory accesses. Generally, the priority of memory bus accesses can be summarized as follows:

SPRS682–DECEMBER 2010

Highest: Data Writes (Simultaneous data and program writes cannot occur on the memory

Program Writes (Simultaneous data and program writes cannot occur on the memory

Data Reads Program (Simultaneous program reads and fetches cannot occur on the memory

Reads bus.)

Lowest: Fetches (Simultaneous program reads and fetches cannot occur on the memory

3.2.3 Peripheral Bus

To enable migration of peripherals between various Texas Instruments (TI) DSC family of devices, the F28335 adopts a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of 16 address lines and 16 or 32 data lines and associated control signals. Three versions of the peripheral bus are supported. One version supports only 16-bit accesses (called peripheral frame 2). Another version supports both 16- and 32-bit accesses (called peripheral frame 1). The third version supports DMA access and both 16- and 32-bit accesses (called peripheral frame 3).

bus.)

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3.2.4 Real-Time JTAG and Analysis

The F28335 implements the standard IEEE 1149.1 JTAG interface. Additionally, the device supports realtime mode of operation whereby the contents of memory, peripheral and register locations can be modified while the processor is running and executing code and servicing interrupts. The user can also single step through non-time critical code while enabling time-critical interrupts to be serviced without interference. The device implements the real-time mode in hardware within the CPU. This is a feature unique to the F28335, requiring no software monitor. Additionally, special analysis hardware is provided that allows setting of hardware breakpoint or data/address watch-points and generate various userselectable break events when a match occurs.

3.2.5 External Interface (XINTF)

This asynchronous interface consists of 20 address lines, 32 data lines, and three chip-select lines. The chip-select lines are mapped to three external zones, Zones 0, 6, and 7. Each of the three zones can be programmed with a different number of wait states, strobe signal setup and hold timing and each zone can be programmed for extending wait states externally or not. The programmable wait-state, chip-select and programmable strobe timing enables glueless interface to external memories and peripherals.

3.2.6 Flash

The F28335 contains 256K × 16 of embedded flash memory, segregated into eight 32K × 16 sectors and a single 1K × 16 of OTP memory at address range 0x380400 – 0x3807FF. The user can individually erase, program, and validate a flash sector while leaving other sectors untouched. However, it is not possible to use one sector of the flash or the OTP to execute flash algorithms that erase/program other sectors. Special memory pipelining is provided to enable the flash module to achieve higher performance. The flash/OTP is mapped to both program and data space; therefore, it can be used to execute code or store data information. Note that addresses 0x33FFF0 – 0x33FFF5 are reserved for data variables and should not contain program code.

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The Flash and OTP wait-states can be configured by the application. This allows applications running at slower frequencies to configure the flash to use fewer wait-states.

Flash effective performance can be improved by enabling the flash pipeline mode in the Flash options register. With this mode enabled, effective performance of linear code execution will be much faster than the raw performance indicated by the wait-state configuration alone. The exact performance gain when using the Flash pipeline mode is application-dependent.

3.2.7 M0, M1 SARAMs

The F28335 contains these two blocks of single access memory, each 1K × 16 in size. The stack pointer points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to execute code or for data variables. The partitioning is performed within the linker. The C28x device presents a unified memory map to the programmer. This makes for easier programming in high-level languages.

3.2.8 L0, L1, L2, L3, L4, L5, L6, L7 SARAMs

The F28335 contains an additional 32K × 16 of single-access RAM, divided into 8 blocks (L0-L7 with 4K each). Each block can be independently accessed to minimize CPU pipeline stalls. Each block is mapped to both program and data space. L4, L5, L6, and L7 are DMA accessible.

NOTE

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3.2.9 Boot ROM

The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell the bootloader software what boot mode to use on power up. The user can select to boot normally or to download new software from an external connection or to select boot software that is programmed in the internal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use in math related algorithms.

Table 3-4. Boot Mode Selection

MODE GPIO87/XA15 GPIO86/XA14 GPIO85/XA13 GPIO84/XA12 MODE

F 1 1 1 1 Jump to Flash E 1 1 1 0 SCI-A boot D 1 1 0 1 SPI-A boot C 1 1 0 0 I2C-A boot B 1 0 1 1 eCAN-A boot A 1 0 1 0 McBSP-A boot

9 1 0 0 1 Jump to XINTF x16

8 1 0 0 0 Jump to XINTF x32

7 0 1 1 1 Jump to OTP

6 0 1 1 0 Parallel GPIO I/O boot

5 0 1 0 1 Parallel XINTF boot

4 0 1 0 0 Jump to SARAM

3 0 0 1 1 Branch to check boot mode

2 0 0 1 0 Branch to Flash, skip ADC calibration

1 0 0 0 1 Branch to SARAM, skip ADC

calibration

0 0 0 0 0 Branch to SCI, skip ADC calibration

(1) All four GPIO pins have an internal pullup.

(1)

3.2.10 Security

The devices support high levels of security to protect the user firmware from being reverse engineered. The security features a 128-bit password (hardcoded for 16 wait-states), which the user programs into the flash. One code security module (CSM) is used to protect the flash/OTP and the L0/L1/L2/L3 SARAM blocks. The security feature prevents unauthorized users from examining the memory contents via the JTAG port, executing code from external memory or trying to boot-load some undesirable software that would export the secure memory contents. To enable access to the secure blocks, the user must write the correct 128-bit KEY value, which matches the value stored in the password locations within the Flash.

In addition to the CSM, the emulation code security logic (ECSL) has been implemented to prevent unauthorized users from stepping through secure code. Any code or data access to flash, user OTP, L0, L1, L2 or L3 memory while the emulator is connected will trip the ECSL and break the emulation connection. To allow emulation of secure code, while maintaining the CSM protection against secure memory reads, the user must write the correct value into the lower 64 bits of the KEY register, which matches the value stored in the lower 64 bits of the password locations within the flash. Note that dummy reads of all 128 bits of the password in the flash must still be performed. If the lower 64 bits of the password locations are all ones (unprogrammed), then the KEY value does not need to match.

NOTE

Modes 0, 1, and 2 in Table 3-4 are for TI debug only. Skipping the ADC calibration function in an application will cause the ADC to operate outside of the stated specifications

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When initially debugging a device with the password locations in flash programmed (i.e., secured), the emulator takes some time to take control of the CPU. During this time, the CPU will start running and may execute an instruction that performs an access to a protected ECSL area. If this happens, the ECSL will trip and cause the emulator connection to be cut. Two solutions to this problem exist:

1. The first is to use the Wait-In-Reset emulation mode, which will hold the device in reset until the emulator takes control. The emulator must support this mode for this option.

2. The second option is to use the “Branch to check boot mode” boot option. This will sit in a loop and continuously poll the boot mode select pins. The user can select this boot mode and then exit this mode once the emulator is connected by re-mapping the PC to another address or by changing the boot mode selection pin to the desired boot mode.

• When the code-security passwords are programmed, all addresses between 0x33FF80

• If the code security feature is not used, addresses 0x33FF80 through 0x33FFEF may be

The 128-bit password (at 0x33 FFF8 – 0x33 FFFF) must not be programmed to zeros. Doing so would permanently lock the device.

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NOTE

and 0x33FFF5 cannot be used as program code or data. These locations must be programmed to 0x0000.

used for code or data. Addresses 0x33FFF0 – 0x33FFF5 are reserved for data and should not contain program code. .

disclaimer

Code Security Module Disclaimer

THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY (EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE.

TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.

IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.

3.2.11 Peripheral Interrupt Expansion (PIE) Block

The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block can support up to 96 peripheral interrupts. On the F28335, 58 of the possible 96 interrupts are used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can be enabled/disabled within the PIE block.

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3.2.12 External Interrupts (XINT1-XINT7, XNMI)

The devices support eight masked external interrupts (XINT1-XINT7, XNMI). XNMI can be connected to the INT13 or NMI interrupt of the CPU. Each of the interrupts can be selected for negative, positive, or both negative and positive edge triggering and can also be enabled/disabled (including the XNMI). XINT1, XINT2, and XNMI also contain a 16-bit free running up counter, which is reset to zero when a valid interrupt edge is detected. This counter can be used to accurately time stamp the interrupt. Unlike the 281x devices, there are no dedicated pins for the external interrupts. XINT1 XINT2, and XNMI interrupts can accept inputs from GPIO0 – GPIO31 pins. XINT3 – XINT7 interrupts can accept inputs from GPIO32 – GPIO63 pins.

3.2.13 Oscillator and PLL

The device can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit. A PLL is provided supporting up to 10 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly in software, enabling the user to scale back on operating frequency if lower power operation is desired. Refer to the Electrical Specification section for timing details. The PLL block can be set in bypass mode.

3.2.14 Watchdog

The devices contain a watchdog timer. The user software must regularly reset the watchdog counter within a certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog can be disabled if necessary.

SPRS682–DECEMBER 2010

3.2.15 Peripheral Clocking

The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption when a peripheral is not in use. Additionally, the system clock to the serial ports (except I2C and eCAN) and the ADC blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to be decoupled from increasing CPU clock speeds.

3.2.16 Low-Power Modes

The devices are full static CMOS devices. Three low-power modes are provided:

IDLE: Place CPU into low-power mode. Peripheral clocks may be turned off selectively and

only those peripherals that need to function during IDLE are left operating. An enabled interrupt from an active peripheral or the watchdog timer will wake the processor from IDLE mode.

STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL

functional. An external interrupt event will wake the processor and the peripherals. Execution begins on the next valid cycle after detection of the interrupt event

HALT: Turns off the internal oscillator. This mode basically shuts down the device and

places it in the lowest possible power consumption mode. A reset or external signal can wake the device from this mode.

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3.2.17 Peripheral Frames 0, 1, 2, 3 (PFn)

The device segregates peripherals into three sections. The mapping of peripherals is as follows:

PF0: PIE: PIE Interrupt Enable and Control Registers Plus PIE Vector Table

Flash: Flash Waitstate Registers XINTF: External Interface Registers DMA DMA Registers Timers: CPU-Timers 0, 1, 2 Registers CSM: Code Security Module KEY Registers ADC: ADC Result Registers (dual-mapped)

PF1: eCAN: eCAN Mailbox and Control Registers

GPIO: GPIO MUX Configuration and Control Registers ePWM: Enhanced Pulse Width Modulator Module and Registers (dual mapped) eCAP: Enhanced Capture Module and Registers eQEP: Enhanced Quadrature Encoder Pulse Module and Registers

PF2: SYS: System Control Registers

SCI: Serial Communications Interface (SCI) Control and RX/TX Registers SPI: Serial Port Interface (SPI) Control and RX/TX Registers ADC: ADC Status, Control, and Result Register I2C: Inter-Integrated Circuit Module and Registers XINT External Interrupt Registers

PF3: McBSP Multichannel Buffered Serial Port Registers

ePWM: Enhanced Pulse Width Modulator Module and Registers (dual mapped)

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3.2.18 General-Purpose Input/Output (GPIO) Multiplexer

Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins are configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power modes.

3.2.19 32-Bit CPU-Timers (0, 1, 2)

CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The timers have a 32-bit count down register, which generates an interrupt when the counter reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is reserved for Real-Time OS (RTOS)/BIOS applications. It is connected to INT14 of the CPU. If DSP/BIOS is not being used, CPU-Timer 2 is available for general use. CPU-Timer 1 is for general use and can be connected to INT13 of the CPU. CPU-Timer 0 is also for general use and is connected to the PIE block.

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3.2.20 Control Peripherals

The F28335 supports the following peripherals which are used for embedded control and communication:

ePWM: The enhanced PWM peripheral supports independent/complementary PWM

generation, adjustable dead-band generation for leading/trailing edges, latched/cycle-by-cycle trip mechanism. Some of the PWM pins support HRPWM features. The ePWM registers are supported by the DMA to reduce the overhead for servicing this peripheral.

eCAP: The enhanced capture peripheral uses a 32-bit time base and registers up to four

programmable events in continuous/one-shot capture modes. This peripheral can also be configured to generate an auxiliary PWM signal.

eQEP: The enhanced QEP peripheral uses a 32-bit position counter, supports low-speed

measurement using capture unit and high-speed measurement using a 32-bit unit timer. This peripheral has a watchdog timer to detect motor stall and input error detection logic to identify simultaneous edge transition in QEP signals.

ADC: The ADC block is a 12-bit converter, single ended, 16-channels. It contains two

sample-and-hold units for simultaneous sampling. The ADC registers are supported by the DMA to reduce the overhead for servicing this peripheral.

3.2.21 Serial Port Peripherals

SPRS682–DECEMBER 2010

The devices support the following serial communication peripherals:

eCAN: This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time

stamping of messages, and is CAN 2.0B-compliant.

McBSP: The multichannel buffered serial port (McBSP) connects to E1/T1 lines, phone-

quality codecs for modem applications or high-quality stereo audio DAC devices. The McBSP receive and transmit registers are supported by the DMA to significantly reduce the overhead for servicing this peripheral. Each McBSP module can be configured as an SPI as required.

SPI: The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of

programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the DSC and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multi-device communications are supported by the master/slave operation of the SPI. On the F28335, the SPI contains a 16-level receive and transmit FIFO for reducing interrupt servicing overhead.

SCI: The serial communications interface is a two-wire asynchronous serial port,

commonly known as UART. The SCI contains a 16-level receive and transmit FIFO for reducing interrupt servicing overhead.

I2C: The inter-integrated circuit (I2C) module provides an interface between a DSC and

other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the DSC through the I2C module. On the F28335, the I2C contains a 16-level receive and transmit FIFO for reducing interrupt servicing overhead.

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3.3 Register Map

The devices contain four peripheral register spaces. The spaces are categorized as follows:

Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus.

See Table 3-5.

Peripheral Frame 1 These are peripherals that are mapped to the 32-bit peripheral bus. See

Table 3-6.

Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See

Table 3-7.

Peripheral Frame 3: These are peripherals that are mapped to the 32-bit DMA-accessible

peripheral bus. See Table 3-8.

Table 3-5. Peripheral Frame 0 Registers

NAME ADDRESS RANGE SIZE (×16) ACCESS TYPE

Device Emulation Registers 0x00 0880 - 0x00 09FF 384 EALLOW protected FLASH Registers Code Security Module Registers 0x00 0AE0 - 0x00 0AEF 16 EALLOW protected ADC registers (dual-mapped) 0x00 0B00 - 0x00 0B0F 16 Not EALLOW protected

0 wait (DMA), 1 wait (CPU), read only XINTF Registers 0x00 0B20 - 0x00 0B3F 32 Not EALLOW protected CPU–TIMER0/1/2 Registers 0x00 0C00 - 0x00 0C3F 64 Not EALLOW protected PIE Registers 0x00 0CE0 - 0x00 0CFF 32 Not EALLOW protected PIE Vector Table 0x00 0D00 - 0x00 0DFF 256 EALLOW protected DMA Registers 0x00 1000 - 0x00 11FF 512 EALLOW protected

(1) Registers in Frame 0 support 16-bit and 32-bit accesses. (2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction

disables writes to prevent stray code or pointers from corrupting register contents.

(3) The Flash Registers are also protected by the Code Security Module (CSM).

(3)

0x00 0A80 - 0x00 0ADF 96 EALLOW protected

(1)

(2)

Table 3-6. Peripheral Frame 1 Registers

NAME ADDRESS RANGE SIZE (×16)

ECAN-A Registers 0x00 6000 - 0x00 61FF 512 ECAN-B Registers 0x00 6200 - 0x00 63FF 512 EPWM1 + HRPWM1 registers 0x00 6800 - 0x00 683F 64 EPWM2 + HRPWM2 registers 0x00 6840 - 0x00 687F 64 EPWM3 + HRPWM3 registers 0x00 6880 - 0x00 68BF 64 EPWM4 + HRPWM4 registers 0x00 68C0 - 0x00 68FF 64 EPWM5 + HRPWM5 registers 0x00 6900 - 0x00 693F 64 EPWM6 + HRPWM6 registers 0x00 6940 - 0x00 697F 64 ECAP1 registers 0x00 6A00 - 0x00 6A1F 32 ECAP2 registers 0x00 6A20 - 0x00 6A3F 32 ECAP3 registers 0x00 6A40 - 0x00 6A5F 32 ECAP4 registers 0x00 6A60 - 0x00 6A7F 32 ECAP5 registers 0x00 6A80 - 0x00 6A9F 32 ECAP6 registers 0x00 6AA0 - 0x00 6ABF 32 EQEP1 registers 0x00 6B00 - 0x00 6B3F 64 EQEP2 registers 0x00 6B40 - 0x00 6B7F 64 GPIO registers 0x00 6F80 - 0x00 6FFF 128

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Table 3-7. Peripheral Frame 2 Registers

NAME ADDRESS RANGE SIZE (×16)

System Control Registers 0x00 7010 - 0x00 702F 32 SPI-A Registers 0x00 7040 - 0x00 704F 16 SCI-A Registers 0x00 7050 - 0x00 705F 16 External Interrupt Registers 0x00 7070 - 0x00 707F 16 ADC Registers 0x00 7100 - 0x00 711F 32 SCI-B Registers 0x00 7750 - 0x00 775F 16 SCI-C Registers 0x00 7770 - 0x00 777F 16 I2C-A Registers 0x00 7900 - 0x00 793F 64

Table 3-8. Peripheral Frame 3 Registers

NAME ADDRESS RANGE SIZE (×16)

McBSP-A Registers (DMA) 0x5000 – 0x503F 64 McBSP-B Registers (DMA) 0x5040 - 0x507F 64 EPWM1 + HRPWM1 (DMA) EPWM2 + HRPWM2 (DMA) 0x5840 - 0x587F 64 EPWM3 + HRPWM3 (DMA) 0x5880 - 0x58BF 64 EPWM4 + HRPWM4 (DMA) 0x58C0 - 0x58FF 64 EPWM5 + HRPWM5 (DMA) 0x5900 - 0x593F 64 EPWM6 + HRPWM6 (DMA) 0x5940 - 0x597F 64

(1) The ePWM/HRPWM modules can be re-mapped to Peripheral Frame 3 where they can be accessed by the DMA module. To achieve

this, bit 0 (MAPEPWM) of MAPCNF register (address 0x702E) must be set to 1. This register is EALLOW protected. When this bit is 0, the ePWM/HRPWM modules are mapped to Peripheral Frame 1.

(1)

0x5800 – 0x583F 64

3.4 Device Emulation Registers

These registers are used to control the protection mode of the C28x CPU and to monitor some critical device signals. The registers are defined in Table 3-9.

Table 3-9. Device Emulation Registers

NAME SIZE (x16) DESCRIPTION

DEVICECNF 2 Device Configuration Register PARTID 0x380090 1 Part ID Register 0x00EF

CLASSID 0x0882 1 0x00EF REVID 0x0883 1 Revision ID 0x0000 - Silicon Rev. 0 - TMX

PROTSTART 0x0884 1 Block Protection Start Address Register PROTRANGE 0x0885 1 Block Protection Range Address Register

ADDRESS

RANGE

0x0880 0x0881

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WDINT

LPMINT

Watchdog

LowPowerModels

Sync

SYSCLKOUT

WAKEINT

DMA

Clear

Peripherals

(SPI,SCI,I2C,CAN,McBSP

C )

(A),

(A)

EPWM ,ECAP,EQEP, AD

(A)

DMA

XINT1

InterruptControl

XINT1CR(15:0)

XINT1CTR(15:0)

XINT1

Latch

MUX

GPIOXINT1SEL(4:0)

DMA

XINT2

InterruptControl

XINT2CR(15:0)

XINT2CTR(15:0)

XINT2

Latch

MUX

GPIOXINT2SEL(4:0)

ADC

XINT2SOC

DMA

TINT0

CPUTimer0

DMA

TINT2

CPUTimer2

CPUTimer1

MUX

TINT1

FlashWrapper

TOUT1

InterruptControl

XNMICR(15:0)

XNMICTR(15:0)

MUX

DMA

NMI

INT13

INT14

INT1

INT12

C28

Core

96Interrupts

PIE

XNMI_

XINT13

Latch

MUX

GPIOXNMISEL(4:0)

GPIO

Mux

GPIO0.int

GPIO31.int

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3.5 Interrupts

Figure 3-3 shows how the various interrupt sources are multiplexed.

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A. DMA-accessible

Figure 3-3. External and PIE Interrupt Sources

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InterruptControl

XINT3CR(15:0)

Latch

Mux

GPIOXINT3SEL(4:0)

DMA

XINT3

InterruptControl

XINT4CR(15:0)

Latch

Mux

GPIOXINT4SEL(4:0)

XINT4

InterruptControl

XINT5CR(15:0)

Mux

GPIOXINT5SEL(4:0)

XINT5

InterruptControl

XINT6CR(15:0)

Mux

GPIOXINT6SEL(4:0)

XINT6

InterruptControl

XINT7CR(15:0)

Mux

GPIOXINT7SEL(4:0)

XINT7

DMA

96Interrupts

PIE

INT1

INT12

C28

Core

GPIO32.int

GPIO63.int

GPIO

Mux

Latch

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Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8

Figure 3-4. External Interrupts

interrupts per group equals 96 possible interrupts. On the F28335, 58 of these are used by peripherals as shown in Table 3-10.

The TRAP #VectorNumber instruction transfers program control to the interrupt service routine corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore, TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior.

When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector from INT1.1, TRAP #2 fetches the vector from INT2.1, and so forth.

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INT12

MUX

INT11

INT2

INT1

CPU

(Enable)(Flag)

INTx

INTx.8

PIEIERx(8:1) PIEIFRx(8:1)

MUX

INTx.7

INTx.6

INTx.5

INTx.4

INTx.3

INTx.2

INTx.1

From

Peripherals or

External

Interrupts

(Enable) (Flag)

IER(12:1)IFR(12:1)

Global Enable

INTM

PIEACKx

(Enable/Flag)

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Figure 3-5. Multiplexing of Interrupts Using the PIE Block

Table 3-10. PIE Peripheral Interrupts

CPU INTERRUPTS

INT1 XINT2 XINT1 Reserved

INT2 Reserved Reserved

INT3 Reserved Reserved

INT4 Reserved Reserved

INT5 Reserved Reserved Reserved Reserved Reserved Reserved

INT6 Reserved Reserved

INT7 Reserved Reserved

INT8 Reserved Reserved Reserved Reserved

INT9

INT10 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT11 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

INT12 Reserved XINT7 XINT6 XINT5 XINT4 XINT3

INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1

WAKEINT TINT0 ADCINT SEQ2INT SEQ1INT (LPM/WD) (TIMER 0) (ADC) (ADC) (ADC)

EPWM6_TZINT EPWM5_TZINT EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT

(ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1)

EPWM6_INT EPWM5_INT EPWM4_INT EPWM3_INT EPWM2_INT EPWM1_INT

(ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1)

ECAP6_INT ECAP5_INT ECAP4_INT ECAP3_INT ECAP2_INT ECAP1_INT

(ECAP6) (ECAP5) (eCAP4) (eCAP3) (eCAP2) (eCAP1)

MXINTA MRINTA MXINTB MRINTB SPITXINTA SPIRXINTA

(McBSP-A) (McBSP-A) (McBSP-B) (McBSP-B) (SPI-A) (SPI-A)

DINTCH6 DINTCH5 DINTCH4 DINTCH3 DINTCH2 DINTCH1

(DMA) (DMA) (DMA) (DMA) (DMA) (DMA)

SCITXINTC SCIRXINTC I2CINT2A I2CINT1A

(SCI-C) (SCI-C) (I2C-A) (I2C-A)

ECAN1_INTB ECAN0_INTB ECAN1_INTA ECAN0_INTA SCITXINTB SCIRXINTB SCITXINTA SCIRXINTA

(CAN-B) (CAN-B) (CAN-A) (CAN-A) (SCI-B) (SCI-B) (SCI-A) (SCI-A)

LUF LVF

(FPU) (FPU)

(1) Out of the 96 possible interrupts, 58 interrupts are currently used. The remaining interrupts are reserved for future devices. These

interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:

1) No peripheral within the group is asserting interrupts.

2) No peripheral interrupts are assigned to the group (example PIE group 11).

PIE INTERRUPTS

(1)

EQEP2_INT EQEP1_INT

(eQEP2) (eQEP1)

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Table 3-11. PIE Configuration and Control Registers

NAME ADDRESS SIZE (X16) DESCRIPTION

PIECTRL 0x0CE0 1 PIE, Control Register PIEACK 0x0CE1 1 PIE, Acknowledge Register PIEIER1 0x0CE2 1 PIE, INT1 Group Enable Register PIEIFR1 0x0CE3 1 PIE, INT1 Group Flag Register PIEIER2 0x0CE4 1 PIE, INT2 Group Enable Register PIEIFR2 0x0CE5 1 PIE, INT2 Group Flag Register PIEIER3 0x0CE6 1 PIE, INT3 Group Enable Register PIEIFR3 0x0CE7 1 PIE, INT3 Group Flag Register PIEIER4 0x0CE8 1 PIE, INT4 Group Enable Register PIEIFR4 0x0CE9 1 PIE, INT4 Group Flag Register PIEIER5 0x0CEA 1 PIE, INT5 Group Enable Register PIEIFR5 0x0CEB 1 PIE, INT5 Group Flag Register PIEIER6 0x0CEC 1 PIE, INT6 Group Enable Register PIEIFR6 0x0CED 1 PIE, INT6 Group Flag Register PIEIER7 0x0CEE 1 PIE, INT7 Group Enable Register PIEIFR7 0x0CEF 1 PIE, INT7 Group Flag Register PIEIER8 0x0CF0 1 PIE, INT8 Group Enable Register PIEIFR8 0x0CF1 1 PIE, INT8 Group Flag Register PIEIER9 0x0CF2 1 PIE, INT9 Group Enable Register PIEIFR9 0x0CF3 1 PIE, INT9 Group Flag Register PIEIER10 0x0CF4 1 PIE, INT10 Group Enable Register PIEIFR10 0x0CF5 1 PIE, INT10 Group Flag Register PIEIER11 0x0CF6 1 PIE, INT11 Group Enable Register PIEIFR11 0x0CF7 1 PIE, INT11 Group Flag Register PIEIER12 0x0CF8 1 PIE, INT12 Group Enable Register PIEIFR12 0x0CF9 1 PIE, INT12 Group Flag Register Reserved 0x0CFA 6 Reserved

0x0CFF

(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table

is protected.

(1)

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3.5.1 External Interrupts

Name Address Size (x16) Description

XINT1CR 0x00 7070 1 XINT1 configuration register XINT2CR 0x00 7071 1 XINT2 configuration register XINT3CR 0x00 7072 1 XINT3 configuration register XINT4CR 0x00 7073 1 XINT4 configuration register XINT5CR 0x00 7074 1 XINT5 configuration register XINT6CR 0x00 7075 1 XINT6 configuration register XINT7CR 0x00 7076 1 XINT7 configuration register XNMICR 0x00 7077 1 XNMI configuration register XINT1CTR 0x00 7078 1 XINT1 counter register XINT2CTR 0x00 7079 1 XINT2 counter register Reserved 0x707A - 0x707E 5 XNMICTR 0x00 707F 1 XNMI counter register

Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and negative edge.

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Table 3-12. External Interrupt Registers

3.6 System Control

This section describes the oscillator, PLL and clocking mechanisms, the watchdog function and the low power modes. Figure 3-6 shows the various clock and reset domains that will be discussed.

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EPWM1/../6,HRPWM1/../6,

ECAP1/../6,EQEP1/2

Peripheral

Registers

Bridge

ClockEnables

I/O

Peripheral

Registers

ClockEnables

I/O

eCAN-A/B

Peripheral

Registers

ClockEnables

I/O

SPI-A,SCI-A/B/C

LOSPCP

LSPCLK

System Control

Bridge

SYSCLKOUT

MemoryBus

C28xCore

GPIO

Mux

ClockEnables

Peripheral

Registers

I/O

McBSP-A/B

LOSPCP

LSPCLK

ClockEnables

Bridge

HISPCP

HSPCLK

DMA

Bus

Result

Registers

Bridge

12-Bit ADC

ADC

Registers

16Channels

DMA

ClockEnables

PeripheralBus

CLKIN

I2C-A

ClockEnables

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A. CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency

as SYSCLKOUT). See Figure 3-7 for an illustration of how CLKIN is derived.

There is a 2-SYSCLKOUT cycle delay from when the write to PCLKCR0/1/2 registers (enables peripheral clocks) occurs to when the action is valid. This delay must be taken into account before attempting to access the peripheral configuration registers.

Figure 3-6. Clock and Reset Domains

NOTE

The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 3-13.

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XCLKIN

(3.3-Vclockinput

fromexternal

oscillator)

On-chip

oscillator

PLLSTS[OSCOFF]

OSCCLK

PLL

VCOCLK

4-bitMultiplierPLLCR[DIV]

OSCCLKor

VCOCLK

CLKIN

OSCCLK

PLLSTS[PLLOFF]

n ≠ 0

PLLSTS[DIVSEL]

External

Crystalor

Resonator

CPU

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Table 3-13. PLL, Clocking, Watchdog, and Low-Power Mode Registers

Name Address Size (x16) Description

PLLSTS 0x00 7011 1 PLL Status Register Reserved 0x00 7012 - 0x00 7018 7 Reserved HISPCP 0x00 701A 1 High-Speed Peripheral Clock Pre-Scaler Register LOSPCP 0x00 701B 1 Low-Speed Peripheral Clock Pre-Scaler Register PCLKCR0 0x00 701C 1 Peripheral Clock Control Register 0 PCLKCR1 0x00 701D 1 Peripheral Clock Control Register 1 LPMCR0 0x00 701E 1 Low Power Mode Control Register 0 Reserved 0x00 701F 1 Low Power Mode Control Register 1 PCLKCR3 0x00 7020 1 Peripheral Clock Control Register 3 PLLCR 0x00 7021 1 PLL Control Register SCSR 0x00 7022 1 System Control and Status Register WDCNTR 0x00 7023 1 Watchdog Counter Register Reserved 0x00 7024 1 Reserved WDKEY 0x00 7025 1 Watchdog Reset Key Register Reserved 0x00 7026 - 0x00 7028 3 Reserved WDCR 0x00 7029 1 Watchdog Control Register Reserved 0x00 702A - 0x00 702D 6 Reserved MAPCNF 0x00 702E 1 ePWM/HRPWM Re-map Register

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3.6.1 OSC and PLL Block

Figure 3-7 shows the OSC and PLL block.

The on-chip oscillator circuit enables a crystal/resonator to be attached to the F28335 using the X1 and X2 pins. If the on-chip oscillator is not used, an external oscillator can be used in either one of the following configurations:

1. A 3.3-V external oscillator can be directly connected to the XCLKIN pin. The X2 pin should be left unconnected and the X1 pin tied low. The logic-high level in this case should not exceed V

2. A 1.9-V (1.8-V for 100 MHz devices) external oscillator can be directly connected to the X1 pin. The X2 pin should be left unconnected and the XCLKIN pin tied low. The logic-high level in this case should not exceed VDD.

The three possible input-clock configurations are shown in Figure 3-8 through Figure 3-10.

Figure 3-7. OSC and PLL Block Diagram

DDIO

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External Clock Signal

(Toggling 0−V

DDIO

)

XCLKIN

External Clock Signal

(Toggling 0−VDD)

XCLKIN

X2X1

Crystal

XCLKIN

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SPRS682–DECEMBER 2010

Figure 3-8. Using a 3.3-V External Oscillator

Figure 3-9. Using a 1.9-V External Oscillator

Figure 3-10. Using the Internal Oscillator

3.6.1.1 External Reference Oscillator Clock Option

The typical specifications for the external quartz crystal for a frequency of 30 MHz are listed below:

• Fundamental mode, parallel resonant

• CL(load capacitance) = 12 pF

• CL1= CL2= 24 pF

• C

shunt

= 6 pF

• ESR range = 25 to 40 Ω

TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the DSC chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding the proper tank component values that will produce proper start up and stability over the entire operating range.

3.6.1.2 PLL-Based Clock Module

The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes 131072 OSCCLK cycles. The input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of the PLL (VCOCLK) does not exceed 300 MHz.

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Table 3-14. PLLCR

PLLCR[DIV] VALUE

0000 (PLL bypass) OSCCLK/4 (Default) OSCCLK/2 OSCCLK

1011 - 1111 Reserved Reserved Reserved

(1) By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes this to /2.) PLLSTS[DIVSEL] must be 0 before writing to the

PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1.

(2) The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog

reset only. A reset issued by the debugger or the missing clock detect logic have no effect.

(3) This register is EALLOW protected.

(2) (3)

0001 (OSCCLK * 1)/4 (OSCCLK * 1)/2 – 0010 (OSCCLK * 2)/4 (OSCCLK * 2)/2 – 0011 (OSCCLK * 3)/4 (OSCCLK * 3)/2 – 0100 (OSCCLK * 4)/4 (OSCCLK * 4)/2 – 0101 (OSCCLK * 5)/4 (OSCCLK * 5)/2 – 0110 (OSCCLK * 6)/4 (OSCCLK * 6)/2 – 0111 (OSCCLK * 7)/4 (OSCCLK * 7)/2 – 1000 (OSCCLK * 8)/4 (OSCCLK * 8)/2 – 1001 (OSCCLK * 9)/4 (OSCCLK * 9)/2 – 1010 (OSCCLK * 10)/4 (OSCCLK * 10)/2 –

PLLSTS[DIVSEL] = 0 or 1

(1)

Bit Descriptions

SYSCLKOUT (CLKIN)

PLLSTS[DIVSEL] = 2 PLLSTS[DIVSEL] = 3

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Table 3-15. CLKIN Divide Options

PLLSTS [DIVSEL] CLKIN DIVIDE

0 /4 1 /4 2 /2 3 /1

(1) This mode can be used only when the PLL is bypassed or off.

(1)

The PLL-based clock module provides two modes of operation:

• Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time base to the device.

• External clock source operation - This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external clock source input on the X1 or the XCLKIN pin.

Table 3-16. Possible PLL Configuration Modes

PLL MODE REMARKS PLLSTS[DIVSEL]

Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block

PLL Off power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass) 2 OSCCLK/2

PLL Bypass 2 OSCCLK/2

PLL Enable

is disabled in this mode. This can be useful to reduce system noise and for low 0, 1 OSCCLK/4 before entering this mode. The CPU clock (CLKIN) is derived directly from the 3 OSCCLK/1

input clock on either X1/X2, X1 or XCLKIN. PLL Bypass is the default PLL configuration upon power-up or after an external

reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or while the PLL locks to a new frequency after the PLLCR register has been modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.

Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the 0, 1 OSCCLK*n/4 PLLCR the device will switch to PLL Bypass mode until the PLL locks. 2 OSCCLK*n/2

0, 1 OSCCLK/4

3 OSCCLK/1

CLKIN AND

SYSCLKOUT

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/512

OSCCLK

WDCR(WDPS[2:0])

WDCLK

WDCNTR(7:0)

WDKEY(7:0)

GoodKey

1 0 1

WDCR(WDCHK[2:0])

Bad WDCHK Key

WDCR(WDDIS)

ClearCounter

SCSR(WDENINT)

Watchdog

Prescaler

Generate

OutputPulse

(512OSCCLKs)

8-Bit

Watchdog

Counter

CLR

WDRST

WDINT

Watchdog

55+AA

KeyDetector

XRS

Core-reset

WDRST

(A)

Internal

Pullup

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3.6.1.3 Loss of Input Clock

In PLL-enabled and PLL-bypass mode, if the input clock OSCCLK is removed or absent, the PLL will still issue a limp-mode clock. The limp-mode clock continues to clock the CPU and peripherals at a typical frequency of 1-5 MHz. Limp mode is not specified to work from power-up, only after input clocks have been present initially. In PLL bypass mode, the limp mode clock from the PLL is automatically routed to the CPU if the input clock is removed or absent.

Normally, when the input clocks are present, the watchdog counter decrements to initiate a watchdog reset or WDINT interrupt. However, when the external input clock fails, the watchdog counter stops decrementing (i.e., the watchdog counter does not change with the limp-mode clock). In addition to this, the device will be reset and the “Missing Clock Status” (MCLKSTS) bit will be set. These conditions could be used by the application firmware to detect the input clock failure and initiate necessary shut-down procedure for the system.

Applications in which the correct CPU operating frequency is absolutely critical should implement a mechanism by which the DSC will be held in reset, should the input clocks ever fail. For example, an R-C circuit may be used to trigger the XRS pin of the DSC, should the capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a periodic basis to prevent it from getting fully charged. Such a circuit would also help in detecting failure of the flash memory and the V

NOTE

DD3VFL

SPRS682–DECEMBER 2010

rail.

3.6.2 Watchdog Block

The watchdog block on the F28335 is similar to the one used on the 240x and 281x devices. The watchdog module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter has reached its maximum value. To prevent this, the user disables the counter or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset the watchdog counter. Figure 3-11 shows the various functional blocks within the watchdog module.

A. TheWDRST signal is driven low for 512 OSCCLK cycles.

The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.

Figure 3-11. Watchdog Module

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In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is the watchdog. The WATCHDOG module will run off OSCCLK. The WDINT signal is fed to the LPM block so that it can wake the device from STANDBY (if enabled). See Section Section 3.7, LowPower Modes Block, for more details.

In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of IDLE mode.

In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so is the WATCHDOG.

3.7 Low-Power Modes Block

The low-power modes on the F28335 are similar to the 240x devices. Table 3-17 summarizes the various modes.

Table 3-17. Low-Power Modes

(3)

, XNMI

(1)

MODE LPMCR0(1:0) OSCCLK CLKIN SYSCLKOUT EXIT

IDLE 00 On On On

STANDBY 01 Off Off

HALT 1X (oscillator and PLL turned off, Off Off

(1) The Exit column lists which signals or under what conditions the low power mode will be exited. A low signal, on any of the signals, will

exit the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise the IDLE mode will not be exited and the device will go back into the indicated low power mode.

(2) The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the CPU (SYSCLKOUT) is

still functional while on the 24x/240x the clock is turned off.

(3) On the C28x, the JTAG port can still function even if the CPU clock (CLKIN) is turned off.

(watchdog still running) signal, debugger

watchdog not functional)

On XRS, Watchdog interrupt, GPIO Port A

Off

(2)

XRS, Watchdog interrupt, any enabled interrupt, XNMI

XRS, GPIO Port A signal, XNMI, debugger

(3)

The various low-power modes operate as follows:

IDLE Mode: This mode is exited by any enabled interrupt or an XNMI that is recognized

by the processor. The LPM block performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0,0.

STANDBY Mode: Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY

mode. The user must select which signal(s) will wake the device in the GPIOLPMSEL register. The selected signal(s) are also qualified by the OSCCLK before waking the device. The number of OSCCLKs is specified in the LPMCR0 register.

HALT Mode: Only the XRS and any GPIO port A signal (GPIO[31:0]) can wake the

device from HALT mode. The user selects the signal in the GPIOLPMSEL register.

The low-power modes do not affect the state of the output pins (PWM pins included). They will be in whatever state the code left them in when the IDLE instruction was executed.

NOTE

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4 Peripherals

The integrated peripherals of the F28335 are described in the following subsections:

• 6-channel Direct Memory Access (DMA)

• Three 32-bit CPU-Timers

• Up to six enhanced PWM modules (ePWM1, ePWM2, ePWM3, ePWM4, ePWM5, ePWM6)

• Up to six enhanced capture modules (eCAP1, eCAP2, eCAP3, eCAP4, eCAP5, eCAP6)

• Up to two enhanced QEP modules (eQEP1, eQEP2)

• Enhanced analog-to-digital converter (ADC) module

• Up to two enhanced controller area network (eCAN) modules (eCAN-A, eCAN-B)

• Up to three serial communications interface modules (SCI-A, SCI-B, SCI-C)

• One serial peripheral interface (SPI) module (SPI-A)

• Inter-integrated circuit module (I2C)

• Up to two multichannel buffered serial port (McBSP-A, McBSP-B) modules

• Digital I/O and shared pin functions

• External Interface (XINTF)

4.1 DMA Overview

Features:

• 6 Channels with independent PIE interrupts

• Trigger Sources: – ePWM SOCA/SOCB – ADC Sequencer 1 and Sequencer 2 – McBSP-A and McBSP-B transmit and receive logic – XINT1-7 and XINT13 – CPU Timers – Software

• Data Sources/Destinations: – L4-L7 16K × 16 SARAM – All XINTF zones – ADC Memory Bus mapped RESULT registers – McBSP-A and McBSP-B transmit and receive buffers – ePWM registers

• Word Size: 16-bit or 32-bit (McBSPs limited to 16-bit)

• Throughput: 4 cycles/word (5 cycles/word for McBSP reads)

SPRS682–DECEMBER 2010

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ADC RESULT registers

ADC CPU

PF0

I/F

ADC

DMA

PF0

I/F

ADC

control

and RESULT registers

ADC

PF2

I/F

L4 I/F

L4 SARAM (4Kx16)

L5 I/F

L5 SARAM (4Kx16)

L6 I/F

L6 SARAM (4Kx16)

L7 I/F

L7 SARAM (4Kx16)

PF3

I/F

McBSP A

McBSP B

Event

triggers

DMA

6-ch

External

interrupts

CPU

timers

CPUbus

DMA bus

PIE

INT7

DINT[CH1:CH6]

CPU

XINTFzonesinterface

XINTFmemoryzones

ePWM/

HRPWM

registers

(A)

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A. The ePWM/HRPWM registers must be remapped to PF3 (through bit 0 of the MAPCNF register) before they can be

accessed by the DMA. The ePWM/HRPWM connection to DMA is not present in silicon revision 0.

Figure 4-1. DMA Functional Block Diagram

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Borrow

Reset

Timer Reload

SYSCLKOUT

TCR.4

(Timer Start Status)

TINT

16-Bit Timer Divide-Down

TDDRH:TDDR

32-Bit Timer Period

PRDH:PRD

32-Bit Counter

TIMH:TIM

16-Bit Prescale Counter

PSCH:PSC

Borrow

INT1

INT12

INT14

28x

CPU

TINT2

TINT0

PIE

CPU-TIMER0

CPU-TIMER2

(ReservedforDSP/BIOS)

INT13

TINT1

CPU-TIMER1

XINT13

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4.2 32-Bit CPU-Timers 0/1/2

There are three 32-bit CPU-timers on the devices (CPU-TIMER0/1/2). Timer 2 is reserved for DSP/BIOS™. CPU-Timer 0 and CPU-Timer 1 can be used in user applications.

These timers are different from the timers that are present in the ePWM modules.

NOTE: If the application is not using DSP/BIOS, then CPU-Timer 2 can be used in the application.

SPRS682–DECEMBER 2010

NOTE

Figure 4-2. CPU-Timers

The timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 4-3.

A. The timer registers are connected to the memory bus of the C28x processor. B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock.

Figure 4-3. CPU-Timer Interrupt Signals and Output Signal

The general operation of the timer is as follows: The 32-bit counter register "TIMH:TIM" is loaded with the value in the period register "PRDH:PRD". The counter register decrements at the SYSCLKOUT rate of the C28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed in Table 4-1 are used to configure the timers.

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Table 4-1. CPU-Timers 0, 1, 2 Configuration and Control Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

TIMER0TIM 0x0C00 1 CPU-Timer 0, Counter Register TIMER0TIMH 0x0C01 1 CPU-Timer 0, Counter Register High TIMER0PRD 0x0C02 1 CPU-Timer 0, Period Register TIMER0PRDH 0x0C03 1 CPU-Timer 0, Period Register High TIMER0TCR 0x0C04 1 CPU-Timer 0, Control Register Reserved 0x0C05 1 TIMER0TPR 0x0C06 1 CPU-Timer 0, Prescale Register TIMER0TPRH 0x0C07 1 CPU-Timer 0, Prescale Register High TIMER1TIM 0x0C08 1 CPU-Timer 1, Counter Register TIMER1TIMH 0x0C09 1 CPU-Timer 1, Counter Register High TIMER1PRD 0x0C0A 1 CPU-Timer 1, Period Register TIMER1PRDH 0x0C0B 1 CPU-Timer 1, Period Register High TIMER1TCR 0x0C0C 1 CPU-Timer 1, Control Register Reserved 0x0C0D 1 TIMER1TPR 0x0C0E 1 CPU-Timer 1, Prescale Register TIMER1TPRH 0x0C0F 1 CPU-Timer 1, Prescale Register High TIMER2TIM 0x0C10 1 CPU-Timer 2, Counter Register TIMER2TIMH 0x0C11 1 CPU-Timer 2, Counter Register High TIMER2PRD 0x0C12 1 CPU-Timer 2, Period Register TIMER2PRDH 0x0C13 1 CPU-Timer 2, Period Register High TIMER2TCR 0x0C14 1 CPU-Timer 2, Control Register Reserved 0x0C15 1 TIMER2TPR 0x0C16 1 CPU-Timer 2, Prescale Register TIMER2TPRH 0x0C17 1 CPU-Timer 2, Prescale Register High

Reserved 40

0x0C18 0x0C3F

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PIE

TZ1

toTZ6

PeripheralBus

ePWM1module

ePWM2module

ePWMxmodule

EPWM1SYNCI

EPWM2SYNCI

EPWM2SYNCO

EPWMxSYNCI

EPWMxSYNCO

ADC

GPIO

MUX

EPWM1SYNCI

EPWM1SYNCO

ADCSOCxO

(A)

EPWMxA

EPWMxB

EPWM2A

EPWM2B

EPWM1A

EPWM1B

EPWM1INT

EPWM1SOC

EPWM2INT

EPWM2SOC

EPWMxINT

EPWMxSOC

toeCAP1

andePWM4

module

(syncin)

TZ1

toTZ6

TZ1 toTZ6

EPWM1SYNCO

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4.3 Enhanced PWM Modules (ePWM1/2/3/4/5/6)

The F28335 contains up to six enhanced PWM Modules (ePWM). Figure 4-4 shows a block diagram of multiple ePWM modules. Figure 4-4 shows the signal interconnections with the ePWM.

Table 4-2 shows the complete ePWM register set per module and Table 4-3 shows the remapped register

configuration.

SPRS682–DECEMBER 2010

A. ADCSOCxO is sent to the DMA as well when the ePWM registers are remapped to PF3 (through bit 0 of the

MAPCNF register).

B. By default, ePWM/HRPWM registers are mapped to Peripheral Frame 1 (PF1). Table 4-2 shows this configuration. To

re-map the registers to Peripheral Frame 3 (PF3) to enable DMA access, bit 0 (MAPEPWM) of MAPCNF register (address 0x702E) must be set to 1. Table 4-3 shows the remapped configuration.

Figure 4-4. Multiple PWM Modules

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Table 4-2. ePWM Control and Status Registers (default configuration in PF1)

NAME EPWM1 EPWM2 EPWM3 EPWM4 EPWM5 EPWM6 DESCRIPTION

TBCTL 0x6800 0x6840 0x6880 0x68C0 0x6900 0x6940 1 / 0 Time Base Control Register TBSTS 0x6801 0x6841 0x6881 0x68C1 0x6901 0x6941 1 / 0 Time Base Status Register TBPHSHR 0x6802 0x6842 0x6882 0x68C2 0x6902 0x6942 1 / 0 Time Base Phase HRPWM Register TBPHS 0x6803 0x6843 0x6883 0x68C3 0x6903 0x6943 1 / 0 Time Base Phase Register TBCTR 0x6804 0x6844 0x6884 0x68C4 0x6904 0x6944 1 / 0 Time Base Counter Register TBPRD 0x6805 0x6845 0x6885 0x68C5 0x6905 0x6945 1 / 1 Time Base Period Register Set CMPCTL 0x6807 0x6847 0x6887 0x68C7 0x6907 0x6947 1 / 0 Counter Compare Control Register CMPAHR 0x6808 0x6848 0x6888 0x68C8 0x6908 0x6948 1 / 1 Time Base Compare A HRPWM Register CMPA 0x6809 0x6849 0x6889 0x68C9 0x6909 0x6949 1 / 1 Counter Compare A Register Set CMPB 0x680A 0x684A 0x688A 0x68CA 0x690A 0x694A 1 / 1 Counter Compare B Register Set AQCTLA 0x680B 0x684B 0x688B 0x68CB 0x690B 0x694B 1 / 0 Action Qualifier Control Register For Output A AQCTLB 0x680C 0x684C 0x688C 0x68CC 0x690C 0x694C 1 / 0 Action Qualifier Control Register For Output B AQSFRC 0x680D 0x684D 0x688D 0x68CD 0x690D 0x694D 1 / 0 Action Qualifier Software Force Register AQCSFRC 0x680E 0x684E 0x688E 0x68CE 0x690E 0x694E 1 / 1 Action Qualifier Continuous S/W Force Register Set DBCTL 0x680F 0x684F 0x688F 0x68CF 0x690F 0x694F 1 / 1 Dead-Band Generator Control Register DBRED 0x6810 0x6850 0x6890 0x68D0 0x6910 0x6950 1 / 0 Dead-Band Generator Rising Edge Delay Count Register DBFED 0x6811 0x6851 0x6891 0x68D1 0x6911 0x6951 1 / 0 Dead-Band Generator Falling Edge Delay Count Register TZSEL 0x6812 0x6852 0x6892 0x68D2 0x6912 0x6952 1 / 0 Trip Zone Select Register TZCTL 0x6814 0x6854 0x6894 0x68D4 0x6914 0x6954 1 / 0 Trip Zone Control Register TZEINT 0x6815 0x6855 0x6895 0x68D5 0x6915 0x6955 1 / 0 Trip Zone Enable Interrupt Register TZFLG 0x6816 0x6856 0x6896 0x68D6 0x6916 0x6956 1 / 0 Trip Zone Flag Register TZCLR 0x6817 0x6857 0x6897 0x68D7 0x6917 0x6957 1 / 0 Trip Zone Clear Register TZFRC 0x6818 0x6858 0x6898 0x68D8 0x6918 0x6958 1 / 0 Trip Zone Force Register ETSEL 0x6819 0x6859 0x6899 0x68D9 0x6919 0x6959 1 / 0 Event Trigger Selection Register ETPS 0x681A 0x685A 0x689A 0x68DA 0x691A 0x695A 1 / 0 Event Trigger Prescale Register ETFLG 0x681B 0x685B 0x689B 0x68DB 0x691B 0x695B 1 / 0 Event Trigger Flag Register ETCLR 0x681C 0x685C 0x689C 0x68DC 0x691C 0x695C 1 / 0 Event Trigger Clear Register ETFRC 0x681D 0x685D 0x689D 0x68DD 0x691D 0x695D 1 / 0 Event Trigger Force Register PCCTL 0x681E 0x685E 0x689E 0x68DE 0x691E 0x695E 1 / 0 PWM Chopper Control Register HRCNFG 0x6820 0x6860 0x68A0 0x68E0 0x6920 0x6960 1 / 0 HRPWM Configuration Register

(1) Registers that are EALLOW protected.

SIZE (x16) /

#SHADOW

(1)

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Table 4-3. ePWM Control and Status Registers (remapped configuration in PF3 - DMA accessible)

NAME EPWM1 EPWM2 EPWM3 EPWM4 EPWM5 EPWM6 DESCRIPTION

TBCTL 0x5800 0x5840 0x5880 0x58C0 0x5900 0x5940 1 / 0 Time Base Control Register TBSTS 0x5801 0x5841 0x5881 0x58C1 0x5901 0x5941 1 / 0 Time Base Status Register TBPHSHR 0x5802 0x5842 0x5882 0x58C2 0x5902 0x5942 1 / 0 Time Base Phase HRPWM Register TBPHS 0x5803 0x5843 0x5883 0x58C3 0x5903 0x5943 1 / 0 Time Base Phase Register TBCTR 0x5804 0x5844 0x5884 0x58C4 0x5904 0x5944 1 / 0 Time Base Counter Register TBPRD 0x5805 0x5845 0x5885 0x58C5 0x5905 0x5945 1 / 1 Time Base Period Register Set CMPCTL 0x5807 0x5847 0x5887 0x58C7 0x5907 0x5947 1 / 0 Counter Compare Control Register CMPAHR 0x5808 0x5848 0x5888 0x58C8 0x5908 0x5948 1 / 1 Time Base Compare A HRPWM Register CMPA 0x5809 0x5849 0x5889 0x58C9 0x5909 0x5949 1 / 1 Counter Compare A Register Set CMPB 0x580A 0x584A 0x588A 0x58CA 0x590A 0x594A 1 / 1 Counter Compare B Register Set AQCTLA 0x580B 0x584B 0x588B 0x58CB 0x590B 0x594B 1 / 0 Action Qualifier Control Register For Output A AQCTLB 0x580C 0x584C 0x588C 0x58CC 0x590C 0x594C 1 / 0 Action Qualifier Control Register For Output B AQSFRC 0x580D 0x584D 0x588D 0x58CD 0x590D 0x594D 1 / 0 Action Qualifier Software Force Register AQCSFRC 0x580E 0x584E 0x588E 0x58CE 0x590E 0x594E 1 / 1 Action Qualifier Continuous S/W Force Register Set DBCTL 0x580F 0x584F 0x588F 0x58CF 0x590F 0x594F 1 / 1 Dead-Band Generator Control Register DBRED 0x5810 0x5850 0x5890 0x58D0 0x5910 0x5950 1 / 0 Dead-Band Generator Rising Edge Delay Count Register DBFED 0x5811 0x5851 0x5891 0x58D1 0x5911 0x5951 1 / 0 Dead-Band Generator Falling Edge Delay Count Register TZSEL 0x5812 0x5852 0x5892 0x58D2 0x5912 0x5952 1 / 0 Trip Zone Select Register TZCTL 0x5814 0x5854 0x5894 0x58D4 0x5914 0x5954 1 / 0 Trip Zone Control Register TZEINT 0x5815 0x5855 0x5895 0x58D5 0x5915 0x5955 1 / 0 Trip Zone Enable Interrupt Register TZFLG 0x5816 0x5856 0x5896 0x58D6 0x5916 0x5956 1 / 0 Trip Zone Flag Register TZCLR 0x5817 0x5857 0x5897 0x58D7 0x5917 0x5957 1 / 0 Trip Zone Clear Register TZFRC 0x5818 0x5858 0x5898 0x58D8 0x5918 0x5958 1 / 0 Trip Zone Force Register ETSEL 0x5819 0x5859 0x5899 0x58D9 0x5919 0x5959 1 / 0 Event Trigger Selection Register ETPS 0x581A 0x585A 0x589A 0x58DA 0x591A 0x595A 1 / 0 Event Trigger Prescale Register ETFLG 0x581B 0x585B 0x589B 0x58DB 0x591B 0x595B 1 / 0 Event Trigger Flag Register ETCLR 0x581C 0x585C 0x589C 0x58DC 0x591C 0x595C 1 / 0 Event Trigger Clear Register ETFRC 0x581D 0x585D 0x589D 0x58DD 0x591D 0x595D 1 / 0 Event Trigger Force Register PCCTL 0x581E 0x585E 0x589E 0x58DE 0x591E 0x595E 1 / 0 PWM Chopper Control Register HRCNFG 0x5820 0x5860 0x58A0 058E0 0x5920 0x5960 1 / 0 HRPWM Configuration Register

(1) Registers that are EALLOW protected.

SIZE (x16) /

#SHADOW

(1)

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CTR=PRD

TBPRDshadow(16)

TBPRDactive(16)

Counter

up/down

(16bit)

TBCNT

active(16)

TBCTL[CNTLDE]

TBCTL[SWFSYNC] (softwareforcedsync)

EPWMxSYNCI

CTR=ZERO

CTR_Dir

CTR=CMPB

Disabled

Sync

in/out

select

Mux

TBCTL[SYNCOSEL]

EPWMxSYNCO

TBPHSactive(24)

TBPHSHR(8)

Phase control

Time−base(TB)

CTR=CMPA

CMPAactive(24)

CMPAshadow(24)

Action

qualifier

(AQ)

Countercompare(CC)

CMPBactive(16)

CTR=CMPB

CMPBshadow(16)

CMPAHR(8)

EPWMA

EPWMB

Dead band

(DB) (PC)

chopper

PWM

zone

(TZ)

Trip

CTR=ZERO

EPWMxAO

EPWMxBO

EPWMxTZINT

TZ1 toTZ6

HiResPWM(HRPWM)

CTR=PRD

CTR=ZERO

CTR=CMPB

CTR=CMPA

CTR_Dir

Event

trigger

and

interrupt

(ET)

EPWMxINT

EPWMxSOCA

EPWMxSOCB

CTR=ZERO

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Figure 4-5. ePWM Submodules Showing Critical Internal Signal Interconnections

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4.4 High-Resolution PWM (HRPWM)

The HRPWM module offers PWM resolution (time granularity) which is significantly better than what can be achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:

• Significantly extends the time resolution capabilities of conventionally derived digital PWM

• Typically used when effective PWM resolution falls below ~ 9-10 bits. This occurs at PWM frequencies greater than ~200 kHz when using a CPU/System clock of 100 MHz.

• This capability can be utilized in both duty cycle and phase-shift control methods.

• Finer time granularity control or edge positioning is controlled via extensions to the Compare A and Phase registers of the ePWM module.

• HRPWM capabilities are offered only on the A signal path of an ePWM module (i.e., on the EPWMxA output). EPWMxB output has conventional PWM capabilities.

4.5 Enhanced CAP Modules (eCAP1/2/3/4/5/6)

The F28335 contains up to six enhanced capture (eCAP) modules. Figure 4-6 shows a functional block diagram of a module.

SPRS682–DECEMBER 2010

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TSCTR

(counter−32 bit)

RST

CAP1

(APRD active)

CAP2

(ACMP active)

CAP3

(APRD shadow)

CAP4

(ACMP shadow)

Continuous /

Oneshot

Capture Control

LD1

LD2

LD3

LD4

PRD [0−31]

CMP [0−31]

CTR [0−31]

eCAPx

Interrupt

Trigger

and

Flag

control

to PIE

CTR=CMP

ACMP

shadow

Event

Pre-scale

CTRPHS

(phase register−32 bit)

SYNCOut

SYNCIn

Event

qualifier

Polarity

select

Polarity

select

Polarity

select

Polarity

select

CTR=PRD

CTR_OVF

PWM

compare

logic

CTR [0−31] PRD [0−31]

CMP [0−31]

CTR=CMP

CTR=PRD

CTR_OVF

OVF

APWM mode

Delta−mode

SYNC

Capture events

CEVT[1:4]

APRD

shadow

MODE SELECT

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Figure 4-6. eCAP Functional Block Diagram

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The eCAP modules are clocked at the SYSCLKOUT rate. The clock enable bits (ECAP1/2/3/4/5/6ENCLK) in the PCLKCR1 register are used to turn off the eCAP modules individually (for low power

operation). Upon reset, ECAP1ENCLK, ECAP2ENCLK, ECAP3ENCLK, ECAP4ENCLK, ECAP5ENCLK, and ECAP6ENCLK are set to low, indicating that the peripheral clock is off.

Table 4-4. eCAP Control and Status Registers

NAME ECAP1 ECAP2 ECAP3 ECAP4 ECAP5 ECAP6 SIZE (x16) DESCRIPTION

TSCTR 0x6A00 0x6A20 0x6A40 0x6A60 0x6A80 0x6AA0 2 Time-Stamp Counter

CTRPHS 0x6A02 0x6A22 0x6A42 0x6A62 0x6A82 0x6AA2 2 Counter Phase Offset Value Register

CAP1 0x6A04 0x6A24 0x6A44 0x6A64 0x6A84 0x6AA4 2 Capture 1 Register CAP2 0x6A06 0x6A26 0x6A46 0x6A66 0x6A86 0x6AA6 2 Capture 2 Register CAP3 0x6A08 0x6A28 0x6A48 0x6A68 0x6A88 0x6AA8 2 Capture 3 Register CAP4 0x6A0A 0x6A2A 0x6A4A 0x6A6A 0x6A8A 0x6AAA 2 Capture 4 Register

Reserved 0x6A0C- 0x6A2C-0x6A32 0x6A4C- 0x6A52 0x6A6C- 0x6A72 0x6A8C- 0x6AAC- 8 Reserved

ECCTL1 0x6A14 0x6A34 0x6A54 0x6A74 0x6A94 0x6AB4 1 Capture Control Register 1 ECCTL2 0x6A15 0x6A35 0x6A55 0x6A75 0x6A95 0x6AB5 1 Capture Control Register 2 ECEINT 0x6A16 0x6A36 0x6A56 0x6A76 0x6A96 0x6AB6 1 Capture Interrupt Enable Register

ECFLG 0x6A17 0x6A37 0x6A57 0x6A77 0x6A97 0x6AB7 1 Capture Interrupt Flag Register ECCLR 0x6A18 0x6A38 0x6A58 0x6A78 0x6A98 0x6AB8 1 Capture Interrupt Clear Register

ECFRC 0x6A19 0x6A39 0x6A59 0x6A79 0x6A99 0x6AB9 1 Capture Interrupt Force Register

Reserved 0x6A1A- 0x6A3A- 0x6A3F 0x6A5A- 0x6A5F 0x6A7A- 0x6A7F 0x6A9A- 0x6ABA- 6 Reserved

0x6A12 0x6A92 0x6AB2

0x6A1F 0x6A9F 0x6ABF

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QWDTMR QWDPRD

QWDOG

UTIME

QUPRD

QUTMR

UTOUT

WDTOUT

Quadrature

capture unit

(QCAP)

QCPRDLAT

QCTMRLAT

QFLG

QEPSTS

QEPCTL

Registers

used by

multiple units

QCLK

QDIR

PHE

PCSOUT

Quadrature

decoder

(QDU)

QDECCTL

Position counter/

control unit

(PCCU)

QPOSLAT

QPOSSLAT

QPOSILAT

EQEPxAIN EQEPxBIN

EQEPxIIN

EQEPxIOUT

EQEPxIOE EQEPxSIN

EQEPxSOUT

EQEPxSOE

GPIO

MUX

EQEPxA/XCLK

EQEPxB/XDIR

EQEPxS

EQEPxI

QPOSCMP

QEINT

QFRC

QCLR

QPOSCTL

1632

QPOSCNT

QPOSMAX

QPOSINIT

PIE

EQEPxINT

Enhanced QEP (eQEP) peripheral

System

control registers

QCTMR

QCPRD

1616

QCAPCTL

EQEPxENCLK

SYSCLKOUT

Data bus

To CPU

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4.6 Enhanced QEP Modules (eQEP1/2)

The device contains up to two enhanced quadrature encoder (eQEP) modules.

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Figure 4-7. eQEP Functional Block Diagram

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Table 4-5. eQEP Control and Status Registers

NAME SIZE(x16)/ REGISTER DESCRIPTION

QPOSCNT 0x6B00 0x6B40 2/0 eQEP Position Counter QPOSINIT 0x6B02 0x6B42 2/0 eQEP Initialization Position Count QPOSMAX 0x6B04 0x6B44 2/0 eQEP Maximum Position Count QPOSCMP 0x6B06 0x6B46 2/1 eQEP Position-compare QPOSILAT 0x6B08 0x6B48 2/0 eQEP Index Position Latch QPOSSLAT 0x6B0A 0x6B4A 2/0 eQEP Strobe Position Latch QPOSLAT 0x6B0C 0x6B4C 2/0 eQEP Position Latch QUTMR 0x6B0E 0x6B4E 2/0 eQEP Unit Timer QUPRD 0x6B10 0x6B50 2/0 eQEP Unit Period Register QWDTMR 0x6B12 0x6B52 1/0 eQEP Watchdog Timer QWDPRD 0x6B13 0x6B53 1/0 eQEP Watchdog Period Register QDECCTL 0x6B14 0x6B54 1/0 eQEP Decoder Control Register QEPCTL 0x6B15 0x6B55 1/0 eQEP Control Register QCAPCTL 0x6B16 0x6B56 1/0 eQEP Capture Control Register QPOSCTL 0x6B17 0x6B57 1/0 eQEP Position-compare Control Register QEINT 0x6B18 0x6B58 1/0 eQEP Interrupt Enable Register QFLG 0x6B19 0x6B59 1/0 eQEP Interrupt Flag Register QCLR 0x6B1A 0x6B5A 1/0 eQEP Interrupt Clear Register QFRC 0x6B1B 0x6B5B 1/0 eQEP Interrupt Force Register QEPSTS 0x6B1C 0x6B5C 1/0 eQEP Status Register QCTMR 0x6B1D 0x6B5D 1/0 eQEP Capture Timer QCPRD 0x6B1E 0x6B5E 1/0 eQEP Capture Period Register QCTMRLAT 0x6B1F 0x6B5F 1/0 eQEP Capture Timer Latch QCPRDLAT 0x6B20 0x6B60 1/0 eQEP Capture Period Latch Reserved 0x6B21- 0x6B61- 31/0

EQEP1 EQEP2

ADDRESS ADDRESS

0x6B3F 0x6B7F

EQEP1

#SHADOW

SPRS682–DECEMBER 2010

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Digital Value + 0,

Digital Value + 4096

Input Analog Voltage* ADCLO

when input ≤ 0 V

when 0 V < input < 3 V

when input ≥ 3 VDigital Value + 4095,

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4.7 Analog-to-Digital Converter (ADC) Module

A simplified functional block diagram of the ADC module is shown in Figure 4-8. The ADC module consists of a 12-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include:

• 12-bit ADC core with built-in S/H

• Analog input: 0.0 V to 3.0 V (Voltages above 3.0 V produce full-scale conversion results.)

• Fast conversion rate: Up to 80 ns at 25-MHz ADC clock, 12.5 MSPS

• 16-channel, MUXed inputs

• Autosequencing capability provides up to 16 "autoconversions" in a single session. Each conversion can be programmed to select any 1 of 16 input channels

• Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer (i.e., two cascaded 8-state sequencers)

• Sixteen result registers (individually addressable) to store conversion values – The digital value of the input analog voltage is derived by:

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A. All fractional values are truncated.

• Multiple triggers as sources for the start-of-conversion (SOC) sequence – S/W - software immediate start – ePWM start of conversion – XINT2 ADC start of conversion

• Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS.

• Sequencer can operate in "start/stop" mode, allowing multiple "time-sequenced triggers" to synchronize conversions.

• SOCA and SOCB triggers can operate independently in dual-sequencer mode.

• Sample-and-hold (S/H) acquisition time window has separate prescale control.

The ADC module in the F28335 has been enhanced to provide flexible interface to ePWM peripherals. The ADC interface is built around a fast, 12-bit ADC module with a fast conversion rate of up to 80 ns at 25-MHz ADC clock. The ADC module has 16 channels, configurable as two independent 8-channel modules. The two independent 8-channel modules can be cascaded to form a 16-channel module. Although there are multiple input channels and two sequencers, there is only one converter in the ADC module. Figure 4-8 shows the block diagram of the ADC module.

The two 8-channel modules have the capability to autosequence a series of conversions, each module has the choice of selecting any one of the respective eight channels available through an analog MUX. In the cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer, once the conversion is complete, the selected channel value is stored in its respective RESULT register. Autosequencing allows the system to convert the same channel multiple times, allowing the user to perform oversampling algorithms. This gives increased resolution over traditional single-sampled conversion results.

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ResultRegisters

EPWMSOCB

S/W

GPIO/

XINT2_ADCSOC

EPWMSOCA

S/W

Sequencer2

Sequencer1

SOCSOC

ADCControlRegisters

70B7h

70B0h

70AFh

70A8h

ResultReg15

ResultReg8

ResultReg7

ResultReg1

ResultReg0

12-Bit

ADC

Module

Analog

MUX

ADCINA0

ADCINA7

ADCINB0

ADCINB7

System

ControlBlock

High-Speed

Prescaler

HSPCLK

ADCENCLK

DSP

SYSCLKOUT

S/H

HALT

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Figure 4-8. Block Diagram of the ADC Module

To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent possible, traces leading to the ADCIN pins should not run in close proximity to the digital signal paths. This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation techniques must be used to isolate the ADC module power pins ( V V

DD2A18

, V

DDA2

, V

DDAIO

) from the digital supply.Figure 4-9 shows the ADC pin connections for the devices.

NOTE

1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the ADC module is controlled by the high-speed peripheral clock (HSPCLK).

2. The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as follows:

– ADCENCLK: On reset, this signal will be low. While reset is active-low (XRS) the

clock to the register will still function. This is necessary to make sure all registers and modes go into their default reset state. The analog module, however, will be in a lowpower inactive state. As soon as reset goes high, then the clock to the registers will be disabled. When the user sets the ADCENCLK signal high, then the clocks to the registers will be enabled and the analog module will be enabled. There will be a certain time delay (ms range) before the ADC is stable and can be used.

– HALT: This mode only affects the analog module. It does not affect the registers. In

this mode, the ADC module goes into low-power mode. This mode also will stop the clock to the CPU, which will stop the HSPCLK; therefore, the ADC register logic will be turned off indirectly.

DD1A18

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ADCINA[7:0] ADCINB[7:0]

ADCLO

ADCREFIN

ADCExternalCurrentBiasResistor ADCRESEXT

ADCREFP

DD1A18

DD2A18

SS1AGND

SS2AGND

DDAIO

SSAIO

DDA2

SSA2

ADCReferencePositiveOutput

ADCREFMADCReferenceMediumOutput

ADCPower

ADCAnalogandReferenceI/OPower

Analoginput0−3VwithrespecttoADCLO

Connecttoanalogground

22k

2.2 F

(A)

2.2 F

(A)

ADCAnalogPowerPin(1.9V) ADCAnalogPowerPin(1.9V)

ADCAnalogPowerPin(3.3V) ADCAnalogI/OGroundPin

ADCAnalogPowerPin(3.3V)

ADCREFPandADCREFMshouldnot beloadedbyexternalcircuitry

ADCAnalogGroundPin

ADC16-ChannelAnalogInputs

Connecttoanaloggroundifinternalreferenceisused

ADCAnalogGroundPin ADCAnalogGroundPin

ADCINA[7:0] ADCINB[7:0]

ADCLO

ADCREFIN

ADCExternalCurrentBiasResistor ADCRESEXT

ADCREFP

DD1A18

DD2A18

SS1AGND

SS2AGND

DDAIO

SSAIO

DDA2

SSA2

ADCReferencePositiveOutput

ADCREFMADCReferenceMediumOutput

ADC AnalogPower

ADC AnalogandReferenceI/OPower

Analoginput0−3Vwithrespectto ADCLO

Connectto AnalogGround

22kΩ

2.2 µF

(A)

ADCREFP and ADCREFMshouldnot

beloadedbyexternalcircuitry

ADC16-Channel AnalogInputs

Connectto1.500,1.024,or2.048-Vprecisionsource

(D)

ADC AnalogPowerPin(1.9V) ADC AnalogPowerPin(1.9V)

ADC AnalogI/OGroundPin

ADC AnalogPowerPin(3.3V) ADC AnalogGroundPin

ADC AnalogGroundPin ADC AnalogGroundPin

ADC AnalogPowerPin(3.3V)

2.2 µF

(A)

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Figure 4-9 shows the ADC pin-biasing for internal reference and Figure 4-10 shows the ADC pin-biasing

for external reference.

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Figure 4-9. ADC Pin Connections With Internal Reference

A. TAIYO YUDEN LMK212BJ225MG-T or equivalent B. External decoupling capacitors are recommended on all power pins. C. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance. D. External voltage on ADCREFIN is enabled by changing bits 15:14 in the ADC Reference Select register depending on

the voltage used on this pin. TI recommends TI part REF3020 or equivalent for 2.048-V generation. Overall gain accuracy will be determined by accuracy of this voltage source.

Figure 4-10. ADC Pin Connections With External Reference

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The temperature rating of any recommended component must match the rating of the end product.

4.7.1 ADC Connections if the ADC Is Not Used

It is recommended to keep the connections for the analog power pins, even if the ADC is not used. Following is a summary of how the ADC pins should be connected, if the ADC is not used in an application:

• V

DD1A18/VDD2A18

• V

, V

DDA2 SS1AGND/VSS2AGND

DDAIO

• ADCLO – Connect to V

• ADCREFIN – Connect to V

• ADCREFP/ADCREFM – Connect a 100-nF cap to V

• ADCRESEXT – Connect a 20-kΩ resistor (very loose tolerance) to VSS.

• ADCINAn, ADCINBn - Connect to V When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power

savings.

– Connect to V

, V

SSA2

DDIO

– Connect to V

SSAIO

SPRS682–DECEMBER 2010

NOTE

When the ADC module is used in an application, unused ADC input pins should be connected to analog ground (V

SS1AGND/VSS2AGND

)

NOTE

ADC parameters for gain error and offset error are specified only if the ADC calibration routine is executed from the Boot ROM. See Section 4.7.3 for more information.

4.7.2 ADC Registers

The ADC operation is configured, controlled, and monitored by the registers listed in Table 4-6.

Table 4-6. ADC Registers

NAME ADDRESS

ADCTRL1 0x7100 1 ADC Control Register 1 ADCTRL2 0x7101 1 ADC Control Register 2

ADCMAXCONV 0x7102 1 ADC Maximum Conversion Channels Register ADCCHSELSEQ1 0x7103 1 ADC Channel Select Sequencing Control Register 1 ADCCHSELSEQ2 0x7104 1 ADC Channel Select Sequencing Control Register 2 ADCCHSELSEQ3 0x7105 1 ADC Channel Select Sequencing Control Register 3 ADCCHSELSEQ4 0x7106 1 ADC Channel Select Sequencing Control Register 4

ADCASEQSR 0x7107 1 ADC Auto-Sequence Status Register ADCRESULT0 0x7108 0x0B00 1 ADC Conversion Result Buffer Register 0 ADCRESULT1 0x7109 0x0B01 1 ADC Conversion Result Buffer Register 1 ADCRESULT2 0x710A 0x0B02 1 ADC Conversion Result Buffer Register 2 ADCRESULT3 0x710B 0x0B03 1 ADC Conversion Result Buffer Register 3 ADCRESULT4 0x710C 0x0B04 1 ADC Conversion Result Buffer Register 4

(1)

ADDRESS

(2)

SIZE (x16) DESCRIPTION

(1)

(1) The registers in this column are Peripheral Frame 2 Registers. (2) The ADC result registers are dual mapped. Locations in Peripheral Frame 2 (0x7108-0x7117) are 2 wait-states and left justified.

Locations in Peripheral frame 0 space (0x0B00-0x0B0F) are 1 wait-state for CPU accesses and 0 wait state for DMA accesses and right justified. During high speed/continuous conversion use of the ADC, use the 0 wait-state locations for fast transfer of ADC results to user memory.

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Table 4-6. ADC Registers (continued)

NAME ADDRESS

ADCRESULT5 0x710D 0x0B05 1 ADC Conversion Result Buffer Register 5 ADCRESULT6 0x710E 0x0B06 1 ADC Conversion Result Buffer Register 6 ADCRESULT7 0x710F 0x0B07 1 ADC Conversion Result Buffer Register 7 ADCRESULT8 0x7110 0x0B08 1 ADC Conversion Result Buffer Register 8 ADCRESULT9 0x7111 0x0B09 1 ADC Conversion Result Buffer Register 9

ADCRESULT10 0x7112 0x0B0A 1 ADC Conversion Result Buffer Register 10 ADCRESULT11 0x7113 0x0B0B 1 ADC Conversion Result Buffer Register 11 ADCRESULT12 0x7114 0x0B0C 1 ADC Conversion Result Buffer Register 12 ADCRESULT13 0x7115 0x0B0D 1 ADC Conversion Result Buffer Register 13 ADCRESULT14 0x7116 0x0B0E 1 ADC Conversion Result Buffer Register 14 ADCRESULT15 0x7117 0x0B0F 1 ADC Conversion Result Buffer Register 15

ADCTRL3 0x7118 1 ADC Control Register 3

ADCST 0x7119 1 ADC Status Register

Reserved 2

ADCREFSEL 0x711C 1 ADC Reference Select Register

ADCOFFTRIM 0x711D 1 ADC Offset Trim Register

Reserved 2

0x711A 0x711B

0x711E 0x711F

(1)

ADDRESS

(2)

SIZE (x16) DESCRIPTION

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4.7.3 ADC Calibration

The ADC_cal() routine is programmed into TI reserved OTP memory by the factory. The boot ROM automatically calls the ADC_cal() routine to initialize the ADCREFSEL and ADCOFFTRIM registers with device specific calibration data. During normal operation, this process occurs automatically and no action is required by the user.

If the boot ROM is bypassed by Code Composer Studio during the development process, then ADCREFSEL and ADCOFFTRIM must be initialized by the application. For working examples, see the ADC initialization in the C2833x, C2823x C/C++ Header Files and Peripheral Examples (SPRC530).

FAILURE TO INITIALIZE THESE REGISTERS WILL CAUSE THE ADC TO FUNCTION OUT OF SPECIFICATION.

If the system is reset or the ADC module is reset using Bit 14 (RESET) from the ADC Control Register 1, the routine must be repeated.

NOTE

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( )

CLKSRG

CLKG =

1 + CLKGDV

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4.8 Multichannel Buffered Serial Port (McBSP) Module

The McBSP module has the following features:

• Full–duplex communication

• Double–buffered data registers that allow a continuous data stream

• Independent framing and clocking for receive and transmit

• External shift clock generation or an internal programmable frequency shift clock

• A wide selection of data sizes including 8–, 12–, 16–, 20–, 24–, or 32–bits

• 8–bit data transfers with LSB or MSB first

• Programmable polarity for both frame synchronization and data clocks

• Highly programmable internal clock and frame generation

• Direct interface to industry–standard CODECs, Analog Interface Chips (AICs), and other serially connected A/D and D/A devices

• Works with SPI–compatible devices

• The following application interfaces can be supported on the McBSP: – T1/E1 framers – IOM–2 compliant devices – AC97–compliant devices (the necessary multiphase frame synchronization capability is provided.) – IIS–compliant devices – SPI

• McBSP clock rate,

SPRS682–DECEMBER 2010

where CLKSRG source could be LSPCLK, CLKX, or CLKR. Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less than the I/O buffer speed limit.

NOTE

See Section 6 for maximum I/O pin toggling speed.

Figure 4-11 shows the block diagram of the McBSP module.

(1)

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McBSP Receive

InterruptSelectLogic

MDXx

MDRx

ExpandLogic

DRR1ReceiveBuffer

Interrupt

DRR2ReceiveBuffer

RBR1RegisterRBR2Register

MCLKXx

MFSXx

MCLKRx

MFSRx

CompandLogic

DXR2 TransmitBuffer

RSR1

XSR2

XSR1

PeripheralReadBus

RSR2

DXR1 TransmitBuffer

LSPCLK

MRINT

ToCPU

RXInterruptLogic

McBSP Transmit

InterruptSelectLogic

Interrupt

MXINT

ToCPU

TXInterruptLogic

16 16

Bridge

DMA Bus

PeripheralBus

PeripheralWriteBus

CPU

SM320F28335-HT

SPRS682–DECEMBER 2010

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Table 4-7 provides a summary of the McBSP registers.

Figure 4-11. McBSP Module

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Table 4-7. McBSP Register Summary

NAME McBSP-A McBSP-B TYPE RESET VALUE DESCRIPTION

DATA REGISTERS, RECEIVE, TRANSMIT

DRR2 0x5000 0x5040 R 0x0000 McBSP Data Receive Register 2 DRR1 0x5001 0x5041 R 0x0000 McBSP Data Receive Register 1 DXR2 0x5002 0x5042 W 0x0000 McBSP Data Transmit Register 2 DXR1 0x5003 0x5043 W 0x0000 McBSP Data Transmit Register 1

McBSP CONTROL REGISTERS

SPCR2 0x5004 0x5044 R/W 0x0000 McBSP Serial Port Control Register 2 SPCR1 0x5005 0x5045 R/W 0x0000 McBSP Serial Port Control Register 1 RCR2 0x5006 0x5046 R/W 0x0000 McBSP Receive Control Register 2 RCR1 0x5007 0x5047 R/W 0x0000 McBSP Receive Control Register 1 XCR2 0x5008 0x5048 R/W 0x0000 McBSP Transmit Control Register 2 XCR1 0x5009 0x5049 R/W 0x0000 McBSP Transmit Control Register 1 SRGR2 0x500A 0x504A R/W 0x0000 McBSP Sample Rate Generator Register 2 SRGR1 0x500B 0x504B R/W 0x0000 McBSP Sample Rate Generator Register 1

MULTICHANNEL CONTROL REGISTERS

MCR2 0x500C 0x504C R/W 0x0000 McBSP Multichannel Register 2 MCR1 0x500D 0x504D R/W 0x0000 McBSP Multichannel Register 1 RCERA 0x500E 0x504E R/W 0x0000 McBSP Receive Channel Enable Register Partition A RCERB 0x500F 0x504F R/W 0x0000 McBSP Receive Channel Enable Register Partition B XCERA 0x5010 0x5050 R/W 0x0000 McBSP Transmit Channel Enable Register Partition A XCERB 0x5011 0x5051 R/W 0x0000 McBSP Transmit Channel Enable Register Partition B PCR 0x5012 0x5052 R/W 0x0000 McBSP Pin Control Register RCERC 0x5013 0x5053 R/W 0x0000 McBSP Receive Channel Enable Register Partition C RCERD 0x5014 0x5054 R/W 0x0000 McBSP Receive Channel Enable Register Partition D XCERC 0x5015 0x5055 R/W 0x0000 McBSP Transmit Channel Enable Register Partition C XCERD 0x5016 0x5056 R/W 0x0000 McBSP Transmit Channel Enable Register Partition D RCERE 0x5017 0x5057 R/W 0x0000 McBSP Receive Channel Enable Register Partition E RCERF 0x5018 0x5058 R/W 0x0000 McBSP Receive Channel Enable Register Partition F XCERE 0x5019 0x5059 R/W 0x0000 McBSP Transmit Channel Enable Register Partition E XCERF 0x501A 0x505A R/W 0x0000 McBSP Transmit Channel Enable Register Partition F RCERG 0x501B 0x505B R/W 0x0000 McBSP Receive Channel Enable Register Partition G RCERH 0x501C 0x505C R/W 0x0000 McBSP Receive Channel Enable Register Partition H XCERG 0x501D 0x505D R/W 0x0000 McBSP Transmit Channel Enable Register Partition G XCERH 0x501E 0x505E R/W 0x0000 McBSP Transmit Channel Enable Register Partition H MFFINT 0x5023 0x5063 R/W 0x0000 McBSP Interrupt Enable Register

ADDRESS ADDRESS

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4.9 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)

The CAN module has the following features:

• Fully compliant with CAN protocol, version 2.0B

• Supports data rates up to 1 Mbps

• Thirty-two mailboxes, each with the following properties: – Configurable as receive or transmit – Configurable with standard or extended identifier – Has a programmable receive mask – Supports data and remote frame – Composed of 0 to 8 bytes of data – Uses a 32-bit time stamp on receive and transmit message – Protects against reception of new message – Holds the dynamically programmable priority of transmit message – Employs a programmable interrupt scheme with two interrupt levels – Employs a programmable alarm on transmission or reception time-out

• Low-power mode

• Programmable wake-up on bus activity

• Automatic reply to a remote request message

• Automatic retransmission of a frame in case of loss of arbitration or error

• 32-bit local network time counter synchronized by a specific message (communication in conjunction with mailbox 16)

• Self-test mode – Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided,

thereby eliminating the need for another node to provide the acknowledge bit.

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NOTE

For a SYSCLKOUT of 100 MHz, the smallest bit rate possible is 15.625 kbps. For a SYSCLKOUT of 150 MHz, the smallest bit rate possible is 23.4 kbps.

The F28335 CAN has passed the conformance test per ISO/DIS 16845. Contact TI for test report and exceptions.

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Mailbox RAM

(512 Bytes)

32-Message Mailbox

of 4 × 32-Bit Words

Memory Management

Unit

CPU Interface,

Receive Control Unit,

Timer Management Unit

eCAN Memory

(512 Bytes)

Registers and Message

Objects Control

32 32

Message Controller

32 3232 3232 32

eCAN Protocol Kernel

Receive Buffer

Transmit Buffer

Control Buffer

Status Buffer

Enhanced CAN Controller

Controls

Address Data

eCAN1INTeCAN0INT

SN65HVD23x

3.3-V CAN Transceiver

CAN Bus

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PART NUMBER VREF OTHER T

SN65HVD230 3.3 V Standby Adjustable Yes – -40°C to 85°C

SN65HVD230Q 3.3 V Standby Adjustable Yes – -40°C to 125°C

SN65HVD231 3.3 V Sleep Adjustable Yes – -40°C to 85°C

SN65HVD231Q 3.3 V Sleep Adjustable Yes – -40°C to 125°C

SN65HVD232 3.3 V None None None – -40°C to 85°C

SN65HVD232Q 3.3 V None None None – -40°C to 125°C

SN65HVD233 3.3 V Standby Adjustable None Diagnostic -40°C to 125°C

SN65HVD234 3.3 V Standby and Sleep Adjustable None – -40°C to 125°C SN65HVD235 3.3 V Standby Adjustable None Autobaud -40°C to 125°C

Figure 4-12. eCAN Block Diagram and Interface Circuit

VOLTAGE MODE CONTROL

SUPPLY LOW-POWER SLOPE

Table 4-8. 3.3-V eCAN Transceivers

Loopback

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Mailbox Enable − CANME

Mailbox Direction − CANMD

Transmission Request Set − CANTRS

Transmission Request Reset − CANTRR

Transmission Acknowledge − CANTA

Abort Acknowledge − CANAA

Received Message Pending − CANRMP

Received Message Lost − CANRML

Remote Frame Pending − CANRFP

Global Acceptance Mask − CANGAM

Master Control − CANMC

Bit-Timing Configuration − CANBTC

Error and Status − CANES

Transmit Error Counter − CANTEC

Receive Error Counter − CANREC

Global Interrupt Flag 0 − CANGIF0

Global Interrupt Mask − CANGIM

Mailbox Interrupt Mask − CANMIM

Mailbox Interrupt Level − CANMIL

Overwrite Protection Control − CANOPC

TX I/O Control − CANTIOC

RX I/O Control − CANRIOC

Time Stamp Counter − CANTSC

Global Interrupt Flag 1 − CANGIF1

Time-Out Control − CANTOC

Time-Out Status − CANTOS

Reserved

eCAN-A Control and Status Registers

Message Identifier − MSGID

61E8h−61E9h

Message Control − MSGCTRL

Message Data Low − MDL

Message Data High − MDH

Message Mailbox (16 Bytes)

Control and Status Registers

6000h

603Fh

Local Acceptance Masks (LAM)

(32 × 32-Bit RAM)

6040h

607Fh

6080h

60BFh

60C0h 60FFh

eCAN-A Memory (512 Bytes)

Message Object Time Stamps (MOTS)

(32 × 32-Bit RAM)

Message Object Time-Out (MOTO)

(32 × 32-Bit RAM)

Mailbox 0

6100h−6107h

Mailbox 1

6108h−610Fh

Mailbox 2

6110h−6117h

Mailbox 3

6118h−611Fh

eCAN-A Memory RAM (512 Bytes)

Mailbox 4

6120h−6127h

Mailbox 28

61E0h−61E7h

Mailbox 29

61E8h−61EFh

Mailbox 30

61F0h−61F7h

Mailbox 31

61F8h−61FFh

61EAh−61EBh 61ECh−61EDh

61EEh−61EFh

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If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for this.

Figure 4-13. eCAN-A Memory Map

NOTE

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Mailbox Enable − CANME

Mailbox Direction − CANMD

Transmission Request Set − CANTRS

Transmission Request Reset − CANTRR

Transmission Acknowledge − CANTA

Abort Acknowledge − CANAA

Received Message Pending − CANRMP

Received Message Lost − CANRML

Remote Frame Pending − CANRFP

Global Acceptance Mask − CANGAM

Master Control − CANMC

Bit-Timing Configuration − CANBTC

Error and Status − CANES

Transmit Error Counter − CANTEC

Receive Error Counter − CANREC

Global Interrupt Flag 0 − CANGIF0

Global Interrupt Mask − CANGIM

Mailbox Interrupt Mask − CANMIM

Mailbox Interrupt Level − CANMIL

Overwrite Protection Control − CANOPC

TX I/O Control − CANTIOC

RX I/O Control − CANRIOC

Time Stamp Counter − CANTSC

Global Interrupt Flag 1 − CANGIF1

Time-Out Control − CANTOC

Time-Out Status − CANTOS

Reserved

eCAN-B Control and Status Registers

Message Identifier − MSGID

63E8h−63E9h

Message Control − MSGCTRL

Message Data Low − MDL

Message Data High − MDH

Message Mailbox (16 Bytes)

Control and Status Registers

6200h

623Fh

Local Acceptance Masks (LAM)

(32 × 32-Bit RAM)

6240h

627Fh

6280h

62BFh

62C0h 62FFh

eCAN-B Memory (512 Bytes)

Message Object Time Stamps (MOTS)

(32 × 32-Bit RAM)

Message Object Time-Out (MOTO)

(32 × 32-Bit RAM)

Mailbox 0

6300h−6307h

Mailbox 1

6308h−630Fh

Mailbox 2

6310h−6317h

Mailbox 3

6318h−631Fh

eCAN-B Memory RAM (512 Bytes)

Mailbox 4

6320h−6327h

Mailbox 28

63E0h−63E7h

Mailbox 29

63E8h−63EFh

Mailbox 30

63F0h−63F7h

Mailbox 31

63F8h−63FFh

63EAh−63EBh 63ECh−63EDh

63EEh−63EFh

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The CAN registers listed in Table 4-9 are used by the CPU to configure and control the CAN controller and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.

Figure 4-14. eCAN-B Memory Map

SPRS682–DECEMBER 2010

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Table 4-9. CAN Register Map

CANME 0x6000 0x6200 1 Mailbox enable CANMD 0x6002 0x6202 1 Mailbox direction

CANTRS 0x6004 0x6204 1 Transmit request set

CANTRR 0x6006 0x6206 1 Transmit request reset

CANTA 0x6008 0x6208 1 Transmission acknowledge

CANAA 0x600A 0x620A 1 Abort acknowledge CANRMP 0x600C 0x620C 1 Receive message pending CANRML 0x600E 0x620E 1 Receive message lost

CANRFP 0x6010 0x6210 1 Remote frame pending

CANGAM 0x6012 0x6212 1 Global acceptance mask

CANMC 0x6014 0x6214 1 Master control

CANBTC 0x6016 0x6216 1 Bit-timing configuration

CANES 0x6018 0x6218 1 Error and status

CANTEC 0x601A 0x621A 1 Transmit error counter CANREC 0x601C 0x621C 1 Receive error counter CANGIF0 0x601E 0x621E 1 Global interrupt flag 0

CANGIM 0x6020 0x6220 1 Global interrupt mask CANGIF1 0x6022 0x6222 1 Global interrupt flag 1

CANMIM 0x6024 0x6224 1 Mailbox interrupt mask

CANMIL 0x6026 0x6226 1 Mailbox interrupt level

CANOPC 0x6028 0x6228 1 Overwrite protection control

CANTIOC 0x602A 0x622A 1 TX I/O control CANRIOC 0x602C 0x622C 1 RX I/O control

CANTSC 0x602E 0x622E 1 Time stamp counter (Reserved in SCC mode) CANTOC 0x6030 0x6230 1 Time-out control (Reserved in SCC mode) CANTOS 0x6032 0x6232 1 Time-out status (Reserved in SCC mode)

(1) These registers are mapped to Peripheral Frame 1.

ECAN-A ECAN-B SIZE

ADDRESS ADDRESS (x32)

(1)

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Baud rate =

LSPCLK

(BRR ) 1) * 8

when BRR ≠ 0

Baud rate = when BRR = 0

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4.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)

The devices include three serial communications interface (SCI) modules. The SCI modules support digital communications between the CPU and other asynchronous peripherals that use the standard nonreturn-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in the fullduplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baudselect register.

Features of each SCI module include:

• Two external pins: – SCITXD: SCI transmit-output pin – SCIRXD: SCI receive-input pin

NOTE: Both pins can be used as GPIO if not used for SCI.

– Baud rate programmable to 64K different rates:

SPRS682–DECEMBER 2010

NOTE

See Section 6 for maximum I/O pin toggling speed.

• Data-word format – One start bit – Data-word length programmable from one to eight bits – Optional even/odd/no parity bit – One or two stop bits

• Four error-detection flags: parity, overrun, framing, and break detection

• Two wake-up multiprocessor modes: idle-line and address bit

• Half- or full-duplex operation

• Double-buffered receive and transmit functions

• Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with status flags.

– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX

EMPTY flag (transmitter-shift register is empty)

– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag

(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)

• Separate enable bits for transmitter and receiver interrupts (except BRKDT)

• NRZ (non-return-to-zero) format

NOTE

All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7-0), and the upper byte (15-8) is read as zeros. Writing to the upper byte has no effect.

Enhanced features:

• Auto baud-detect hardware logic

• 16-level transmit/receive FIFO

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The SCI port operation is configured and controlled by the registers listed in Table 4-10, Table 4-11, and

Table 4-12.

Table 4-10. SCI-A Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

SCICCRA 0x7050 1 SCI-A Communications Control Register

SCICTL1A 0x7051 1 SCI-A Control Register 1

SCIHBAUDA 0x7052 1 SCI-A Baud Register, High Bits

SCILBAUDA 0x7053 1 SCI-A Baud Register, Low Bits

SCICTL2A 0x7054 1 SCI-A Control Register 2

SCIRXSTA 0x7055 1 SCI-A Receive Status Register

SCIRXEMUA 0x7056 1 SCI-A Receive Emulation Data Buffer Register

SCIRXBUFA 0x7057 1 SCI-A Receive Data Buffer Register

SCITXBUFA 0x7059 1 SCI-A Transmit Data Buffer Register SCIFFTXA SCIFFRXA SCIFFCTA

SCIPRIA 0x705F 1 SCI-A Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce

undefined results.

(2) These registers are new registers for the FIFO mode.

(2) (2) (2)

0x705A 1 SCI-A FIFO Transmit Register 0x705B 1 SCI-A FIFO Receive Register 0x705C 1 SCI-A FIFO Control Register

(1)

Table 4-11. SCI-B Registers

(1) (2)

NAME ADDRESS SIZE (x16) DESCRIPTION

SCICCRB 0x7750 1 SCI-B Communications Control Register

SCICTL1B 0x7751 1 SCI-B Control Register 1

SCIHBAUDB 0x7752 1 SCI-B Baud Register, High Bits

SCILBAUDB 0x7753 1 SCI-B Baud Register, Low Bits

SCICTL2B 0x7754 1 SCI-B Control Register 2

SCIRXSTB 0x7755 1 SCI-B Receive Status Register

SCIRXEMUB 0x7756 1 SCI-B Receive Emulation Data Buffer Register

SCIRXBUFB 0x7757 1 SCI-B Receive Data Buffer Register

SCITXBUFB 0x7759 1 SCI-B Transmit Data Buffer Register SCIFFTXB SCIFFRXB SCIFFCTB

(2) (2) (2)

0x775A 1 SCI-B FIFO Transmit Register 0x775B 1 SCI-B FIFO Receive Register 0x775C 1 SCI-B FIFO Control Register

SCIPRIB 0x775F 1 SCI-B Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce

undefined results.

(2) These registers are new registers for the FIFO mode.

Table 4-12. SCI-C Registers

(1) (2)

NAME ADDRESS SIZE (x16) DESCRIPTION

SCICCRC 0x7770 1 SCI-C Communications Control Register

SCICTL1C 0x7771 1 SCI-C Control Register 1

SCIHBAUDC 0x7772 1 SCI-C Baud Register, High Bits

SCILBAUDC 0x7773 1 SCI-C Baud Register, Low Bits

SCICTL2C 0x7774 1 SCI-C Control Register 2

(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce

undefined results.

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TXFIFO_0

LSPCLK

WUT

FrameFormatandMode

Even/Odd Enable

Parity

SCIRXInterruptselectlogic

BRKDT

RXRDY

SCIRXST.6

SCICTL1.3

SCICTL2.1

RX/BKINTENA

SCIRXD

SCIRXST.1

TXENA

SCITXInterruptselectlogic

TXEMPTY

TXRDY

SCICTL2.0

TXINTENA

SCITXD

RXENA

SCIRXD

RXWAKE

SCICTL1.6

RXERRINTENA

TXWAKE

SCITXD

SCICCR.6SCICCR.5

SCITXBUF.7-0

SCIHBAUD.15-8

BaudRate

MSbyte

SCILBAUD.7-0

Transmitter-Data

BufferRegister

SCICTL2.6

SCICTL2.7

BaudRate

LSbyte

RXSHF

TXSHF

SCIRXST.5

TXFIFO_1

-----

TXFIFO_15

TXFIFOregisters

TXFIFO

TXInterrupt

Logic

TXINT

SCIFFTX.14

RXFIFO_15

SCIRXBUF.7-0

ReceiveData Bufferregister SCIRXBUF.7-0

-----

RXFIFO_1

RXFIFO_0

RXFIFOregisters

SCICTL1.0

RXInterrupt

Logic

RXINT

RXFIFO

SCIFFRX.15

RXFFOVF

RXError

SCIRXST.7

PEFE OE

RXError

SCIRXST.4-2

ToCPU

AutoBaudDetectlogic

SCICTL1.1

SCIFFENA

Interrupts

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Table 4-12. SCI-C Registers (continued)

NAME ADDRESS SIZE (x16) DESCRIPTION

SCIRXSTC 0x7775 1 SCI-C Receive Status Register

SCIRXEMUC 0x7776 1 SCI-C Receive Emulation Data Buffer Register

SCIRXBUFC 0x7777 1 SCI-C Receive Data Buffer Register

SCITXBUFC 0x7779 1 SCI-C Transmit Data Buffer Register SCIFFTXC SCIFFRXC SCIFFCTC

(2)

0x777A 1 SCI-C FIFO Transmit Register 0x777B 1 SCI-C FIFO Receive Register 0x777C 1 SCI-C FIFO Control Register

SCIPRC 0x777F 1 SCI-C Priority Control Register

Figure 4-15 shows the SCI module block diagram.

SPRS682–DECEMBER 2010

Figure 4-15. Serial Communications Interface (SCI) Module Block Diagram

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Baud rate =

LSPCLK

(SPIBRR ) 1)

when SPIBRR = 3 to 127

Baud rate = when SPIBRR = 0,1, 2

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4.11 Serial Peripheral Interface (SPI) Module (SPI-A)

The device includes the four-pin serial peripheral interface (SPI) module. One SPI module (SPI-A) is available. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bittransfer rate. Normally, the SPI is used for communications between the DSC controller and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI.

The SPI module features include:

• Four external pins: – SPISOMI: SPI slave-output/master-input pin – SPISIMO: SPI slave-input/master-output pin – SPISTE: SPI slave transmit-enable pin – SPICLK: SPI serial-clock pin

NOTE: All four pins can be used as GPIO if the SPI module is not used.

• Two operational modes: master and slave Baud rate: 125 different programmable rates.

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NOTE

See Section 6 for maximum I/O pin toggling speed.

• Data word length: one to sixteen data bits

• Four clocking schemes (controlled by clock polarity and clock phase bits) include: – Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the

SPICLK signal and receives data on the rising edge of the SPICLK signal.

– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the

falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.

– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the

SPICLK signal and receives data on the falling edge of the SPICLK signal.

– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the

falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.

• Simultaneous receive and transmit operation (transmit function can be disabled in software)

• Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.

• Nine SPI module control registers: Located in control register frame beginning at address 7040h.

NOTE

All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7-0), and the upper byte (15-8) is read as zeros. Writing to the upper byte has no effect.

Enhanced feature:

• 16-level transmit/receive FIFO

• Delayed transmit control

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The SPI port operation is configured and controlled by the registers listed in Table 4-13.

Table 4-13. SPI-A Registers

NAME ADDRESS SIZE (X16) DESCRIPTION

SPICCR 0x7040 1 SPI-A Configuration Control Register

SPICTL 0x7041 1 SPI-A Operation Control Register SPISTS 0x7042 1 SPI-A Status Register

SPIBRR 0x7044 1 SPI-A Baud Rate Register

SPIRXEMU 0x7046 1 SPI-A Receive Emulation Buffer Register

SPIRXBUF 0x7047 1 SPI-A Serial Input Buffer Register SPITXBUF 0x7048 1 SPI-A Serial Output Buffer Register

SPIDAT 0x7049 1 SPI-A Serial Data Register

SPIFFTX 0x704A 1 SPI-A FIFO Transmit Register SPIFFRX 0x704B 1 SPI-A FIFO Receive Register SPIFFCT 0x704C 1 SPI-A FIFO Control Register

SPIPRI 0x704F 1 SPI-A Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined

results.

(1)

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SPICTL.0

SPIINTFLAG

SPIINT

ENA

SPISTS.6

Clock

Polarity

Talk

LSPCLK

456 123 0

0123

SPIBitRate

StateControl

SPIRXBUF

BufferRegister

Clock

Phase

Receiver

OverrunFlag

SPICTL.4

Overrun INTENA

SPICCR.3 − 0

SPIBRR.6 − 0

SPICCR.6 SPICTL.3

SPIDAT.15 − 0

SPICTL.1

Master/Slave

SPISTS.7

SPIDAT

DataRegister

SPICTL.2

SPIChar

SPISIMO

SPISOMI

SPICLK

SW2

SW3

ToCPU

SW1

SPITXBUF

BufferRegister

RXFIFO_0 RXFIFO_1

−−−−−

RXFIFO_15

TXFIFOregisters

TXFIFO_0

TXFIFO_1

−−−−−

TXFIFO_15

RXFIFOregisters

TXInterrupt

Logic

RXInterrupt

Logic

SPIINT/SPIRXINT

SPITXINT

SPIFFOVFFLAG

SPIFFRX.15

TXFIFOInterrupt

RXFIFOInterrupt

SPIRXBUF

SPITXBUF

SPIFFTX.14

SPIFFENA

SPISTE

(A)

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SPRS682–DECEMBER 2010

Figure 4-16 is a block diagram of the SPI in slave mode.

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A. SPISTE is driven low by the master for a slave device.

Figure 4-16. SPI Module Block Diagram (Slave Mode)

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SYSRS

Data[16]

SYSCLKOUT

Data[16]

Addr[16]

Control

I2CINT1A

I2CINT2A

C28X CPU

GPIO

MUX

I2C−A

System Control

Block

I2CAENCLK

PIE

Block

SDAA

SCLA

Peripheral Bus

SM320F28335-HT

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4.12 Inter-Integrated Circuit (I2C)

The device contains one I2C Serial Port. Figure 4-15 shows how the I2C peripheral module interfaces within the device.

SPRS682–DECEMBER 2010

A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are

also at the SYSCLKOUT rate.

B. The clock enable bit (I2CAENCLK) in the PCLKCR0 register turns off the clock to the I2C port for low power

operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off.

Figure 4-17. I2C Peripheral Module Interfaces

The I2C module has the following features:

• Compliance with the Philips Semiconductors I2C-bus specification (version 2.1): – Support for 1-bit to 8-bit format transfers – 7-bit and 10-bit addressing modes – General call – START byte mode – Support for multiple master-transmitters and slave-receivers – Support for multiple slave-transmitters and master-receivers – Combined master transmit/receive and receive/transmit mode – Data transfer rate of from 10 kbps up to 400 kbps (Philips Fast-mode rate)

• One 16-word receive FIFO and one 16-word transmit FIFO

• One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following conditions:

– Transmit-data ready – Receive-data ready – Register-access ready – No-acknowledgment received

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– Arbitration lost – Stop condition detected – Addressed as slave

• An additional interrupt that can be used by the CPU when in FIFO mode

• Module enable/disable capability

• Free data format mode

The registers in Table 4-14 configure and control the I2C port operation.

NAME ADDRESS DESCRIPTION

I2COAR 0x7900 I2C own address register

I2CIER 0x7901 I2C interrupt enable register

I2CSTR 0x7902 I2C status register

I2CCLKL 0x7903 I2C clock low-time divider register

I2CCLKH 0x7904 I2C clock high-time divider register

I2CCNT 0x7905 I2C data count register

I2CDRR 0x7906 I2C data receive register

I2CSAR 0x7907 I2C slave address register I2CDXR 0x7908 I2C data transmit register I2CMDR 0x7909 I2C mode register I2CISRC 0x790A I2C interrupt source register

I2CPSC 0x790C I2C prescaler register

I2CFFTX 0x7920 I2C FIFO transmit register

I2CFFRX 0x7921 I2C FIFO receive register

I2CRSR - I2C receive shift register (not accessible to the CPU)

I2CXSR - I2C transmit shift register (not accessible to the CPU)

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Table 4-14. I2C-A Registers

4.13 GPIO MUX

On the F28335, the GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition to providing individual pin bit-banging IO capability. The GPIO MUX block diagram per pin is shown in Figure 4-18. Because of the open drain capabilities of the I2C pins, the GPIO MUX block diagram for these pins differ.

NOTE

There is a 2-SYSCLKOUT cycle delay from when the write to the GPxMUXn and GPxQSELn registers occurs to when the action is valid.

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GPxDAT(read)

Input

Qualification

GPxMUX1/2

HighImpedance

OutputControl

GPIOxpin

XRS

0=Input,1=Output

LowPower

ModesBlock

GPxDIR(latch)

Peripheral2Input

Peripheral3Input

Peripheral1Output

Peripheral2Output

Peripheral3Output

Peripheral1OutputEnable

Peripheral2OutputEnable

Peripheral3OutputEnable

GPxCTRL

Peripheral1Input

N/C

GPxPUD

LPMCR0

Internal

Pullup

GPIOLMPSEL

GPxQSEL1/2

GPxSET

GPxDAT(latch)

GPxCLEAR

GPxTOGGLE

GPIOXINT7SEL

GPIOXNMISEL

=DefaultatReset

PIE

ExternalInterrupt

MUX

Asynchronous

path

Asynchronouspath

GPIOXINT1SEL

GPIOXINT2SEL

GPIOXINT3SEL



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A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register

depending on the particular GPIO pin selected. B. GPxDAT latch/read are accessed at the same memory location. C. This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins.

Figure 4-18. GPIO MUX Block Diagram

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The device supports 88 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 4-15 shows the GPIO register mapping.

Table 4-15. GPIO Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

GPIO CONTROL REGISTERS (EALLOW PROTECTED)

GPACTRL 0x6F80 2 GPIO A Control Register (GPIO0 to 31) GPAQSEL1 0x6F82 2 GPIO A Qualifier Select 1 Register (GPIO0 to 15) GPAQSEL2 0x6F84 2 GPIO A Qualifier Select 2 Register (GPIO16 to 31)

GPAMUX1 0x6F86 2 GPIO A MUX 1 Register (GPIO0 to 15) GPAMUX2 0x6F88 2 GPIO A MUX 2 Register (GPIO16 to 31)

GPADIR 0x6F8A 2 GPIO A Direction Register (GPIO0 to 31) GPAPUD 0x6F8C 2 GPIO A Pull Up Disable Register (GPIO0 to 31) Reserved 0x6F8E – 0x6F8F 2

GPBCTRL 0x6F90 2 GPIO B Control Register (GPIO32 to 63) GPBQSEL1 0x6F92 2 GPIO B Qualifier Select 1 Register (GPIO32 to 47) GPBQSEL2 0x6F94 2 GPIOB Qualifier Select 2 Register (GPIO48 to 63)

GPBMUX1 0x6F96 2 GPIO B MUX 1 Register (GPIO32 to 47) GPBMUX2 0x6F98 2 GPIO B MUX 2 Register (GPIO48 to 63)

GPBDIR 0x6F9A 2 GPIO B Direction Register (GPIO32 to 63) GPBPUD 0x6F9C 2 GPIO B Pull Up Disable Register (GPIO32 to 63) Reserved 0x6F9E – 0x6FA5 8

GPCMUX1 0x6FA6 2 GPIO C MUX1 Register (GPIO64 to 79) GPCMUX2 0x6FA8 2 GPIO C MUX2 Register (GPIO80 to 87)

GPCDIR 0x6FAA 2 GPIO C Direction Register (GPIO64 to 87) GPCPUD 0x6FAC 2 GPIO C Pull Up Disable Register (GPIO64 to 87) Reserved 0x6FAE – 0x6FBF 18

GPIO DATA REGISTERS (NOT EALLOW PROTECTED)

GPADAT 0x6FC0 2 GPIO A Data Register (GPIO0 to 31)

GPASET 0x6FC2 2 GPIO A Data Set Register (GPIO0 to 31)

GPACLEAR 0x6FC4 2 GPIO A Data Clear Register (GPIO0 to 31)

GPATOGGLE 0x6FC6 2 GPIO A Data Toggle Register (GPIO0 to 31)

GPBDAT 0x6FC8 2 GPIO B Data Register (GPIO32 to 63)

GPBSET 0x6FCA 2 GPIO B Data Set Register (GPIO32 to 63)

GPBCLEAR 0x6FCC 2 GPIO B Data Clear Register (GPIO32 to 63)

GPBTOGGLE 0x6FCE 2 GPIOB Data Toggle Register (GPIO32 to 63)

GPCDAT 0x6FD0 2 GPIO C Data Register (GPIO64 to 87) GPCSET 0x6FD2 2 GPIO C Data Set Register (GPIO64 to 87)

GPCCLEAR 0x6FD4 2 GPIO C Data Clear Register (GPIO64 to 87)

GPCTOGGLE 0x6FD6 2 GPIO C Data Toggle Register (GPIO64 to 87)

Reserved 0x6FD8 0x6FDF 8

GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)

GPIOXINT1SEL 0x6FE0 1 XINT1 GPIO Input Select Register (GPIO0 to 31) GPIOXINT2SEL 0x6FE1 1 XINT2 GPIO Input Select Register (GPIO0 to 31)

GPIOXNMISEL 0x6FE2 1 XNMI GPIO Input Select Register (GPIO0 to 31) GPIOXINT3SEL 0x6FE3 1 XINT3 GPIO Input Select Register (GPIO32 to 63) GPIOXINT4SEL 0x6FE4 1 XINT4 GPIO Input Select Register (GPIO32 to 63) GPIOXINT5SEL 0x6FE5 1 XINT5 GPIO Input Select Register (GPIO32 to 63)

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Table 4-15. GPIO Registers (continued)

NAME ADDRESS SIZE (x16) DESCRIPTION

GPIOXINT6SEL 0x6FE6 1 XINT6 GPIO Input Select Register (GPIO32 to 63)

GPIOINT7SEL 0x6FE7 1 XINT7 GPIO Input Select Register (GPIO32 to 63)

GPIOLPMSEL 0x6FE8 2 LPM GPIO Select Register (GPIO0 to 31)

Reserved 0x6FEA – 0x6FFF 22

Table 4-16. GPIO-A Mux Peripheral Selection Matrix

GPADIR GPAMUX1 GPIOx PER1 PER2 PER3

GPADAT GPAQSEL1 GPAMUX1=0,0 GPAMUX1 = 0, 1 GPAMUX1 = 1, 0 GPAMUX1 = 1, 1

GPASET

GPACLR

GPATOGGLE

QUALPRD0 0 1, 0 GPIO0 (I/O) EPWM1A (O)

1 3, 2 GPIO1 (I/O) EPWM1B (O) ECAP6 (I/O) MFSRB (I/O) 2 5, 4 GPIO2 (I/O) EPWM2A (O) 3 7, 6 GPIO3 (I/O) EPWM2B (O) ECAP5 (I/O) MCLKRB (I/O) 4 9, 8 GPIO4 (I/O) EPWM3A (O) 5 11, 10 GPIO5 (I/O) EPWM3B (O) MFSRA (I/O) ECAP1 (I/O) 6 13, 12 GPIO6 (I/O) EPWM4A (O) EPWMSYNCI (I) EPWMSYNCO (O) 7 15, 14 GPIO7 (I/O) EPWM4B (O) MCLKRA (I/O) ECAP2 (I/O)

QUALPRD1 8 17, 16 GPIO8 (I/O) EPWM5A (O) CANTXB (O) ADCSOCAO (O)

9 19, 18 GPIO9 (I/O) EPWM5B (O) SCITXDB (O) ECAP3 (I/O) 10 21, 20 GPIO10 (I/O) EPWM6A (O) CANRXB (I) ADCSOCBO (O) 11 23, 22 GPIO11 (I/O) EPWM6B (O) SCIRXDB (I) ECAP4 (I/O) 12 25, 24 GPIO12 (I/O) TZ1 (I) CANTXB (O) MDXB (O) 13 27, 26 GPIO13 (I/O) TZ2 (I) CANRXB (I) MDRB (I) 14 29, 28 GPIO14 (I/O) TZ3 (I)/XHOLD (I) SCITXDB (O) MCLKXB (I/O) 15 31, 30 GPIO15 (I/O) TZ4 (I)/XHOLDA (O) SCIRXDB (I) MFSXB (I/O)

GPAMUX2 GPAMUX2 =0, 0 GPAMUX2 = 0, 1 GPAMUX2 = 1, 0 GPAMUX2 = 1, 1

GPAQSEL2

QUALPRD2 16 1, 0 GPIO16 (I/O) SPISIMOA (I/O) CANTXB (O) TZ5 (I)

17 3, 2 GPIO17 (I/O) SPISOMIA (I/O) CANRXB (I) TZ6 (I) 18 5, 4 GPIO18 (I/O) SPICLKA (I/O) SCITXDB (O) CANRXA (I) 19 7, 6 GPIO19 (I/O) SPISTEA (I/O) SCIRXDB (I) CANTXA (O) 20 9, 8 GPIO20 (I/O) EQEP1A (I) MDXA (O) CANTXB (O) 21 11, 10 GPIO21 (I/O) EQEP1B (I) MDRA (I) CANRXB (I) 22 13, 12 GPIO22 (I/O) EQEP1S (I/O) MCLKXA (I/O) SCITXDB (O) 23 15, 14 GPIO23 (I/O) EQEP1I (I/O) MFSXA (I/O) SCIRXDB (I)

QUALPRD3 24 17, 16 GPIO24 (I/O) ECAP1 (I/O) EQEP2A (I) MDXB (O)

25 19, 18 GPIO25 (I/O) ECAP2 (I/O) EQEP2B (I) MDRB (I) 26 21, 20 GPIO26 (I/O) ECAP3 (I/O) EQEP2I (I/O) MCLKXB (I/O) 27 23, 22 GPIO27 (I/O) ECAP4 (I/O) EQEP2S (I/O) MFSXB (I/O) 28 25, 24 GPIO28 (I/O) SCIRXDA (I) XZCS6 (O) 29 27, 26 GPIO29 (I/O) SCITXDA (O) XA19 (O) 30 29, 28 GPIO30 (I/O) CANRXA (I) XA18 (O) 31 31, 30 GPIO31 (I/O) CANTXA (O) XA17 (O)

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Table 4-17. GPIO-B Mux Peripheral Selection Matrix

GPBDIR GPBMUX1 GPIOx PER1 PER2 PER3

GPBDAT GPBQSEL1 GPBMUX1=0, 0 GPBMUX1 = 0, 1 GPBMUX1 = 1, 0 GPBMUX1 = 1, 1

GPBSET

GPBCLR

GPBTOGGLE

QUALPRD0 0 1, 0 GPIO32 (I/O) SDAA (I/OC)

1 3, 2 GPIO33 (I/O) SCLA (I/OC)

2 5, 4 GPIO34 (I/O) ECAP1 (I/O) XREADY (I)

3 7, 6 GPIO35 (I/O) SCITXDA (O) XR/W (O)

4 9, 8 GPIO36 (I/O) SCIRXDA (I) XZCS0 (O)

5 11, 10 GPIO37 (I/O) ECAP2 (I/O) XZCS7 (O)

6 13, 12 GPIO38 (I/O) XWE0 (O)

7 15, 14 GPIO39 (I/O) XA16 (O)

QUALPRD1 8 17, 16 GPIO40 (I/O) XA0/XWE1 (O)

9 19, 18 GPIO41 (I/O) XA1 (O)

10 21, 20 GPIO42 (I/O) XA2 (O) 11 23, 22 GPIO43 (I/O) XA3 (O) 12 25, 24 GPIO44 (I/O) XA4 (O) 13 27, 26 GPIO45 (I/O) XA5 (O) 14 29, 28 GPIO46 (I/O) XA6 (O) 15 31, 30 GPIO47 (I/O) XA7 (O)

GPBMUX2 GPBMUX2 =0, 0 GPBMUX2 = 0, 1 GPBMUX2 = 1, 0 GPBMUX2 = 1, 1

GPBQSEL2

QUALPRD2 16 1, 0 GPIO48 (I/O) ECAP5 (I/O) XD31 (I/O)

17 3, 2 GPIO49 (I/O) ECAP6 (I/O) XD30 (I/O) 18 5, 4 GPIO50 (I/O) EQEP1A (I) XD29 (I/O) 19 7, 6 GPIO51 (I/O) EQEP1B (I) XD28 (I/O) 20 9, 8 GPIO52 (I/O) EQEP1S (I/O) XD27 (I/O) 21 11, 10 GPIO53 (I/O) EQEP1I (I/O) XD26 (I/O) 22 13, 12 GPIO54 (I/O) SPISIMOA (I/O) XD25 (I/O) 23 15, 14 GPIO55 (I/O) SPISOMIA (I/O) XD24 (I/O)

QUALPRD3 24 17, 16 GPIO56 (I/O) SPICLKA (I/O) XD23 (I/O)

25 19, 18 GPIO57 (I/O) SPISTEA (I/O) XD22 (I/O) 26 21, 20 GPIO58 (I/O) MCLKRA (I/O) XD21 (I/O) 27 23, 22 GPIO59 (I/O) MFSRA (I/O) XD20 (I/O) 28 25, 24 GPIO60 (I/O) MCLKRB (I/O) XD19 (I/O) 29 27, 26 GPIO61 (I/O) MFSRB (I/O) XD18 (I/O) 30 29, 28 GPIO62 (I/O) SCIRXDC (I) XD17 (I/O) 31 31, 30 GPIO63 (I/O) SCITXDC (O) XD16 (I/O)

(1) Open drain

Reserved

(1)

EPWMSYNCI (I) ADCSOCAO (O)

EPWMSYNCO (O) ADCSOCBO (O)

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Table 4-18. GPIO-C Mux Peripheral Selection Matrix

GPCDIR GPCMUX1 GPIOx or PER1 PER2 or PER3 GPCDAT GPCMUX1 = 0, 0 or 0, 1 GPCMUX1 = 1, 0 or 1, 1 GPCSET GPCCLR

GPCTOGGLE

no qual 0 1, 0 GPIO64 (I/O) XD15 (I/O)

1 3, 2 GPIO65 (I/O) XD14 (I/O) 2 5, 4 GPIO66 (I/O) XD13 (I/O) 3 7, 6 GPIO67 (I/O) XD12 (I/O) 4 9, 8 GPIO68 (I/O) XD11 (I/O) 5 11, 10 GPIO69 (I/O) XD10 (I/O) 6 13, 12 GPIO70 (I/O) XD9 (I/O) 7 15, 14 GPIO71 (I/O) XD8 (I/O)

no qual 8 17, 16 GPIO72 (I/O) XD7 (I/O)

9 19, 18 GPIO73 (I/O) XD6 (I/O) 10 21, 20 GPIO74 (I/O) XD5 (I/O) 11 23, 22 GPIO75 (I/O) XD4 (I/O) 12 25, 24 GPIO76 (I/O) XD3 (I/O) 13 27, 26 GPIO77 (I/O) XD2 (I/O) 14 29, 28 GPIO78 (I/O) XD1 (I/O) 15 31, 30 GPIO79 (I/O) XD0 (I/O)

GPCMUX2 GPCMUX2 = 0, 0 or 0, 1 GPCMUX2 = 1, 0 or 1, 1

no qual 16 1, 0 GPIO80 (I/O) XA8 (O)

17 3, 2 GPIO81 (I/O) XA9 (O) 18 5, 4 GPIO82 (I/O) XA10 (O) 19 7, 6 GPIO83 (I/O) XA11 (O) 20 9, 8 GPIO84 (I/O) XA12 (O) 21 11, 10 GPIO85 (I/O) XA13 (O) 22 13, 12 GPIO86 (I/O) XA14 (O) 23 15, 14 GPIO87 (I/O) XA15 (O)

The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from four choices:

• Synchronization To SYSCLKOUT Only (GPxQSEL1/2=0, 0): This is the default mode of all GPIO pins at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).

• Qualification Using Sampling Window (GPxQSEL1/2=0, 1 and 1, 0): In this mode the input signal, after synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before the input is allowed to change.

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GPyCTRL Reg

SYNC

SYSCLKOUT

Qualification

Input Signal Qualified By 3 or 6 Samples

GPIOx

Time between samples

GPxQSEL

Number of Samples

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• The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The sampling window is either 3-samples or 6-samples wide and the output is only changed when ALL samples are the same (all 0s or all 1s) as shown in Figure 4-18 (for 6 sample mode).

• No Synchronization (GPxQSEL1/2=1,1): This mode is used for peripherals where synchronization is not required (synchronization is performed within the peripheral).

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Figure 4-19. Qualification Using Sampling Window

Due to the multi-level multiplexing that is required on the device, there may be cases where a peripheral input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the input signal will default to either a 0 or 1 state, depending on the peripheral.

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XD(31:0)

XA(19:0)

XZCS0

XZCS6

XZCS7

XWE0

XR/W

XREADY

XHOLD

XHOLDA

XCLKOUT

XRD

XINTFZone0

(8Kx16)

XINTFZone7

(1Mx16)

0x0030−0000

0x0020−0000

0x0010−0000

0x0000−5000

0x0000−4000

0x0000−0000

DataSpace ProgSpace

XINTFZone6

(1Mx16)

XA0/XWE1

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4.14 External Interface (XINTF)

This section gives a top-level view of the external interface (XINTF) that is implemented on the F28335. The XINTF is a non-multiplexed asynchronous bus, similar to the 2812 XINTF. The XINTF is mapped into

three fixed zones shown in Figure 4-20.

SPRS682–DECEMBER 2010

A. Each zone can be programmed with different wait states, setup and hold timings, and is supported by zone chip

selects that toggle when an access to a particular zone is performed. These features enable glueless connection to

many external memories and peripherals. B. Zones 1 – 5 are reserved for future expansion. C. Zones 0, 6, and 7 are always enabled.

Figure 4-20. External Interface Block Diagram

Figure 4-21 and Figure 4-22 show typical 16-bit and 32-bit data bus XINTF connections, illustrating how

the functionality of the XA0 and XWE1 signals change, depending on the configuration. Table 4-19 defines XINTF configuration and control registers.

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A(19:1)

A(0)

D(15:0)

16-bits

External wait-state generator

XREADY

XCLKOUT

XZCS0/6/7

XA(19:1)

XA0/XWE1

XRD

XWE0

XD(15:0)

XINTF

A(18:0)

D(15:0)

Low16-bits

External wait-state generator

XREADY

XCLKOUT

XA(19:1)

XRD

XWE0

XD(15:0)

XINTF

A(18:0)

D(31:16)

XZCS0/6/7

XA0/ (select

XWE1

XWE1)

XD(31:16)

High16-bits

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Figure 4-21. Typical 16-bit Data Bus XINTF Connections

Figure 4-22. Typical 32-bit Data Bus XINTF Connections

NAME ADDRESS SIZE (x16) DESCRIPTION

XTIMING0 0x00−0B20 2 XINTF Timing Register, Zone 0 XTIMING6 XTIMING7 0x00−0B2E 2 XINTF Timing Register, Zone 7 XINTCNF2 XBANK 0x00−0B38 1 XINTF Bank Control Register XREVISION 0x00−0B3A 1 XINTF Revision Register XRESET 0x00 083D 1 XINTF Reset Register

(1) XTIMING1 - XTIMING5 are reserved for future expansion and are not currently used. (2) XINTCNF1 is reserved and not currently used.

(1)

(2)

Table 4-19. XINTF Configuration and Control Register Mapping

0x00−0B2C 2 XINTF Timing Register, Zone 6

0x00−0B34 2 XINTF Configuration Register

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5 Device Support

Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of DSCs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.

The following products support development of F28335-based applications:

Software Development Tools

• Code Composer Studio™ Integrated Development Environment (IDE) – C/C++ Compiler – Code generation tools – Assembler/Linker – Cycle Accurate Simulator

• Application algorithms

• Sample applications code

Hardware Development Tools

• Development board

• Evaluation modules

• JTAG-based emulators - SPI515, XDS510PP, XDS510PP Plus, XDS510USB

• Universal 5-V dc power supply

• Documentation and cables

SPRS682–DECEMBER 2010

6 Electrical Specifications

This section provides the absolute maximum ratings and the recommended operating conditions.

6.1 Absolute Maximum Ratings

Unless otherwise noted, the list of absolute maximum ratings are specified over operating temperature ranges.

Supply voltage range, V Supply voltage range, V Supply voltage range, V Supply voltage range, V Supply voltage range, V Input voltage range, V Output voltage range, V Input clamp current, IIK(VIN< 0 or VIN> V Output clamp current, IOK(VO< 0 or VO> V Operating case temperature range, T

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.2 is not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to VSS, unless otherwise noted. (3) Continuous clamp current per pin is ± 2 mA. This includes the analog inputs which have an internal clamping circuit that clamps the

voltage to a diode drop above V

DDIO DDA2 DD DD1A18 SSA2

, V

DD3VFL DDAIO

, V

DD2A18

SSAIO

, V

SS1AGND

DDA2

(1) (2)

with respect to V with respect to V with respect to V with respect to V

, V

SS2AGND

(3)

)

DDIO

) ± 20 mA

DDIO

or below V

SSA2

with respect to V

SS SSA SS SSA SS

– 0.3 V to 4.6 V – 0.3 V to 4.6 V – 0.3 V to 2.5 V – 0.3 V to 2.5 V – 0.3 V to 0.3 V – 0.3 V to 4.6 V – 0.3 V to 4.6 V

– 55°C to 210°C

± 20 mA

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0.00

20,000.00

40,000.00

80,000.00

100,000.00

160,000.00

125 130 135 140 150 155 160 165 170 175 180 185 190 195 200 205 210

Die Junction Temperature (°C)

Lifetime (Hours)

145

140,000.00

120,000.00

60,000.00

SM320F28335-HT

SPRS682–DECEMBER 2010

A. See the data sheet for absolute maximum and minimum recommended operating conditions. B. The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the

dominant failure mechanism affecting device wearout for the specific device process and design characteristics.

Figure 6-1. SM320F28335 Operating Life Derating Chart

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6.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

Device supply voltage, I/O, V Device supply voltage CPU, V Supply ground, VSS, V

SS1AGND

, V

SS2AGND

ADC supply voltage (3.3 V), V ADC supply voltage, V Flash supply voltage, V

Device clock frequency (system clock), f

SYSCLKOUT

High-level input voltage, V Low-level input voltage, V

High-level output source current, VOH= 2.4 V, I

Low-level output sink current, VOL= VOLMAX, I

Case temperature, T

SSIO

DD1A18

DD3VFL

, V

DDIO

SSAIO

DDA2

, V

DD2A18

, V

SSA2

DDAIO

TC= – 55°C to 125°C 2 150 TC= 210°C 2 100

All I/Os except Group 2 – 4 Group 2

(1)

All I/Os except Group 2 4 Group 2

(1)

S version – 55 210

(1) Group 2 pins are as follows: GPIO28, GPIO29, GPIO30, GPIO31, TDO, XCLKOUT, EMU0, EMU1, XINTF pins, GPIO35-87, XRD.

3.135 3.3 3.465 V

1.805 1.9 1.995 V 0 V

3.135 3.3 3.465 V

1.805 1.9 1.995 V

3.135 3.3 3.465 V

2 V

DDIO

0.8

- 8

MHz

6.3 Electrical Characteristics

Minimum and maximum parameters are characterized for operation at TC= 210°C unless otherwise noted, but may not be production tested at that temperature. Production test limits with statistical guardbands are used to ensure high temperature performance.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level output voltage V

Low-level output voltage IOL= IOLMAX 0.4 V

Pin with pullup

Input current (low level)

enabled Pin with pulldown

enabled Pin with pullup

Input current (high level)

enabled Pin with pulldown

enabled

Output current, pullup or

pulldown disabled

CIInput capacitance 2 pF

IOH= IOHMAX 2.4 IOH= 50 mA V

= 3.3 V, VIN= 0 V All I/Os (including XRS) – 80 – 140 – 190

DDIO

= 3.3 V, VIN= 0 V ± 2

DDIO

= 3.3 V, VIN= V

DDIO

= 3.3 V, VIN= V

DDIO

VO= V

DDIO

or 0 V ± 2 mA

DDIO

– 0.2

DDIO

28 50 80

± 2

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6.4 Current Consumption

Table 6-1. Current Consumption by Power Supply Pins

MODE TEST CONDITIONS UNITS

The following peripheral TC= -55°C to clocks are enabled: 125°C at

• ePWM1/2/3/4/5/6

• eCAP1/2/3/4/5/6

• eQEP1/2

• eCAN-A

• SCI-A/B (FIFO

Operational

(6)

(Flash)

IDLE mA

STANDBY Peripheral clocks are mA

(8)

HALT

(1) I

DDIO

(2) The I

During flash programming, extra current is drawn from the VDDand V

mode)

• SPI-A (FIFO mode)

• ADC

• I2C

• CPU Timer 0/1/2

All PWM pins are toggled at 150 kHz. All I/O pins are left unconnected.

Flash is powered down. TC= -55°C to XCLKOUT is turned off. 125°C at The following peripheral 150-MHz clocks are enabled: SYSCLKOUT

• eCAN-A

• SCI-A

• SPI-A

• I2C

Flash is powered down. off.

Flash is powered down. Peripheral clocks are off. mA Input clock is disabled.

(7)

(9)

current is dependent on the electrical loading on the I/O pins.

current indicated in this table is the flash read-current and does not include additional current for erase/write operations.

DD3VFL

150-MHz SYSCLKOUT

TC= 210°C at 100-MHz 200 30 50 35 40 35 40 1.5 2 SYSCLKOUT

TC= 210°C at 100-MHz 120 160 0.110 0.300 0.002 0.010 0.130 0.060 0.015 0.020 SYSCLKOUT

TC= -55°C to 125°C at 150-MHz SYSCLKOUT

TC= 210°C at 100-MHz 20 60 0.110 0.300 0.002 0.010 0.130 0.600 0.015 0.020 SYSCLKOUT

TC= -55°C to 125°C at 150-MHz SYSCLKOUT

TC= 210°C at 100-MHz 5 0.110 0.300 0.002 0.010 0.130 0.600 0.015 0.020 SYSCLKOUT

(5)

TYP

0.150 0.060 0.120 0.002 0.010 0.005 0.060 0.015 0.020

MAX TYP

290 315 30 50 3 40 30 35 1.5 2

100 120 0.060 0.120 0.002 0.010 0.005 0.060 0.015 0.020

8 15 0.060 0.120 0.002 0.010 0.005 0.060 0.015 0.020

involves on-board flash programming, this extra current must be taken into account while architecting the power-supply stage.

(3) I (4) I

(5) The TYP numbers are applicable over room temperature and nominal voltage. MAX numbers are at 125°C, and MAX voltage (VDD= 2.0 (6) When the identical code is run off SARAM, IDDwould increase as the code operates with zero wait states.

includes current into V

DDA18

clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.

includes current into V

DDA33

V; V

DDIO

, V

DD3VFL

, V

DDA

= 3.6 V).

DD1A18

DDA2

and V

DD2A18

DDAIO

pins. In order to realize the I

pins.

(1)

DDIO (5)

MAX TYP MAX TYP

rails, as indicated in Table 6-66. If the user application

DD3VFL

DDA18

(7) The following is done in a loop:

• Data is continuously transmitted out of the SCI-A, SCI-B, SPI-A, McBSP-A, and eCAN-A ports.

• Multiplication/addition operations are performed.

• Watchdog is reset.

• ADC is performing continuous conversion. Data from ADC is transferred to SARAM through the DMA.

• 32-bit read/write of the XINTF is performed.

• GPIO19 is toggled. (8) HALT mode IDDcurrents will increase with temperature in a non-linear fashion. (9) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the internal oscillator.

DD3VFL

(2)

DDA18

(5)

(3)

MAX TYP

DDA33 (5)

(4)

MAX

currents shown for IDLE, STANDBY, and HALT,

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NOTE

The peripheral - I/O multiplexing implemented in the device prevents all available peripherals from being used at the same time. This is because more than one peripheral function may share an I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time, although such a configuration is not useful. If this is done, the current drawn by the device will be more than the numbers specified in the current consumption tables.

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6.4.1 Reducing Current Consumption

The F28335 DSC incorporates a method to reduce the device current consumption. Since each peripheral unit has an individual clock-enable bit, reduction in current consumption can be achieved by turning off the clock to any peripheral module that is not used in a given application. Furthermore, any one of the three low-power modes could be taken advantage of to reduce the current consumption even further. Table 6-2 indicates the typical reduction in current consumption achieved by turning off the clocks.

Table 6-2. Typical Current Consumption by Various

Peripherals (at 150 MHz)

PERIPHERAL IDDCURRENT

MODULE REDUCTION/MODULE (mA)

ADC 8

I2C 2.5

eQEP 5

ePWM 5

eCAP 2

SCI 5 SPI 4

eCAN 8

McBSP 7

CPU - Timer 2

XINTF 10

DMA 10

FPU 15

(1) All peripheral clocks are disabled upon reset. Writing to/reading from

peripheral registers is possible only after the peripheral clocks are

turned on. (2) Not production tested. (3) For peripherals with multiple instances, the current quoted is per

module. For example, the 5 mA number quoted for ePWM is for one

ePWM module. (4) This number represents the current drawn by the digital portion of

the ADC module. Turning off the clock to the ADC module results in

the elimination of the current drawn by the analog portion of the ADC

) as well.

DDA18

(5) Operating the XINTF bus has a significant effect on IDDIO current. It

will increase considerably based on the following:

• How many address/data pins toggle from one cycle to another

• How fast they toggle

• Whether 16-bit or 32-bit interface is used and

• The load on these pins.

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(1)(2)

(3)

(4)

(5)

Following are other methods to reduce power consumption further:

• The Flash module may be powered down if code is run off SARAM. This results in a current reduction of 35 mA (typical) in the V

• I

current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.

DDIO

• Significant savings in I

DD3VFL

DDIO

rail.

may be realized by disabling the pullups on pins that assume an output

function and on XINTF pins. A savings of 35 mW (typical) can be achieved by this.

The baseline IDDcurrent (current when the core is executing a dummy loop with no peripherals enabled) is 165 mA, (typical). To arrive at the IDDcurrent for a given application, the current-drawn by the peripherals (enabled by that application) must be added to the baseline IDDcurrent.

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Current vs Frequency

0.00

50.00

100.00

150.00

200.00

250.00

300.00

350.00

10 20 30 40 50 60 70 80 90 100 110 120 130 140 150

Frequency (MHz)

Current (mA)

IDD IDDA18 IDD3VFL IDDA33 IDDIO 1.9V Supply 3.3V Supply

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6.4.2 Current Consumption Graphs

SPRS682–DECEMBER 2010

Figure 6-2. Typical Operational Current Versus Frequency for TA= 25°C

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Current vs Frequency

0.00

50.00

100.00

150.00

200.00

250.00

300.00

10 20 30 40 50 60 70 80 90 100

Frequency(MHz)

Current (mA)

IDD IDDIO IDDA18 IDDA33 IDD3VFL 1.9V Supply 3.3V Supply

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6.4.3 Thermal Design Considerations

6.5 Emulator Connection Without Signal Buffering for the DSP

Figure 6-3. Typical Operational Current Versus Frequency for TA= 210°C

Based on the end application design and operational profile, the IDDand I Systems with more than 1 Watt power dissipation may require a product level thermal design. Care should be taken to keep Tjwithin specified limits. In the end applications, T the operating junction temperature Tj. T

is normally measured at the center of the package top side

case

should be measured to estimate

case

surface.

Figure 6-4 shows the connection between the DSP and JTAG header for a single-processor configuration.

If the distance between the JTAG header and the DSP is greater than 6 inches, the emulation signals must be buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 6-4 shows the simpler, no-buffering situation. For the pullup/pulldown resistor values, see the pin description section.

currents could vary.

DDIO

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Texas instruments SM320F28335-HT Data Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 SM320F28335 DSC

1.1 Features

1.2 SUPPORTS EXTREME TEMPERATURE APPLICATIONS

2 Introduction

2.1 Pin Assignments

2.2 Signal Descriptions

3 Functional Overview

3.1 Memory Maps

3.2 Brief Descriptions

3.2.1 C28x CPU

3.2.2 Memory Bus (Harvard Bus Architecture)

3.2.3 Peripheral Bus

3.2.4 Real-Time JTAG and Analysis

3.2.5 External Interface (XINTF)

3.2.6 Flash

3.2.7 M0, M1 SARAMs

3.2.8 L0, L1, L2, L3, L4, L5, L6, L7 SARAMs

3.2.9 Boot ROM

3.2.10 Security

3.2.11 Peripheral Interrupt Expansion (PIE) Block

3.2.12 External Interrupts (XINT1-XINT7, XNMI)

3.2.13 Oscillator and PLL

3.2.14 Watchdog

3.2.15 Peripheral Clocking

3.2.16 Low-Power Modes

3.2.17 Peripheral Frames 0, 1, 2, 3 (PFn)

3.2.18 General-Purpose Input/Output (GPIO) Multiplexer

3.2.19 32-Bit CPU-Timers (0, 1, 2)

3.2.20 Control Peripherals

3.2.21 Serial Port Peripherals

3.3 Register Map

3.4 Device Emulation Registers

3.5 Interrupts

3.5.1 External Interrupts

3.6 System Control

3.6.1 OSC and PLL Block

3.6.1.1 External Reference Oscillator Clock Option

3.6.1.2 PLL-Based Clock Module

3.6.1.3 Loss of Input Clock

3.6.2 Watchdog Block

3.7 Low-Power Modes Block

4 Peripherals

4.1 DMA Overview

4.2 32-Bit CPU-Timers 0/1/2

4.3 Enhanced PWM Modules (ePWM1/2/3/4/5/6)

4.4 High-Resolution PWM (HRPWM)

4.5 Enhanced CAP Modules (eCAP1/2/3/4/5/6)

4.6 Enhanced QEP Modules (eQEP1/2)

4.7 Analog-to-Digital Converter (ADC) Module

4.7.1 ADC Connections if the ADC Is Not Used

4.7.2 ADC Registers

4.7.3 ADC Calibration

4.8 Multichannel Buffered Serial Port (McBSP) Module

4.9 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)

4.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)

4.11 Serial Peripheral Interface (SPI) Module (SPI-A)

4.12 Inter-Integrated Circuit (I2C)

4.13 GPIO MUX

4.14 External Interface (XINTF)

5 Device Support

6 Electrical Specifications

6.1 Absolute Maximum Ratings

6.2 Recommended Operating Conditions

6.3 Electrical Characteristics

6.4 Current Consumption

6.4.1 Reducing Current Consumption

6.4.2 Current Consumption Graphs

6.4.3 Thermal Design Considerations

6.5 Emulator Connection Without Signal Buffering for the DSP