Texas Instruments SM320F2812-HT User Manual

SM320F2812-HT

Digital Signal Processor

Data Manual

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Literature Number: SGUS062A
June 2009–Revised April 2010

SM320F2812-HT

SGUS062A–JUNE 2009–REVISED APRIL 2010

www.ti.com

Contents

1 Features ........................................................................................................................... 11

1.1 SUPPORTS EXTREME TEMPERATURE APPLICATIONS ......................................................... 12

2 Introduction ...................................................................................................................... 13

2.1 Description ................................................................................................................. 13

2.2 Device Summary .......................................................................................................... 14

2.3 Die Layout .................................................................................................................. 15

2.4 Pin Assignments ........................................................................................................... 16

2.5 Signal Descriptions ........................................................................................................ 17

3 Functional Overview .......................................................................................................... 27

3.1 Memory Map ............................................................................................................... 28

3.2 Brief Descriptions .......................................................................................................... 31

3.2.1 C28x CPU ....................................................................................................... 31

3.2.2 Memory Bus (Harvard Bus Architecture) .................................................................... 31

3.2.3 Peripheral Bus .................................................................................................. 31

3.2.4 Real-Time JTAG and Analysis ................................................................................ 31

3.2.5 External Interface (XINTF) .................................................................................... 32

3.2.6 Flash ............................................................................................................. 32

3.2.7 L0, L1, H0 SARAMs ............................................................................................ 32

3.2.8 Boot ROM ....................................................................................................... 32

3.2.9 Security .......................................................................................................... 33

3.2.10 Peripheral Interrupt Expansion (PIE) Block ................................................................. 34

3.2.11 External Interrupts (XINT1, XINT2, XINT13, XNMI) ........................................................ 34

3.2.12 Oscillator and PLL .............................................................................................. 34

3.2.13 Watchdog ........................................................................................................ 34

3.2.14 Peripheral Clocking ............................................................................................. 34

3.2.15 Low-Power Modes .............................................................................................. 34

3.2.16 Peripheral Frames 0, 1, 2 (PFn) .............................................................................. 35

3.2.17 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 35

3.2.18 32-Bit CPU Timers (0, 1, 2) ................................................................................... 35

3.2.19 Control Peripherals ............................................................................................. 35

3.2.20 Serial Port Peripherals ......................................................................................... 36

3.3 Register Map ............................................................................................................... 36

3.4 Device Emulation Registers .............................................................................................. 39

3.5 External Interface, XINTF ................................................................................................ 39

3.5.1 Timing Registers ................................................................................................ 41

3.5.2 XREVISION Register ........................................................................................... 41

3.6 Interrupts .................................................................................................................... 42

3.6.1 External Interrupts .............................................................................................. 45

3.7 System Control ............................................................................................................ 46

3.8 OSC and PLL Block ....................................................................................................... 48

3.8.1 Loss of Input Clock ............................................................................................. 49

3.9 PLL-Based Clock Module ................................................................................................ 49

3.10 External Reference Oscillator Clock Option ........................................................................... 49

3.11 Watchdog Block ........................................................................................................... 50

3.12 Low-Power Modes Block ................................................................................................. 51

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4 Peripherals ....................................................................................................................... 52

4.1 32-Bit CPU-Timers 0/1/2 ................................................................................................. 52

4.2 Event Manager Modules (EVA, EVB) ................................................................................... 55

4.2.1 General-Purpose (GP) Timers ................................................................................ 58

4.2.2 Full-Compare Units ............................................................................................. 58

4.2.3 Programmable Deadband Generator ........................................................................ 58

4.2.4 PWM Waveform Generation .................................................................................. 58

4.2.5 Double Update PWM Mode ................................................................................... 58

4.2.6 PWM Characteristics ........................................................................................... 59

4.2.7 Capture Unit ..................................................................................................... 59

4.2.8 Quadrature-Encoder Pulse (QEP) Circuit ................................................................... 59

4.2.9 External ADC Start-of-Conversion ........................................................................... 59

4.3 Enhanced Analog-to-Digital Converter (ADC) Module ............................................................... 60

4.4 Enhanced Controller Area Network (eCAN) Module .................................................................. 65

4.5 Multichannel Buffered Serial Port (McBSP) Module .................................................................. 69

4.6 Serial Communications Interface (SCI) Module ....................................................................... 73

4.7 Serial Peripheral Interface (SPI) Module ............................................................................... 76

4.8 GPIO MUX ................................................................................................................. 79

5 Development Support ........................................................................................................ 82

5.1 Device and Development Support Tool Nomenclature ............................................................... 82

5.2 Documentation Support ................................................................................................... 83

6 Electrical Specifications ..................................................................................................... 85

6.1 Absolute Maximum Ratings .............................................................................................. 85

6.2 Recommended Operating Conditions .................................................................................. 86

6.3 Electrical Characteristics ................................................................................................. 86

6.4 Current Consumption by Power-Supply Pins Over Recommended Operating Conditions During

Low-Power Modes at 150-MHz SYSCLKOUT ......................................................................... 88

6.5 Current Consumption Graphs ............................................................................................ 89

6.6 Reducing Current Consumption ......................................................................................... 90

6.7 Power Sequencing Requirements ....................................................................................... 90

6.8 Signal Transition Levels .................................................................................................. 91

6.9 Timing Parameter Symbology ........................................................................................... 92

6.10 General Notes on Timing Parameters .................................................................................. 93

6.11 Test Load Circuit .......................................................................................................... 93

6.12 Device Clock Table ........................................................................................................ 94

6.13 Clock Requirements and Characteristics ............................................................................... 94

6.13.1 Input Clock Requirements ..................................................................................... 94

6.13.2 Output Clock Characteristics .................................................................................. 95

6.14 Reset Timing ............................................................................................................... 96

6.15 Low-Power Mode Wakeup Timing ..................................................................................... 100

6.16 Event Manager Interface ................................................................................................ 104

6.16.1 PWM Timing ................................................................................................... 104

6.16.2 Interrupt Timing ................................................................................................ 106

6.17 General-Purpose Input/Output (GPIO) – Output Timing ............................................................ 107

6.18 General-Purpose Input/Output (GPIO) – Input Timing .............................................................. 108

6.19 SPI Master Mode Timing ................................................................................................ 109

Copyright © 2009–2010, Texas Instruments Incorporated Contents 3

SM320F2812-HT

SGUS062A–JUNE 2009–REVISED APRIL 2010

6.20 SPI Slave Mode Timing ................................................................................................. 113

6.21 External Interface (XINTF) Timing ..................................................................................... 117

6.22 XINTF Signal Alignment to XCLKOUT ................................................................................ 121

6.23 External Interface Read Timing ........................................................................................ 122

6.24 External Interface Write Timing ........................................................................................ 123

6.25 External Interface Ready-on-Read Timing With One External Wait State ....................................... 125

6.26 External Interface Ready-on-Write Timing With One External Wait State ........................................ 128

6.27 XHOLD and XHOLDA ................................................................................................... 131

6.28 XHOLD/XHOLDA Timing ............................................................................................... 132

6.29 On-Chip Analog-to-Digital Converter .................................................................................. 134

6.29.1 ADC Absolute Maximum Ratings ........................................................................... 134

6.29.2 ADC Electrical Characteristics Over Recommended Operating Conditions ........................... 135

6.29.3 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK) ...................... 136

6.29.4 ADC Power-Up Control Bit Timing .......................................................................... 137

6.29.5 Detailed Description .......................................................................................... 138

6.29.5.1 Reference Voltage ................................................................................ 138

6.29.5.2 Analog Inputs ..................................................................................... 138

6.29.5.3 Converter .......................................................................................... 138

6.29.5.4 Conversion Modes ............................................................................... 138

6.29.6 Sequential Sampling Mode (Single Channel) (SMODE = 0) ............................................ 138

6.29.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) .......................................... 140

6.29.8 Definitions of Specifications and Terminology ............................................................. 141

6.29.8.1 Integral Nonlinearity .............................................................................. 141

6.29.8.2 Differential Nonlinearity .......................................................................... 141

6.29.8.3 Zero Offset ........................................................................................ 141

6.29.8.4 Gain Error ......................................................................................... 141

6.29.8.5 Signal-to-Noise Ratio + Distortion (SINAD) ................................................... 141

6.29.8.6 Effective Number of Bits (ENOB) ............................................................... 141

6.29.8.7 Total Harmonic Distortion (THD) ............................................................... 141

6.29.8.8 Spurious Free Dynamic Range (SFDR) ....................................................... 141

6.30 Multichannel Buffered Serial Port (McBSP) Timing ................................................................. 142

6.30.1 McBSP Transmit and Receive Timing ...................................................................... 142

6.30.2 McBSP as SPI Master or Slave Timing .................................................................... 145

6.31 Flash Timing .............................................................................................................. 149

6.31.1 Recommended Operating Conditions ...................................................................... 149

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7 Mechanical Data .............................................................................................................. 151

4 Contents Copyright © 2009–2010, Texas Instruments Incorporated

SM320F2812-HT

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SGUS062A–JUNE 2009–REVISED APRIL 2010

List of Figures

2-1 SM320F2812 Die Layout........................................................................................................ 15

2-2 SM320F2812 172-Pin HFG CQFP (Top View)............................................................................... 16

3-1 Functional Block Diagram....................................................................................................... 28

3-2 F2812 Memory Map (See Notes A. Through G.) ............................................................................ 28

3-3 External Interface Block Diagram .............................................................................................. 40

3-4 Interrupt Sources ................................................................................................................. 42

3-5 Multiplexing of Interrupts Using the PIE Block ............................................................................... 43

3-6 Clock and Reset Domains ...................................................................................................... 46

3-7 OSC and PLL Block.............................................................................................................. 48

3-8 Recommended Crystal/Clock Connection .................................................................................... 49

3-9 Watchdog Module ................................................................................................................ 50

4-1 CPU-Timers....................................................................................................................... 52

4-2 CPU-Timer Interrupts Signals and Output Signal (See Notes A. and B.)................................................. 53

4-3 Event Manager A Functional Block Diagram (See Note A.)................................................................ 58

4-4 Block Diagram of the F2812 ADC Module.................................................................................... 61

4-5 ADC Pin Connections With Internal Reference (See Notes A and B)..................................................... 62

4-6 ADC Pin Connections With External Reference ............................................................................. 63

4-7 eCAN Block Diagram and Interface Circuit................................................................................... 66

4-8 eCAN Memory Map .............................................................................................................. 67

4-9 McBSP Module With FIFO...................................................................................................... 70

4-10 Serial Communications Interface (SCI) Module Block Diagram............................................................ 75

4-11 Serial Peripheral Interface Module Block Diagram (Slave Mode).......................................................... 78

4-12 GPIO/Peripheral Pin Multiplexing .............................................................................................. 81

5-1 28x Device Nomenclature....................................................................................................... 83

6-1 SM320F2812-HT Life Expectancy Curve ..................................................................................... 87

6-2 Typical Current Consumption Over Frequency............................................................................... 89

6-3 Typical Power Consumption Over Frequency................................................................................ 90

6-4 F2812 Typical Power-Up and Power-Down Sequence – Option 2 ........................................................ 91

6-5 Output Levels ..................................................................................................................... 92

6-6 Input Levels ....................................................................................................................... 92

6-7 3.3-V Test Load Circuit.......................................................................................................... 93

6-8 Clock Timing ...................................................................................................................... 96

6-9 Power-on Reset in Microcomputer Mode (XMP/MC = 0) (See Note A)................................................... 98

6-10 Power-on Reset in Microprocessor Mode (XMP/MC = 1)................................................................... 99

6-11 Warm Reset in Microcomputer Mode.......................................................................................... 99

6-12 Effect of Writing Into PLLCR Register......................................................................................... 99

6-13 IDLE Entry and Exit Timing.................................................................................................... 100

6-14 STANDBY Entry and Exit Timing............................................................................................. 102

6-15 HALT Wakeup Using XNMI ................................................................................................... 104

6-16 PWM Output Timing............................................................................................................ 105

6-17 TDIRx Timing.................................................................................................................... 106

6-18 EVASOC Timing................................................................................................................ 106

6-19 EVBSOC Timing................................................................................................................ 106

6-20 External Interrupt Timing....................................................................................................... 107

6-21 General-Purpose Output Timing.............................................................................................. 108

6-22 GPIO Input Qualifier – Example Diagram for QUALPRD = 1............................................................. 108

Copyright © 2009–2010, Texas Instruments Incorporated List of Figures 5

SM320F2812-HT

SGUS062A–JUNE 2009–REVISED APRIL 2010

6-23 General-Purpose Input Timing................................................................................................ 109

6-24 SPI Master Mode External Timing (Clock Phase = 0) ..................................................................... 110

6-25 SPI Master External Timing (Clock Phase = 1)............................................................................. 112

6-26 SPI Slave Mode External Timing (Clock Phase = 0)....................................................................... 114

6-27 SPI Slave Mode External Timing (Clock Phase = 1)....................................................................... 116

6-28 Relationship Between XTIMCLK and SYSCLKOUT ....................................................................... 120

6-29 Example Read Access......................................................................................................... 122

6-30 Example Write Access......................................................................................................... 124

6-31 Example Read With Synchronous XREADY Access ...................................................................... 126

6-32 Example Read With Asynchronous XREADY Access..................................................................... 127

6-33 Write With Synchronous XREADY Access.................................................................................. 129

6-34 Write With Asynchronous XREADY Access ................................................................................ 130

6-35 External Interface Hold Waveform............................................................................................ 132

6-36 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK).................................................. 133

6-37 ADC Analog Input Impedance Model ........................................................................................ 137

6-38 ADC Power-Up Control Bit Timing ........................................................................................... 137

6-39 Sequential Sampling Mode (Single-Channel) Timing...................................................................... 139

6-40 Simultaneous Sampling Mode Timing ....................................................................................... 140

6-41 McBSP Receive Timing........................................................................................................ 144

6-42 McBSP Transmit Timing....................................................................................................... 144

6-43 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0................................................... 145

6-44 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0................................................... 146

6-45 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1................................................... 147

6-46 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1................................................... 148

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6 List of Figures Copyright © 2009–2010, Texas Instruments Incorporated

SM320F2812-HT

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SGUS062A–JUNE 2009–REVISED APRIL 2010

List of Tables

2-1 Hardware Features............................................................................................................... 14

2-2 Bare Die Information............................................................................................................. 15

2-3 Signal Descriptions .............................................................................................................. 17

3-1 Addresses of Flash Sectors in F2812 ......................................................................................... 29

3-2 Wait States ........................................................................................................................ 30

3-3 Boot Mode Selection............................................................................................................. 33

3-4 Peripheral Frame 0 Registers .................................................................................................. 37

3-5 Peripheral Frame 1 Registers .................................................................................................. 37

3-6 Peripheral Frame 2 Registers .................................................................................................. 38

3-7 Device Emulation Registers..................................................................................................... 39

3-8 XINTF Configuration and Control Register Mappings....................................................................... 41

3-9 XREVISION Register Bit Definitions........................................................................................... 41

3-10 PIE Peripheral Interrupts ....................................................................................................... 43

3-11 PIE Configuration and Control Registers ..................................................................................... 44

3-12 External Interrupts Registers ................................................................................................... 45

3-13 PLL, Clocking, Watchdog, and Low-Power Mode Registers .............................................................. 47

3-14 PLLCR Register Bit Definitions................................................................................................. 48

3-15 Possible PLL Configuration Modes ............................................................................................ 49

3-16 F2812 Low-Power Modes....................................................................................................... 51

4-1 CPU-Timers 0, 1, 2 Configuration and Control Registers................................................................... 54

4-2 Module and Signal Names for EVA and EVB ................................................................................ 55

4-3 EVA Registers ................................................................................................................... 56

4-4 ADC Registers ................................................................................................................... 64

4-5 3.3-V eCAN Transceivers for the SM320F2812 DSP....................................................................... 66

4-6 CAN Registers Map ............................................................................................................. 68

4-7 McBSP Register Summary...................................................................................................... 71

4-8 SCI-A Registers .................................................................................................................. 74

4-9 SCI-B Registers .................................................................................................................. 74

4-10 SPI Registers .................................................................................................................... 77

4-11 GPIO Mux Registers ............................................................................................................ 79

4-12 GPIO Data Registers ............................................................................................................ 80

6-1 Typical Current Consumption by Various Peripherals (at 150 MHz) ..................................................... 90

6-2 Recommended Low-Dropout Regulators ..................................................................................... 91

6-3 Clock Table and Nomenclature................................................................................................. 94

6-4 Input Clock Frequency .......................................................................................................... 94

6-5 XCLKIN Timing Requirements – PLL Bypassed or Enabled .............................................................. 95

6-6 XCLKIN Timing Requirements – PLL Disabled .............................................................................. 95

6-7 Possible PLL Configuration Modes ........................................................................................... 95

6-8 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ....................................................... 95

6-9 Reset (XRS) Timing Requirements ........................................................................................... 96

6-10 IDLE Mode Switching Characteristics ....................................................................................... 100

6-11 STANDBY Mode Switching Characteristics ................................................................................ 101

6-12 HALT Mode Switching Characteristics ...................................................................................... 103

6-13 PWM Switching Characteristics .............................................................................................. 105

6-14 Timer and Capture Unit Timing Requirements ............................................................................. 105

6-15 External ADC Start-of-Conversion – EVA – Switching Characteristics ................................................. 106

Copyright © 2009–2010, Texas Instruments Incorporated List of Tables 7

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SGUS062A–JUNE 2009–REVISED APRIL 2010

6-16 External ADC Start-of-Conversion – EVB – Switching Characteristics ................................................. 106

6-17 Interrupt Switching Characteristics ........................................................................................... 106

6-18 Interrupt Timing Requirements................................................................................................ 107

6-19 General-Purpose Output Switching Characteristics........................................................................ 107

6-20 General-Purpose Input Timing Requirements .............................................................................. 108

6-21 SPI Master Mode External Timing (Clock Phase = 0) .................................................................... 109

6-22 SPI Master Mode External Timing (Clock Phase = 1) .................................................................... 111

6-23 SPI Slave Mode External Timing (Clock Phase = 0) ...................................................................... 113

6-24 SPI Slave Mode External Timing (Clock Phase = 1) ...................................................................... 115

6-25 Relationship Between Parameters Configured in XTIMING and Duration of Pulse ................................... 117

6-26 XTIMING Register Configuration Restrictions .............................................................................. 117

6-27 Valid and Invalid Timing ....................................................................................................... 117

6-28 XTIMING Register Configuration Restrictions .............................................................................. 118

6-29 Valid and Invalid Timing when using Synchronous XREADY ............................................................ 118

6-30 XTIMING Register Configuration Restrictions .............................................................................. 118

6-31 XTIMING Register Configuration Restrictions .............................................................................. 119

6-32 Asynchronous XREADY ...................................................................................................... 119

6-33 XINTF Clock Configurations................................................................................................... 119

6-34 External Memory Interface Read Switching Characteristics ............................................................. 122

6-35 External Memory Interface Read Timing Requirements .................................................................. 122

6-36 External Memory Interface Write Switching Characteristics .............................................................. 123

6-37 External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State) ....................... 125

6-38 External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) ............................ 125

6-39 Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... 125

6-40 Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ...................................... 125

6-41 External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) ........................ 128

6-42 Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ....................................... 128

6-43 Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ...................................... 128

6-44 XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) ...................................................... 132

6-45 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) ................................................. 133

6-46 DC Specifications .............................................................................................................. 135

6-47 AC Specifications .............................................................................................................. 136

6-48 Current Consumption .......................................................................................................... 136

6-49 ADC Power-Up Delays ........................................................................................................ 137

6-50 Sequential Sampling Mode Timing .......................................................................................... 139

6-51 Simultaneous Sampling Mode Timing ....................................................................................... 140

6-52 McBSP Timing Requirements ................................................................................................ 142

6-53 McBSP Switching Characteristics ........................................................................................... 143

6-54 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) ............................... 145

6-55 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) ........................... 145

6-56 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) ............................... 146

6-57 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) ........................... 146

6-58 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) ............................... 147

6-59 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) ........................... 147

6-60 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) ............................... 148

6-61 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) ........................... 148

6-62 Flash Parameters at 150-MHz SYSCLKOUT .............................................................................. 149

6-63 Flash/OTP Access Timing .................................................................................................... 149

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8 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated

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SGUS062A–JUNE 2009–REVISED APRIL 2010

6-64 Minimum Required Wait-States at Different Frequencies ................................................................ 149

Copyright © 2009–2010, Texas Instruments Incorporated List of Tables 9

SM320F2812-HT

SGUS062A–JUNE 2009–REVISED APRIL 2010

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10 List of Tables Copyright © 2009–2010, Texas Instruments Incorporated

SM320F2812-HT

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SGUS062A–JUNE 2009–REVISED APRIL 2010

Digital Signal Processor

Check for Samples: SM320F2812-HT

1 Features

12

• High-Performance Static CMOS Technology • 128 Bit Security Key/Lock
– 150 MHz (6.67 ns Cycle Time) – Protects Flash/ROM/OTP and L0/L1 SARAM
– Low Power (1.8 V Core at 135 MHz, 1.9 V, – Prevents Firmware Reverse Engineering

Core at 150 MHz, 3.3 V I/O) Design

– 3.3 V Flash Voltage

• JTAG Boundary Scan Support

(1)

• High-Performance 32 Bit CPU (TMS320C28x)
– 16 × 16 and 32 x 32 MAC Operations
– 16 × 16 Dual MAC
– Harvard Bus Architecture
– Atomic Operations (SCIs), Standard UART
– Fast Interrupt Response and Processing – Enhanced Controller Area Network (eCAN)
– Unified Memory Programming Model – Multichannel Buffered Serial Port (McBSP)
– 4M Linear Program Address Reach
– 4M Linear Data Address Reach
– Code-Efficient (in C/C++ and Assembly)
– TMS320F24x/LF240x Processor Source Code

Compatible – Single/Simultaneous Conversions

• On-Chip Memory – Fast Conversion Rate: 80 ns/12.5 MSPS
– Flash Devices: Up to 128K × 16 Flash (Four • Up to 56 Individually Programmable,

8K × 16 and Six 16K × 16 Sectors) Multiplexed General-Purpose Input / Output
– ROM Devices: Up to 128K × 16 ROM
– 1K × 16 OTP ROM
– L0 and L1: 2 Blocks of 4K × 16 Each

Single-Access RAM (SARAM) – Real-Time Debug via Hardware
– H0: 1 Block of 8K × 16 SARAM • Development Tools Include
– M0 and M1: 2 Blocks of 1K × 16 Each – ANSI C/C++ Compiler/Assembler/Linker

SARAM

• Boot ROM (4K × 16)
– With Software Boot Modes
– Standard Math Tables

• External Interface (TI) or Third-Party]
– Up to 1M Total Memory – Evaluation Modules
– Programmable Wait States – Broad Third-Party Digital Motor Control
– Programmable Read/Write Strobe Timing
– Three Individual Chip Selects

• Clock and System Control
– Dynamic PLL Ratio Changes Supported
– On-Chip Oscillator
– Watchdog Timer Module

• Three External Interrupts xxx

• Peripheral Interrupt Expansion (PIE) Block That
Supports 45 Peripheral Interrupts

(1) IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port

1TMS320C24x, Code Composer Studio, DSP/BIOS, C28x, TMS320C2000, TMS320C54x, TMS320C55x, TMS320C28x are trademarks of

Texas Instruments.

2eZdsp is a trademark of Spectrum Digital Incorporated.

• Three 32 Bit CPU Timers

• Motor Control Peripherals
– Two Event Managers (EVA, EVB)
– Compatible to 240xA Devices

• Serial Port Peripherals
– Serial Peripheral Interface (SPI)
– Two Serial Communications Interfaces

With SPI Mode

• 12 Bit ADC, 16 Channels
– 2 × 8 Channel Input Multiplexer
– Two Sample-and-Hold

(GPIO) Pins

• Advanced Emulation Features
– Analysis and Breakpoint Functions

– Supports TMS320C24x™/240x Instructions
– Code Composer Studio™ IDE
– DSP/BIOS™
– JTAG Scan Controllers [Texas Instruments

Support

• Low-Power Modes and Power Savings
– IDLE, STANDBY, HALT Modes Supported
– Disable Individual Peripheral Clocks

xxx
xxx

xxx
xxx

Copyright © 2009–2010, Texas Instruments Incorporated Features 11

SM320F2812-HT

SGUS062A–JUNE 2009–REVISED APRIL 2010

xxx

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1.1 SUPPORTS EXTREME TEMPERATURE APPLICATIONS

• Controlled Baseline

• One Assembly/Test Site

• One Fabrication Site

• Available in Extreme (–55°C/220°C) Temperature Range

• Extended Product Life Cycle

• Extended Product-Change Notification

• Product Traceability

• Texas Instruments high temperature products utilize highly optimized silicon (die) solutions with
design and process enhancements to maximize performance over extended temperatures.

(2) Custom temperature ranges available

(2)

12 Features Copyright © 2009–2010, Texas Instruments Incorporated

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2 Introduction

This section provides a summary of the device features, lists the pin assignments, and describes the
function of each pin. This document also provides detailed descriptions of peripherals, electrical
specifications, parameter measurement information, and mechanical data about the available packaging.

3

2.1 Description

The SM320F2812 device, member of the C28xE DSP generation, is a highly integrated, high-performance
solution for demanding control applications. The functional blocks and the memory maps are described in
Section 3, Functional Overview.

Throughout this document SM320F2812 is abbreviated as F2812.

SGUS062A–JUNE 2009–REVISED APRIL 2010

3

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2009–2010, Texas Instruments Incorporated

SM320F2812-HT

SGUS062A–JUNE 2009–REVISED APRIL 2010

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2.2 Device Summary

Table 2-1 provides a summary of the device features.

Table 2-1. Hardware Features

FEATURE F2812

Instruction Cycle (at 150 MHz) 6.67 ns
Single-Access RAM (SARAM) (16 bit word) 18K

3.3 V On-Chip Flash (16 bit word) 128K
On-Chip ROM (16-bit word) —
Code Security for On-Chip Flash/SARAM/OTP/ROM Yes
Boot ROM Yes
OTP ROM (1K × 16) Yes
External Memory Interface Yes
Event Managers A and B (EVA and EVB) EVA, EVB

• General-Purpose (GP) Timers 4

• Compare (CMP)/PWM 16

• Capture (CAP)/QEP Channels 6/2
Watchdog Timer Yes
12 Bit ADC Yes

• Channels 16
32 Bit CPU Timers 3
SPI Yes
SCIA, SCIB SCIA, SCIB
CAN Yes
McBSP Yes
Digital I/O Pins (Shared) 56
External Interrupts 3
Supply Voltage 1.8-V Core, (135 MHz) 1.9-V Core

Temperature Options S: –55°C to 220°C Yes

(150 MHz), 3.3-V I/O

14 Introduction Copyright © 2009–2010, Texas Instruments Incorporated

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2.3 Die Layout

The SM320F2812 die layout is shown in Figure 2-1. See Table 2-3 for a description of each pad's
function.

SGUS062A–JUNE 2009–REVISED APRIL 2010

Figure 2-1. SM320F2812 Die Layout

Table 2-2. Bare Die Information

DIE SIZE DIE PAD SIZE COMPOSITI

219.4 x 207.0 (mils); Silicon with

5572.0 x 5258.0 (mm) backgrind

Copyright © 2009–2010, Texas Instruments Incorporated Introduction 15

55.0 x 64.0 (mm) See Table 2-3 11.0 mils AlCu/TiN Ground

DIE PAD DIE BACKSIDE BACKSIDE

COORDINATES THICKNESS FINISH POTENTIAL

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DIE PAD

ON

V

DDAIO

1

130

172

ADCINB0

ADCINB1

ADCINB2

ADCINB3

ADCINB4

ADCINB5

ADCINB6

ADCINB7

ADCREFM

ADCREFP

AVSSREFBG

AVDDREFBG

V

DDA1

V

SSA1

ADCRESEXT

MC

XMP/

XA[0]

MDRA

XD[0]

MDXA

V

DD

XD[1]

MCLKRA

MFSXA

XD[2]

MCLKXA

MFSRA

XD[3]

V

DDIO

V

SS

XD[4]

SPICLKA

SPISTEA

XD[5]

V

DD

V

SS

XD[6]

SPISIMOA

SPISOMIA

XRD

XA[1]

XZCS0AND1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

XA[11]

TDI

XA[10]

TDO

TMS

XA[9]

XA[8]

XCLKOUT

XA[7]

TCLKINA

TDIRA

XA[6]

CAP3_QEPI1

XA[5]

CAP2_QEP2

CAP1_QEP1

T2PWM_T2CMP

XA[4]

T1PWM_T1CMP

PWM6

PWM5

XD[13]

XD[12]

PWM4

PWM3

PWM2

PWM1

SCIRXDB

SCITXDB

CANRXA

V

SS

V

DD

V

SS

T1CTRIP_PDPINTA

V

DD

V

SS

V

DDIO

T2CTRIP / EVASOC

C1TRIP

C2TRIP

C3TRIP

V

DD

V

PWM8

PWM9

PWM10

PWM11

PWM12

XR/W

V

SS

T3PWM_T3CMP

XD[7]

T4PWM_T4CMP

V

DD

CAP4_QEP3

V

SS

CAP5_QEP4

CAP6_QEPI2

C4TRIP

C5TRIP

C6TRIP

V

DDIO

XD[8]

TEST2

TEST1

XD[9]

V

DD3VFL

TDIRB

TCLKINB

XD[10]

XD[11]

V

DD

X2

X1/XCLKIN

V

SS

T3CTRIP_PDPINTB

XA[2]

V

DDIO

XHOLDA

T4CTRIP/EVBSOC

XWE

XA[3]

V

SS

CANTXA

XZCS2

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171

86

44

129 87

43

TESTSEL

TRST

TCK

EMU0

XA[12]
XD[14]

XA[13]

V

SS

V

DD
XA[14]
V

DDIO

EMU1
XD[15]
XA[15]

XINT1_XBIO

XA[16]

V

DD

SCITXDA

XA[17]

SCIRXDA

XA[18]

XHOLD

XRS

XREADY

V

DD1

V

SS1

V

SSA2

V

DDA2
ADCINA7
ADCINA6
ADCINA5

ADCINA4

ADCINA3
ADCINA2
ADCINA1
ADCINA0

ADCLO

V

SSAIO

45

89

88

132
133

XZCS6AND7

XF_XPLLDIS

XNMI_XINT13

XINT2_ADCSOC

ADCBGREFIN

PWM7

131

SM320F2812-HT

SGUS062A–JUNE 2009–REVISED APRIL 2010

2.4 Pin Assignments

The SM320F2812 172-pin HFG ceramic quad flatpack (CQFP) pin assignments are shown in Figure 2-2.
See Table 2-3 for a description of each pin’s function(s).

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Figure 2-2. SM320F2812 172-Pin HFG CQFP (Top View)

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2.5 Signal Descriptions

Table 2-3 specifies the signals on the F2812 device. All digital inputs are TTL-compatible. All outputs are

3.3 V with CMOS levels. Inputs are not 5 V tolerant. A 100 mA (or 20 mA) pullup/pulldown is used.

Table 2-3. Signal Descriptions

PIN NO.

NAME X-CENTER Y-CENTER I/O/Z

XA[18] 154 173 42.6 2281.5 O/Z –
XA[17] 152 171 42.6 2485.3 O/Z –
XA[16] 149 167 42.6 2819.6 O/Z –
XA[15] 145 163 42.6 3182.9 O/Z –
XA[14] 141 157 42.6 3774.9 O/Z –
XA[13] 138 154 42.6 4029.4 O/Z –
XA[12] 135 151 42.6 4401.3 O/Z –
XA[11] 129 145 255.7 5057.5 O/Z
XA[10] 127 143 474.4 5057.5 O/Z –
XA[9] 122 138 996.5 5057.5 O/Z – 19-bit XINTF Address Bus
XA[8] 118 134 1492.4 5057.5 O/Z –
XA[7] 116 131 1825.2 5057.5 O/Z –
XA[6] 109 124 2566.0 5057.5 O/Z –
XA[5] 106 121 2937.9 5057.5 O/Z –
XA[4] 101 116 3518.7 5057.5 O/Z –
XA[3] 83 96 5361.5 4471.5 O/Z –
XA[2] 78 91 5361.5 3927.2 O/Z –
XA[1] 42 49 5024.5 42.6 O/Z –
XA[0] 18 24 2403.5 42.6 O/Z
XD[15] 144 162 42.6 3306.9 I/O/Z PU
XD[14] 136 152 42.6 4277.3 I/O/Z PU
XD[13] 95 110 4194.1 5057.5 I/O/Z PU
XD[12] 94 109 4318.1 5057.5 I/O/Z PU
XD[11] 72 85 5361.5 3382.2 I/O/Z PU
XD[10] 71 84 5361.5 3258.3 I/O/Z PU
XD[9] 67 77 5361.5 2608.4 I/O/Z PU
XD[8] 64 74 5361.5 2312.1 I/O/Z PU
XD[7] 53 60 5361.5 1045.9 I/O/Z PU
XD[6] 38 45 4586.0 42.6 I/O/Z PU
XD[5] 35 42 4281.2 42.6 I/O/Z PU
XD[4] 32 39 3966.6 42.6 I/O/Z PU
XD[3] 29 36 3652.0 42.6 I/O/Z PU
XD[2] 26 33 3337.5 42.6 I/O/Z PU
XD[1] 23 30 3022.9 42.6 I/O/Z PU
XD[0] 20 27 2708.3 42.6 I/O/Z PU

172-PIN

HFG

DIE PAD

NO.

DIE PAD DIE PAD

(mm) (mm)

XINTF SIGNALS

(2)

(1)

PU/PD

(3)

16-bit XINTF Data Bus

DESCRIPTION

(1) Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are

8 mA.
(2) I = Input, O = Output, Z = High impedance
(3) PU = pin has internal pullup; PD = pin has internal pulldown

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Table 2-3. Signal Descriptions

PIN NO.

NAME X-CENTER Y-CENTER I/O/Z

XMP/MC 17 23 2308.2 42.6 I PD external interface and on-chip boot ROM

XHOLD 155 174 42.6 2157.6 I PU strobes into a high-impedance state. The

XHOLDA 80 93 5361.5 4137.4 O/Z –

XZCS0AND1 43 50 5148.5 42.6 O/Z –

XZCS2 86 100 5361.5 4844.2 O/Z – (low) when an access to the XINTF Zone 2

XZCS6AND7 130 146 42.6 4888.6 O/Z –

XWE 82 95 5361.5 4347.5 O/Z –

XRD 41 48 4900.6 42.6 O/Z –

XR/W 50 57 5361.5 755.0 O/Z –

XREADY 157 176 42.6 1972.4 I PU XREADY can be configured to be a

172-PIN

HFG

DIE PAD

NO.

DIE PAD DIE PAD

(mm) (mm)

(1)

(continued)

(2)

PU/PD

(3)

Microprocessor/Microcomputer Mode
Select. Switches between microprocessor
and microcomputer mode. When high,
Zone 7 is enabled on the external interface.
When low, Zone 7 is disabled from the

may be accessed instead. This signal is
latched into the XINTCNF2 register on a
reset and the user can modify this bit in
software. The state of the XMP/MC pin is
ignored after reset.

External Hold Request. XHOLD, when
active (low), requests the XINTF to release
the external bus and place all buses and

XINTF releases the bus when any current
access is complete and there are no
pending accesses on the XINTF.

External Hold Acknowledge. XHOLDA is
driven active (low) when the XINTF has
granted a XHOLD request. All XINTF buses
and strobe signals are in a high-impedance
state. XHOLDA is released when the
XHOLD signal is released. External devices
should only drive the external bus when
XHOLDA is active (low).

XINTF Zone 0 and Zone 1 Chip Select.
XZCS0AND1 is active (low) when an
access to the XINTF Zone 0 or Zone 1 is
performed.

XINTF Zone 2 Chip Select. XZCS2 is active
is performed.

XINTF Zone 6 and Zone 7 Chip Select.
XZCS6AND7 is active (low) when an
access to the XINTF Zone 6 or Zone 7 is
performed.

Write Enable. Active-low write strobe. The
write strobe waveform is specified, per zone
basis, by the Lead, Active, and Trail periods
in the XTIMINGx registers.

Read Enable. Active-low read strobe. The
read strobe waveform is specified, per zone
basis, by the Lead, Active, and Trail periods
in the XTIMINGx registers.
NOTE: The XRD and XWE signals are
mutually exclusive.

Read Not Write Strobe. Normally held high.
When low, XR/W indicates write cycle is
active; when high, XR/W indicates read
cycle is active.

Ready Signal. Indicates peripheral is ready
to complete the access when asserted to 1.

synchronous or an asynchronous input.
See the timing diagrams for more details.

DESCRIPTION

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Table 2-3. Signal Descriptions

PIN NO.

NAME X-CENTER Y-CENTER I/O/Z

172-PIN

HFG

DIE PAD

NO.

DIE PAD DIE PAD

(mm) (mm)

(1)

(continued)

(2)

PU/PD

SGUS062A–JUNE 2009–REVISED APRIL 2010

(3)

DESCRIPTION

JTAG AND MISCELLANEOUS SIGNALS

Oscillator Input – input to the internal
oscillator. This pin is also used to feed an
external clock. The 28× can be operated
with an external clock source, provided that
the proper voltage levels be driven on the
X1/XCLKIN pin. It should be noted that the

X1/XCLKIN 75 88 5361.5 3668.7 I

X1/XCLKIN pin is referenced to the 1.8-V
(or 1.9-V) core digital power supply (VDD),
rather than the 3.3-V I/O supply (V
clamping diode may be used to clamp a

DDIO

buffered clock signal to ensure that the
logic-high level does not exceed V
(1.8 V or 1.9 V) or a 1.8-V oscillator may be

DD

used.

X2 74 87 5361.5 3582.6 O Oscillator Output

Output clock derived from SYSCLKOUT to
be used for external wait-state generation
and as a general-purpose clock source.
XCLKOUT is either the same frequency,

XCLKOUT 117 132 1701.2 5057.5 O – 1/2 the frequency, or 1/4 the frequency of

SYSCLKOUT. At reset, XCLKOUT =
SYSCLKOUT/4. The XCLKOUT signal can
be turned off by setting bit 3 (CLKOFF) of
the XINTCNF2 register to 1.

TESTSEL 131 147 42.6 4764.6 I PD

Test Pin. Reserved for TI. Must be
connected to ground.

Device Reset (in) and Watchdog Reset
(out).

Device reset. XRS causes the device to
terminate execution. The PC points to the
address contained at the location
0x3FFFC0. When XRS is brought to a high
level, execution begins at the location

XRS 156 175 42.6 2077.8 I/O PU

pointed to by the PC. This pin is driven low
by the DSP when a watchdog reset occurs.
During watchdog reset, the XRS pin is
driven low for the watchdog reset duration
of 512 XCLKIN cycles.

The output buffer of this pin is an
open-drain with an internal pullup (100 mA,
typical). It is recommended that this pin be
driven by an open-drain device.

TEST1 66 76 5361.5 2522.3 I/O –

TEST2 65 75 5361.5 2436.1 I/O –

Test Pin. Reserved for TI. On F281x
devices, TEST1 must be left unconnected.

Test Pin. Reserved for TI. On F281x
devices, TEST2 must be left unconnected.

). A

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Table 2-3. Signal Descriptions

PIN NO.

NAME X-CENTER Y-CENTER I/O/Z

TRST 132 148 42.6 4684.8 I PD

TCK 133 149 42.6 4605.1 I PU JTAG test clock with internal pullup

TMS 123 139 872.5 5057.5 I PU

TDI 128 144 350.4 5057.5 I PU

TDO 124 140 777.9 5057.5 O/Z –

EMU0 133 150 42.6 4525.3 I/O/Z PU

EMU1 143 161 42.6 3430.9 I/O/Z PU

172-PIN

HFG

DIE PAD

NO.

DIE PAD DIE PAD

(mm) (mm)

(1)

(continued)

(2)

PU/PD

(3)

JTAG test reset with internal pulldown.
TRST, when driven high, gives the scan
system control of the operations of the
device. If this signal is not connected or
driven low, the device operates in its
functional mode, and the test reset signals
are ignored.

NOTE: Do not use pullup resistors on
TRST; it has an internal pulldown device. In
a low-noise environment, TRST can be left
floating. In a high-noise environment, an
additional pulldown resistor may be
needed. The value of this resistor should be
based on drive strength of the debugger
pods applicable to the design. A 2.2-kΩ
resistor generally offers adequate
protection. Since this is application specific,
it is recommended that each target board is
validated for proper operation of the
debugger and the application.

JTAG test-mode select (TMS) with internal
pullup. This serial control input is clocked
into the TAP controller on the rising edge of
TCK.

JTAG test data input (TDI) with internal
pullup. TDI is clocked into the selected
register (instruction or data) on a rising
edge of TCK.

JTAG scan out, test data output (TDO). The
contents of the selected register (instruction
or data) is shifted out of TDO on the falling
edge of TCK.

Emulator pin 0. When TRST is driven high,
this pin is used as an interrupt to or from
the emulator system and is defined as
input/output through the JTAG scan.

Emulator pin 1. When TRST is driven high,
this pin is used as an interrupt to or from
the emulator system and is defined as
input/output through the JTAG scan.

DESCRIPTION

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Table 2-3. Signal Descriptions

PIN NO.

NAME X-CENTER Y-CENTER I/O/Z

172-PIN

HFG

DIE PAD

NO.

DIE PAD DIE PAD

(mm) (mm)

(1)

(continued)

(2)

PU/PD

SGUS062A–JUNE 2009–REVISED APRIL 2010

(3)

DESCRIPTION

ADC ANALOG INPUT SIGNALS

ADCINA7 163 186 42.6 1253.9 I
ADCINA6 164 188 42.6 1094.3 I
ADCINA5 165 190 42.6 954.0 I
ADCINA4 166 192 42.6 794.4 I
ADCINA3 167 194 42.6 654.1 I
ADCINA2 168 196 42.6 513.9 I

Eight-channel analog inputs for
Sample-and-Hold A. The ADC pins should
not be driven before V
V

pins have been fully powered up.

DDAIO

DDA1

ADCINA1 169 197 42.6 434.1 I
ADCINA0 170 198 42.6 354.3 I
ADCINB7 9 13 1355.2 42.6 I
ADCINB6 8 11 1164.6 42.6 I
ADCINB5 7 10 1069.2 42.6 I
ADCINB4 6 8 878.6 42.6 I
ADCINB3 5 6 688.0 42.6 I
ADCINB2 4 4 497.4 42.6 I

Eight-channel analog inputs for
Sample-and-Hold B. The ADC pins should
not be driven before the V
V

pins have been fully powered up.

DDAIO

ADCINB1 3 3 402.1 42.6 I
ADCINB0 2 2 306.8 42.6 I

ADC Voltage Reference Output (2 V).
Requires a low ESR (50 mΩ – 1.5 Ω)
ceramic bypass capacitor of 10 mF to
analog ground. (Can accept external

ADCREFP 11 15 1545.8 42.6 O reference input

(2 V) if the software bit is enabled for this
mode. 1-mF to 10-mF low ESR capacitor
can be used in the external reference
mode.)

ADC Voltage Reference Output (1 V).
Requires a low ESR (50 mΩ – 1.5 Ω)
ceramic bypass capacitor of 10 mF to
analog ground. (Can accept external

ADCREFM 10 14 1450.5 42.6 O reference input

(1 V) if the software bit is enabled for this
mode. 1-mF to 10-mF low ESR capacitor
can be used in the external reference
mode.)

ADCRESEXT 16 22 2212.9 42.63 O

ADCBGREFIN 160 180 42.6 1680.9 I

ADC External Current Bias Resistor
(24.9 kΩ ±5%)

Test Pin. Reserved for TI. Must be left

unconnected.
AVSSREFBG 12 17 1831.7 42.6 I ADC Analog GND
AVDDREFBG 13 18 1736.4 42.6 I ADC Analog Power (3.3 V)

ADCLO 171 199 42.6 274.5 I
V

SSA1

V

SSA2

V

DDA1

V

DDA2

V

SS1

V

DD1

V

DDAIO

V

SSAIO

15 21 2117.6 42.6 I ADC Analog GND

161 182 42.6 1550.7 I ADC Analog GND

14 19 1927.0 42.6 I ADC Analog 3.3-V Supply
162 184 42.6 1394.2 I ADC Analog 3.3-V Supply
159 178 42.6 1830.8 I ADC Digital GND
158 177 42.6 1901.0 I ADC Digital 1.8-V (or 1.9-V) Supply

1 1 211.5 42.6 3.3-V Analog I/O Power Pin

172 200 42.6 204.3 Analog I/O Ground Pin

Common Low Side Analog Input. Connect
to analog ground.

, V

DDA1

DDA2

, V

, and

DDA2

, and

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Table 2-3. Signal Descriptions

PIN NO.

NAME X-CENTER Y-CENTER I/O/Z

172-PIN

HFG

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

DDIO

V

DDIO

V

DDIO

V

DDIO

V

DDIO

V

DDIO

V

DD3VFL

22 29 2927.6 42.6

36 43 4395.4 42.6

55 62 5361.5 1256.0

73 86 5361.5 3496.4

98 113 3861.3 5057.5
110 125 2451.9 5057.5
125 141 663.7 5057.5
140 156 42.6 3845.1
150 169 42.6 2635.3

31 38 3871.3 42.6

37 44 4490.7 42.6

51 58 5361.5 869.2

57 65 5361.5 1514.6

76 89 5361.5 3754.9

84 97 5361.5 4585.7

97 112 3956.0 5057.5
103 118 3280.5 5057.5
111 126 2357.2 5057.5

126 142 569.0 5057.5
139 155 42.6 3915.2

30 37 3776.0 42.6

63 73 5361.5 2226.0

79 92 5361.5 4051.2

112 127 2262.5 5057.5
142 160 42.6 3510.7

68 78 5361.5 2732.4

DIE PAD

NO.

- 98 5361.5 4671.835

- 25 2517.7 42.6

- 79 5361.5 2818.6

- 133 1587.1 5057.5

- 159 42.6 3580.8

- 168 42.6 2705.4

- 105 4784.7 5057.5

DIE PAD DIE PAD

(mm) (mm)

POWER SIGNALS

(1)

(continued)

(2)

PU/PD

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(3)

DESCRIPTION

1.8-V or 1.9-V Core Digital Power Pins. See
Section 6.2, Recommended Operating
Conditions, for voltage requirements.

Core and Digital I/O Ground Pins

3.3–V I/O Digital Power Pins

3.3–V Flash Core Power Pin. This pin
should be connected to 3.3 V at all times
after power-up sequence requirements
have been met. This pin is used as VDDIO
in ROM parts and must be connected to

3.3 V in ROM parts as well.

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Signal Descriptions (Continued)

GPIO DIE PAD NO. I/O/Z

GPIOA0 PWM1 (O) 90 104 4908.6 5057.5 I/O/Z PU

GPIOA1 PWM2 (O) 91 106 4690.0 5057.5 I/O/Z PU

GPIOA2 PWM3 (O) 92 107 4566.0 5057.5 I/O/Z PU

GPIOA3 PWM4 (O) 93 108 4442.1 5057.5 I/O/Z PU

GPIOA4 PWM5 (O) 96 111 4070.1 5057.5 I/O/Z PU

GPIOA5 PWM6 (O) 99 114 3766.6 5057.5 I/O/Z PU

GPIOA6 T1PWM_T1CMP (I) 100 115 3642.7 5057.5 I/O/Z PU

GPIOA7 T2PWM_T2CMP (I) 102 117 3394.7 5057.5 I/O/Z PU

GPIOA8 CAP1_QEP1 (I) 104 119 3185.9 5057.5 I/O/Z PU

GPIOA9 CAP2_QEP2 (I) 105 120 3061.9 5057.5 I/O/Z PU

GPIOA10 CAP3_QEPI1 (I) 107 122 2814.0 5057.5 I/O/Z PU

GPIOA11 TDIRA (I) 114 129 2073.2 5057.5 I/O/Z PU

GPIOA12 TCLKINA (I) 115 130 1949.2 5057.5 I/O/Z PU

GPIOA13 C1TRIP (I) 119 135 1368.4 5057.5 I/O/Z PU

GPIOA14 C2TRIP (I) 120 136 1244.5 5057.5 I/O/Z PU

GPIOA15 C3TRIP (I) 121 137 1120.5 5057.5 I/O/Z PU

GPIOB0 PWM7 (O) 44 51 5361.5 211.5 I/O/Z PU

GPIOB1 PWM8 (O) 45 52 5361.5 302.1 I/O/Z PU

GPIOB2 PWM9 (O) 46 53 5361.5 392.7 I/O/Z PU

GPIOB3 PWM10 (O) 47 54 5361.5 483.2 I/O/Z PU

GPIOB4 PWM11 (O) 48 55 5361.5 573.8 I/O/Z PU

GPIOB5 PWM12 (O) 49 56 5361.5 664.4 I/O/Z PU

GPIOB6 T3PWM_T3CMP (I) 52 59 5361.5 955.3 I/O/Z PU

GPIOB7 T4PWM_T4CMP (I) 54 61 5361.5 1169.9 I/O/Z PU

PERIPHERAL DIE PAD DIE PAD

SIGNAL X-CENTER Y-CENTER

PIN NO.

172-PIN

HFG

GPIO OR PERIPHERAL SIGNALS

GPIOA OR EVA SIGNALS

GPIOB OR EVB SIGNALS

SGUS062A–JUNE 2009–REVISED APRIL 2010

(1)

(2)

PU/PD

(3)

DESCRIPTION

GPIO or PWM
Output Pin #1

GPIO or PWM
Output Pin #2

GPIO or PWM
Output Pin #3

GPIO or PWM
Output Pin #4

GPIO or PWM
Output Pin #5

GPIO or PWM
Output Pin #6

GPIO or Timer 1
Output

GPIO or Timer 2
Output

GPIO or Capture
Input #1

GPIO or Capture
Input #2

GPIO or Capture
Input #3

GPIO or Timer
Direction

GPIO or Timer Clock
Input

GPIO or Compare 1
Output Trip

GPIO or Compare 2
Output Trip

GPIO or Compare 3
Output Trip

GPIO or PWM
Output Pin #7

GPIO or PWM
Output Pin #8

GPIO or PWM
Output Pin #9

GPIO or PWM
Output Pin #10

GPIO or PWM
Output Pin #11

GPIO or PWM
Output Pin #12

GPIO or Timer 3
Output

GPIO or Timer 4
Output

(1) Typical drive strength of the output buffer for all pins [except TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins] is 4 mA typical.
(2) I = Input, O = Output, Z = High impedance
(3) PU = pin has internal pullup; PD = pin has internal pulldown

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Signal Descriptions (Continued)

GPIO DIE PAD NO. I/O/Z

GPIOB8 CAP4_QEP3 (I) 56 64 5361.5 1428.4 I/O/Z PU

GPIOB9 CAP5_QEP4 (I) 58 66 5361.5 1600.7 I/O/Z PU

GPIOB10 CAP6_QEPI2 (I) 59 67 5361.5 1691.3 I/O/Z PU

GPIOB11 TDIRB (I) 69 81 5361.5 2990.9 I/O/Z PU

GPIOB12 TCLKINB (I) 70 82 5361.5 3081.5 I/O/Z PU

GPIOB13 C4TRIP (I) 60 69 5361.5 1868.1 I/O/Z PU

GPIOB14 C5TRIP (I) 61 71 5361.5 2044.8 I/O/Z PU

GPIOB15 C6TRIP (I) 62 72 5361.5 2135.4 I/O/Z PU

GPIOD0 T1CTRIP_PDPINTA (I) 108 123 2690.0 5057.5 I/O/Z PU

GPIOD1 T2CTRIP/EVASOC (I) 113 128 2167.8 5057.5 I/O/Z PU External ADC

GPIOD5 T3CTRIP_PDPINTB (I) 77 90 5361.5 3841.1 I/O/Z PU

GPIOD6 T4CTRIP/EVBSOC (I) 81 94 5361.5 4261.4 I/O/Z PU External ADC

GPIOE0 XINT1_XBIO (I) 146 164 42.6 3059.0 I/O/Z –

GPIOE1 XINT2_ADCSOC (I) 148 166 42.6 2899.4 I/O/Z – ADC start of

GPIOE2 XNMI_XINT13 (I) 147 165 42.6 2979.2 I/O/Z PU

GPIOF0 SPISIMOA (O) 39 46 4709.9 42.6 I/O/Z –

GPIOF1 SPISOMIA (I) 40 47 4805.3 42.6 I/O/Z –­GPIOF2 SPICLKA (I/O) 33 40 4090.6 42.6 I/O/Z – GPIO or SPI clock
GPIOF3 SPISTEA (I/O) 34 41 4185.9 42.6 I/O/Z –

GPIOF4 SCITXDA (O) 151 170 42.6 2565.1 I/O/Z PU asynchronous serial

GPIOF5 SCIRXDA (I) 153 172 42.6 2361.3 I/O/Z PU asynchronous serial

PERIPHERAL DIE PAD DIE PAD

SIGNAL X-CENTER Y-CENTER

PIN NO.

172-PIN

HFG

GPIOD OR EVA SIGNALS

GPIOD OR EVB SIGNALS

GPIOE OR INTERRUPT SIGNALS

GPIOF OR SPI SIGNALS

GPIOF OR SCI-A SIGNALS

(1)

(continued)

(2)

PU/PD

(3)

GPIO or Capture
Input #4

GPIO or Capture
Input #5

GPIO or Capture
Input #6

GPIO or Timer
Direction

GPIO or Timer Clock
Input

GPIO or Compare 4
Output Trip

GPIO or Compare 5
Output Trip

GPIO or Compare 6
Output Trip

Timer 1 Compare
Output Trip

Timer 2 Compare
Output Trip or

Start-of-Conversion
EV-A

Timer 3 Compare
Output Trip

Timer 4 Compare
Output Trip or

Start-of-Conversion
EV-B

GPIO or XINT1 or
XBIO input

GPIO or XINT2 or
conversion

GPIO or XNMI or
XINT13

GPIO or SPI slave
in, master out

GPIO or SPI slave
out, master in

GPIO or SPI slave
transmit enable

GPIO or SCI
port TX data

GPIO or SCI
port RX data

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DESCRIPTION

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Signal Descriptions (Continued)

GPIO DIE PAD NO. I/O/Z

GPIOF6 CANTXA (O) 85 99 5361.5 4758.0 I/O/Z PU

GPIOF7 CANRXA (I) 87 101 5192.7 5057.5 I/O/Z PU

GPIOF8 MCLKXA (I/O) 27 34 3461.4 42.6 I/O/Z PU

GPIOF9 MCLKRA (I/O) 24 31 3146.8 42.6 I/O/Z PU

GPIOF10 MFSXA (I/O) 25 32 3242.2 42.6 I/O/Z PU

GPIOF11 MFSRA (I/O) 28 35 3556.7 42.6 I/O/Z PU

GPIOF12 MDXA (O) 21 28 2832.3 42.6 I/O/Z –

GPIOF13 MDRA (I) 19 26 2613.0 42.6 I/O/Z PU

GPIOF14 XF_XPLLDIS (O) 137 153 42.6 4153.3 I/O/Z PU

PERIPHERAL DIE PAD DIE PAD

SIGNAL X-CENTER Y-CENTER

PIN NO.

172-PIN

HFG

GPIOF OR CAN SIGNALS

GPIOF OR McBSP SIGNALS

GPIOF OR XF CPU OUTPUT SIGNAL

(1)

(continued)

SGUS062A–JUNE 2009–REVISED APRIL 2010

(2)

PU/PD

(3)

DESCRIPTION

GPIO or eCAN
transmit data

GPIO or eCAN
receive data

GPIO or transmit
clock

GPIO or receive
clock

GPIO or transmit
frame synch

GPIO or receive
frame synch

GPIO or transmitted
serial data

GPIO or received
serial data

This pin has three
functions:

1. XF –
General-purpose
output pin.

2. XPLLDIS – This
pin is sampled
during reset to check
if the PLL needs to
be disabled. The
PLL will be disabled
if this pin is sensed
low. HALT and
STANDBY modes
cannot be used
when the PLL is
disabled.

3. GPIO – GPIO
function

Copyright © 2009–2010, Texas Instruments Incorporated Introduction 25

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Signal Descriptions (Continued)

GPIO DIE PAD NO. I/O/Z

GPIOG4 SCITXDB (O) 88 102 5098.0 5057.5 I/O/Z – asynchronous serial

GPIOG5 SCIRXDB (I) 89 103 5003.3 5057.5 I/O/Z – asynchronous serial

PERIPHERAL DIE PAD DIE PAD

SIGNAL X-CENTER Y-CENTER

PIN NO.

172-PIN

HFG

GPIOG OR SCI-B SIGNALS

(1)

(continued)

(2)

PU/PD

(3)

GPIO or SCI
port transmit data

GPIO or SCI
port receive data

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DESCRIPTION

NOTE

Other than the power supply pins, no pin should be driven before the 3.3-V rail has reached
recommended operating conditions.

26 Introduction Copyright © 2009–2010, Texas Instruments Incorporated

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M0 SARAM

1K x 16

CPU-Timer 0

CPU-Timer 1

INT[12:1]

CLKIN

Real-Time JTAG

CPU-Timer 2

Peripheral Bus

C28x CPU

H0 SARAM

8K ⋅ 16

INT14

NMI

INT13

Memory Bus

M1 SARAM

1K x 16

Flash

128K x 16

Boot ROM

4K ⋅ 16

eCAN

SCIA/SCIB

12-Bit ADC

External Interrupt

Control

(XINT1/2/13, XNMI)

EVA/EVB

Memory Bus

OTP

1K x 16

McBSP

System Control

(Oscillator and PLL

+

Peripheral Clocking

+

Low-Power

Modes

+

WatchDog)

FIFO

FIFO

PIE

(96 interrupts)

†

RS

SPI FIFO

TINT0

TINT1

TINT2

Control

Address(19)

Data(16)

External

Interface

(XINTF)

16 Channels

†

45 of the possible 96 interrupts are used on the device.

GPIO Pins

XRS

X1/XCLKIN

X2

XF_XPLLDIS

Protected by the code-security module.

XINT13

G

P

I

O

M

U

X

L1 SARAM

4K x 16

XNMI

L0 SARAM

4K x 16

‡

‡

‡

‡

‡

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3 Functional Overview

SGUS062A–JUNE 2009–REVISED APRIL 2010

Figure 3-1. Functional Block Diagram

Copyright © 2009–2010, Texas Instruments Incorporated Functional Overview 27

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Block

Start Address

Low 64K

(24x/240x Equivalent Data Space)

0x00 0000

M0 Vector − RAM (32 × 32)

(Enabled if VMAP = 0)

Data Space Prog Space

M0 SARAM (1K × 16)
M1 SARAM (1K × 16)

Peripheral Frame 0

(2K × 16)

0x00 0040
0x00 0400

0x00 0800

PIE Vector - RAM

(256 × 16)

(Enabled if VMAP

= 1, ENPIE = 1)

Reserved

Reserved

Reserved

L0 SARAM (4K × 16, Secure Block)

Peripheral Frame 1

(4K × 16, Protected)

Reserved

Peripheral Frame 2

(4K × 16, Protected)

L1 SARAM (4K × 16, Secure Block)

Reserved

OTP (or ROM) (1K × 16, Secure Block)

Flash (or ROM) (128K × 16, Secure Block)

128-Bit Password

H0 SARAM (8K × 16)

Reserved

Boot ROM (4K × 16)

(Enabled if MP/MC

= 0)

BROM Vector - ROM (32 × 32)

(Enabled if VMAP = 1, MP/MC

= 0, ENPIE = 0)

0x00 0D00

0x00 0E00
0x00 2000

0x00 6000

0x00 7000

0x00 8000
0x00 9000

0x00 A000

0x3D 7800
0x3D 7C00

0x3F 7FF8

0x3F 8000

0x3F A000

0x3F F000

0x3F FFC0

High 64K

(24x/240x Equivalent

Program Space)

Data Space Prog Space

Reserved

XINTF Zone 0 (8K × 16, XZCS0AND1

)

XINTF Zone 1 (8K × 16, XZCS0AND1) (Protected)

Reserved

XINTF Zone 2 (0.5M × 16, XZCS2

)

XINTF Zone 6 (0.5M × 16, XZCS6AND7)

Reserved

XINTF Zone 7 (16K × 16, XZCS6AND7)

(Enabled if MP/MC

= 1)

XINTF Vector - RAM (32 × 32)

(Enabled if VMAP = 1, MP/MC

= 1, ENPIE = 0)

On-Chip Memory External Memory XINTF

Only one of these vector maps—M0 vector, PIE vector, BROM vector, XINTF vector—should be enabled at a time.

LEGEND:

0x08 0000

0x00 4000

0x10 0000
0x18 0000

0x3F C000

0x00 2000

Reserved (1K)

0x3D 8000

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SGUS062A–JUNE 2009–REVISED APRIL 2010

3.1 Memory Map

A. Memory blocks are not to scale.
B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Boot ROM and Zone 7 memory maps are active either in on-chip or XINTF zone depending on MP/MC, not in both.
D. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.

E. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
F. Certain memory ranges are EALLOW protected against spurious writes after configuration.
G. Zones 0 and 1 and Zones 6 and 7 share the same chip select; hence, these memory blocks have mirrored locations.

28 Functional Overview Copyright © 2009–2010, Texas Instruments Incorporated

User program cannot access these memory maps in program space.

Figure 3-2. F2812 Memory Map (See Notes A. Through G.)

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Table 3-1. Addresses of Flash Sectors in F2812

ADDRESS RANGE PROGRAM AND DATA SPACE

0x3D 8000
0x3D 9FFF

0x3D A000

0x3D BFFF
0x3D C000

0x3D FFFF

0x3E 0000
0x3E 3FFF

0x3E 4000
0x3E 7FFF

0x3E 8000

0x3E BFFF

0x3E C000

0x3E FFFF

0x3F 0000
0x3F 3FFF

0x3F 4000
0x3F 5FFF

0x3F 6000 Sector A, 8K × 16
0x3F 7F80 Program to 0x0000 when using the

0x3F 7FF5 Code Security Module
0x3F 7FF6 Boot-to-Flash (or ROM) Entry Point

0x3F 7FF7 (program branch instruction here)
0x3F 7FF8 Security Password (128-Bit)

0x3F 7FFF (Do not program to all zeros)

Sector J, 8K × 16

Sector I, 8K × 16

Sector H, 16K × 16

Sector G, 16K × 16

Sector F, 16K × 16

Sector E, 16K × 16

Sector D, 16K × 16

Sector C, 16K × 16

Sector B, 8K × 16

The Low 64K of the memory address range maps into the data space of the 240x. The High 64K of the
memory address range maps into the program space of the 24x/240x. 24x/240x-compatible code only
executes from the High 64K memory area. Hence, the top 32K of Flash/ROM and H0 SARAM block can
be used to run 24x/240x-compatible code (if MP/MC mode is low) or, on the F2812, code can be executed
from XINTF Zone 7 (if MP/MC mode is high).

The XINTF consists of five independent zones. One zone has its own chip select and the remaining four
zones share two chip selects. Each zone can be programmed with its own timing (wait states) and to
either sample or ignore external ready signal. This makes interfacing to external peripherals easy and
glueless.

NOTE

The chip selects of XINTF Zone 0 and Zone 1 are merged together into a single chip select
(XZCS0AND1); and the chip selects of XINTF Zone 6 and Zone 7 are merged together into a
single chip select (XZCS6AND7). See Section 3.5, External Interface, XINTF (2812 only), for
details.

Peripheral Frame 1, Peripheral Frame 2, and XINTF Zone 1 are grouped together so as to enable these
blocks to be write/read peripheral block protected. The protected mode ensures that all accesses to these
blocks happen as written. Because of the C28x pipeline, a write immediately followed by a read, to
different memory locations, appears in reverse order on the memory bus of the CPU. This can cause
problems in certain peripheral applications where the user expected the write to occur first (as written).
The C28x CPU supports a block protection mode where a region of memory can be protected so as to
make sure that operations occur as written (the penalty is extra cycles are added to align the operations).
This mode is programmable and by default, it protects the selected zones.

On the F2812, at reset, XINTF Zone 7 is accessed if the XMP/MC pin is pulled high. This signal selects
microprocessor or microcomputer mode of operation. In microprocessor mode, Zone 7 is mapped to high

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memory such that the vector table is fetched externally. The Boot ROM is disabled in this mode. In
microcomputer mode, Zone 7 is disabled such that the vectors are fetched from Boot ROM. This allows
the user to either boot from on-chip memory or from off-chip memory. The state of the XMP/MC signal on
reset is stored in an MP/MC mode bit in the XINTCNF2 register. The user can change this mode in
software and hence control the mapping of Boot ROM and XINTF Zone 7. No other memory blocks are
affected by XMP/MC.

I/O space is not supported on the F2812 XINTF.
The wait states for the various spaces in the memory map area are listed in Table 3-2.

Table 3-2. Wait States

AREA WAIT-STATES COMMENTS

M0 and M1 SARAMs 0-wait Fixed

Peripheral Frame 0 0-wait Fixed
Peripheral Frame 1 Fixed

Peripheral Frame 2 Fixed
L0 and L1 SARAMs 0-wait

OTP (or ROM)

Flash (or ROM) CPU frequency. The CSM password locations are hardwired for 16 wait-states.

H0 SARAM 0-wait Fixed

Boot-ROM 1-wait Fixed

XINTF Cycles can be extended by external memory or peripheral.

0-wait (writes)
2-wait (reads)

0-wait (writes)
2-wait (reads)

Programmable, Programmed via the Flash registers. 1-wait-state operation is possible at a reduced

1-wait minimum CPU frequency. See Section 3.2.6, Flash (F281x Only), for more information.

Programmable,

0-wait minimum

Programmable,

1-wait minimum

Programmed via the Flash registers. 0-wait-state operation is possible at reduced
See Section 3.2.6, Flash (F281x Only), for more information.

Programmed via the XINTF registers.
0-wait operation is not possible.

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