Texas Instruments SM320F2812-HT User Manual

SM320F2812-HT

Digital Signal Processor

Data Manual

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Literature Number: SGUS062A June 2009–Revised April 2010

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Contents

1 Features ........................................................................................................................... 11

1.1 SUPPORTS EXTREME TEMPERATURE APPLICATIONS ......................................................... 12

2 Introduction ...................................................................................................................... 13

2.1 Description ................................................................................................................. 13

2.2 Device Summary .......................................................................................................... 14

2.3 Die Layout .................................................................................................................. 15

2.4 Pin Assignments ........................................................................................................... 16

2.5 Signal Descriptions ........................................................................................................ 17

3 Functional Overview .......................................................................................................... 27

3.1 Memory Map ............................................................................................................... 28

3.2 Brief Descriptions .......................................................................................................... 31

3.2.1 C28x CPU ....................................................................................................... 31

3.2.2 Memory Bus (Harvard Bus Architecture) .................................................................... 31

3.2.3 Peripheral Bus .................................................................................................. 31

3.2.4 Real-Time JTAG and Analysis ................................................................................ 31

3.2.5 External Interface (XINTF) .................................................................................... 32

3.2.6 Flash ............................................................................................................. 32

3.2.7 L0, L1, H0 SARAMs ............................................................................................ 32

3.2.8 Boot ROM ....................................................................................................... 32

3.2.9 Security .......................................................................................................... 33

3.2.10 Peripheral Interrupt Expansion (PIE) Block ................................................................. 34

3.2.11 External Interrupts (XINT1, XINT2, XINT13, XNMI) ........................................................ 34

3.2.12 Oscillator and PLL .............................................................................................. 34

3.2.13 Watchdog ........................................................................................................ 34

3.2.14 Peripheral Clocking ............................................................................................. 34

3.2.15 Low-Power Modes .............................................................................................. 34

3.2.16 Peripheral Frames 0, 1, 2 (PFn) .............................................................................. 35

3.2.17 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 35

3.2.18 32-Bit CPU Timers (0, 1, 2) ................................................................................... 35

3.2.19 Control Peripherals ............................................................................................. 35

3.2.20 Serial Port Peripherals ......................................................................................... 36

3.3 Register Map ............................................................................................................... 36

3.4 Device Emulation Registers .............................................................................................. 39

3.5 External Interface, XINTF ................................................................................................ 39

3.5.1 Timing Registers ................................................................................................ 41

3.5.2 XREVISION Register ........................................................................................... 41

3.6 Interrupts .................................................................................................................... 42

3.6.1 External Interrupts .............................................................................................. 45

3.7 System Control ............................................................................................................ 46

3.8 OSC and PLL Block ....................................................................................................... 48

3.8.1 Loss of Input Clock ............................................................................................. 49

3.9 PLL-Based Clock Module ................................................................................................ 49

3.10 External Reference Oscillator Clock Option ........................................................................... 49

3.11 Watchdog Block ........................................................................................................... 50

3.12 Low-Power Modes Block ................................................................................................. 51

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4 Peripherals ....................................................................................................................... 52

4.1 32-Bit CPU-Timers 0/1/2 ................................................................................................. 52

4.2 Event Manager Modules (EVA, EVB) ................................................................................... 55

4.2.1 General-Purpose (GP) Timers ................................................................................ 58

4.2.2 Full-Compare Units ............................................................................................. 58

4.2.3 Programmable Deadband Generator ........................................................................ 58

4.2.4 PWM Waveform Generation .................................................................................. 58

4.2.5 Double Update PWM Mode ................................................................................... 58

4.2.6 PWM Characteristics ........................................................................................... 59

4.2.7 Capture Unit ..................................................................................................... 59

4.2.8 Quadrature-Encoder Pulse (QEP) Circuit ................................................................... 59

4.2.9 External ADC Start-of-Conversion ........................................................................... 59

4.3 Enhanced Analog-to-Digital Converter (ADC) Module ............................................................... 60

4.4 Enhanced Controller Area Network (eCAN) Module .................................................................. 65

4.5 Multichannel Buffered Serial Port (McBSP) Module .................................................................. 69

4.6 Serial Communications Interface (SCI) Module ....................................................................... 73

4.7 Serial Peripheral Interface (SPI) Module ............................................................................... 76

4.8 GPIO MUX ................................................................................................................. 79

5 Development Support ........................................................................................................ 82

5.1 Device and Development Support Tool Nomenclature ............................................................... 82

5.2 Documentation Support ................................................................................................... 83

6 Electrical Specifications ..................................................................................................... 85

6.1 Absolute Maximum Ratings .............................................................................................. 85

6.2 Recommended Operating Conditions .................................................................................. 86

6.3 Electrical Characteristics ................................................................................................. 86

6.4 Current Consumption by Power-Supply Pins Over Recommended Operating Conditions During

Low-Power Modes at 150-MHz SYSCLKOUT ......................................................................... 88

6.5 Current Consumption Graphs ............................................................................................ 89

6.6 Reducing Current Consumption ......................................................................................... 90

6.7 Power Sequencing Requirements ....................................................................................... 90

6.8 Signal Transition Levels .................................................................................................. 91

6.9 Timing Parameter Symbology ........................................................................................... 92

6.10 General Notes on Timing Parameters .................................................................................. 93

6.11 Test Load Circuit .......................................................................................................... 93

6.12 Device Clock Table ........................................................................................................ 94

6.13 Clock Requirements and Characteristics ............................................................................... 94

6.13.1 Input Clock Requirements ..................................................................................... 94

6.13.2 Output Clock Characteristics .................................................................................. 95

6.14 Reset Timing ............................................................................................................... 96

6.15 Low-Power Mode Wakeup Timing ..................................................................................... 100

6.16 Event Manager Interface ................................................................................................ 104

6.16.1 PWM Timing ................................................................................................... 104

6.16.2 Interrupt Timing ................................................................................................ 106

6.17 General-Purpose Input/Output (GPIO) – Output Timing ............................................................ 107

6.18 General-Purpose Input/Output (GPIO) – Input Timing .............................................................. 108

6.19 SPI Master Mode Timing ................................................................................................ 109

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6.20 SPI Slave Mode Timing ................................................................................................. 113

6.21 External Interface (XINTF) Timing ..................................................................................... 117

6.22 XINTF Signal Alignment to XCLKOUT ................................................................................ 121

6.23 External Interface Read Timing ........................................................................................ 122

6.24 External Interface Write Timing ........................................................................................ 123

6.25 External Interface Ready-on-Read Timing With One External Wait State ....................................... 125

6.26 External Interface Ready-on-Write Timing With One External Wait State ........................................ 128

6.27 XHOLD and XHOLDA ................................................................................................... 131

6.28 XHOLD/XHOLDA Timing ............................................................................................... 132

6.29 On-Chip Analog-to-Digital Converter .................................................................................. 134

6.29.1 ADC Absolute Maximum Ratings ........................................................................... 134

6.29.2 ADC Electrical Characteristics Over Recommended Operating Conditions ........................... 135

6.29.3 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK) ...................... 136

6.29.4 ADC Power-Up Control Bit Timing .......................................................................... 137

6.29.5 Detailed Description .......................................................................................... 138

6.29.5.1 Reference Voltage ................................................................................ 138

6.29.5.2 Analog Inputs ..................................................................................... 138

6.29.5.3 Converter .......................................................................................... 138

6.29.5.4 Conversion Modes ............................................................................... 138

6.29.6 Sequential Sampling Mode (Single Channel) (SMODE = 0) ............................................ 138

6.29.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) .......................................... 140

6.29.8 Definitions of Specifications and Terminology ............................................................. 141

6.29.8.1 Integral Nonlinearity .............................................................................. 141

6.29.8.2 Differential Nonlinearity .......................................................................... 141

6.29.8.3 Zero Offset ........................................................................................ 141

6.29.8.4 Gain Error ......................................................................................... 141

6.29.8.5 Signal-to-Noise Ratio + Distortion (SINAD) ................................................... 141

6.29.8.6 Effective Number of Bits (ENOB) ............................................................... 141

6.29.8.7 Total Harmonic Distortion (THD) ............................................................... 141

6.29.8.8 Spurious Free Dynamic Range (SFDR) ....................................................... 141

6.30 Multichannel Buffered Serial Port (McBSP) Timing ................................................................. 142

6.30.1 McBSP Transmit and Receive Timing ...................................................................... 142

6.30.2 McBSP as SPI Master or Slave Timing .................................................................... 145

6.31 Flash Timing .............................................................................................................. 149

6.31.1 Recommended Operating Conditions ...................................................................... 149

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7 Mechanical Data .............................................................................................................. 151

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List of Figures

2-1 SM320F2812 Die Layout........................................................................................................ 15

2-2 SM320F2812 172-Pin HFG CQFP (Top View)............................................................................... 16

3-1 Functional Block Diagram....................................................................................................... 28

3-2 F2812 Memory Map (See Notes A. Through G.) ............................................................................ 28

3-3 External Interface Block Diagram .............................................................................................. 40

3-4 Interrupt Sources ................................................................................................................. 42

3-5 Multiplexing of Interrupts Using the PIE Block ............................................................................... 43

3-6 Clock and Reset Domains ...................................................................................................... 46

3-7 OSC and PLL Block.............................................................................................................. 48

3-8 Recommended Crystal/Clock Connection .................................................................................... 49

3-9 Watchdog Module ................................................................................................................ 50

4-1 CPU-Timers....................................................................................................................... 52

4-2 CPU-Timer Interrupts Signals and Output Signal (See Notes A. and B.)................................................. 53

4-3 Event Manager A Functional Block Diagram (See Note A.)................................................................ 58

4-4 Block Diagram of the F2812 ADC Module.................................................................................... 61

4-5 ADC Pin Connections With Internal Reference (See Notes A and B)..................................................... 62

4-6 ADC Pin Connections With External Reference ............................................................................. 63

4-7 eCAN Block Diagram and Interface Circuit................................................................................... 66

4-8 eCAN Memory Map .............................................................................................................. 67

4-9 McBSP Module With FIFO...................................................................................................... 70

4-10 Serial Communications Interface (SCI) Module Block Diagram............................................................ 75

4-11 Serial Peripheral Interface Module Block Diagram (Slave Mode).......................................................... 78

4-12 GPIO/Peripheral Pin Multiplexing .............................................................................................. 81

5-1 28x Device Nomenclature....................................................................................................... 83

6-1 SM320F2812-HT Life Expectancy Curve ..................................................................................... 87

6-2 Typical Current Consumption Over Frequency............................................................................... 89

6-3 Typical Power Consumption Over Frequency................................................................................ 90

6-4 F2812 Typical Power-Up and Power-Down Sequence – Option 2 ........................................................ 91

6-5 Output Levels ..................................................................................................................... 92

6-6 Input Levels ....................................................................................................................... 92

6-7 3.3-V Test Load Circuit.......................................................................................................... 93

6-8 Clock Timing ...................................................................................................................... 96

6-9 Power-on Reset in Microcomputer Mode (XMP/MC = 0) (See Note A)................................................... 98

6-10 Power-on Reset in Microprocessor Mode (XMP/MC = 1)................................................................... 99

6-11 Warm Reset in Microcomputer Mode.......................................................................................... 99

6-12 Effect of Writing Into PLLCR Register......................................................................................... 99

6-13 IDLE Entry and Exit Timing.................................................................................................... 100

6-14 STANDBY Entry and Exit Timing............................................................................................. 102

6-15 HALT Wakeup Using XNMI ................................................................................................... 104

6-16 PWM Output Timing............................................................................................................ 105

6-17 TDIRx Timing.................................................................................................................... 106

6-18 EVASOC Timing................................................................................................................ 106

6-19 EVBSOC Timing................................................................................................................ 106

6-20 External Interrupt Timing....................................................................................................... 107

6-21 General-Purpose Output Timing.............................................................................................. 108

6-22 GPIO Input Qualifier – Example Diagram for QUALPRD = 1............................................................. 108

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6-23 General-Purpose Input Timing................................................................................................ 109

6-24 SPI Master Mode External Timing (Clock Phase = 0) ..................................................................... 110

6-25 SPI Master External Timing (Clock Phase = 1)............................................................................. 112

6-26 SPI Slave Mode External Timing (Clock Phase = 0)....................................................................... 114

6-27 SPI Slave Mode External Timing (Clock Phase = 1)....................................................................... 116

6-28 Relationship Between XTIMCLK and SYSCLKOUT ....................................................................... 120

6-29 Example Read Access......................................................................................................... 122

6-30 Example Write Access......................................................................................................... 124

6-31 Example Read With Synchronous XREADY Access ...................................................................... 126

6-32 Example Read With Asynchronous XREADY Access..................................................................... 127

6-33 Write With Synchronous XREADY Access.................................................................................. 129

6-34 Write With Asynchronous XREADY Access ................................................................................ 130

6-35 External Interface Hold Waveform............................................................................................ 132

6-36 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK).................................................. 133

6-37 ADC Analog Input Impedance Model ........................................................................................ 137

6-38 ADC Power-Up Control Bit Timing ........................................................................................... 137

6-39 Sequential Sampling Mode (Single-Channel) Timing...................................................................... 139

6-40 Simultaneous Sampling Mode Timing ....................................................................................... 140

6-41 McBSP Receive Timing........................................................................................................ 144

6-42 McBSP Transmit Timing....................................................................................................... 144

6-43 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0................................................... 145

6-44 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0................................................... 146

6-45 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1................................................... 147

6-46 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1................................................... 148

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List of Tables

2-1 Hardware Features............................................................................................................... 14

2-2 Bare Die Information............................................................................................................. 15

2-3 Signal Descriptions .............................................................................................................. 17

3-1 Addresses of Flash Sectors in F2812 ......................................................................................... 29

3-2 Wait States ........................................................................................................................ 30

3-3 Boot Mode Selection............................................................................................................. 33

3-4 Peripheral Frame 0 Registers .................................................................................................. 37

3-5 Peripheral Frame 1 Registers .................................................................................................. 37

3-6 Peripheral Frame 2 Registers .................................................................................................. 38

3-7 Device Emulation Registers..................................................................................................... 39

3-8 XINTF Configuration and Control Register Mappings....................................................................... 41

3-9 XREVISION Register Bit Definitions........................................................................................... 41

3-10 PIE Peripheral Interrupts ....................................................................................................... 43

3-11 PIE Configuration and Control Registers ..................................................................................... 44

3-12 External Interrupts Registers ................................................................................................... 45

3-13 PLL, Clocking, Watchdog, and Low-Power Mode Registers .............................................................. 47

3-14 PLLCR Register Bit Definitions................................................................................................. 48

3-15 Possible PLL Configuration Modes ............................................................................................ 49

3-16 F2812 Low-Power Modes....................................................................................................... 51

4-1 CPU-Timers 0, 1, 2 Configuration and Control Registers................................................................... 54

4-2 Module and Signal Names for EVA and EVB ................................................................................ 55

4-3 EVA Registers ................................................................................................................... 56

4-4 ADC Registers ................................................................................................................... 64

4-5 3.3-V eCAN Transceivers for the SM320F2812 DSP....................................................................... 66

4-6 CAN Registers Map ............................................................................................................. 68

4-7 McBSP Register Summary...................................................................................................... 71

4-8 SCI-A Registers .................................................................................................................. 74

4-9 SCI-B Registers .................................................................................................................. 74

4-10 SPI Registers .................................................................................................................... 77

4-11 GPIO Mux Registers ............................................................................................................ 79

4-12 GPIO Data Registers ............................................................................................................ 80

6-1 Typical Current Consumption by Various Peripherals (at 150 MHz) ..................................................... 90

6-2 Recommended Low-Dropout Regulators ..................................................................................... 91

6-3 Clock Table and Nomenclature................................................................................................. 94

6-4 Input Clock Frequency .......................................................................................................... 94

6-5 XCLKIN Timing Requirements – PLL Bypassed or Enabled .............................................................. 95

6-6 XCLKIN Timing Requirements – PLL Disabled .............................................................................. 95

6-7 Possible PLL Configuration Modes ........................................................................................... 95

6-8 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ....................................................... 95

6-9 Reset (XRS) Timing Requirements ........................................................................................... 96

6-10 IDLE Mode Switching Characteristics ....................................................................................... 100

6-11 STANDBY Mode Switching Characteristics ................................................................................ 101

6-12 HALT Mode Switching Characteristics ...................................................................................... 103

6-13 PWM Switching Characteristics .............................................................................................. 105

6-14 Timer and Capture Unit Timing Requirements ............................................................................. 105

6-15 External ADC Start-of-Conversion – EVA – Switching Characteristics ................................................. 106

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6-16 External ADC Start-of-Conversion – EVB – Switching Characteristics ................................................. 106

6-17 Interrupt Switching Characteristics ........................................................................................... 106

6-18 Interrupt Timing Requirements................................................................................................ 107

6-19 General-Purpose Output Switching Characteristics........................................................................ 107

6-20 General-Purpose Input Timing Requirements .............................................................................. 108

6-21 SPI Master Mode External Timing (Clock Phase = 0) .................................................................... 109

6-22 SPI Master Mode External Timing (Clock Phase = 1) .................................................................... 111

6-23 SPI Slave Mode External Timing (Clock Phase = 0) ...................................................................... 113

6-24 SPI Slave Mode External Timing (Clock Phase = 1) ...................................................................... 115

6-25 Relationship Between Parameters Configured in XTIMING and Duration of Pulse ................................... 117

6-26 XTIMING Register Configuration Restrictions .............................................................................. 117

6-27 Valid and Invalid Timing ....................................................................................................... 117

6-28 XTIMING Register Configuration Restrictions .............................................................................. 118

6-29 Valid and Invalid Timing when using Synchronous XREADY ............................................................ 118

6-30 XTIMING Register Configuration Restrictions .............................................................................. 118

6-31 XTIMING Register Configuration Restrictions .............................................................................. 119

6-32 Asynchronous XREADY ...................................................................................................... 119

6-33 XINTF Clock Configurations................................................................................................... 119

6-34 External Memory Interface Read Switching Characteristics ............................................................. 122

6-35 External Memory Interface Read Timing Requirements .................................................................. 122

6-36 External Memory Interface Write Switching Characteristics .............................................................. 123

6-37 External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State) ....................... 125

6-38 External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) ............................ 125

6-39 Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... 125

6-40 Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ...................................... 125

6-41 External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) ........................ 128

6-42 Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ....................................... 128

6-43 Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ...................................... 128

6-44 XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) ...................................................... 132

6-45 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) ................................................. 133

6-46 DC Specifications .............................................................................................................. 135

6-47 AC Specifications .............................................................................................................. 136

6-48 Current Consumption .......................................................................................................... 136

6-49 ADC Power-Up Delays ........................................................................................................ 137

6-50 Sequential Sampling Mode Timing .......................................................................................... 139

6-51 Simultaneous Sampling Mode Timing ....................................................................................... 140

6-52 McBSP Timing Requirements ................................................................................................ 142

6-53 McBSP Switching Characteristics ........................................................................................... 143

6-54 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) ............................... 145

6-55 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) ........................... 145

6-56 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) ............................... 146

6-57 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) ........................... 146

6-58 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) ............................... 147

6-59 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) ........................... 147

6-60 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) ............................... 148

6-61 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) ........................... 148

6-62 Flash Parameters at 150-MHz SYSCLKOUT .............................................................................. 149

6-63 Flash/OTP Access Timing .................................................................................................... 149

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6-64 Minimum Required Wait-States at Different Frequencies ................................................................ 149

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Digital Signal Processor

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1 Features

• High-Performance Static CMOS Technology • 128 Bit Security Key/Lock – 150 MHz (6.67 ns Cycle Time) – Protects Flash/ROM/OTP and L0/L1 SARAM – Low Power (1.8 V Core at 135 MHz, 1.9 V, – Prevents Firmware Reverse Engineering

Core at 150 MHz, 3.3 V I/O) Design

– 3.3 V Flash Voltage

• JTAG Boundary Scan Support

(1)

• High-Performance 32 Bit CPU (TMS320C28x) – 16 × 16 and 32 x 32 MAC Operations – 16 × 16 Dual MAC – Harvard Bus Architecture – Atomic Operations (SCIs), Standard UART – Fast Interrupt Response and Processing – Enhanced Controller Area Network (eCAN) – Unified Memory Programming Model – Multichannel Buffered Serial Port (McBSP) – 4M Linear Program Address Reach – 4M Linear Data Address Reach – Code-Efficient (in C/C++ and Assembly) – TMS320F24x/LF240x Processor Source Code

Compatible – Single/Simultaneous Conversions

• On-Chip Memory – Fast Conversion Rate: 80 ns/12.5 MSPS – Flash Devices: Up to 128K × 16 Flash (Four • Up to 56 Individually Programmable,

8K × 16 and Six 16K × 16 Sectors) Multiplexed General-Purpose Input / Output – ROM Devices: Up to 128K × 16 ROM – 1K × 16 OTP ROM – L0 and L1: 2 Blocks of 4K × 16 Each

Single-Access RAM (SARAM) – Real-Time Debug via Hardware – H0: 1 Block of 8K × 16 SARAM • Development Tools Include – M0 and M1: 2 Blocks of 1K × 16 Each – ANSI C/C++ Compiler/Assembler/Linker

SARAM

• Boot ROM (4K × 16) – With Software Boot Modes – Standard Math Tables

• External Interface (TI) or Third-Party] – Up to 1M Total Memory – Evaluation Modules – Programmable Wait States – Broad Third-Party Digital Motor Control – Programmable Read/Write Strobe Timing – Three Individual Chip Selects

• Clock and System Control – Dynamic PLL Ratio Changes Supported – On-Chip Oscillator – Watchdog Timer Module

• Three External Interrupts xxx

• Peripheral Interrupt Expansion (PIE) Block That Supports 45 Peripheral Interrupts

(1) IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port

1TMS320C24x, Code Composer Studio, DSP/BIOS, C28x, TMS320C2000, TMS320C54x, TMS320C55x, TMS320C28x are trademarks of

Texas Instruments.

2eZdsp is a trademark of Spectrum Digital Incorporated.

• Three 32 Bit CPU Timers

• Motor Control Peripherals – Two Event Managers (EVA, EVB) – Compatible to 240xA Devices

• Serial Port Peripherals – Serial Peripheral Interface (SPI) – Two Serial Communications Interfaces

With SPI Mode

• 12 Bit ADC, 16 Channels – 2 × 8 Channel Input Multiplexer – Two Sample-and-Hold

(GPIO) Pins

• Advanced Emulation Features – Analysis and Breakpoint Functions

– Supports TMS320C24x™/240x Instructions – Code Composer Studio™ IDE – DSP/BIOS™ – JTAG Scan Controllers [Texas Instruments

Support

• Low-Power Modes and Power Savings – IDLE, STANDBY, HALT Modes Supported – Disable Individual Peripheral Clocks

xxx xxx

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xxx

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1.1 SUPPORTS EXTREME TEMPERATURE APPLICATIONS

• Controlled Baseline

• One Assembly/Test Site

• One Fabrication Site

• Available in Extreme (–55°C/220°C) Temperature Range

• Extended Product Life Cycle

• Extended Product-Change Notification

• Product Traceability

• Texas Instruments high temperature products utilize highly optimized silicon (die) solutions with design and process enhancements to maximize performance over extended temperatures.

(2) Custom temperature ranges available

(2)

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2 Introduction

This section provides a summary of the device features, lists the pin assignments, and describes the function of each pin. This document also provides detailed descriptions of peripherals, electrical specifications, parameter measurement information, and mechanical data about the available packaging.

2.1 Description

The SM320F2812 device, member of the C28xE DSP generation, is a highly integrated, high-performance solution for demanding control applications. The functional blocks and the memory maps are described in Section 3, Functional Overview.

Throughout this document SM320F2812 is abbreviated as F2812.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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2.2 Device Summary

Table 2-1 provides a summary of the device features.

Table 2-1. Hardware Features

FEATURE F2812

Instruction Cycle (at 150 MHz) 6.67 ns Single-Access RAM (SARAM) (16 bit word) 18K

3.3 V On-Chip Flash (16 bit word) 128K On-Chip ROM (16-bit word) — Code Security for On-Chip Flash/SARAM/OTP/ROM Yes Boot ROM Yes OTP ROM (1K × 16) Yes External Memory Interface Yes Event Managers A and B (EVA and EVB) EVA, EVB

• General-Purpose (GP) Timers 4

• Compare (CMP)/PWM 16

• Capture (CAP)/QEP Channels 6/2 Watchdog Timer Yes 12 Bit ADC Yes

• Channels 16 32 Bit CPU Timers 3 SPI Yes SCIA, SCIB SCIA, SCIB CAN Yes McBSP Yes Digital I/O Pins (Shared) 56 External Interrupts 3 Supply Voltage 1.8-V Core, (135 MHz) 1.9-V Core

Temperature Options S: –55°C to 220°C Yes

(150 MHz), 3.3-V I/O

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2.3 Die Layout

The SM320F2812 die layout is shown in Figure 2-1. See Table 2-3 for a description of each pad's function.

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Figure 2-1. SM320F2812 Die Layout

Table 2-2. Bare Die Information

DIE SIZE DIE PAD SIZE COMPOSITI

219.4 x 207.0 (mils); Silicon with

5572.0 x 5258.0 (mm) backgrind

55.0 x 64.0 (mm) See Table 2-3 11.0 mils AlCu/TiN Ground

DIE PAD DIE BACKSIDE BACKSIDE

COORDINATES THICKNESS FINISH POTENTIAL

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DIE PAD

DDAIO

130

172

ADCINB0

ADCINB1

ADCINB2

ADCINB3

ADCINB4

ADCINB5

ADCINB6

ADCINB7

ADCREFM

ADCREFP

AVSSREFBG

AVDDREFBG

DDA1

SSA1

ADCRESEXT

XMP/

XA[0]

MDRA

XD[0]

MDXA

XD[1]

MCLKRA

MFSXA

XD[2]

MCLKXA

MFSRA

XD[3]

DDIO

XD[4]

SPICLKA

SPISTEA

XD[5]

XD[6]

SPISIMOA

SPISOMIA

XRD

XA[1]

XZCS0AND1

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

XA[11]

TDI

XA[10]

TDO

TMS

XA[9]

XA[8]

XCLKOUT

XA[7]

TCLKINA

TDIRA

XA[6]

CAP3_QEPI1

XA[5]

CAP2_QEP2

CAP1_QEP1

T2PWM_T2CMP

XA[4]

T1PWM_T1CMP

PWM6

PWM5

XD[13]

XD[12]

PWM4

PWM3

PWM2

PWM1

SCIRXDB

SCITXDB

CANRXA

T1CTRIP_PDPINTA

DDIO

T2CTRIP / EVASOC

C1TRIP

C2TRIP

C3TRIP

PWM8

PWM9

PWM10

PWM11

PWM12

XR/W

T3PWM_T3CMP

XD[7]

T4PWM_T4CMP

CAP4_QEP3

CAP5_QEP4

CAP6_QEPI2

C4TRIP

C5TRIP

C6TRIP

DDIO

XD[8]

TEST2

TEST1

XD[9]

DD3VFL

TDIRB

TCLKINB

XD[10]

XD[11]

X1/XCLKIN

T3CTRIP_PDPINTB

XA[2]

DDIO

XHOLDA

T4CTRIP/EVBSOC

XWE

XA[3]

CANTXA

XZCS2

134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171

129 87

TESTSEL

TRST

TCK

EMU0

XA[12] XD[14]

XA[13]

DD XA[14] V

DDIO

EMU1 XD[15] XA[15]

XINT1_XBIO

XA[16]

SCITXDA

XA[17]

SCIRXDA

XA[18]

XHOLD

XRS

XREADY

DD1

SS1

SSA2

DDA2 ADCINA7 ADCINA6 ADCINA5

ADCINA4

ADCINA3 ADCINA2 ADCINA1 ADCINA0

ADCLO

SSAIO

132 133

XZCS6AND7

XF_XPLLDIS

XNMI_XINT13

XINT2_ADCSOC

ADCBGREFIN

PWM7

131

SM320F2812-HT

SGUS062A–JUNE 2009–REVISED APRIL 2010

2.4 Pin Assignments

The SM320F2812 172-pin HFG ceramic quad flatpack (CQFP) pin assignments are shown in Figure 2-2. See Table 2-3 for a description of each pin’s function(s).

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Figure 2-2. SM320F2812 172-Pin HFG CQFP (Top View)

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2.5 Signal Descriptions

Table 2-3 specifies the signals on the F2812 device. All digital inputs are TTL-compatible. All outputs are

3.3 V with CMOS levels. Inputs are not 5 V tolerant. A 100 mA (or 20 mA) pullup/pulldown is used.

Table 2-3. Signal Descriptions

PIN NO.

NAME X-CENTER Y-CENTER I/O/Z

XA[18] 154 173 42.6 2281.5 O/Z – XA[17] 152 171 42.6 2485.3 O/Z – XA[16] 149 167 42.6 2819.6 O/Z – XA[15] 145 163 42.6 3182.9 O/Z – XA[14] 141 157 42.6 3774.9 O/Z – XA[13] 138 154 42.6 4029.4 O/Z – XA[12] 135 151 42.6 4401.3 O/Z – XA[11] 129 145 255.7 5057.5 O/Z XA[10] 127 143 474.4 5057.5 O/Z – XA[9] 122 138 996.5 5057.5 O/Z – 19-bit XINTF Address Bus XA[8] 118 134 1492.4 5057.5 O/Z – XA[7] 116 131 1825.2 5057.5 O/Z – XA[6] 109 124 2566.0 5057.5 O/Z – XA[5] 106 121 2937.9 5057.5 O/Z – XA[4] 101 116 3518.7 5057.5 O/Z – XA[3] 83 96 5361.5 4471.5 O/Z – XA[2] 78 91 5361.5 3927.2 O/Z – XA[1] 42 49 5024.5 42.6 O/Z – XA[0] 18 24 2403.5 42.6 O/Z XD[15] 144 162 42.6 3306.9 I/O/Z PU XD[14] 136 152 42.6 4277.3 I/O/Z PU XD[13] 95 110 4194.1 5057.5 I/O/Z PU XD[12] 94 109 4318.1 5057.5 I/O/Z PU XD[11] 72 85 5361.5 3382.2 I/O/Z PU XD[10] 71 84 5361.5 3258.3 I/O/Z PU XD[9] 67 77 5361.5 2608.4 I/O/Z PU XD[8] 64 74 5361.5 2312.1 I/O/Z PU XD[7] 53 60 5361.5 1045.9 I/O/Z PU XD[6] 38 45 4586.0 42.6 I/O/Z PU XD[5] 35 42 4281.2 42.6 I/O/Z PU XD[4] 32 39 3966.6 42.6 I/O/Z PU XD[3] 29 36 3652.0 42.6 I/O/Z PU XD[2] 26 33 3337.5 42.6 I/O/Z PU XD[1] 23 30 3022.9 42.6 I/O/Z PU XD[0] 20 27 2708.3 42.6 I/O/Z PU

172-PIN

HFG

DIE PAD

NO.

DIE PAD DIE PAD

(mm) (mm)

XINTF SIGNALS

(2)

(1)

PU/PD

(3)

16-bit XINTF Data Bus

DESCRIPTION

(1) Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are

8 mA. (2) I = Input, O = Output, Z = High impedance (3) PU = pin has internal pullup; PD = pin has internal pulldown

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Table 2-3. Signal Descriptions

PIN NO.

NAME X-CENTER Y-CENTER I/O/Z

XMP/MC 17 23 2308.2 42.6 I PD external interface and on-chip boot ROM

XHOLD 155 174 42.6 2157.6 I PU strobes into a high-impedance state. The

XHOLDA 80 93 5361.5 4137.4 O/Z –

XZCS0AND1 43 50 5148.5 42.6 O/Z –

XZCS2 86 100 5361.5 4844.2 O/Z – (low) when an access to the XINTF Zone 2

XZCS6AND7 130 146 42.6 4888.6 O/Z –

XWE 82 95 5361.5 4347.5 O/Z –

XRD 41 48 4900.6 42.6 O/Z –

XR/W 50 57 5361.5 755.0 O/Z –

XREADY 157 176 42.6 1972.4 I PU XREADY can be configured to be a

172-PIN

HFG

DIE PAD

NO.

DIE PAD DIE PAD

(mm) (mm)

(1)

(continued)

(2)

PU/PD

(3)

Microprocessor/Microcomputer Mode Select. Switches between microprocessor and microcomputer mode. When high, Zone 7 is enabled on the external interface. When low, Zone 7 is disabled from the

may be accessed instead. This signal is latched into the XINTCNF2 register on a reset and the user can modify this bit in software. The state of the XMP/MC pin is ignored after reset.

External Hold Request. XHOLD, when active (low), requests the XINTF to release the external bus and place all buses and

XINTF releases the bus when any current access is complete and there are no pending accesses on the XINTF.

External Hold Acknowledge. XHOLDA is driven active (low) when the XINTF has granted a XHOLD request. All XINTF buses and strobe signals are in a high-impedance state. XHOLDA is released when the XHOLD signal is released. External devices should only drive the external bus when XHOLDA is active (low).

XINTF Zone 0 and Zone 1 Chip Select. XZCS0AND1 is active (low) when an access to the XINTF Zone 0 or Zone 1 is performed.

XINTF Zone 2 Chip Select. XZCS2 is active is performed.

XINTF Zone 6 and Zone 7 Chip Select. XZCS6AND7 is active (low) when an access to the XINTF Zone 6 or Zone 7 is performed.

Write Enable. Active-low write strobe. The write strobe waveform is specified, per zone basis, by the Lead, Active, and Trail periods in the XTIMINGx registers.

Read Enable. Active-low read strobe. The read strobe waveform is specified, per zone basis, by the Lead, Active, and Trail periods in the XTIMINGx registers. NOTE: The XRD and XWE signals are mutually exclusive.

Read Not Write Strobe. Normally held high. When low, XR/W indicates write cycle is active; when high, XR/W indicates read cycle is active.

Ready Signal. Indicates peripheral is ready to complete the access when asserted to 1.

synchronous or an asynchronous input. See the timing diagrams for more details.

DESCRIPTION

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Table 2-3. Signal Descriptions

PIN NO.

NAME X-CENTER Y-CENTER I/O/Z

172-PIN

HFG

DIE PAD

NO.

DIE PAD DIE PAD

(mm) (mm)

(1)

(continued)

(2)

PU/PD

SGUS062A–JUNE 2009–REVISED APRIL 2010

(3)

DESCRIPTION

JTAG AND MISCELLANEOUS SIGNALS

Oscillator Input – input to the internal oscillator. This pin is also used to feed an external clock. The 28× can be operated with an external clock source, provided that the proper voltage levels be driven on the X1/XCLKIN pin. It should be noted that the

X1/XCLKIN 75 88 5361.5 3668.7 I

X1/XCLKIN pin is referenced to the 1.8-V (or 1.9-V) core digital power supply (VDD), rather than the 3.3-V I/O supply (V clamping diode may be used to clamp a

DDIO

buffered clock signal to ensure that the logic-high level does not exceed V (1.8 V or 1.9 V) or a 1.8-V oscillator may be

used.

X2 74 87 5361.5 3582.6 O Oscillator Output

Output clock derived from SYSCLKOUT to be used for external wait-state generation and as a general-purpose clock source. XCLKOUT is either the same frequency,

XCLKOUT 117 132 1701.2 5057.5 O – 1/2 the frequency, or 1/4 the frequency of

SYSCLKOUT. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting bit 3 (CLKOFF) of the XINTCNF2 register to 1.

TESTSEL 131 147 42.6 4764.6 I PD

Test Pin. Reserved for TI. Must be connected to ground.

Device Reset (in) and Watchdog Reset (out).

Device reset. XRS causes the device to terminate execution. The PC points to the address contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the location

XRS 156 175 42.6 2077.8 I/O PU

pointed to by the PC. This pin is driven low by the DSP when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 XCLKIN cycles.

The output buffer of this pin is an open-drain with an internal pullup (100 mA, typical). It is recommended that this pin be driven by an open-drain device.

TEST1 66 76 5361.5 2522.3 I/O –

TEST2 65 75 5361.5 2436.1 I/O –

Test Pin. Reserved for TI. On F281x devices, TEST1 must be left unconnected.

Test Pin. Reserved for TI. On F281x devices, TEST2 must be left unconnected.

). A

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Table 2-3. Signal Descriptions

PIN NO.

NAME X-CENTER Y-CENTER I/O/Z

TRST 132 148 42.6 4684.8 I PD

TCK 133 149 42.6 4605.1 I PU JTAG test clock with internal pullup

TMS 123 139 872.5 5057.5 I PU

TDI 128 144 350.4 5057.5 I PU

TDO 124 140 777.9 5057.5 O/Z –

EMU0 133 150 42.6 4525.3 I/O/Z PU

EMU1 143 161 42.6 3430.9 I/O/Z PU

172-PIN

HFG

DIE PAD

NO.

DIE PAD DIE PAD

(mm) (mm)

(1)

(continued)

(2)

PU/PD

(3)

JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored.

NOTE: Do not use pullup resistors on TRST; it has an internal pulldown device. In a low-noise environment, TRST can be left floating. In a high-noise environment, an additional pulldown resistor may be needed. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since this is application specific, it is recommended that each target board is validated for proper operation of the debugger and the application.

JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK.

JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK.

JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) is shifted out of TDO on the falling edge of TCK.

Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan.

Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan.

DESCRIPTION

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Table 2-3. Signal Descriptions

PIN NO.

NAME X-CENTER Y-CENTER I/O/Z

172-PIN

HFG

DIE PAD

NO.

DIE PAD DIE PAD

(mm) (mm)

(1)

(continued)

(2)

PU/PD

SGUS062A–JUNE 2009–REVISED APRIL 2010

(3)

DESCRIPTION

ADC ANALOG INPUT SIGNALS

ADCINA7 163 186 42.6 1253.9 I ADCINA6 164 188 42.6 1094.3 I ADCINA5 165 190 42.6 954.0 I ADCINA4 166 192 42.6 794.4 I ADCINA3 167 194 42.6 654.1 I ADCINA2 168 196 42.6 513.9 I

Eight-channel analog inputs for Sample-and-Hold A. The ADC pins should not be driven before V V

pins have been fully powered up.

DDAIO

DDA1

ADCINA1 169 197 42.6 434.1 I ADCINA0 170 198 42.6 354.3 I ADCINB7 9 13 1355.2 42.6 I ADCINB6 8 11 1164.6 42.6 I ADCINB5 7 10 1069.2 42.6 I ADCINB4 6 8 878.6 42.6 I ADCINB3 5 6 688.0 42.6 I ADCINB2 4 4 497.4 42.6 I

Eight-channel analog inputs for Sample-and-Hold B. The ADC pins should not be driven before the V V

pins have been fully powered up.

DDAIO

ADCINB1 3 3 402.1 42.6 I ADCINB0 2 2 306.8 42.6 I

ADC Voltage Reference Output (2 V). Requires a low ESR (50 mΩ – 1.5 Ω) ceramic bypass capacitor of 10 mF to analog ground. (Can accept external

ADCREFP 11 15 1545.8 42.6 O reference input

(2 V) if the software bit is enabled for this mode. 1-mF to 10-mF low ESR capacitor can be used in the external reference mode.)

ADC Voltage Reference Output (1 V). Requires a low ESR (50 mΩ – 1.5 Ω) ceramic bypass capacitor of 10 mF to analog ground. (Can accept external

ADCREFM 10 14 1450.5 42.6 O reference input

(1 V) if the software bit is enabled for this mode. 1-mF to 10-mF low ESR capacitor can be used in the external reference mode.)

ADCRESEXT 16 22 2212.9 42.63 O

ADCBGREFIN 160 180 42.6 1680.9 I

ADC External Current Bias Resistor (24.9 kΩ ±5%)

Test Pin. Reserved for TI. Must be left

unconnected. AVSSREFBG 12 17 1831.7 42.6 I ADC Analog GND AVDDREFBG 13 18 1736.4 42.6 I ADC Analog Power (3.3 V)

ADCLO 171 199 42.6 274.5 I V

SSA1

SSA2

DDA1

DDA2

SS1

DD1

DDAIO

SSAIO

15 21 2117.6 42.6 I ADC Analog GND

161 182 42.6 1550.7 I ADC Analog GND

14 19 1927.0 42.6 I ADC Analog 3.3-V Supply 162 184 42.6 1394.2 I ADC Analog 3.3-V Supply 159 178 42.6 1830.8 I ADC Digital GND 158 177 42.6 1901.0 I ADC Digital 1.8-V (or 1.9-V) Supply

1 1 211.5 42.6 3.3-V Analog I/O Power Pin

172 200 42.6 204.3 Analog I/O Ground Pin

Common Low Side Analog Input. Connect to analog ground.

, V

DDA1

DDA2

, V

, and

DDA2

, and

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Table 2-3. Signal Descriptions

PIN NO.

NAME X-CENTER Y-CENTER I/O/Z

172-PIN

HFG

DDIO

DD3VFL

22 29 2927.6 42.6

36 43 4395.4 42.6

55 62 5361.5 1256.0

73 86 5361.5 3496.4

98 113 3861.3 5057.5 110 125 2451.9 5057.5 125 141 663.7 5057.5 140 156 42.6 3845.1 150 169 42.6 2635.3

31 38 3871.3 42.6

37 44 4490.7 42.6

51 58 5361.5 869.2

57 65 5361.5 1514.6

76 89 5361.5 3754.9

84 97 5361.5 4585.7

97 112 3956.0 5057.5 103 118 3280.5 5057.5 111 126 2357.2 5057.5

126 142 569.0 5057.5 139 155 42.6 3915.2

30 37 3776.0 42.6

63 73 5361.5 2226.0

79 92 5361.5 4051.2

112 127 2262.5 5057.5 142 160 42.6 3510.7

68 78 5361.5 2732.4

DIE PAD

NO.

- 98 5361.5 4671.835

- 25 2517.7 42.6

- 79 5361.5 2818.6

- 133 1587.1 5057.5

- 159 42.6 3580.8

- 168 42.6 2705.4

- 105 4784.7 5057.5

DIE PAD DIE PAD

(mm) (mm)

POWER SIGNALS

(1)

(continued)

(2)

PU/PD

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(3)

DESCRIPTION

1.8-V or 1.9-V Core Digital Power Pins. See Section 6.2, Recommended Operating Conditions, for voltage requirements.

Core and Digital I/O Ground Pins

3.3–V I/O Digital Power Pins

3.3–V Flash Core Power Pin. This pin should be connected to 3.3 V at all times after power-up sequence requirements have been met. This pin is used as VDDIO in ROM parts and must be connected to

3.3 V in ROM parts as well.

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Signal Descriptions (Continued)

GPIO DIE PAD NO. I/O/Z

GPIOA0 PWM1 (O) 90 104 4908.6 5057.5 I/O/Z PU

GPIOA1 PWM2 (O) 91 106 4690.0 5057.5 I/O/Z PU

GPIOA2 PWM3 (O) 92 107 4566.0 5057.5 I/O/Z PU

GPIOA3 PWM4 (O) 93 108 4442.1 5057.5 I/O/Z PU

GPIOA4 PWM5 (O) 96 111 4070.1 5057.5 I/O/Z PU

GPIOA5 PWM6 (O) 99 114 3766.6 5057.5 I/O/Z PU

GPIOA6 T1PWM_T1CMP (I) 100 115 3642.7 5057.5 I/O/Z PU

GPIOA7 T2PWM_T2CMP (I) 102 117 3394.7 5057.5 I/O/Z PU

GPIOA8 CAP1_QEP1 (I) 104 119 3185.9 5057.5 I/O/Z PU

GPIOA9 CAP2_QEP2 (I) 105 120 3061.9 5057.5 I/O/Z PU

GPIOA10 CAP3_QEPI1 (I) 107 122 2814.0 5057.5 I/O/Z PU

GPIOA11 TDIRA (I) 114 129 2073.2 5057.5 I/O/Z PU

GPIOA12 TCLKINA (I) 115 130 1949.2 5057.5 I/O/Z PU

GPIOA13 C1TRIP (I) 119 135 1368.4 5057.5 I/O/Z PU

GPIOA14 C2TRIP (I) 120 136 1244.5 5057.5 I/O/Z PU

GPIOA15 C3TRIP (I) 121 137 1120.5 5057.5 I/O/Z PU

GPIOB0 PWM7 (O) 44 51 5361.5 211.5 I/O/Z PU

GPIOB1 PWM8 (O) 45 52 5361.5 302.1 I/O/Z PU

GPIOB2 PWM9 (O) 46 53 5361.5 392.7 I/O/Z PU

GPIOB3 PWM10 (O) 47 54 5361.5 483.2 I/O/Z PU

GPIOB4 PWM11 (O) 48 55 5361.5 573.8 I/O/Z PU

GPIOB5 PWM12 (O) 49 56 5361.5 664.4 I/O/Z PU

GPIOB6 T3PWM_T3CMP (I) 52 59 5361.5 955.3 I/O/Z PU

GPIOB7 T4PWM_T4CMP (I) 54 61 5361.5 1169.9 I/O/Z PU

PERIPHERAL DIE PAD DIE PAD

SIGNAL X-CENTER Y-CENTER

PIN NO.

172-PIN

HFG

GPIO OR PERIPHERAL SIGNALS

GPIOA OR EVA SIGNALS

GPIOB OR EVB SIGNALS

SGUS062A–JUNE 2009–REVISED APRIL 2010

(1)

(2)

PU/PD

(3)

DESCRIPTION

GPIO or PWM Output Pin #1

GPIO or PWM Output Pin #2

GPIO or PWM Output Pin #3

GPIO or PWM Output Pin #4

GPIO or PWM Output Pin #5

GPIO or PWM Output Pin #6

GPIO or Timer 1 Output

GPIO or Timer 2 Output

GPIO or Capture Input #1

GPIO or Capture Input #2

GPIO or Capture Input #3

GPIO or Timer Direction

GPIO or Timer Clock Input

GPIO or Compare 1 Output Trip

GPIO or Compare 2 Output Trip

GPIO or Compare 3 Output Trip

GPIO or PWM Output Pin #7

GPIO or PWM Output Pin #8

GPIO or PWM Output Pin #9

GPIO or PWM Output Pin #10

GPIO or PWM Output Pin #11

GPIO or PWM Output Pin #12

GPIO or Timer 3 Output

GPIO or Timer 4 Output

(1) Typical drive strength of the output buffer for all pins [except TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins] is 4 mA typical. (2) I = Input, O = Output, Z = High impedance (3) PU = pin has internal pullup; PD = pin has internal pulldown

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Signal Descriptions (Continued)

GPIO DIE PAD NO. I/O/Z

GPIOB8 CAP4_QEP3 (I) 56 64 5361.5 1428.4 I/O/Z PU

GPIOB9 CAP5_QEP4 (I) 58 66 5361.5 1600.7 I/O/Z PU

GPIOB10 CAP6_QEPI2 (I) 59 67 5361.5 1691.3 I/O/Z PU

GPIOB11 TDIRB (I) 69 81 5361.5 2990.9 I/O/Z PU

GPIOB12 TCLKINB (I) 70 82 5361.5 3081.5 I/O/Z PU

GPIOB13 C4TRIP (I) 60 69 5361.5 1868.1 I/O/Z PU

GPIOB14 C5TRIP (I) 61 71 5361.5 2044.8 I/O/Z PU

GPIOB15 C6TRIP (I) 62 72 5361.5 2135.4 I/O/Z PU

GPIOD0 T1CTRIP_PDPINTA (I) 108 123 2690.0 5057.5 I/O/Z PU

GPIOD1 T2CTRIP/EVASOC (I) 113 128 2167.8 5057.5 I/O/Z PU External ADC

GPIOD5 T3CTRIP_PDPINTB (I) 77 90 5361.5 3841.1 I/O/Z PU

GPIOD6 T4CTRIP/EVBSOC (I) 81 94 5361.5 4261.4 I/O/Z PU External ADC

GPIOE0 XINT1_XBIO (I) 146 164 42.6 3059.0 I/O/Z –

GPIOE1 XINT2_ADCSOC (I) 148 166 42.6 2899.4 I/O/Z – ADC start of

GPIOE2 XNMI_XINT13 (I) 147 165 42.6 2979.2 I/O/Z PU

GPIOF0 SPISIMOA (O) 39 46 4709.9 42.6 I/O/Z –

GPIOF1 SPISOMIA (I) 40 47 4805.3 42.6 I/O/Z –GPIOF2 SPICLKA (I/O) 33 40 4090.6 42.6 I/O/Z – GPIO or SPI clock GPIOF3 SPISTEA (I/O) 34 41 4185.9 42.6 I/O/Z –

GPIOF4 SCITXDA (O) 151 170 42.6 2565.1 I/O/Z PU asynchronous serial

GPIOF5 SCIRXDA (I) 153 172 42.6 2361.3 I/O/Z PU asynchronous serial

PERIPHERAL DIE PAD DIE PAD

SIGNAL X-CENTER Y-CENTER

PIN NO.

172-PIN

HFG

GPIOD OR EVA SIGNALS

GPIOD OR EVB SIGNALS

GPIOE OR INTERRUPT SIGNALS

GPIOF OR SPI SIGNALS

GPIOF OR SCI-A SIGNALS

(1)

(continued)

(2)

PU/PD

(3)

GPIO or Capture Input #4

GPIO or Capture Input #5

GPIO or Capture Input #6

GPIO or Timer Direction

GPIO or Timer Clock Input

GPIO or Compare 4 Output Trip

GPIO or Compare 5 Output Trip

GPIO or Compare 6 Output Trip

Timer 1 Compare Output Trip

Timer 2 Compare Output Trip or

Start-of-Conversion EV-A

Timer 3 Compare Output Trip

Timer 4 Compare Output Trip or

Start-of-Conversion EV-B

GPIO or XINT1 or XBIO input

GPIO or XINT2 or conversion

GPIO or XNMI or XINT13

GPIO or SPI slave in, master out

GPIO or SPI slave out, master in

GPIO or SPI slave transmit enable

GPIO or SCI port TX data

GPIO or SCI port RX data

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DESCRIPTION

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Signal Descriptions (Continued)

GPIO DIE PAD NO. I/O/Z

GPIOF6 CANTXA (O) 85 99 5361.5 4758.0 I/O/Z PU

GPIOF7 CANRXA (I) 87 101 5192.7 5057.5 I/O/Z PU

GPIOF8 MCLKXA (I/O) 27 34 3461.4 42.6 I/O/Z PU

GPIOF9 MCLKRA (I/O) 24 31 3146.8 42.6 I/O/Z PU

GPIOF10 MFSXA (I/O) 25 32 3242.2 42.6 I/O/Z PU

GPIOF11 MFSRA (I/O) 28 35 3556.7 42.6 I/O/Z PU

GPIOF12 MDXA (O) 21 28 2832.3 42.6 I/O/Z –

GPIOF13 MDRA (I) 19 26 2613.0 42.6 I/O/Z PU

GPIOF14 XF_XPLLDIS (O) 137 153 42.6 4153.3 I/O/Z PU

PERIPHERAL DIE PAD DIE PAD

SIGNAL X-CENTER Y-CENTER

PIN NO.

172-PIN

HFG

GPIOF OR CAN SIGNALS

GPIOF OR McBSP SIGNALS

GPIOF OR XF CPU OUTPUT SIGNAL

(1)

(continued)

SGUS062A–JUNE 2009–REVISED APRIL 2010

(2)

PU/PD

(3)

DESCRIPTION

GPIO or eCAN transmit data

GPIO or eCAN receive data

GPIO or transmit clock

GPIO or receive clock

GPIO or transmit frame synch

GPIO or receive frame synch

GPIO or transmitted serial data

GPIO or received serial data

This pin has three functions:

1. XF – General-purpose output pin.

2. XPLLDIS – This pin is sampled during reset to check if the PLL needs to be disabled. The PLL will be disabled if this pin is sensed low. HALT and STANDBY modes cannot be used when the PLL is disabled.

3. GPIO – GPIO function

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Signal Descriptions (Continued)

GPIO DIE PAD NO. I/O/Z

GPIOG4 SCITXDB (O) 88 102 5098.0 5057.5 I/O/Z – asynchronous serial

GPIOG5 SCIRXDB (I) 89 103 5003.3 5057.5 I/O/Z – asynchronous serial

PERIPHERAL DIE PAD DIE PAD

SIGNAL X-CENTER Y-CENTER

PIN NO.

172-PIN

HFG

GPIOG OR SCI-B SIGNALS

(1)

(continued)

(2)

PU/PD

(3)

GPIO or SCI port transmit data

GPIO or SCI port receive data

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DESCRIPTION

NOTE

Other than the power supply pins, no pin should be driven before the 3.3-V rail has reached recommended operating conditions.

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M0 SARAM

1K x 16

CPU-Timer 0

CPU-Timer 1

INT[12:1]

CLKIN

Real-Time JTAG

CPU-Timer 2

Peripheral Bus

C28x CPU

H0 SARAM

8K ⋅ 16

INT14

NMI

INT13

Memory Bus

M1 SARAM

1K x 16

Flash

128K x 16

Boot ROM

4K ⋅ 16

eCAN

SCIA/SCIB

12-Bit ADC

External Interrupt

Control

(XINT1/2/13, XNMI)

EVA/EVB

Memory Bus

OTP

1K x 16

McBSP

System Control

(Oscillator and PLL

Peripheral Clocking

Low-Power

Modes

WatchDog)

FIFO

PIE

(96 interrupts)

†

SPI FIFO

TINT0

TINT1

TINT2

Control

Address(19)

Data(16)

External

Interface

(XINTF)

16 Channels

†

45 of the possible 96 interrupts are used on the device.

GPIO Pins

XRS

X1/XCLKIN

XF_XPLLDIS

Protected by the code-security module.

XINT13

L1 SARAM

4K x 16

XNMI

L0 SARAM

4K x 16

‡

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3 Functional Overview

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Figure 3-1. Functional Block Diagram

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Block

Start Address

Low 64K

(24x/240x Equivalent Data Space)

0x00 0000

M0 Vector − RAM (32 × 32)

(Enabled if VMAP = 0)

Data Space Prog Space

M0 SARAM (1K × 16) M1 SARAM (1K × 16)

Peripheral Frame 0

(2K × 16)

0x00 0040 0x00 0400

0x00 0800

PIE Vector - RAM

(256 × 16)

(Enabled if VMAP

= 1, ENPIE = 1)

Reserved

L0 SARAM (4K × 16, Secure Block)

Peripheral Frame 1

(4K × 16, Protected)

Reserved

Peripheral Frame 2

(4K × 16, Protected)

L1 SARAM (4K × 16, Secure Block)

Reserved

OTP (or ROM) (1K × 16, Secure Block)

Flash (or ROM) (128K × 16, Secure Block)

128-Bit Password

H0 SARAM (8K × 16)

Reserved

Boot ROM (4K × 16)

(Enabled if MP/MC

= 0)

BROM Vector - ROM (32 × 32)

(Enabled if VMAP = 1, MP/MC

= 0, ENPIE = 0)

0x00 0D00

0x00 0E00 0x00 2000

0x00 6000

0x00 7000

0x00 8000 0x00 9000

0x00 A000

0x3D 7800 0x3D 7C00

0x3F 7FF8

0x3F 8000

0x3F A000

0x3F F000

0x3F FFC0

High 64K

(24x/240x Equivalent

Program Space)

Data Space Prog Space

Reserved

XINTF Zone 0 (8K × 16, XZCS0AND1

)

XINTF Zone 1 (8K × 16, XZCS0AND1) (Protected)

Reserved

XINTF Zone 2 (0.5M × 16, XZCS2

)

XINTF Zone 6 (0.5M × 16, XZCS6AND7)

Reserved

XINTF Zone 7 (16K × 16, XZCS6AND7)

(Enabled if MP/MC

= 1)

XINTF Vector - RAM (32 × 32)

(Enabled if VMAP = 1, MP/MC

= 1, ENPIE = 0)

On-Chip Memory External Memory XINTF

Only one of these vector maps—M0 vector, PIE vector, BROM vector, XINTF vector—should be enabled at a time.

LEGEND:

0x08 0000

0x00 4000

0x10 0000 0x18 0000

0x3F C000

0x00 2000

Reserved (1K)

0x3D 8000

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3.1 Memory Map

A. Memory blocks are not to scale. B. Reserved locations are reserved for future expansion. Application should not access these areas. C. Boot ROM and Zone 7 memory maps are active either in on-chip or XINTF zone depending on MP/MC, not in both. D. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.

E. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order. F. Certain memory ranges are EALLOW protected against spurious writes after configuration. G. Zones 0 and 1 and Zones 6 and 7 share the same chip select; hence, these memory blocks have mirrored locations.

User program cannot access these memory maps in program space.

Figure 3-2. F2812 Memory Map (See Notes A. Through G.)

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Table 3-1. Addresses of Flash Sectors in F2812

ADDRESS RANGE PROGRAM AND DATA SPACE

0x3D 8000 0x3D 9FFF

0x3D A000

0x3D BFFF 0x3D C000

0x3D FFFF

0x3E 0000 0x3E 3FFF

0x3E 4000 0x3E 7FFF

0x3E 8000

0x3E BFFF

0x3E C000

0x3E FFFF

0x3F 0000 0x3F 3FFF

0x3F 4000 0x3F 5FFF

0x3F 6000 Sector A, 8K × 16 0x3F 7F80 Program to 0x0000 when using the

0x3F 7FF5 Code Security Module 0x3F 7FF6 Boot-to-Flash (or ROM) Entry Point

0x3F 7FF7 (program branch instruction here) 0x3F 7FF8 Security Password (128-Bit)

0x3F 7FFF (Do not program to all zeros)

Sector J, 8K × 16

Sector I, 8K × 16

Sector H, 16K × 16

Sector G, 16K × 16

Sector F, 16K × 16

Sector E, 16K × 16

Sector D, 16K × 16

Sector C, 16K × 16

Sector B, 8K × 16

The Low 64K of the memory address range maps into the data space of the 240x. The High 64K of the memory address range maps into the program space of the 24x/240x. 24x/240x-compatible code only executes from the High 64K memory area. Hence, the top 32K of Flash/ROM and H0 SARAM block can be used to run 24x/240x-compatible code (if MP/MC mode is low) or, on the F2812, code can be executed from XINTF Zone 7 (if MP/MC mode is high).

The XINTF consists of five independent zones. One zone has its own chip select and the remaining four zones share two chip selects. Each zone can be programmed with its own timing (wait states) and to either sample or ignore external ready signal. This makes interfacing to external peripherals easy and glueless.

NOTE

The chip selects of XINTF Zone 0 and Zone 1 are merged together into a single chip select (XZCS0AND1); and the chip selects of XINTF Zone 6 and Zone 7 are merged together into a single chip select (XZCS6AND7). See Section 3.5, External Interface, XINTF (2812 only), for details.

Peripheral Frame 1, Peripheral Frame 2, and XINTF Zone 1 are grouped together so as to enable these blocks to be write/read peripheral block protected. The protected mode ensures that all accesses to these blocks happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different memory locations, appears in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral applications where the user expected the write to occur first (as written). The C28x CPU supports a block protection mode where a region of memory can be protected so as to make sure that operations occur as written (the penalty is extra cycles are added to align the operations). This mode is programmable and by default, it protects the selected zones.

On the F2812, at reset, XINTF Zone 7 is accessed if the XMP/MC pin is pulled high. This signal selects microprocessor or microcomputer mode of operation. In microprocessor mode, Zone 7 is mapped to high

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memory such that the vector table is fetched externally. The Boot ROM is disabled in this mode. In microcomputer mode, Zone 7 is disabled such that the vectors are fetched from Boot ROM. This allows the user to either boot from on-chip memory or from off-chip memory. The state of the XMP/MC signal on reset is stored in an MP/MC mode bit in the XINTCNF2 register. The user can change this mode in software and hence control the mapping of Boot ROM and XINTF Zone 7. No other memory blocks are affected by XMP/MC.

I/O space is not supported on the F2812 XINTF. The wait states for the various spaces in the memory map area are listed in Table 3-2.

Table 3-2. Wait States

AREA WAIT-STATES COMMENTS

M0 and M1 SARAMs 0-wait Fixed

Peripheral Frame 0 0-wait Fixed Peripheral Frame 1 Fixed

Peripheral Frame 2 Fixed L0 and L1 SARAMs 0-wait

OTP (or ROM)

Flash (or ROM) CPU frequency. The CSM password locations are hardwired for 16 wait-states.

H0 SARAM 0-wait Fixed

Boot-ROM 1-wait Fixed

XINTF Cycles can be extended by external memory or peripheral.

0-wait (writes) 2-wait (reads)

Programmable, Programmed via the Flash registers. 1-wait-state operation is possible at a reduced

1-wait minimum CPU frequency. See Section 3.2.6, Flash (F281x Only), for more information.

Programmable,

0-wait minimum

Programmable,

1-wait minimum

Programmed via the Flash registers. 0-wait-state operation is possible at reduced See Section 3.2.6, Flash (F281x Only), for more information.

Programmed via the XINTF registers. 0-wait operation is not possible.

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3.2 Brief Descriptions

3.2.1 C28x CPU

The C28x™ DSP generation is the newest member of the TMS320C2000™ DSP platform. The C28x is source code compatible to the 24x/240x DSP devices, hence existing 240x users can leverage their significant software investment. Additionally, the C28x is a very efficient C/C++ engine, hence enabling users to develop not only their system control software in a high-level language, but also enables math algorithms to be developed using C/C++. The C28x is as efficient in DSP math tasks as it is in system control tasks that typically are handled by microcontroller devices. This efficiency removes the need for a second processor in many systems. The 32 × 32-bit MAC capabilities of the C28x and its 64-bit processing capabilities, enable the C28x to efficiently handle higher numerical resolution problems that would otherwise demand a more expensive floating-point processor solution. Add to this the fast interrupt response with automatic context save of critical registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency. The C28x has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables the C28x to execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional operations further improve performance.

3.2.2 Memory Bus (Harvard Bus Architecture)

As with many DSP type devices, multiple busses are used to move data between the memories and peripherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and memories attached to the memory bus prioritizes memory accesses. Generally, the priority of Memory Bus accesses can be summarized as follows:

Highest: Data Writes

Program Writes Data Reads Program Reads

Lowest: Fetches

(1)

(2)

SGUS062A–JUNE 2009–REVISED APRIL 2010

3.2.3 Peripheral Bus

To enable migration of peripherals between various Texas Instruments (TI) DSP families, the F2812 adopts a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of 16 address lines and 16 or 32 data lines and associated control signals. Two versions of the peripheral bus are supported on the F2812. One version only supports 16-bit accesses (called peripheral frame 2) and this retains compatibility with C240x-compatible peripherals. The other version supports both 16- and 32-bit accesses (called peripheral frame 1).

3.2.4 Real-Time JTAG and Analysis

The F2812 implement the standard IEEE 1149.1 JTAG interface. Additionally, the F2812 supports real-time mode of operation whereby the contents of memory, peripheral and register locations can be modified while the processor is running and executing code and servicing interrupts. The user can also

(1) Simultaneous Data and Program writes cannot occur on the Memory Bus. (2) Simultaneous Program Reads and Fetches cannot occur on the Memory Bus.

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single step through non-time critical code while enabling time-critical interrupts to be serviced without interference. The F2812 implements the real-time mode in hardware within the CPU. This is a unique feature to the F2812, no software monitor is required. Additionally, special analysis hardware is provided which allows the user to set hardware breakpoint or data/address watch-points and generate various user selectable break events when a match occurs.

3.2.5 External Interface (XINTF)

This asynchronous interface consists of 19 address lines, 16 data lines, and three chip-select lines. The chip-select lines are mapped to five external zones, Zones 0, 1, 2, 6, and 7. Zones 0 and 1 share a single chip-select; Zones 6 and 7 also share a single chip-select. Each of the five zones can be programmed with a different number of wait states, strobe signal setup and hold timing and each zone can be programmed for extending wait states externally or not. The programmable wait-state, chip-select, and programmable strobe timing enables glueless interface to external memories and peripherals.

3.2.6 Flash

The F2812 contains 128K × 16 of embedded flash memory, segregated into four 8K × 16 sectors, and six 16K × 16 sectors. The F2810 has 64K × 16 of embedded flash, segregated into two 8K × 16 sectors, and three 16K × 16 sectors. The device also contains a single 1K × 16 of OTP memory at address range 0x3D 7800 - 0x3D 7BFF. The user can individually erase, program, and validate a flash sector while leaving other sectors untouched. However, it is not possible to use one sector of the flash or the OTP to execute flash algorithms that erase/program other sectors. Special memory pipelining is provided to enable the flash module to achieve higher performance. The flash/OTP is mapped to both program and data space; therefore, it can be used to execute code or store data information.

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The F2812 Flash and OTP wait states can be configured by the application. This allows applications running at slower frequencies to configure the flash to use fewer wait states.

Flash effective performance can be improved by enabling the flash pipeline mode in the Flash options register. With this mode enabled, effective performance of linear code execution is much faster than the raw performance indicated by the wait state configuration alone. The exact performance gain when using the Flash pipeline mode is application-dependent. The pipeline mode is not available for the OTP block.

For more information on the Flash options, Flash wait-state, and OTP wait-state registers, see the TMS320x281x System Control and Interrupts Reference Guide (SPRU078).

3.2.7 L0, L1, H0 SARAMs

The F2812 contains an additional 16K × 16 of single-access RAM, divided into three blocks (4K + 4K + 8K). Each block can be independently accessed hence minimizing pipeline stalls. Each block is mapped to both program and data space.

3.2.8 Boot ROM

The Boot ROM is factory-programmed with boot-loading software. The Boot ROM program executes after device reset and checks several GPIO pins to determine which boot mode to enter. For example, the user can select to execute code already present in the internal Flash or download new software to internal RAM through one of several serial ports. Other boot modes exist as well. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use in math-related algorithms. Table 3-3 shows the details of how various boot modes may be invoked. See the TMS320x281x DSP Boot ROM Reference Guide (SPRS095), for more information.

NOTE

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Table 3-3. Boot Mode Selection

BOOT MODE SELECTED

GPIO PU status Jump to Flash/ROM address 0x3F 7FF6

A branch instruction must have been programmed here prior to 1 x x x reset to redirect code execution as desired.

Call SPI_Boot to load from an external serial SPI EEPROM 0 1 x x Call SCI_Boot to load from SCI-A 0 0 1 1 Jump to H0 SARAM address 0x3F 8000 0 0 1 0 Jump to OTP address 0x3D 7800 0 0 0 1 Call Parallel_Boot to load from GPIO Port B 0 0 0 0

(1) If the boot mode selected is Flash, H0, or OTP, then no external code is loaded by the bootloader. (2) Extra care must be taken due to any effect toggling SPICLK to select a boot mode may have on external logic. (3) PU = pin has an internal pullup. No PU = pin does not have an internal pullup

(3)

(1)

GPIOF4 GPIOF12 GPIOF3 GPIOF2

(SCITXDA) (MDXA) (SPISTEA) (SPICLK)

PU No PU No PU No PU

3.2.9 Security

The F2812 supports high levels of security to protect the user firmware from being reversed engineered. The security features a 128–bit password (hardcoded for 16 wait states), which the user programs into the flash. One code security module (CSM) is used to protect the flash/ROM/OTP and the L0/L1 SARAM blocks. The security feature prevents unauthorized users from examining the memory contents via the JTAG port, executing code from external memory or trying to boot–load some undesirable software that would export the secure memory contents. To enable access to the secure blocks, the user must write the correct 128–bit KEY value, which matches the value stored in the password locations within the Flash/ROM.

(2)

NOTE

For code security operation, all addresses between 0x3F7F80 and 0x3F7FF5 cannot be used as program code or data, but must be programmed to 0x0000 when the Code Security Passwords are programmed. If security is not a concern, then these addresses may be used for code or data.

The 128-bit password (at 0x3F 7FF8 – 0x3F 7FFF) must not be programmed to zeros. Doing so would permanently lock the device.

Code Security Module Disclaimer

The Code Security Module (CSM) included on this device was designed to password protect the data stored in the associated memory (either ROM or Flash) and is warranted by Texas Instruments (TI), in accordance with its standard terms and conditions, to conform to TI’s published specifications for the warranty period applicable for this device.

TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.

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IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.

3.2.10 Peripheral Interrupt Expansion (PIE) Block

The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block can support up to 96 peripheral interrupts. On the F2812, 45 of the possible 96 interrupts are used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is, supported by its own vector stored in a dedicated RAM block that can be overwritten by the user. The vector is, automatically fetched by the CPU on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can be enabled/disabled within the PIE block.

3.2.11 External Interrupts (XINT1, XINT2, XINT13, XNMI)

The F2812 supports three masked external interrupts (XINT1, 2, 13). XINT13 is combined with one non-masked external interrupt (XNMI). The combined signal name is XNMI_XINT13. Each of the interrupts can be selected for negative or positive edge triggering and can also be enabled/disabled (including the XNMI). The masked interrupts also contain a 16-bit free running up counter, which is reset to zero when a valid interrupt edge is detected. This counter can be used to accurately time stamp the interrupt.

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3.2.12 Oscillator and PLL

The F2812 can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit. A PLL is provided supporting up to 10-input clock-scaling ratios. The PLL ratios can be changed on-the-fly in software, enabling the user to scale back on operating frequency if lower power operation is desired. Refer to the Electrical Specification section for timing details. The PLL block can be set in bypass mode.

3.2.13 Watchdog

The F2812 supports a watchdog timer. The user software must regularly reset the watchdog counter within a certain time frame; otherwise, the watchdog generates a reset to the processor. The watchdog can be disabled if necessary.

3.2.14 Peripheral Clocking

The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption when a peripheral is not in use. Additionally, the system clock to the serial ports (except eCAN) and the event managers, CAP and QEP blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to be decoupled from increasing CPU clock speeds.

3.2.15 Low-Power Modes

The F2812 device is a full-static CMOS device. Three low-power modes are provided:

IDLE: Place CPU into low-power mode. Peripheral clocks may be turned off selectively

and only those peripherals that need to function during IDLE are left operating. An enabled interrupt from an active peripheral wakes the processor from IDLE mode.

STANDBY: Turn off clock to CPU and peripherals. This mode leaves the oscillator and PLL

functional. An external interrupt event wakes the processor and the peripherals. Execution begins on the next valid cycle after detection of the interrupt event.

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HALT: Turn off oscillator. This mode basically shuts down the device and places it in the

lowest possible power consumption mode. Only a reset or XNMI wakes the device from this mode.

3.2.16 Peripheral Frames 0, 1, 2 (PFn)

The F2812 segregates peripherals into three sections. The mapping of peripherals is as follows:

PF0: XINTF: External Interface Configuration Registers (2812 only)

PIE: PIE Interrupt Enable and Control Registers Plus PIE Vector Table Flash: Flash Control, Programming, Erase, Verify Registers Timers: CPU-Timers 0, 1, 2 Registers CSM: Code Security Module KEY Registers

PF1: eCAN: eCAN Mailbox and Control Registers PF2: SYS: System Control Registers

GPIO: GPIO Mux Configuration and Control Registers EV: Event Manager (EVA/EVB) Control Registers McBSP: McBSP Control and TX/RX Registers SCI: Serial Communications Interface (SCI) Control and RX/TX Registers SPI: Serial Peripheral Interface (SPI) Control and RX/TX Registers ADC: 12-Bit ADC Registers

SGUS062A–JUNE 2009–REVISED APRIL 2010

3.2.17 General-Purpose Input/Output (GPIO) Multiplexer

Most of the peripheral signals are multiplexed with general-purpose I/O (GPIO) signals. This enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, all GPIO pins are configured as inputs. The user can then individually program each pin for GPIO mode or Peripheral Signal mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter unwanted noise glitches.

3.2.18 32-Bit CPU Timers (0, 1, 2)

CPU Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The timers have a 32-bit count down register, which generates an interrupt when the counter reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU Timer 2 is reserved for Real-Time OS (RTOS)/BIOS applications. CPU Timer 1 is also reserved for TI system functions. CPU Timer 2 is connected to INT14 of the CPU. CPU Timer 1 can be connected to INT13 of the CPU. CPU Timer 0 is for general use and is connected to the PIE block.

3.2.19 Control Peripherals

The F2812 supports the following peripherals which are used for embedded control and communication:

EV: The event manager module includes general-purpose timers, full-compare/PWM units,

capture inputs (CAP) and quadrature-encoder pulse (QEP) circuits. Two such event managers are provided which enable two three-phase motors to be driven or four two-phase motors. The event managers on the F2812 is compatible to the event managers on the 240x devices (with some minor enhancements).

ADC: The ADC block is a 12-bit converter, single ended, 16-channels. It contains two

sample-and-hold units for simultaneous sampling.

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3.2.20 Serial Port Peripherals

The F2812 supports the following serial communication peripherals:

eCAN: This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time

stamping of messages, and is CAN 2.0B-compliant.

McBSP This is the multichannel buffered serial port that is used to connect to E1/T1 lines, : phone-quality codecs for modem applications or high-quality stereo-quality Audio DAC

devices. The McBSP receive and transmit registers are supported by a 16-level FIFO. This significantly reduces the overhead for servicing this peripheral.

SPI: The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of

programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the DSP controller and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multi-device communications are supported by the master/slave operation of the SPI. On the F2812, the port supports a 16-level receive and transmit FIFO for reducing servicing overhead.

SCI: The serial communications interface is a two-wire asynchronous serial port, commonly

known as UART. On the F2812, the port supports a 16-level receive and transmit FIFO for reducing servicing overhead.

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3.3 Register Map

The F2812 device contains three peripheral register spaces. The spaces are categorized as follows:

• Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus. See

Table 3-4.

• Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus. See

Table 3-5.

• Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See

Table 3-6.

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Table 3-4. Peripheral Frame 0 Registers

NAME ADDRESS RANGE SIZE (×16) ACCESS TYPE

Device Emulation Registers 384 EALLOW protected

reserved 128

FLASH Registers

Code Security Module Registers 16 EALLOW protected

reserved 48

XINTF Registers 32 Not EALLOW protected

reserved 192

CPU-TIMER0/1/2 Registers 64 Not EALLOW protected

reserved 160

PIE Registers 32 Not EALLOW protected

PIE Vector Table 256 EALLOW protected

Reserved 512

(1) Registers in Frame 0 support 16-bit and 32-bit accesses. (2) If registers are EALLOW protected, then writes cannot be performed until the user executes the EALLOW instruction. The EDIS

instruction disables writes. This prevents stray code or pointers from corrupting register contents.

(3) The Flash Registers are also protected by the Code Security Module (CSM).

(3)

0x00 0880

0x00 09FF 0x00 0A00

0x00 0A7F 0x00 0A80 EALLOW protected

0x00 0ADF CSM Protected 0x00 0AE0

0x00 0AEF 0x00 0AF0

0x00 0B1F 0x00 0B20

0x00 0B3F 0x00 0B40

0x00 0BFF 0x00 0C00

0x00 0C3F 0x00 0C40

0x00 0CDF 0x00 0CE0

0x00 0CFF

0x00 0D00

0x00 0DFF

0x00 0E00 0x00 0FFF

SGUS062A–JUNE 2009–REVISED APRIL 2010

(1)

(2)

Table 3-5. Peripheral Frame 1 Registers

NAME ADDRESS RANGE SIZE (×16) ACCESS TYPE

eCAN Registers

eCAN Mailbox RAM Not EALLOW-protected

reserved 3584

(1) The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries.

0x00 6000 256 Some eCAN control registers (and selected bits in

0x00 60FF (128 × 32) other eCAN control registers) are EALLOW-protected.

0x00 6100 256

0x00 61FF (128 × 32)

0x00 6200

0x00 6FFF

(1)

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Table 3-6. Peripheral Frame 2 Registers

NAME ADDRESS RANGE SIZE (×16) ACCESS TYPE

reserved 16

System Control Registers 32 EALLOW Protected

reserved 16

SPI-A Registers 16 Not EALLOW Protected

SCI-A Registers 16 Not EALLOW Protected

reserved 16

External Interrupt Registers 16 Not EALLOW Protected

reserved 64

GPIO Mux Registers 32 EALLOW Protected

GPIO Data Registers 32 Not EALLOW Protected

ADC Registers 32 Not EALLOW Protected

reserved 736

EV-A Registers 64 Not EALLOW Protected

reserved 192

EV-B Registers 64 Not EALLOW Protected

reserved 528

SCI-B Registers 16 Not EALLOW Protected

reserved 160

McBSP Registers 64 Not EALLOW Protected

reserved 1984

(1) Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written).

0x00 7000 0x00 700F

0x00 7010 0x00 702F

0x00 7030 0x00 703F

0x00 7040 0x00 704F

0x00 7050 0x00 705F

0x00 7060 0x00 706F

0x00 7070 0x00 707F

0x00 7080

0x00 70BF 0x00 70C0

0x00 70DF 0x00 70E0

0x00 70FF

0x00 7100 0x00 711F

0x00 7120

0x00 73FF

0x00 7400 0x00 743F

0x00 7440

0x00 74FF

0x00 7500 0x00 753F

0x00 7540 0x00 774F

0x00 7750 0x00 775F

0x00 7760

0x00 77FF

0x00 7800 0x00 783F

0x00 7840

0x00 7FFF

(1)

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3.4 Device Emulation Registers

These registers are used to control the protection mode of the C28x CPU and to monitor some critical device signals. The registers are defined in Table 3-7.

Table 3-7. Device Emulation Registers

NAME ADDRESS RANGE SIZE (×16) DESCRIPTION

DEVICECNF 2 Device Configuration Register reserved 0x00 0882 1 Not supported on Revision C and later silicon

DEVICEID 0x00 0883 1 Device ID Register (0x0004 – Reserved)

PROTSTART 0x00 0884 1 Block Protection Start Address Register PROTRANGE 0x00 0885 1 Block Protection Range Address Register

reserved 378

0x00 0880 0x00 0881

Device ID Register (0x0003 – Silicon – Rev. C and D) Device ID Register (0x0005 – Silicon – Rev. E)

0x00 0886

0x00 09FF

3.5 External Interface, XINTF

This section gives a top-level view of the external interface (XINTF) that is implemented on the F2812 device.

The external interface is a non-multiplexed asynchronous bus, similar to the C240x external interface. The external interface on the F2812 is mapped into five fixed zones shown in Figure 3-3.

Figure 3-3 shows the F2812 XINTF signals.

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XD(15:0)

XA(18:0)

XZCS6

XZCS7

XZCS6AND7

XZCS2

XWE

XR/W XREADY XMP/MC

XHOLD XHOLDA XCLKOUT

XRD

XINTF Zone 0

(8K × 16)

XINTF Zone 1

(8K × 16)

XINTF Zone 6

(512K × 16)

XINTF Zone 7

(16K × 16)

(mapped here if MP/MC

= 1)

0x40 0000

0x3F C000

0x18 0000

0x10 0000

0x00 6000

0x00 4000

0x00 2000

0x00 0000

Data Space Prog Space

XINTF Zone 2

(512K × 16)

0x08 0000

XZCS0AND1

XZCS0 XZCS1

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A. The mapping of XINTF Zone 7 is dependent on the XMP/MC device input signal and the MP/MC mode bit (bit 8 of

XINTCNF2 register). Zones 0, 1, 2, and 6 are always enabled.

B. Each zone can be programmed with different wait states, setup and hold timing, and is supported by zone chip

selects (XZCS0AND1, XZCS2, XZCS6AND7), which toggle when an access to a particular zone is performed. These features enable glueless connection to many external memories and peripherals.

C. The chip selects for Zone 0 and 1 are ANDed internally together to form one chip select (XZCS0AND1). Any external

memory that is connected to XZCS0AND1 is dually mapped to both Zones 0 and Zone 1.

D. The chip selects for Zone 6 and 7 are ANDed internally together to form one chip select (XZCS6AND7). Any external

memory that is connected to XZCS6AND7 is dually mapped to both Zones 6 and Zone 7. This means that if Zone 7 is disabled (via the MP/MC mode) then any external memory is still accessible via Zone 6 address space.

Figure 3-3. External Interface Block Diagram

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The operation and timing of the external interface, can be controlled by the registers listed in Table 3-8.

Table 3-8. XINTF Configuration and Control Register Mappings

NAME ADDRESS SIZE (×16) DESCRIPTION

XTIMING0 0x00 0B20 2

XTIMING1 0x00 0B22 2

XTIMING2 0x00 0B24 2

XTIMING6 0x00 0B2C 2

XTIMING7 0x00 0B2E 2

XINTCNF2 0x00 0B34 2 XBANK 0x00 0B38 1 XINTF Bank Control Register

XREVISION 0x00 0B3A 1 XINTF Revision Register

XINTF Timing Register, Zone 0 can access as two 16-bit registers or one 32-bit register

XINTF Timing Register, Zone 1 can access as two 16-bit registers or one 32-bit register

XINTF Timing Register, Zone 2 can access as two 16-bit registers or one 32-bit register

XINTF Timing Register, Zone 6 can access as two 16-bit registers or one 32-bit register

XINTF Timing Register, Zone 7 can access as two 16-bit registers or one 32-bit register

XINTF Configuration Register can access as two 16-bit registers or one 32-bit register

3.5.1 Timing Registers

XINTF signal timing can be tuned to match specific external device requirements such as setup and hold times to strobe signals for contention avoidance and maximizing bus efficiency. The timing parameters can be configured individually for each zone. This allows the programmer to maximize the efficiency of the bus, based on the type of memory or peripheral that the user needs to access. All XINTF timing values are with respect to XTIMCLK, which is equal to or one-half of the SYSCLKOUT rate, as shown in Figure 6-27.

SGUS062A–JUNE 2009–REVISED APRIL 2010

For detailed information on the XINTF timing and configuration register bit fields, see the TMS320x281x DSP External Interface (XINTF) Reference Guide (SPRU067).

3.5.2 XREVISION Register

The XREVISION register contains a unique number to identify the particular version of XINTF used in the product. For the F2812, this register is configured as described in Table 3-9.

Table 3-9. XREVISION Register Bit Definitions

BIT(S) NAME TYPE RESET DESCRIPTION

15-0 REVISION R 0x0004

Current XINTF Revision. For internal use/reference. Test purposes only. Subject to change.

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C28x CPU

PIE

TIMER 2 (for RTOS)

TIMER 0

Watchdog

Peripherals (SPI, SCI, McBSP, CAN, EV, ADC)

(41 Interrupts)

96 Interrupts

†

TINT0

Interrupt Control

XNMICR(15:0)

XINT1

Interrupt Control

XINT1CR(15:0)

XINT2

Interrupt Control

XINT2CR(15:0)

GPIO

MUX

WDINT

INT1 to INT12

INT13

INT14

NMI

XINT1CTR(15:0)

XINT2CTR(15:0)

XNMICTR(15:0)

TIMER 1 (for RTOS)

TINT2

Low-Power Modes

LPMINT

WAKEINT

XNMI_XINT13

MUX

TINT1

enable

select

†

Out of a possible 96 interrupts, 45 are currently used by peripherals.

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3.6 Interrupts

Figure 3-4 shows how the various interrupt sources are multiplexed within the F2812 device.

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Figure 3-4. Interrupt Sources

Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts per group equals 96 possible interrupts. On the F2812, 45 of these are used by peripherals as shown in Table 3-10.

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INT12

MUX

INT11

INT2

INT1

CPU

(Enable)(Flag)

INTx

INTx.8

PIEIERx(8:1) PIEIFRx(8:1)

MUX

INTx.7

INTx.6

INTx.5

INTx.4

INTx.3

INTx.2

INTx.1

From

Peripherals or

External

Interrupts

(Enable) (Flag)

IER(12:1)IFR(12:1)

Global

Enable

INTM

PIEACKx

(Enable/Flag)

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Figure 3-5. Multiplexing of Interrupts Using the PIE Block

Table 3-10. PIE Peripheral Interrupts

CPU

INTERRUPTS

INT1 XINT2 XINT1 reserved

INT2 reserved

INT3 reserved

INT4 reserved

INT5 reserved

INT6 reserved reserved reserved reserved INT7 reserved reserved reserved reserved reserved reserved reserved reserved

INT8 reserved reserved reserved reserved reserved reserved reserved reserved INT9 reserved reserved

INT10 reserved reserved reserved reserved reserved reserved reserved reserved INT11 reserved reserved reserved reserved reserved reserved reserved reserved INT12 reserved reserved reserved reserved reserved reserved reserved reserved

(1) Out of the 96 possible interrupts, 45 interrupts are currently used. the remaining interrupts are reserved for future devices. However,

these interrupts can be used as software interrupts if they are enabled at the PIEIFRx level.

INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1

WAKEINT TINT0 ADCINT PDPINTB PDPINTA

(LPM/WD) (TIMER 0) (ADC) (EV-B) (EV-A)

T1OFINT T1UFINT T1CINT T1PINT CMP3INT CMP2INT CMP1INT

(EV-A) (EV-A) (EV-A) (EV-A) (EV-A) (EV-A) (EV-A)

CAPINT3 CAPINT2 CAPINT1 T2OFINT T2UFINT T2CINT T2PINT

(EV-A) (EV-A) (EV-A) (EV-A) (EV-A) (EV-A) (EV-A)

T3OFINT T3UFINT T3CINT T3PINT CMP6INT CMP5INT CMP4INT

(EV-B) (EV-B) (EV-B) (EV-B) (EV-B) (EV-B) (EV-B)

CAPINT6 CAPINT5 CAPINT4 T4OFINT T4UFINT T4CINT T4PINT

(EV-B) (EV-B) (EV-B) (EV-B) (EV-B) (EV-B) (EV-B)

MXINT MRINT SPITXINTA SPIRXINTA

(McBSP) (McBSP) (SPI) (SPI)

ECAN1INT ECAN0INT SCITXINTB SCIRXINTB SCITXINTA SCIRXINTA

(CAN) (CAN) (SCI-B) (SCI-B) (SCI-A) (SCI-A)

PIE INTERRUPTS

(1)

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Table 3-11. PIE Configuration and Control Registers

NAME ADDRESS SIZE (×16) DESCRIPTION

PIECTRL 0x0000-0CE0 1 PIE, Control Register PIEACK 0x0000-0CE1 1 PIE, Acknowledge Register PIEIER1 0x0000-0CE2 1 PIE, INT1 Group Enable Register PIEIFR1 0x0000-0CE3 1 PIE, INT1 Group Flag Register PIEIER2 0x0000-0CE4 1 PIE, INT2 Group Enable Register PIEIFR2 0x0000-0CE5 1 PIE, INT2 Group Flag Register PIEIER3 0x0000-0CE6 1 PIE, INT3 Group Enable Register PIEIFR3 0x0000-0CE7 1 PIE, INT3 Group Flag Register PIEIER4 0x0000-0CE8 1 PIE, INT4 Group Enable Register PIEIFR4 0x0000-0CE9 1 PIE, INT4 Group Flag Register PIEIER5 0x0000-0CEA 1 PIE, INT5 Group Enable Register PIEIFR5 0x0000-0CEB 1 PIE, INT5 Group Flag Register PIEIER6 0x0000-0CEC 1 PIE, INT6 Group Enable Register PIEIFR6 0x0000-0CED 1 PIE, INT6 Group Flag Register PIEIER7 0x0000-0CEE 1 PIE, INT7 Group Enable Register PIEIFR7 0x0000-0CEF 1 PIE, INT7 Group Flag Register PIEIER8 0x0000-0CF0 1 PIE, INT8 Group Enable Register PIEIFR8 0x0000-0CF1 1 PIE, INT8 Group Flag Register PIEIER9 0x0000-0CF2 1 PIE, INT9 Group Enable Register PIEIFR9 0x0000-0CF3 1 PIE, INT9 Group Flag Register PIEIER10 0x0000-0CF4 1 PIE, INT10 Group Enable Register PIEIFR10 0x0000-0CF5 1 PIE, INT10 Group Flag Register PIEIER11 0x0000-0CF6 1 PIE, INT11 Group Enable Register PIEIFR11 0x0000-0CF7 1 PIE, INT11 Group Flag Register PIEIER12 0x0000-0CF8 1 PIE, INT12 Group Enable Register PIEIFR12 0x0000-0CF9 1 PIE, INT12 Group Flag Register

Reserved 6 Reserved

(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table is protected.

0x0000-0CFA 0x0000-0CFF

(1)

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3.6.1 External Interrupts

Table 3-12. External Interrupts Registers

NAME ADDRESS SIZE (×16) DESCRIPTION

XINT1CR 0x00 7070 1 XINT1 control register XINT2CR 0x00 7071 1 XINT2 control register

reserved 5 XNMICR 0x00 7077 1 XNMI control register

XINT1CTR 0x00 7078 1 XINT1 counter register XINT2CTR 0x00 7079 1 XINT2 counter register

reserved 5 XNMICTR 0x00 707F 1 XNMI counter register

Each external interrupt can be enabled/disabled or qualified using positive or negative going edge. For more information, see the TMS320x281x System Control and Interrupts Reference Guide (SPRU078).

0x00 7072 0x00 7076

0x00 707A 0x00 707E

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3.7 System Control

This section describes the F2812 oscillator, PLL and clocking mechanisms, the watchdog function and the low power modes. Figure 3-6 shows the various clock and reset domains in the F2812 device that are discussed.

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A. CLKIN is the clock input to the CPU. SYSCLKOUT is the output clock of the CPU. They are of the same frequency.

Figure 3-6. Clock and Reset Domains

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The PLL, clocking, watchdog, and low-power modes are controlled by the registers listed in Table 3-13.

Table 3-13. PLL, Clocking, Watchdog, and Low-Power Mode Registers

NAME ADDRESS SIZE (×16) DESCRIPTION

reserved 8 reserved 0x00 7018 1

reserved 0x00 7019 1 HISPCP 0x00 701A 1 High-Speed Peripheral Clock Prescaler Register for HSPCLK clock LOSPCP 0x00 701B 1 Low-Speed Peripheral Clock Prescaler Register for LSPCLK clock PCLKCR 0x00 701C 1 Peripheral Clock Control Register reserved 0x00 701D 1 LPMCR0 0x00 701E 1 Low Power Mode Control Register 0 LPMCR1 0x00 701F 1 Low Power Mode Control Register 1 reserved 0x00 7020 1 PLLCR 0x00 7021 1 PLL Control Register SCSR 0x00 7022 1 System Control & Status Register WDCNTR 0x00 7023 1 Watchdog Counter Register reserved 0x00 7024 1 WDKEY 0x00 7025 1 Watchdog Reset Key Register

reserved 3 WDCR 0x00 7029 1 Watchdog Control Register reserved 6

(1) All of the above registers can only be accessed by executing the EALLOW instruction. (2) The PLL control register (PLLCR) is reset to a known state by the XRS signal only. Emulation reset (through Code Composer Studio)

does not reset PLLCR.

0x00 7010 0x00 7017

(2)

0x00 7026 0x00 7028

0x00 702A 0x00 702F

(1)

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X1/XCLKIN

On-Chip

Oscillator

(OSC)

PLL

Bypass

XF_XPLLDIS

OSCCLK (PLL Disabled)

Latch

XPLLDIS

XRS

PLL

4-Bit PLL Select

SYSCLKOUT

CLKIN

CPU

4-Bit PLL Select

XCLKIN

PLL Block

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3.8 OSC and PLL Block

Figure 3-7 shows the OSC and PLL block on the F2812.

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Figure 3-7. OSC and PLL Block

The on-chip oscillator circuit enables a crystal to be attached to the F2812 device using the X1/XCLKIN and X2 pins. If a crystal is not used, then an external oscillator can be directly connected to the X1/XCLKIN pin and the X2 pin is left unconnected. The logic-high level in this case should not exceed VDD. The PLLCR bits [3:0] set the clocking ratio.

Table 3-14. PLLCR Register Bit Definitions

(1)

SYSCLKOUT = (XCLKIN x n)/2, where n is the PLL multiplication factor.

Bit Value n SYSCLKOUT

0000 PLL Bypassed XCLKIN/2 0001 1 XCLKIN/2 0010 2 XCLKIN 0011 3 XCLKIN × 1.5 0100 4 XCLKIN × 2 0101 5 XCLKIN × 2.5 0110 6 XCLKIN × 3 0111 7 XCLKIN × 3.5 1000 8 XCLKIN × 4 1001 9 XCLKIN × 4.5 1010 10 XCLKIN × 5 1011 11 Reserved 1100 12 Reserved 1101 13 Reserved 1110 14 Reserved 1111 15 Reserved

DESCRIPTION

BIT(S) NAME TYPE XRS RESET

15:04 reserved R = 0 0:00

3:00 DIV R/W 0,0,0,0

(1) The PLLCR register is reset to a known state by the XRS reset line. If a reset is issued by the debugger, the PLL clocking ratio is not

changed.

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External Clock Signal

(Toggling 0−VDD)

(see Note A)

X2X1/XCLKIN X1/XCLKIN X2

Crystal

(see Note A)

(a) (b)

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3.8.1 Loss of Input Clock

In PLL enabled mode, if the input clock XCLKIN or the oscillator clock is removed or absent, the PLL still issues a limp-mode clock. The limp-mode clock continues to clock the CPU and peripherals at a typical frequency of 1 MHz to 4 MHz. The PLLCR register should have been written to with a non-zero value for this feature to work.

Normally, when the input clocks are present, the watchdog counter decrements to initiate a watchdog reset or WDINT interrupt. However, when the external input clock fails, the watchdog counter stops decrementing (i.e., the watchdog counter does not change with the limp-mode clock). This condition could be used by the application firmware to detect the input clock failure and initiate necessary shut-down procedure for the system.

3.9 PLL-Based Clock Module

The F2812 has an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control to select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes 131 072 XCLKIN cycles.

The PLL-based clock module provides two modes of operation:

• Crystal operation This mode allows the use of an external crystal/resonator to provide the time base to the device.

• External clock source operation This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external clock source input on the X1/XCLKIN pin.

SGUS062A–JUNE 2009–REVISED APRIL 2010

A. TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the

DSP chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding the proper tank component values that ensures start-up and stability over the entire operating range.

Figure 3-8. Recommended Crystal/Clock Connection

Table 3-15. Possible PLL Configuration Modes

PLL MODE REMARKS SYSCLKOUT

PLL Disabled XCLKIN

PLL Bypassed However, the /2 module in the PLL block divides the clock input at the X1/XCLKIN pin by XCLKIN/2

PLL Enabled (XCLKIN × n) / 2

Invoked by tying XPLLDIS pin low upon reset. PLL block is completely disabled. Clock input to the CPU (CLKIN) is directly derived from the clock signal present at the X1/XCLKIN pin.

Default PLL configuration upon power-up, if PLL is not disabled. The PLL itself is bypassed. two before feeding it to the CPU.

Achieved by writing a non-zero value n into PLLCR register. The /2 module in the PLL block now divides the output of the PLL by two before feeding it to the CPU.

3.10 External Reference Oscillator Clock Option

The typical specifications for the external quartz crystal for a frequency of 30 MHz are listed below:

• Fundamental mode, parallel resonant

• CL(load capacitance) = 12 pF

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/512

OSCCLK

WDCR (WDPS(2:0))

WDCLK

WDCNTR(7:0)

WDKEY(7:0)

Bad Key

Good Key

1 0 1

WDCR (WDCHK(2:0))

Bad WDCHK Key

WDCR (WDDIS)

Clear Counter

SCSR (WDENINT)

Watchdog

Prescaler

Generate

Output Pulse

(512 OSCCLKs)

8-Bit

Watchdog

Counter

CLR

WDRST

WDINT

Watchdog

55 + AA

Key Detector

XRS

Core-reset

WDRST

(See Note A)

Internal

Pullup

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• CL1= CL2= 24 pF

• C

shunt

= 6 pF

• ESR range = 25 to 40 Ω

3.11 Watchdog Block

The watchdog block on the F2812 is identical to the one used on the 240x devices. The watchdog module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter has reached its maximum value. To prevent this, the user disables the counter or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register which resets the watchdog counter. Figure 3-9 shows the various functional blocks within the watchdog module.

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A. The WDRST signal is driven low for 512 OSCCLK cycles.

The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode timer. In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains

Figure 3-9. Watchdog Module

functional is the watchdog. The WATCHDOG module runs off the PLL clock or the oscillator clock. The WDINT signal is fed to the LPM block so that it can wake the device from STANDBY (if enabled). See Section 3.12, Low-Power Modes Block, for more details.

In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of IDLE mode.

In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so is the WATCHDOG.

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3.12 Low-Power Modes Block

The low-power modes on the F2812 are similar to the 240x devices. Table 3-16 summarizes the various modes.

Table 3-16. F2812 Low-Power Modes

MODE LPM(1:0) OSCCLK CLKIN SYSCLKOUT EXIT

Normal X,X on on on –

IDLE 0,0 on on on

STANDBY 0,1 off off

HALT 1,X (oscillator and PLL turned off, off off XNMI,

(1) The Exit column lists which signals or under what conditions the low power mode is exited. A low signal, on any of the signals, exits the

low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the IDLE mode is not exited and the device goes back into the indicated low power mode.

(2) The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the core (SYSCLKOUT) is

still functional while on the 24x/240x the clock is turned off. (3) On the C28x, the JTAG port can still function even if the core clock (CLKIN) is turned off. (4) On the C28x, the JTAG port can still function even if the core clock (CLKIN) is turned off.

(watchdog still running) C1/2/3/4/5/6TRIP,

watchdog not functional) Debugger

on T1/2/3/4CTRIP,

off XRS,

(2)

Any Enabled Interrupt,

(1)

XRS,

WDINT,

XNMI

Debugger

XRS,

WDINT,

XINT1,

XNMI,

SCIRXDA, SCIRXDB,

CANRX,

Debugger

(3)

(4)

The various low-power modes operate as follows:

IDLE Mode: This mode is exited by any enabled interrupt or an XNMI that is recognized

by the processor. The LPM block performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0,0.

STANDBY Mode: All other signals (including XNMI) wake the device from STANDBY mode if

selected by the LPMCR1 register. The user needs to select which signal(s) wakes the device. The selected signal(s) are also qualified by the OSCCLK before waking the device. The number of OSCCLKs is specified in the LPMCR0 register.

HALT Mode: Only the XRS and XNMI external signals can wake the device from HALT

mode. The XNMI input to the core has an enable/disable bit. Hence, it is safe to use the XNMI signal for this function.

NOTE

The low-power modes do not affect the state of the output pins (PWM pins included). They are in whatever state the code left them in when the IDLE instruction was executed.

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Borrow

Reset

Timer Reload

SYSCLKOUT

TCR.4

(Timer Start Status)

TINT

16-Bit Timer Divide-Down

TDDRH:TDDR

32-Bit Timer Period

PRDH:PRD

32-Bit Counter

TIMH:TIM

16-Bit Prescale Counter

PSCH:PSC

Borrow

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SGUS062A–JUNE 2009–REVISED APRIL 2010

4 Peripherals

The integrated peripherals of the F2812 are described in the following subsections:

• Three 32-bit CPU-Timers

• Two event-manager modules (EVA, EVB)

• Enhanced analog-to-digital converter (ADC) module

• Enhanced controller area network (eCAN) module

• Multichannel buffered serial port (McBSP) module

• Serial communications interface modules (SCI-A, SCI-B)

• Serial peripheral interface (SPI) module

• Digital I/O and shared pin functions

4.1 32-Bit CPU-Timers 0/1/2

There are three 32-bit CPU-timers on the F2812 devices (CPU-TIMER0/1/2). CPU-Timers 1 and 2 are reserved for the real-time OS (such as DSP/BIOS). CPU-Timer 0 can be used in

user applications. These timers are different from the general-purpose (GP) timers that are present in the Event Manager modules (EVA, EVB).

If the application is not using DSP/BIOS, then CPU-Timers 1 and 2 can be used in the application.

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NOTE

Figure 4-1. CPU-Timers

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INT1

INT12

INT14

C28x

TINT2

TINT0

PIE

CPU-TIMER 0

CPU-TIMER 2

(Reserved for TI

system functions)

INT13

TINT1

CPU-TIMER 1

(Reserved for TI

system functions)

XINT13

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In the F2812 device, the timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in

Figure 4-2.

A. The timer registers are connected to the Memory Bus of the C28x processor. B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock.

Figure 4-2. CPU-Timer Interrupts Signals and Output Signal (See Notes A. and B.)

SGUS062A–JUNE 2009–REVISED APRIL 2010

The general operation of the timer is as follows: The 32-bit counter register TIMH:TIM is loaded with the value in the period register PRDH:PRD. The counter register, decrements at the SYSCLKOUT rate of the C28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed in Table 4-1 are used to configure the timers. For more information, see the TMS320x281x System Control and Interrupts Reference Guide (literature number SPRU078).

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Table 4-1. CPU-Timers 0, 1, 2 Configuration and Control Registers

NAME ADDRESS SIZE (×16) DESCRIPTION

TIMER0TIM 0x00 0C00 1 CPU-Timer 0, Counter Register TIMER0TIMH 0x00 0C01 1 CPU-Timer 0, Counter Register High TIMER0PRD 0x00 0C02 1 CPU-Timer 0, Period Register TIMER0PRDH 0x00 0C03 1 CPU-Timer 0, Period Register High TIMER0TCR 0x00 0C04 1 CPU-Timer 0, Control Register reserved 0x00 0C05 1 TIMER0TPR 0x00 0C06 1 CPU-Timer 0, Prescale Register TIMER0TPRH 0x00 0C07 1 CPU-Timer 0, Prescale Register High TIMER1TIM 0x00 0C08 1 CPU-Timer 1, Counter Register TIMER1TIMH 0x00 0C09 1 CPU-Timer 1, Counter Register High TIMER1PRD 0x00 0C0A 1 CPU-Timer 1, Period Register TIMER1PRDH 0x00 0C0B 1 CPU-Timer 1, Period Register High TIMER1TCR 0x00 0C0C 1 CPU-Timer 1, Control Register reserved 0x00 0C0D 1 TIMER1TPR 0x00 0C0E 1 CPU-Timer 1, Prescale Register TIMER1TPRH 0x00 0C0F 1 CPU-Timer 1, Prescale Register High TIMER2TIM 0x00 0C10 1 CPU-Timer 2, Counter Register TIMER2TIMH 0x00 0C11 1 CPU-Timer 2, Counter Register High TIMER2PRD 0x00 0C12 1 CPU-Timer 2, Period Register TIMER2PRDH 0x00 0C13 1 CPU-Timer 2, Period Register High TIMER2TCR 0x00 0C14 1 CPU-Timer 2, Control Register reserved 0x00 0C15 1 TIMER2TPR 0x00 0C16 1 CPU-Timer 2, Prescale Register TIMER2TPRH 0x00 0C17 1 CPU-Timer 2, Prescale Register High

reserved 40

0x00 0C18

0x00 0C3F

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4.2 Event Manager Modules (EVA, EVB)

The event-manager modules include general-purpose (GP) timers, full-compare/PWM units, capture units, and quadrature-encoder pulse (QEP) circuits. EVA and EVB timers, compare units, and capture units function identically. However, timer/unit names differ for EVA and EVB. Table 4-2 shows the module and signal names used. Table 4-2 shows the features and functionality available for the event-manager modules and highlights EVA nomenclature.

Event managers A and B have identical peripheral register sets with EVA starting at 7400h and EVB starting at 7500h. The paragraphs in this section describe the function of GP timers, compare units, capture units, and QEPs using EVA nomenclature. These paragraphs are applicable to EVB with regard to function—however, module/signal names would differ. Table 4-3 lists the EVA registers. For more information, see the TMS320x281x DSP Event Manager (EV) Reference Guide (literature number SPRU065).

Table 4-2. Module and Signal Names for EVA and EVB

EVENT MANAGER MODULES

GP Timers

Compare Units Compare 2 PWM3/4 Compare 5 PWM9/10

Capture Units Capture 2 CAP2 Capture 5 CAP5

QEP Channels QEP2 QEP4

External Clock Inputs

External Trip Inputs Compare C2TRIP Compare C5TRIP

External Trip Inputs

(1) In the 24x/240x-compatible mode, the T1CTRIP_PDPINTA pin functions as PDPINTA and the T3CTRIP_PDPINTB pin functions as

PDPINTB.

MODULE SIGNAL MODULE SIGNAL

GP Timer 1 T1PWM/T1CMP GP Timer 3 T3PWM/T3CMP GP Timer 2 T2PWM/T2CMP GP Timer 4 T4PWM/T4CMP

Compare 1 PWM1/2 Compare 4 PWM7/8 Compare 3 PWM5/6 Compare 6 PWM11/12

Capture 1 CAP1 Capture 4 CAP4 Capture 3 CAP3 Capture 6 CAP6

QEP1 QEP3

QEPI1 QEPI2

Direction TDIRA Direction TDIRB

External Clock TCLKINA External Clock TCLKINB

EVA EVB

QEP1 QEP3 QEP2 QEP4

C1TRIP C4TRIP C3TRIP C6TRIP

T1CTRIP_PDPINTA

T2CTRIP/EVASOC

(1)

T3CTRIP_PDPINTB

T4CTRIP/EVBSOC

(1)

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Table 4-3. EVA Registers

NAME ADDRESS SIZE (×16) DESCRIPTION

GPTCONA 0x00 7400 1 GP Timer Control Register A

T1CNT 0x00 7401 1 GP Timer 1 Counter Register

T1CMPR 0x00 7402 1 GP Timer 1 Compare Register

T1PR 0x00 7403 1 GP Timer 1 Period Register

T1CON 0x00 7404 1 GP Timer 1 Control Register

T2CNT 0x00 7405 1 GP Timer 2 Counter Register

T2CMPR 0x00 7406 1 GP Timer 2 Compare Register

T2PR 0x00 7407 1 GP Timer 2 Period Register

T2CON 0x00 7408 1 GP Timer 2 Control Register

EXTCONA

COMCONA 0x00 7411 1 Compare Control Register A

ACTRA 0x00 7413 1 Compare Action Control Register A

DBTCONA 0x00 7415 1 Dead–Band Timer Control Register A

CMPR1 0x00 7417 1 Compare Register 1 CMPR2 0x00 7418 1 Compare Register 2

CMPR3 0x00 7419 1 Compare Register 3 CAPCONA 0x00 7420 1 Capture Control Register A CAPFIFOA 0x00 7422 1 Capture FIFO Status Register A CAP1FIFO 0x00 7423 1 Two-Level Deep Capture FIFO Stack 1 CAP2FIFO 0x00 7424 1 Two-Level Deep Capture FIFO Stack 2 CAP3FIFO 0x00 7425 1 Two–Level Deep Capture FIFO Stack 3

CAP1FBOT 0x00 7427 1 Bottom Register Of Capture FIFO Stack 1 CAP2FBOT 0x00 7428 1 Bottom Register Of Capture FIFO Stack 2 CAP3FBOT 0x00 7429 1 Bottom Register Of Capture FIFO Stack 3

EVAIMRA 0x00 742C 1 Interrupt Mask Register A EVAIMRB 0x00 742D 1 Interrupt Mask Register B EVAIMRC 0x00 742E 1 Interrupt Mask Register C

EVAIFRA 0x00 742F 1 Interrupt Flag Register A EVAIFRB 0x00 7430 1 Interrupt Flag Register B EVAIFRC 0x00 7431 1 Interrupt Flag Register C

(1) The EV-B register set is identical except the address range is from 0x00–7500 to 0x00–753F. The above registers are mapped to Zone

2. This space allows only 16-bit accesses. 32-bit accesses produce undefined results.

(2) New register compared to 24x/240x

(2)

0x00 7409 1 GP Extension Control Register A

(1)

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GPTCONA(12:4), CAPCONA(8), EXTCONA[0]

EVATO ADC (Internal)

Timer 1 Compare

Output

Logic

T1PWM_T1CMP

GPTCONA(1,0)

T1CON(1)

GP Timer 1

TCLKINA

Prescaler

HSPCLK

T1CON(10:8)

T1CON(5,4)

clock

Full Compare 1

Full Compare 2

Full Compare 3

SVPWM

State

Machine

Dead

Band

Logic

Output

Logic

PWM1 PWM2 PWM3

PWM4 PWM5 PWM6

T1CON(15:11,6,3,2)

TDIRA

dir

Timer 2 Compare

GP Timer 2

Capture Units

COMCONA(15:5,2:0)

T1CTRIP/PDPINTA, T2CTRIP, C1TRIP, C2TRIP, C3TRIP

Output

Logic

T2PWM_T2CMP

GPTCONA(3,2)

T2CON(1)

T2CON(15:11,7,6,3,2,0)

ACTRA(15:12),

COMCONA(12),

T1CON(13:11)

CAPCONA(10,9)

DBTCONA(15:0)

ACTRA(11:0)

TCLKINA

Prescaler

HSPCLK

T2CON(10:8)

T2CON(5,4)

clock dir

CAPCONA(15:12,7:0)

CAP1_QEP1 CAP2_QEP2

CAP3_QEPI1

QEP

Logic

QEPCLK

QEPDIR

reset

EVAENCLK

Control Logic

Peripheral Bus

TDIRA

Index Qual

EXTCONA(1:2)

EVASOC ADC (External)

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A. The EVB module is similar to the EVA module.

Figure 4-3. Event Manager A Functional Block Diagram (See Note A.)

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4.2.1 General-Purpose (GP) Timers

There are two GP timers. The GP timer x (x = 1 or 2 for EVA; x = 3 or 4 for EVB) includes:

• A 16-bit timer, up-/down-counter, TxCNT, for reads or writes

• A 16-bit timer-compare register, TxCMPR (double-buffered with shadow register), for reads or writes

• A 16-bit timer-period register, TxPR (double-buffered with shadow register), for reads or writes

• A 16-bit timer-control register, TxCON, for reads or writes

• Selectable internal or external input clocks

• A programmable prescaler for internal or external clock inputs

• Control and interrupt logic, for four maskable interrupts: underflow, overflow, timer compare, and period

interrupts

• A selectable direction input pin (TDIRx) (to count up or down when directional up- / down-count mode is selected)

The GP timers can be operated independently or synchronized with each other. The compare register associated with each GP timer can be used for compare function and PWM-waveform generation. There are three continuous modes of operations for each GP timer in up- or up / down-counting operations. Internal or external input clocks with programmable prescaler are used for each GP timer. GP timers also provide the time base for the other event-manager submodules: GP timer 1 for all the compares and PWM circuits, GP timer 2/1 for the capture units and the quadrature-pulse counting operations. Double-buffering of the period and compare registers allows programmable change of the timer (PWM) period and the compare/PWM pulse width as needed.

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4.2.2 Full-Compare Units

There are three full-compare units on each event manager. These compare units use GP timer1 as the time base and generate six outputs for compare and PWM-waveform generation using programmable deadband circuit. The state of each of the six outputs is configured independently. The compare registers of the compare units are double-buffered, allowing programmable change of the compare/PWM pulse widths as needed.

4.2.3 Programmable Deadband Generator

Deadband generation can be enabled/disabled for each compare unit output individually. The deadband-generator circuit produces two outputs (with or without deadband zone) for each compare unit output signal. The output states of the deadband generator are configurable and changeable as needed by way of the double-buffered ACTRx register.

4.2.4 PWM Waveform Generation

Up to eight PWM waveforms (outputs) can be generated simultaneously by each event manager: three independent pairs (six outputs) by the three full-compare units with programmable deadbands, and two independent PWMs by the GP-timer compares.

4.2.5 Double Update PWM Mode

The F2812 Event Manager supports Double Update PWM Mode. This mode refers to a PWM operation mode in which the position of the leading edge and the position of the trailing edge of a PWM pulse are independently modifiable in each PWM period. To support this mode, the compare register that determines the position of the edges of a PWM pulse must allow (buffered) compare value update once at the beginning of a PWM period and another time in the middle of a PWM period. The compare registers in F2812 Event Managers are all buffered and support three compare value reload/update (value in buffer becoming active) modes. These modes have earlier been documented as compare value reload conditions. The reload condition that supports double update PWM mode is reloaded on Underflow (beginning of PWM period) OR Period (middle of PWM period). Double update PWM mode can be achieved by using this condition for compare value reload.

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4.2.6 PWM Characteristics

Characteristics of the PWMs are as follows:

• 16-bit registers

• Wide range of programmable deadband for the PWM output pairs

• Change of the PWM carrier frequency for PWM frequency wobbling as needed

• Change of the PWM pulse widths within and after each PWM period as needed

• External-maskable power and drive-protection interrupts

• Pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space vector PWM waveforms

• Minimized CPU overhead using auto-reload of the compare and period registers

• The PWM pins are driven to a high-impedance state when the PDPINTx pin is driven low and after PDPINTx signal qualification. The PDPINTx pin (after qualification) is reflected in bit 8 of the COMCONx register.

– PDPINTA pin status is reflected in bit 8 of COMCONA register. – PDPINTB pin status is reflected in bit 8 of COMCONB register.

• EXTCON register bits provide options to individually trip control for each PWM pair of signals

4.2.7 Capture Unit

The capture unit provides a logging function for different events or transitions. The values of the selected GP timer counter are captured and stored in the two-level-deep FIFO stacks when selected transitions are detected on capture input pins, CAPx (x = 1, 2, or 3 for EVA; and x = 4, 5, or 6 for EVB). The capture unit consists of three capture circuits.

• Capture units include the following features: – One 16-bit capture control register, CAPCONx (R/W) – One 16-bit capture FIFO status register, CAPFIFOx – Selection of GP timer 1/2 (for EVA) or 3/4 (for EVB) as the time base – Three 16-bit 2-level-deep FIFO stacks, one for each capture unit – Three capture input pins (CAP1/2/3 for EVA, CAP4/5/6 for EVB)—one input pin per capture unit.

[All inputs are synchronized with the device (CPU) clock. In order for a transition to be captured, the input must hold at its current level to meet the input qualification circuitry requirements. The input

pins CAP1/2 and CAP4/5 can also be used as QEP inputs to the QEP circuit.] – User-specified transition (rising edge, falling edge, or both edges) detection – Three maskable interrupt flags, one for each capture unit – The capture pins can also be used as general-purpose interrupt pins, if they are not used for the

capture function.

SGUS062A–JUNE 2009–REVISED APRIL 2010

4.2.8 Quadrature-Encoder Pulse (QEP) Circuit

Two capture inputs (CAP1 and CAP2 for EVA; CAP4 and CAP5 for EVB) can be used to interface the on-chip QEP circuit with a quadrature encoder pulse. Full synchronization of these inputs is performed on-chip. Direction or leading-quadrature pulse sequence is detected, and GP timer 2/4 is incremented or decremented by the rising and falling edges of the two input signals (four times the frequency of either input pulse).

With EXTCONA register bits, the EVA QEP circuit can use CAP3 as a capture index pin as well. Similarly, with EXTCONB register bits, the EVB QEP circuit can use CAP6 as a capture index pin.

4.2.9 External ADC Start-of-Conversion

EVA/EVB start-of-conversion (SOC) can be sent to an external pin (EVASOC/EVBSOC) for external ADC interface. EVASOC and EVBSOC are MUXed with T2CTRIP and T4CTRIP, respectively.

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Input Analog Voltage ADCLO

4096 ,

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4.3 Enhanced Analog-to-Digital Converter (ADC) Module

A simplified functional block diagram of the ADC module is shown in Figure 4-4. The ADC module consists of a 12-bit ADC with a built-in sample-and-hold (S / H) circuit. Functions of the ADC module include:

• 12-bit ADC core with built-in S/H

• Analog input: 0.0 V to 3.0 V (Voltages above 3.0 V produce full-scale conversion results.)

• Fast conversion rate: 80 ns at 25-MHz ADC clock, 12.5 MSPS

• 16-channel, MUXed inputs

• Autosequencing capability provides up to 16 autoconversions in a single session. Each conversion can be programmed to select any 1 of 16 input channels

• Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer (i.e., two cascaded 8-state sequencers)

• Sixteen result registers (individually addressable) to store conversion values – The digital value of the input analog voltage is derived by:

Digital Value = 0, when input ≤ 0 V Digital Value = when 0 v < input < 3 V

Digital Value = 4095, when input ≥ 3 V

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• Multiple triggers as sources for the start-of-conversion (SOC) sequence – S/W - software immediate start – EVA - Event manager A (multiple event sources within EVA) – EVB - Event manager B (multiple event sources within EVB)

• Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS

• Sequencer can operate in start/stop mode, allowing multiple time-sequenced triggers to synchronize conversions

• EVA and EVB triggers can operate independently in dual-sequencer mode

• Sample-and-hold (S/H) acquisition time window has separate prescale control

The ADC module in the F2812 has been enhanced to provide flexible interface to event managers A and B. The ADC interface is built around a fast, 12-bit ADC module with a fast conversion rate of 80 ns at 25-MHz ADC clock. The ADC module has 16 channels, configurable as two independent 8-channel modules to service event managers A and B. The two independent 8-channel modules can be cascaded to form a 16-channel module. Although there are multiple input channels and two sequencers, there is only one converter in the ADC module. Figure 4-4 shows the block diagram of the F2812 ADC module.

The two 8-channel modules have the capability to autosequence a series of conversions, each module has the choice of selecting any one of the respective eight channels available through an analog MUX. In the cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer, once the conversion is complete, the selected channel value is stored in its respective RESULT register. Autosequencing allows the system to convert the same channel multiple times, allowing the user to perform oversampling algorithms. This gives increased resolution over traditional single-sampled conversion results.

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Result Registers

EVB

S/W

ADCSOC

EVA

S/W

Sequencer 2

Sequencer 1

SOCSOC

ADC Control Registers

70B7h

70B0h

70AFh

70A8h

Result Reg 15

Result Reg 8

Result Reg 7

Result Reg 1

Result Reg 0

Module

ADC

12-Bit

Analog

MUX

ADCINA0

ADCINA7

ADCINB0

ADCINB7

System

Control Block

High-Speed

Prescaler

HSPCLKADCENCLK

C28x

SYSCLKOUT

S/H

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Figure 4-4. Block Diagram of the F2812 ADC Module

To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent possible, traces leading to the ADCIN pins should not run in close proximity to the digital signal paths. This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation techniques must be used to isolate the ADC module power pins ( V

DDA1/VDDA2

F2812 device.

1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the

2. The behavior of the ADC module based on the state of the ADCENCLK and HALT

, AV

DDREFBG

) from the digital supply. Figure 4-5 shows the ADC pin connections for the

ADC module is controlled by the high-speed peripheral clock (HSPCLK).

signals is as follows: ADCENCLK: On reset, this signal is low. While reset is active-low (XRS), the clock to the

register still functions. This is necessary to make sure all registers and modes go into their default reset state. The analog module is in a low-power inactive state. As soon as reset goes high, then the clock to the registers is disabled. When the user sets the ADCENCLK signal high, then the clocks to the registers is enabled and the analog module is enabled. There is a certain time delay (ms range) before the ADC is stable and can be used. HALT: This signal only affects the analog module. It does not affect the registers. If low, the ADC module is powered. If high, the ADC module goes into low-power mode. The HALT mode stops the clock to the CPU, which stops the HSPCLK. Therefore the ADC register logic is turned off indirectly.

NOTE

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ADCINA[7:0] ADCINB[7:0]

ADCLO

ADCBGREFIN

†

ADC External Current Bias Resistor ADCRESEXT

ADCREFP

DDA1

DDA2

SSA1

SSA2

AVDDREFBG

AVSSREFBG

DDAIO

SSAIO

DD1

SS1

Test Pin

ADC Reference Positive Output

ADCREFMADC Reference Medium Output

ADC Analog Power

ADC Reference Power

ADC Analog I/O Power

ADC Digital Power

Analog input 0−3 V with respect to ADCLO

Connect to Analog Ground

24.9 k/20 k (See Note C)

10 F

‡

10 F

‡

Analog 3.3 V Analog 3.3 V

Analog 3.3 V

Analog 3.3 V Analog Ground

1.8 V

ADCREFP and ADCREFM should not be loaded by external circuitry

can use the same 1.8 V (or 1.9 V) supply as the digital core but separate the two with a ferrite bead or a filter

Digital Ground

ADC 16-Channel Analog Inputs

†

Provide access to this pin in PCB layouts. Intended for test purposes only.

‡

TAIYO YUDEN EMK325F106ZH, EMK325BJ106MD, or equivalent

NOTES: A. External decoupling capacitors are recommended on all power pins.

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Figure 4-5 shows the ADC pin-biasing for internal reference and Figure 4-6 shows the ADC pin-biasing for

external reference.

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Figure 4-5. ADC Pin Connections With Internal Reference (See Notes A and B)

The temperature rating of any recommended component must match the rating of the end product.

NOTE

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ADCINA[7:0] ADCINB[7:0]

ADCLO

ADCBGREFIN

ADC External Current Bias Resistor ADCRESEXT

ADCREFP

DDA1

DDA2

SSA1

SSA2

AVDDREFBG

AVSSREFBG

DDAIO

SSAIO

DD1

SS1

Test Pin

ADC Reference Positive Input

ADCREFMADC Reference Medium Input

ADC Analog Power

ADC Reference Power

ADC Analog I/O Power

ADC Digital Power

Analog Input 0−3 V With Respect to ADCLO Connect to Analog Ground

24.9 k20 k (See Note C)

Analog 3.3 V Analog 3.3 V

Analog 3.3 V

Analog 3.3 V Analog Ground

1.8 V Can use the same 1.8-V (or 1.9-V) supply as the digital core but separate the two with a ferrite bead or a filter

Digital Ground

ADC 16-Channel Analog Inputs

1 F −10 F

2 V 1 V

1 F − 10 F

NOTES: A. External decoupling capacitors are recommended on all power pins.

B. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance. C. Use 24.9 kΩ for ADC clock range 1 − 18.75 MHz; use 20 kΩ for ADC clock range 18.75 − 25 MHz. D. It is recommended that buffered external references be provided with a voltage difference of (ADCREFP−ADCREFM)

= 1 V $ 0.1% or better.

External reference is enabled using bit 8 in the ADCTRL3 Register at ADC power up. In this mode, the accuracy of external reference is critical for overall gain. The voltage ADCREFP−ADCREFM determines the overall accuracy. Do not enable internal references when external references are connected to ADCREFP and ADCREFM. See the TMS320x281x DSP Analog-to-Digital Converter (ADC) Reference Guide (literature number SPRU060) for more information.

(See

Note D)

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Figure 4-6. ADC Pin Connections With External Reference

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The ADC operation is configured, controlled, and monitored by the registers listed in Table 4-4.

Table 4-4. ADC Registers

NAME ADDRESS SIZE (×16) DESCRIPTION

ADCTRL1 0x00 7100 1 ADC Control Register 1 ADCTRL2 0x00 7101 1 ADC Control Register 2

ADCMAXCONV 0x00 7102 1 ADC Maximum Conversion Channels Register ADCCHSELSEQ1 0x00 7103 1 ADC Channel Select Sequencing Control Register 1 ADCCHSELSEQ2 0x00 7104 1 ADC Channel Select Sequencing Control Register 2 ADCCHSELSEQ3 0x00 7105 1 ADC Channel Select Sequencing Control Register 3 ADCCHSELSEQ4 0x00 7106 1 ADC Channel Select Sequencing Control Register 4

ADCASEQSR 0x00 7107 1 ADC Auto–Sequence Status Register ADCRESULT0 0x00 7108 1 ADC Conversion Result Buffer Register 0 ADCRESULT1 0x00 7109 1 ADC Conversion Result Buffer Register 1 ADCRESULT2 0x00 710A 1 ADC Conversion Result Buffer Register 2 ADCRESULT3 0x00 710B 1 ADC Conversion Result Buffer Register 3 ADCRESULT4 0x00 710C 1 ADC Conversion Result Buffer Register 4 ADCRESULT5 0x00 710D 1 ADC Conversion Result Buffer Register 5 ADCRESULT6 0x00 710E 1 ADC Conversion Result Buffer Register 6 ADCRESULT7 0x00 710F 1 ADC Conversion Result Buffer Register 7 ADCRESULT8 0x00 7110 1 ADC Conversion Result Buffer Register 8 ADCRESULT9 0x00 7111 1 ADC Conversion Result Buffer Register 9

ADCRESULT10 0x00 7112 1 ADC Conversion Result Buffer Register 10 ADCRESULT11 0x00 7113 1 ADC Conversion Result Buffer Register 11 ADCRESULT12 0x00 7114 1 ADC Conversion Result Buffer Register 12 ADCRESULT13 0x00 7115 1 ADC Conversion Result Buffer Register 13 ADCRESULT14 0x00 7116 1 ADC Conversion Result Buffer Register 14 ADCRESULT15 0x00 7117 1 ADC Conversion Result Buffer Register 15

ADCTRL3 0x00 7118 1 ADC Control Register 3

ADCST 0x00 7119 1 ADC Status Register

reserved 4

(1) The above registers are Peripheral Frame 2 Registers.

0x00 711C 0x00 711F

(1)

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4.4 Enhanced Controller Area Network (eCAN) Module

The CAN module has the following features:

• Fully compliant with CAN protocol, version 2.0B

• Supports data rates up to 1 Mbps

• Thirty-two mailboxes, each with the following properties: – Configurable as receive or transmit – Configurable with standard or extended identifier – Has a programmable receive mask – Supports data and remote frame – Composed of 0 to 8 bytes of data – Uses a 32-bit time stamp on receive and transmit message – Protects against reception of new message – Holds the dynamically programmable priority of transmit message – Employs a programmable interrupt scheme with two interrupt levels – Employs a programmable alarm on transmission or reception time-out

• Low-power mode

• Programmable wake-up on bus activity

• Automatic reply to a remote request message

• Automatic retransmission of a frame in case of loss of arbitration or error

• 32-bit local network time counter synchronized by a specific message (communication in conjunction with mailbox 16)

• Self-test mode – Operates in a loopback mode receiving its own message. A dummy acknowledge is provided,

thereby eliminating the need for another node to provide the acknowledge bit.

SGUS062A–JUNE 2009–REVISED APRIL 2010

NOTE

For a SYSCLKOUT of 150 MHz, the smallest bit rate possible is 23.4 kbps.

The 28x CAN has passed the conformance test per ISO/DIS 16845. Contact TI for further details.

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Mailbox RAM

(512 Bytes)

32-Message Mailbox

of 4 × 32-Bit Words

Memory Management

Unit

CPU Interface,

Receive Control Unit,

Timer Management Unit

eCAN Memory

(512 Bytes)

Registers and Message

Objects Control

32 32

Message Controller

32 3232 3232 32

eCAN Protocol Kernel

Receive Buffer

Transmit Buffer

Control Buffer

Status Buffer

Enhanced CAN Controller

Controls

Address Data

eCAN1INTeCAN0INT

SN65HVD23x

3.3-V CAN Transceiver

CAN Bus

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Figure 4-7. eCAN Block Diagram and Interface Circuit

Table 4-5. 3.3-V eCAN Transceivers for the SM320F2812 DSP

PART NUMBER VREF OTHER T

SN65HVD230 3.3 V Standby Adjustable Yes – –40°C to 85°C SN65HVD230Q 3.3 V Standby Adjustable Yes – –40°C to 125°C SN65HVD231 3.3 V Sleep Adjustable Yes – –40°C to 85°C SN65HVD231Q 3.3 V Sleep Adjustable Yes – –40°C to 125°C SN65HVD232 3.3 V None None None – –40°C to 85°C SN65HVD232Q 3.3 V None None None – –40°C to 125°C SN65HVD233 3.3 V Standby Adjustable None Diagnostic Loopback –40°C to 125°C SN65HVD234 3.3 V Standby & Sleep Adjustable None – –40°C to 125°C SN65HVD235 3.3 V Standby Adjustable None Autobaud Loopback –40°C to 125°C

SUPPLY LOW-POWER SLOPE

VOLTAGE MODE CONTROL

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Mailbox Enable − CANME

Mailbox Direction − CANMD

Transmission Request Set − CANTRS

Transmission Request Reset − CANTRR

Transmission Acknowledge − CANTA

Abort Acknowledge − CANAA

Received Message Pending − CANRMP

Received Message Lost − CANRML

Remote Frame Pending − CANRFP

Global Acceptance Mask − CANGAM

Master Control − CANMC

Bit-Timing Configuration − CANBTC

Error and Status − CANES

Transmit Error Counter − CANTEC

Receive Error Counter − CANREC Global Interrupt Flag 0 − CANGIF0

Global Interrupt Mask − CANGIM

Mailbox Interrupt Mask − CANMIM

Mailbox Interrupt Level − CANMIL

Overwrite Protection Control − CANOPC

TX I/O Control − CANTIOC

RX I/O Control − CANRIOC

Time Stamp Counter − CANTSC

Global Interrupt Flag 1 − CANGIF1

Time-Out Control − CANTOC

Time-Out Status − CANTOS

Reserved

eCAN Control and Status Registers

Message Identifier − MSGID

61E8h−61E9h

Message Control − MSGCTRL

Message Data Low − MDL

Message Data High − MDH

Message Mailbox (16 Bytes)

Control and Status Registers

6000h

603Fh

Local Acceptance Masks (LAM)

(32 × 32-Bit RAM)

6040h

607Fh

6080h

60BFh

60C0h

60FFh

eCAN Memory (512 Bytes)

Message Object Time Stamps (MOTS)

(32 × 32-Bit RAM)

Message Object Time-Out (MOTO)

(32 × 32-Bit RAM)

Mailbox 0

6100h−6107h

Mailbox 1

6108h−610Fh

Mailbox 2

6110h−6117h

Mailbox 3

6118h−611Fh

eCAN Memory RAM (512 Bytes)

Mailbox 4

6120h−6127h

Mailbox 28

61E0h−61E7h

Mailbox 29

61E8h−61EFh

Mailbox 30

61F0h−61F7h

Mailbox 31

61F8h−61FFh

61EAh−61EBh 61ECh−61EDh

61EEh−61EFh

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Figure 4-8. eCAN Memory Map

SGUS062A–JUNE 2009–REVISED APRIL 2010

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The CAN registers listed in Table 4-6 are used by the CPU to configure and control the CAN controller and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.

Table 4-6. CAN Registers Map

CANME 0x00 6000 1 Mailbox enable

CANMD 0x00 6002 1 Mailbox direction CANTRS 0x00 6004 1 Transmit request set CANTRR 0x00 6006 1 Transmit request reset

CANTA 0x00 6008 1 Transmission acknowledge

CANAA 0x00 600A 1 Abort acknowledge CANRMP 0x00 600C 1 Receive message pending CANRML 0x00 600E 1 Receive message lost

CANRFP 0x00 6010 1 Remote frame pending

CANGAM 0x00 6012 1 Global acceptance mask

CANMC 0x00 6014 1 Master control

CANBTC 0x00 6016 1 Bit-timing configuration

CANES 0x00 6018 1 Error and status

CANTEC 0x00 601A 1 Transmit error counter CANREC 0x00 601C 1 Receive error counter CANGIF0 0x00 601E 1 Global interrupt flag 0

CANGIM 0x00 6020 1 Global interrupt mask CANGIF1 0x00 6022 1 Global interrupt flag 1

CANMIM 0x00 6024 1 Mailbox interrupt mask

CANMIL 0x00 6026 1 Mailbox interrupt level

CANOPC 0x00 6028 1 Overwrite protection control

CANTIOC 0x00 602A 1 TX I/O control CANRIOC 0x00 602C 1 RX I/O control

CANTSC 0x00 602E 1 Time stamp counter (Reserved in SCC mode) CANTOC 0x00 6030 1 Time-out control (Reserved in SCC mode)

CANTOS 0x00 6032 1 Time-out status (Reserved in SCC mode)

(1) These registers are mapped to Peripheral Frame 1.

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(1)

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CLKSRG

McBSP clock rate CLKG ,

1 CLKGDIV

= =

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4.5 Multichannel Buffered Serial Port (McBSP) Module

The McBSP module has the following features:

• Compatible to McBSP in TMS320C54x™/ TMS320C55x™ DSP devices, except the DMA features

• Full-duplex communication

• Double-buffered data registers which allow a continuous data stream

• Independent framing and clocking for receive and transmit

• External shift clock generation or an internal programmable frequency shift clock

• A wide selection of data sizes including 8/12/16/20/24 or 32-bits

• 8-bit data transfers with LSB or MSB first

• Programmable polarity for both frame synchronization and data clocks

• Highly programmable internal clock and frame generation

• Support A-bis mode

• Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially connected A/D and D/A devices

• Works with SPI-compatible devices

• Two 16 x 16-level FIFO for Transmit channel

• Two 16 x 16-level FIFO for Receive channel

The following application interfaces can be supported on the McBSP:

• T1/E1 framers

• MVIP switching-compatible and ST-BUS-compliant devices including: – MVIP framers – H.100 framers – SCSA framers – IOM-2 compliant devices – AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.) – IIS-compliant devices

SGUS062A–JUNE 2009–REVISED APRIL 2010

• where CLKSRG source could be LSPCLK, CLKX, or CLKR.

(2) Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is

less than the I/O buffer speed limit—20-MHz maximum.

(2)

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McBSP Receive

Interrupt Select Logic

Expand Logic

DRR1 Receive Buffer

RX FIFO Interrupt

DRR2 Receive Buffer

RX FIFO Registers

RBR1 RegisterRBR2 Register

McBSP Registers

and Control Logic

CLKX

FSX

CLKR

FSR

Compand Logic

DXR2 Transmit Buffer

RSR1

XSR2

XSR1

Peripheral Read Bus

RSR2

DXR1 Transmit Buffer

LSPCLK

MRINT

To CPU

McBSP

RX Interrupt Logic

RX FIFO _15

— RX FIFO _1 RX FIFO _0

RX FIFO _15

— RX FIFO _1 RX FIFO _0

McBSP Transmit

Interrupt Select Logic

TX FIFO

Interrupt

TX FIFO Registers

MXINT

To CPU

TX Interrupt Logic

TX FIFO _15

— TX FIFO _1 TX FIFO _0

TX FIFO _15

— TX FIFO _1 TX FIFO _0

Peripheral Write Bus

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SGUS062A–JUNE 2009–REVISED APRIL 2010

Figure 4-9 shows the block diagram of the McBSP module with FIFO, interfaced to the F2812 version of

Peripheral Frame 2.

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Figure 4-9. McBSP Module With FIFO

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Table 4-7 provides a summary of the McBSP registers.

Table 4-7. McBSP Register Summary

NAME DESCRIPTION

– – – 0x0000 McBSP Receive Buffer Register – – – 0x0000 McBSP Receive Shift Register – – – 0x0000 McBSP Transmit Shift Register

DRR2 0 R 0x0000

DRR1 01 R 0x0000 –Read Second if the word size is greater than 16 bits, else read DRR1

DXR2 02 W 0x0000

DXR1 03 W 0x0000 –Write Second if the word size is greater than 16 bits, else write to DXR1

SPCR2 04 R/W 0x0000 McBSP Serial Port Control Register 2 SPCR1 05 R/W 0x0000 McBSP Serial Port Control Register 1

RCR2 06 R/W 0x0000 McBSP Receive Control Register 2 RCR1 07 R/W 0x0000 McBSP Receive Control Register 1 XCR2 08 R/W 0x0000 McBSP Transmit Control Register 2

XCR1 09 R/W 0x0000 McBSP Transmit Control Register 1 SRGR2 0A R/W 0x0000 McBSP Sample Rate Generator Register 2 SRGR1 0B R/W 0x0000 McBSP Sample Rate Generator Register 1

MCR2 0C R/W 0x0000 McBSP Multichannel Register 2

MCR1 0D R/W 0x0000 McBSP Multichannel Register 1 RCERA 0E R/W 0x0000 McBSP Receive Channel Enable Register Partition A RCERB 0F R/W 0x0000 McBSP Receive Channel Enable Register Partition B XCERA 10 R/W 0x0000 McBSP Transmit Channel Enable Register Partition A XCERB 11 R/W 0x0000 McBSP Transmit Channel Enable Register Partition B

PCR 12 R/W 0x0000 McBSP Pin Control Register RCERC 13 R/W 0x0000 McBSP Receive Channel Enable Register Partition C RCERD 14 R/W 0x0000 McBSP Receive Channel Enable Register Partition D

XCERC 15 R/W 0x0000 McBSP Transmit Channel Enable Register Partition C XCERD 16 R/W 0x0000 McBSP Transmit Channel Enable Register Partition D RCERE 17 R/W 0x0000 McBSP Receive Channel Enable Register Partition E RCERF 18 R/W 0x0000 McBSP Receive Channel Enable Register Partition F XCERE 19 R/W 0x0000 McBSP Transmit Channel Enable Register Partition E

XCERF 1A R/W 0x0000 McBSP Transmit Channel Enable Register Partition F RCERG 1B R/W 0x0000 McBSP Receive Channel Enable Register Partition G RCERH 1C R/W 0x0000 McBSP Receive Channel Enable Register Partition H XCERG 1D R/W 0x0000 McBSP Transmit Channel Enable Register Partition G

XCERH 1E R/W 0x0000 McBSP Transmit Channel Enable Register Partition H

(1) DRR2/DRR1 and DXR2/DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode.

ADDRESS TYPE RESET VALUE 0x00 78xxh (R/W) (HEX)

DATA REGISTERS, RECEIVE, TRANSMIT

McBSP CONTROL REGISTERS

MULTICHANNEL CONTROL REGISTERS

(1)

McBSP Data Receive Register 2 –Read First if the word size is greater than 16 bits, else ignore DRR2

McBSP Data Receive Register 1 only

McBSP Data Transmit Register 2 –Write First if the word size is greater than 16 bits, else ignore DXR2

McBSP Data Transmit Register 1 only

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Table 4-7. McBSP Register Summary (continued)

NAME DESCRIPTION

DRR2 00 R 0x0000

DRR1 01 R 0x0000

DXR2 02 W 0x0000

DXR1 03 W 0x0000

MFFTX 20 R/W 0xA000 McBSP Transmit FIFO Register

MFFRX 21 R/W 0x201F McBSP Receive FIFO Register

MFFCT 22 R/W 0x0000 McBSP FIFO Control Register MFFINT 23 R/W 0x0000 McBSP FIFO Interrupt Register

MFFST 24 R/W 0x0000 McBSP FIFO Status Register

(1) FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers.

ADDRESS TYPE RESET VALUE 0x00 78xxh (R/W) (HEX)

FIFO MODE REGISTERS (applicable only in FIFO mode)

FIFO Data Registers

FIFO Control Registers

(1)

McBSP Data Receive Register 2 – Top of receive FIFO –Read First FIFO pointers does not advance

McBSP Data Receive Register 1 – Top of receive FIFO –Read Second for FIFO pointers to advance

McBSP Data Transmit Register 2 – Top of transmit FIFO –Write First FIFO pointers does not advance

McBSP Data Transmit Register 1 – Top of transmit FIFO –Write Second for FIFO pointers to advance

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LSPCLK

(BRR 1) 8+ ·

LSPCLK

150 MHz

Max bit rate 9.375 10 b / s

2 8

= = ´

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4.6 Serial Communications Interface (SCI) Module

The F2812 device include two serial communications interface (SCI) modules. The SCI modules support digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to over 65 000 different speeds through a 16-bit baud-select register.

Features of each SCI module include:

• Two external pins: – SCITXD: SCI transmit-output pin – SCIRXD: SCI receive-input pin

NOTE

Both pins can be used as GPIO if not used for SCI.

• Baud rate programmable to 64K different rates

– Baud rate

when BRR ≠ 0

SGUS062A–JUNE 2009–REVISED APRIL 2010

= when BRR = 0

• Data-word format – One start bit – Data-word length programmable from one to eight bits – Optional even/odd/no parity bit – One or two stop bits

• Four error-detection flags: parity, overrun, framing, and break detection

• Two wake-up multiprocessor modes: idle-line and address bit

• Half- or full-duplex operation

• Double-buffered receive and transmit functions

• Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with status flags.

– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) andTX

EMPTY flag (transmitter-shift register is empty)

– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag

(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)

• Separate enable bits for transmitter and receiver interrupts (except BRKDT)

•

• NRZ (non-return-to-zero) format

• Ten SCI module control registers located in the control register frame beginning at address 7050h

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All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect.

Enhanced features:

• Auto baud-detect hardware logic

• 16-level transmit/receive FIFO

The SCI port operation is configured and controlled by the registers listed in Table 4-8 and Table 4-9.

Table 4-8. SCI-A Registers

NAME ADDRESS SIZE (×16) DESCRIPTION

SCICCRA 0x00 7050 1 SCI-A Communications Control Register

SCICTL1A 0x00 7051 1 SCI-A Control Register 1

SCIHBAUDA 0x00 7052 1 SCI-A Baud Register, High Bits

SCILBAUDA 0x00 7053 1 SCI-A Baud Register, Low Bits

SCICTL2A 0x00 7054 1 SCI-A Control Register 2

SCIRXSTA 0x00 7055 1 SCI-A Receive Status Register

SCIRXEMUA 0x00 7056 1 SCI-A Receive Emulation Data Buffer Register

SCIRXBUFA 0x00 7057 1 SCI-A Receive Data Buffer Register

SCITXBUFA 0x00 7059 1 SCI-A Transmit Data Buffer Register

SCIFFTXA 0x00 705A 1 SCI-A FIFO Transmit Register SCIFFRXA 0x00 705B 1 SCI-A FIFO Receive Register SCIFFCTA 0x00 705C 1 SCI-A FIFO Control Register

SCIPRIA 0x00 705F 1 SCI-A Priority Control Register

(1) Shaded registers are new registers for the FIFO mode.

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NOTE

(1)

Table 4-9. SCI-B Registers

NAME ADDRESS SIZE (×16) DESCRIPTION

SCICCRB 0x00 7750 1 SCI-B Communications Control Register

SCICTL1B 0x00 7751 1 SCI-B Control Register 1

SCIHBAUDB 0x00 7752 1 SCI-B Baud Register, High Bits

SCILBAUDB 0x00 7753 1 SCI-B Baud Register, Low Bits

SCICTL2B 0x00 7754 1 SCI-B Control Register 2 SCIRXSTB 0x00 7755 1 SCI-B Receive Status Register

SCIRXEMUB 0x00 7756 1 SCI-B Receive Emulation Data Buffer Register

SCIRXBUFB 0x00 7757 1 SCI-B Receive Data Buffer Register

SCITXBUFB 0x00 7759 1 SCI-B Transmit Data Buffer Register

SCIFFTXB 0x00 775A 1 SCI-B FIFO Transmit Register SCIFFRXB 0x00 775B 1 SCI-B FIFO Receive Register SCIFFCTB 0x00 775C 1 SCI-B FIFO Control Register

SCIPRIB 0x00 775F 1 SCI-B Priority Control Register

(1) Shaded registers are new registers for the FIFO mode. (2) Registers in this table are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit accesses produce

undefined results.

(1) (2)

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TX FIFO _0

LSPCLK

WUT

Frame Format and Mode

Even/Odd Enable

Parity

SCI RX Interrupt select logic

BRKDT

RXRDY

SCIRXST.6

SCICTL1.3

SCICTL2.1

RX/BK INT ENA

SCIRXD

SCIRXST.1

TXENA

SCI TX Interrupt select logic

TX EMPTY

TXRDY

SCICTL2.0

TX INT ENA

SCITXD

RXENA

SCIRXD

RXWAKE

SCICTL1.6

RX ERR INT ENA

TXWAKE

SCITXD

SCICCR.6 SCICCR.5

SCITXBUF.7−0

SCIHBAUD. 15 − 8

Baud Rate

MSbyte

SCILBAUD. 7 − 0

Transmitter−Data

Buffer Register

SCICTL2.6

SCICTL2.7

Baud Rate

LSbyte

RXSHF Register

TXSHF

SCIRXST.5

TX FIFO _1

−−−−−

TX FIFO _15

TX FIFO registers

TX FIFO

TX Interrupt

Logic

TXINT

SCIFFTX.14

RX FIFO _15

SCIRXBUF.7−0

Receive Data Buffer register SCIRXBUF.7−0

−−−−−

RX FIFO_1 RX FIFO _0

RX FIFO registers

SCICTL1.0

RX Interrupt

Logic

RXINT

RX FIFO

SCIFFRX.15

RXFFOVF

RX Error

SCIRXST.7

PEFE OE

RX Error

SCIRXST.4 − 2

To CPU

AutoBaud Detect logic

SCICTL1.1

SCIFFENA

Interrupts

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Figure 4-10 shows the SCI module block diagram.

SGUS062A–JUNE 2009–REVISED APRIL 2010

Figure 4-10. Serial Communications Interface (SCI) Module Block Diagram

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LSPCLK

(SPIBRR 1)+

LSPCLK

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4.7 Serial Peripheral Interface (SPI) Module

The F2812 device includes the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the DSP controller and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI.

The SPI module features include:

• Four external pins: – SPISOMI: SPI slave-output/master-input pin – SPISIMO: SPI slave-input/master-output pin – SPISTE: SPI slave transmit-enable pin – SPICLK: SPI serial-clock pin

All four pins can be used as GPIO, if the SPI module is not used.

• Two operational modes: master and slave

• Baud rate: 125 different programmable rates

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NOTE

– Baud rate

when BRR ≠ 0

= when BRR = 0, 1, 2, 3

Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less than the I/O buffer speed limit—20 MHz maximum.

• Data word length: one to sixteen data bits

• Four clocking schemes (controlled by clock polarity and clock phase bits) include: – Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the

SPICLK signal and receives data on the rising edge of the SPICLK signal.

– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the

falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.

– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the

SPICLK signal and receives data on the falling edge of the SPICLK signal.

– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the

falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.

• Simultaneous receive and transmit operation (transmit function can be disabled in software)

• Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.

• Nine SPI module control registers: Located in control register frame beginning at address 7040h.

NOTE

All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect.

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Enhanced feature:

• 16-level transmit/receive FIFO

• Delayed transmit control

The SPI port operation is configured and controlled by the registers listed in Table 4-10.

Table 4-10. SPI Registers

NAME ADDRESS SIZE (×16) DESCRIPTION

SPICCR 0x00 7040 1 SPI Configuration Control Register

SPICTL 0x00 7041 1 SPI Operation Control Register SPISTS 0x00 7042 1 SPI Status Register SPIBRR 0x00 7044 1 SPI Baud Rate Register

SPIRXEMU 0x00 7046 1 SPI Receive Emulation Buffer Register

SPIRXBUF 0x00 7047 1 SPI Serial Input Buffer Register SPITXBUF 0x00 7048 1 SPI Serial Output Buffer Register

SPIDAT 0x00 7049 1 SPI Serial Data Register

SPIFFTX 0x00 704A 1 SPI FIFO Transmit Register

SPIFFRX 0x00 704B 1 SPI FIFO Receive Register

SPIFFCT 0x00 704C 1 SPI FIFO Control Register

SPIPRI 0x00 704F 1 SPI Priority Control Register

(1) The above registers are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined

results.

(1)

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SPICTL.0

SPI INT FLAG

SPI INT

ENA

SPISTS.6

Clock

Polarity

Talk

LSPCLK

456 123 0

0123

SPI Bit Rate

State Control

SPIRXBUF

Buffer Register

Clock

Phase

Receiver

Overrun Flag

SPICTL.4

Overrun INT ENA

SPICCR.3 − 0

SPIBRR.6 − 0

SPICCR.6 SPICTL.3

SPIDAT.15 − 0

SPICTL.1

Master/Slave

SPISTS.7

SPIDAT

Data Register

SPICTL.2

SPI Char

SPISIMO

SPISOMI

SPICLK

SW2

SW3

To CPU

SW1

SPITXBUF

Buffer Register

RX FIFO _0 RX FIFO _1

−−−−−

RX FIFO _15

TX FIFO registers

TX FIFO _0

TX FIFO _1

−−−−−

TX FIFO _15

RX FIFO registers

TX Interrupt

Logic

RX Interrupt

Logic

SPIINT/SPIRXINT

SPITXINT

SPIFFOVF FLAG

SPIFFRX.15

TX FIFO Interrupt

RX FIFO Interrupt

SPIRXBUF

SPITXBUF

SPIFFTX.14

SPIFFENA

SPISTE

†

SPISTE

is driven low by the master for a slave device.

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Figure 4-11 is a block diagram of the SPI in slave mode.

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Figure 4-11. Serial Peripheral Interface Module Block Diagram (Slave Mode)

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4.8 GPIO MUX

The GPIO Mux registers are used to select the operation of shared pins on the F2812 device. The pins can be individually selected to operate as Digital I/O or connected to Peripheral I/O signals (via the GPxMUX registers). If selected for Digital I/O mode, registers are provided to configure the pin direction (via the GPxDIR registers) and to qualify the input signal to remove unwanted noise (via the GPxQUAL) registers). Table 4-11 lists the GPIO Mux Registers.

Table 4-11. GPIO Mux Registers

NAME ADDRESS SIZE (×16) REGISTER DESCRIPTION

GPAMUX 0x00 70C0 1 GPIO A Mux Control Register

GPADIR 0x00 70C1 1 GPIO A Direction Control Register

GPAQUAL 0x00 70C2 1 GPIO A Input Qualification Control Register

reserved 0x00 70C3 1

GPBMUX 0x00 70C4 1 GPIO B Mux Control Register

GPBDIR 0x00 70C5 1 GPIO B Direction Control Register

GPBQUAL 0x00 70C6 1 GPIO B Input Qualification Control Register

reserved 0x00 70C7 1 reserved 0x00 70C8 1 reserved 0x00 70C9 1 reserved 0x00 70CA 1 reserved 0x00 70CB 1

GPDMUX 0x00 70CC 1 GPIO D Mux Control Register

GPDDIR 0x00 70CD 1 GPIO D Direction Control Register

GPDQUAL 0x00 70CE 1 GPIO D Input Qualification Control Register

reserved 0x00 70CF 1

GPEMUX 0x00 70D0 1 GPIO E Mux Control Register

GPEDIR 0x00 70D1 1 GPIO E Direction Control Register

GPEQUAL 0x00 70D2 1 GPIO E Input Qualification Control Register

reserved 0x00 70D3 1

GPFMUX 0x00 70D4 1 GPIO F Mux Control Register

GPFDIR 0x00 70D5 1 GPIO F Direction Control Register reserved 0x00 70D6 1 reserved 0x00 70D7 1

GPGMUX 0x00 70D8 1 GPIO G Mux Control Register

GPGDIR 0x00 70D9 1 GPIO G Direction Control Register reserved 0x00 70DA 1 reserved 0x00 70DB 1

reserved 4

(1) Reserved locations returns undefined values and writes is ignored. (2) Not all inputs support input signal qualification. (3) These registers are EALLOW protected. This prevents spurious writes from overwriting the contents and corrupting the system.

0x00 70DC 0x00 70DF

(1) (2) (3)

If configured for Digital I/O mode, additional registers are provided for setting individual I/O signals (via the GPxSET registers), for clearing individual I/O signals (via the GPxCLEAR registers), for toggling individual I/O signals (via the GPxTOGGLE registers), or for reading/writing to the individual I/O signals (via the GPxDAT registers). Table 4-12 lists the GPIO Data Registers. For more information, see the TMS320x281x System Control and Interrupts Reference Guide (literature number SPRU078).

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Table 4-12. GPIO Data Registers

NAME ADDRESS SIZE (×16) REGISTER DESCRIPTION

GPADAT 0x00 70E0 1 GPIO A Data Register GPASET 0x00 70E1 1 GPIO A Set Register

GPACLEAR 0x00 70E2 1 GPIO A Clear Register

GPATOGGLE 0x00 70E3 1 GPIO A Toggle Register

GPBDAT 0x00 70E4 1 GPIO B Data Register GPBSET 0x00 70E5 1 GPIO B Set Register

GPBCLEAR 0x00 70E6 1 GPIO B Clear Register

GPBTOGGLE 0x00 70E7 1 GPIO B Toggle Register

reserved 0x00 70E8 1 reserved 0x00 70E9 1 reserved 0x00 70EA 1

reserved 0x00 70EB 1 GPDDAT 0x00 70EC 1 GPIO D Data Register GPDSET 0x00 70ED 1 GPIO D Set Register

GPDCLEAR 0x00 70EE 1 GPIO D Clear Register

GPDTOGGLE 0x00 70EF 1 GPIO D Toggle Register

GPEDAT 0x00 70F0 1 GPIO E Data Register GPESET 0x00 70F1 1 GPIO E Set Register

GPECLEAR 0x00 70F2 1 GPIO E Clear Register

GPETOGGLE 0x00 70F3 1 GPIO E Toggle Register

GPFDAT 0x00 70F4 1 GPIO F Data Register GPFSET 0x00 70F5 1 GPIO F Set Register

GPFCLEAR 0x00 70F6 1 GPIO F Clear Register

GPFTOGGLE 0x00 70F7 1 GPIO F Toggle Register

GPGDAT 0x00 70F8 1 GPIO G Data Register

GPGSET 0x00 70F9 1 GPIO G Set Register

GPGCLEAR 0x00 70FA 1 GPIO G Clear Register

GPGTOGGLE 0x00 70FB 1 GPIO G Toggle Register

reserved 4

(1) Reserved location returns undefined values and writes are ignored. (2) These registers are NOT EALLOW protected. The above registers are typically accessed regularly by the user.

0x00 70FC 0x00 70FF

(1) (2)

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Peripheral I/O

MUX

0 1

MUX

Internal (Pullup or Pulldown)

Digital I/O

XRS

High-Impedance Enable (1)

High-

Impedance

Control

GPxDIR

GPxMUX

GPxQUAL

GPxDAT/SET/CLEAR/TOGGLE

Input Qualification

SYSCLKOUT

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Figure 4-12 shows how the various register bits select the various modes of operation for GPIO function.

SGUS062A–JUNE 2009–REVISED APRIL 2010

A. In the GPIO mode, when the GPIO pin is configured for output operation, reading the GPxDAT data register only

gives the value written, not the value at the pin. In the peripheral mode, the state of the pin can be read through the

GPxDAT register, provided the corresponding direction bit is zero (input mode).

B. Some selected input signals are qualified by the SYSCLKOUT. The GPxQUAL register specifies the qualification

sampling period. The sampling window is 6 samples wide and the output is only changed when all samples are the

same (all 0's or all 1's). This feature removes unwanted spikes from the input signal.

Figure 4-12. GPIO/Peripheral Pin Multiplexing

The input function of the GPIO pin and the input path to the peripheral are always enabled. It is the output function of the GPIO pin that is multiplexed with the output path of the primary (peripheral) function. Since the output buffer of a pin connects back to the input buffer, any GPIO signal present at the pin is propagated to the peripheral module as well. Therefore, when a pin is configured for GPIO operation, the corresponding peripheral functionality (and interrupt-generating capability) must be disabled. Otherwise, interrupts may be inadvertently triggered. This is especially critical when the PDPINTA and PDPINTB pins are used as GPIO pins, since a value of zero for GPDDAT.0 or GPDDAT.5 (PDPINTx) puts PWM pins in a high-impedance state. The CxTRIP and TxCTRIP pins also put the corresponding PWM pins in high impedance, if they are driven low (as GPIO pins) and bit EXTCONx.0 = 1.

NOTE

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5 Development Support

Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of DSPs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.

The following products support development of F2812-based applications:

Software Development Tools

• Code Composer Studio™ Integrated Development Environment (IDE) – C/C++ Compiler – Code generation tools – Assembler/Linker – Cycle Accurate Simulator

• Application algorithms

• Sample applications code

Hardware Development Tools

• F2812 eZdsp

• JTAG-based emulators - SPI515, XDS510PP, XDS510PP Plus, XDS510 USB

• Universal 5-V dc power supply

• Documentation and cables

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5.1 Device and Development Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all [TMS320] DSP devices and support tools. Each [TMS320] DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., TMS320F2812GHH). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).

TMX—Experimental device that is not necessarily representative of the final device's electrical specifications

TMP—Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification

TMS/SM—Fully qualified production device SMJ—Fully qualified production device

Support tool development evolutionary flow:

TMDX—Development-support product that has not yet completed Texas Instruments internal qualification testing.

TMDS—Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:

Developmental product is intended for internal evaluation purposes. TMS devices and TMDS development-support tools have been characterized fully, and the quality and

reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard

production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. Figure 5-1 provides a legend for reading the complete device name for any TMS320x28x family member.

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PREFIX

SM 320 F 2812 HFG

TMX = experimental device TMP = prototype device TMS = qualified device SM = commercial processing SMJ = MIL-PRF-38535 (QML)

DEVICE FAMILY

320 = TMS320

DSP Family

TECHNOLOGY

PACKAGETYPE

†

HFG = 172-pin CQFP KGD = Die

DEVICE

2810

TEMPERATURE RANGE

S = -55°C to 220°C

F = Flash EEPROM (1.8-V/1.9-V Core/3.3-V I/O) C = ROM (1.8-V/1.9-V Core/3.3-V I/O)

2811 2812

†

Not all combinations of processing options, temperature ranges and packages are available.

CQFP = Ceramic Quad Flatpack

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5.2 Documentation Support

SGUS062A–JUNE 2009–REVISED APRIL 2010

Figure 5-1. 28x Device Nomenclature

Extensive documentation supports all of the TMS320E DSP family generations of devices from product announcement through applications development. The types of documentation available include: data sheets and data manuals, with design specifications; and hardware and software applications. Useful reference documentation includes:

TMS320C28x DSP CPU and Instruction Set Reference Guide (literature number SPRU430) describes the central processing unit (CPU) and the assembly language instructions of the TMS320C28x™ fixed-point digital signal processors (DSPs). It also describes emulation features available on these DSPs.

TMS320x281x Analog-to-Digital Converter (ADC) Reference Guide (literature number SPRU060) describes the ADC module. The module is a 12-bit pipelined ADC. The analog circuits of this converter, referred to as the core in this document, include the front-end analog multiplexers (MUXs), sample-and-hold (S/H) circuits, the conversion core, voltage regulators, and other analog supporting circuits. Digital circuits, referred to as the wrapper in this document, include programmable conversion sequencer, result registers, interface to analog circuits, interface to device peripheral bus, and interface to other on-chip modules.

TMS320x281x Boot ROM Reference Guide (literature number SPRU095) describes the purpose and features of the bootloader (factory-programmed boot-loading software). It also describes other contents of the device on-chip boot ROM and identifies where all of the information is located within that memory.

TMS320x281x Event Manager (EV) Reference Guide (literature number SPRU065) describes the EV modules that provide a broad range of functions and features that are particularly useful in motion control and motor control applications. The EV modules include general-purpose (GP) timers, full-compare/PWM units, capture units, and quadrature-encoder pulse (QEP) circuits.

TMS320x281x External Interface (XINTF) Reference Guide (literature number SPRU067) describes the external interface (XINTF) of the 281x digital signal processors (DSPs).

TMS320x281x Multi-channel Buffered Serial Ports (McBSPs) Reference Guide (literature number SPRU061) describes the McBSP) available on the 281x devices. The McBSPs allow direct interface between a DSP and other devices in a system.

TMS320x281x System Control and Interrupts Reference Guide (literature number SPRU078) describes the various interrupts and system control features of the 281x digital signal processors (DSPs).

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TMS320x281x, 280x Enhanced Controller Area Network (eCAN) Reference Guide (literature number SPRU074) describes the eCAN that uses established protocol to communicate serially with other controllers in electrically noisy environments. With 32 fully configurable mailboxes and time-stamping feature, the eCAN module provides a versatile and robust serial communication interface. The eCAN module implemented in the C28x DSP is compatible with the CAN 2.0B standard (active).

TMS320x281x, 280x Peripheral Reference Guide (literature number SPRU566) describes the peripheral reference guides of the 28x digital signal processors (DSPs).

TMS320x281x, 280x Serial Communication Interface (SCI) Reference Guide (literature number SPRU051) describes the SCI that is a two-wire asynchronous serial port, commonly known as a UART. The SCI modules support digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format.

TMS320x281x, 280x Serial Peripheral Interface (SPI) Reference Guide (literature number SPRU059) describes the SPI – a high-speed synchronous serial input/output (I/O) port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is used for communications between the DSP controller and external peripherals or another controller.

3.3 V DSP for Digital Motor Control Application Report (literature number SPRA550). New generations

of motor control digital signal processors (DSPs) lower their supply voltages from 5 V to 3.3 V to offer higher performance at lower cost. Replacing traditional 5-V digital control circuitry by 3.3-V designs introduce no additional system cost and no significant complication in interfacing with TTL and CMOS compatible components, as well as with mixed voltage ICs such as power transistor gate drivers. Just like 5-V based designs, good engineering practice should be exercised to minimize noise and EMI effects by proper component layout and PCB design when 3.3-V DSP, ADC, and digital circuitry are used in a mixed signal environment, with high and low voltage analog and switching signals, such as a motor control system. In addition, software techniques such as Random PWM method can be used by special features of the Texas Instruments (TI) TMS320x24xx DSP controllers to significantly reduce noise effects caused by EMI radiation.

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This application report reviews designs of 3.3-V DSP versus 5-V DSP for low HP motor control applications. The application report first describes a scenario of a 3.3-V-only motor controller indicating that for most applications, no significant issue of interfacing between 3.3 V and 5 V exists. Cost-effective

3.3-V – 5-V interfacing techniques are then discussed for the situations where such interfacing is needed.

On-chip 3.3-V ADC versus 5-V ADC is also discussed. Sensitivity and noise effects in 3.3-V and 5-V ADC conversions are addressed. Guidelines for component layout and printed circuit board (PCB) design that can reduce system's noise and EMI effects are summarized in the last section.

The TMS320C28x Instruction Set Simulator Technical Overview (literature number SPRU608) describes the simulator, available within the Code Composer Studio for TMS320C2000 IDE, that simulates the instruction set of the C28x core.

TMS320C28x DSP/BIOS Application Programming Interface (API) Reference Guide (literature number SPRU625) describes development using DSP/BIOS.

TMS320C28x Assembly Language Tools User's Guide (literature number SPRU513) describes the assembly language tools (assembler and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the TMS320C28x™ device.

TMS320C28x Optimizing C Compiler User's Guide (literature number SPRU514) describes the TMS320C28x™ C/C++ compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320™ DSP assembly language source code for the TMS320C28x device.

A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal processing research and education. The TMS320™ DSP newsletter, Details on Signal Processing, is published quarterly and distributed to update TMS320™ DSP customers on product information.

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Updated information on the TMS320™ DSP controllers can be found on the worldwide web at:

http://www.ti.com .

To send comments regarding this TMS320F281x/TMS320C281x data manual (literature number SPRS174), use the commentsatbooks.sc.ti.com email address, which is a repository for feedback. For questions and support, contact the Product Information Center listed at the

http://www.ti.com/sc/docs/pic/home.htm site.

6 Electrical Specifications

This section provides the absolute maximum ratings and the recommended operating conditions for the SM/SMJ320F2812 DSP.

6.1 Absolute Maximum Ratings

Unless otherwise noted, the list of absolute maximum ratings are specified over operating temperature ranges. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.2 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to VSS.

VALUE UNIT

Supply voltage range, V AV

DDREFBG

Supply voltage range, VDD, V V Input voltage range, V Output voltage range, V Input clamp current, IIK(VIN< 0 or VIN> V Output clamp current, IOK(VO< 0 or VO> V Operating ambient temperature range, T

(1) Continuous clamp current per pin is ±2 mA (2) Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device

life.

range –0.3 to 4.6 V

DD3VFL

DDIO

, V

DD1

DDA1

, V

DDA2

, V

, and

DDAIO

(1)

)

DDIO

) ±20 mA

DDIO

(2)

S Temp –55 to 220 °C

–0.3 to 4.6 V –0.5 to 2.5 V

–0.3 to 4.6 V –0.3 to 4.6 V

±20 mA

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6.2 Recommended Operating Conditions

(1)

See

DDIO

VDD, V

DD1

, V

DDA1

DDREFBG

DD3VFL

SYSCLKOUT

DDA2

, V

Device supply voltage, I/O 3.14 3.3 3.47 V

Device supply voltage, CPU V

1.8 V (135 MHz) 1.71 1.8 1.89

1.9 V (150 MHz) 1.81 1.9 2

Supply ground 0 V

ADC supply voltage 3.14 3.3 3.47 V

DDAIO

Flash programming supply voltage

Device clock frequency (system clock)

High-level input voltage V

Low-level input voltage V

VDD= 1.9 V ± 5% 2 150 VDD= 1.8 V ± 5% 2 135 All inputs except XCLKIN 2 V XCLKIN (at 50 mA max) 0.7V All inputs except XCLKIN 0.8 XCLKIN (at 50 mA max) 0.3V

High-level output source All I/Os except Group 2 –4

(1) See Section 6.7 for power sequencing of V (2) Group 2 pins are as follows: XINTF pins, PDPINTA, TDO, XCLKOUT, XF, EMU0, and EMU1.

current, mA VOH= 2.4 V

Low-level output sink current, VOL= VOLMAX

(2)

Group 2 All I/Os except Group 2 4

(2)

Group 2

Ambient temperature –55 25 220 °C

, V

DDIO

DDAIO

, VDD, V

DDA1/VDDA2

/AV

DDREFBG

, and V

In Revision C, EVA (GPIOA0–GPIOA15) and GPIOD0 are 4 mA drive.

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MIN NOM MAX UNIT

3.14 3.3 3.47 V

MHz

DDIO

–8

DD3VFL

6.3 Electrical Characteristics

Over recommended operating conditions (unless otherwise noted)

(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

IOH= IOHMAX 2.4

High-level output voltage V

Low-level output voltage IOL= IOLMAX 0.4 V

Input

current mA

(low level)

With pullup

With pulldown V

Input With pullup V current

(high level)

Output current,

high-impedance state (off-state)

Input capacitance 7 pF

Output capacitance 7 pF

With pulldown

(3)

IOH= 50 mA

(2)

= 3.3 V,

DDIO

VIN= 0 V

= 3.3 V, VIN= 0 V ±2

DDIO

= 3.3 V, VIN= V

DDIO

= 3.3 V,

DDIO

VIN= V

VO= V

DDIO

All I/Os except EVB

GPIOB/EVB –13 –25 –35

or 0 V ±2 mA

(including XRS)

DDIO

– 0.2

–80 –140 –190

28 50 80

±2

(1) Minimum and maximum parameters are characterized for operation at TA= 220°C unless otherwise noted, but may not be production

tested at that temperature. Production test limits with statistical guardbands are used to ensure high temperature performance. (2) The following pins have no internal PU/PD: GPIOE0, GPIOE1, GPIOF0, GPIOF1, GPIOF2, GPIOF3, GPIOF12, GPIOG4, and GPIOG5. (3) The following pins have an internal pulldown: XMP/MC, TESTSEL, and TRST.

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1.00E+06

1.00E+05

1.00E+04

1.00E+03

1.00E+02 70 150 200 220

Die Junction Temperature (°C)

Hours

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Notes:

1. See data sheet for absolute maximum and minimum recommended operating conditions.

2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package

SGUS062A–JUNE 2009–REVISED APRIL 2010

Figure 6-1. SM320F2812-HT Life Expectancy Curve

interconnect life).

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6.4 Current Consumption by Power-Supply Pins Over Recommended Operating Conditions During Low-Power Modes at 150-MHz SYSCLKOUT

TA= –55°C to 125°C TA= 220°C

MODE TEST CONDITIONS I

All peripheral clocks are enabled. All PWM pins are toggled at 100 kHz. Data is continuously

Operational SCIA, SCIB, and 195 mA 230 mA 15 mA 30 mA 40 mA 45 mA 40 mA 50 mA 275 mA 330 mA 17 mA 30 mA 45 mA 50 mA 40 mA 52 mA

IDLE 125 mA 150 mA 5 mA 10 mA 2 mA 4 mA 1 mA 35 mA 200 mA 10 mA 56 mA 100 mA 320 mA 450 mA

STANDBY are turned off 5 mA 10 mA 5 mA 20 mA 2 mA 4 mA 1 mA 35 mA 27 mA 40 mA 160 mA 200 mA 56 mA 100 mA 320 mA 450 mA

HALT –Pins without an 70 mA 5 mA 20 mA 2 mA 4 mA 1mA 35 mA 9.8 mA 160 mA 200 mA 56 mA 100 mA 320 mA 450 mA

(1) I (2) MAX numbers are at 125°C, and max voltage (VDD= 2.0 V; V

transmitted out of the CAN ports. The

hardware multiplier is exercised. Code is running out of flash with 5 wait-states.

–Flash is powered down –XCLKOUT is turned off –All peripheral clocks are on, except ADC

–Flash is powered down –Peripheral clocks

–Pins without an internal PU/PD are tied high/low

–Flash is powered down –Peripheral clocks are turned off

internal PU/PD are tied high/low – Input clock is disabled

includes current into V

DDA

TYP MAX

, V

DDA1

DDA2

(2)

, V

DDIO

TYP MAX

, AV

DD1

(2)

TYP MAX

DDREFBG

DD3VFL

, and V

DDIO

(2)

DDAIO

, V

(1)

DDA

TYP MAX

pins.

, V

DD3VFL

(2)

DDA

TYP MAX TYP MAX TYP MAX TYP MAX

= 3.6 V).

DDIO

DD3VFL

(1)

DDA

NOTE

HALT and STANDBY modes cannot be used when the PLL is disabled.

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100

150

200

250

0 20 40 60 80 100 120 140 160

SYSCLKOUT (MHz)

IDD

IDDIO

IDD3VFL IDDA Total 3.3−V current

Current (mA)

100

200

300

400

500

600

700

0 20 40 60 80 100 120 140 160

SYSCLKOUT (MHz)

TOTAL POWER

Power (mW)

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6.5 Current Consumption Graphs

A. Test conditions are as defined in Table 6-5 for operational currents under nominal process voltage and temperature

conditions.

B. IDDrepresents the total current drawn from the 1.8-V rail (VDD). It includes a trivial amount of current (<1 mA) drawn

by V

. C. IDDA represents the current drawn by VDDA1 and VDDA2 rails. D. Total 3.3-V current is the sum of I

DD1

VDDAIO.

DDIO

, I

DD3VFL

, and I

. It includes a trivial amount of current (<1 mA) drawn by

DDA

Figure 6-2. Typical Current Consumption Over Frequency

Figure 6-3. Typical Power Consumption Over Frequency

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6.6 Reducing Current Consumption

28x DSPs incorporate a unique method to reduce the device current consumption. A reduction in current consumption can be achieved by turning off the clock to any peripheral module which is not used in a given application. Table 6-1 indicates the typical reduction in current consumption achieved by turning off the clocks to various peripherals.

Table 6-1. Typical Current Consumption by Various Peripherals (at 150 MHz)

PERIPHERAL MODULE IDDCURRENT REDUCTION (mA)

eCAN 12

EVA 6 EVB 6 ADC 8

SCI 4 SPI 5

McBSP 13

(1) All peripheral clocks are disabled upon reset. Writing to/reading from peripheral registers is

possible only after the peripheral clocks are turned on.

(2) Not production tested. (3) This number represents the current drawn by the digital portion of the ADC module. Turning off the

clock to the ADC module results in the elimination of the current drawn by the analog portion of the ADC (I

CCA

) as well.

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(1)

(2)

(3)

6.7 Power Sequencing Requirements

SM320F2812 silicon requires dual voltages (1.8-V or 1.9-V and 3.3-V) to power up the CPU, Flash, ROM, ADC, and the I/Os. To ensure the correct reset state for all modules during power up, there are some requirements to be met while powering up/powering down the device. The current F2812 silicon reference schematics (Spectrum Digital Incorporated eZdsp. board) suggests two options for the power sequencing circuit.

• Option 1: In this approach, an external power sequencing circuit enables V

1.9 V). After 1.8 V (or 1.9 V) ramps, the 3.3 V for Flash (V modules are ramped up. While option 1 is still valid, TI has simplified the requirement. Option 2 is the recommended approach.

• Option 2: Enable power to all 3.3-V supply pins (V

1.8 V (or 1.9 V) (VDD/V

1.8 V or 1.9 V (VDD/V signal from the I/O pin has propagated through the I/O buffer to provide power-on reset to all the modules inside the device. See Figure 6-8 for power-on reset timing.

• Power-Down Sequencing: During power-down, the device reset should be asserted low (8 ms, minimum) before the VDDsupply reaches 1.5 V. This helps to keep on-chip flash logic in reset prior to the V ramping down. It is recommended that the device reset control from Low-Dropout (LDO) regulators or voltage supervisors be used to meet this constraint. LDO regulators that facilitate power-sequencing (with the aid of additional external components) may be used to meet the power sequencing requirement. See www.spectrumdigital.com for F2812 eZdsp™ schematics and updates.

) supply pins.

DD1

) should not reach 0.3 V until V

DD1

DDIO

, V

DD3VFL

DDIO

) and ADC (V

DD3VFL

, V

DDA1/VDDA2/VDDAIO

has reached 2.5 V. This ensures the reset

DDIO

first, then VDDand V

DDA1/VDDA2

/AV

DDREFBG

DDIO/VDD

/AV

) and thenramp

power supplies

(1.8 V or

DD1

DDREFBG

)

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SeeFigure6-8,

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Table 6-2. Recommended Low-Dropout Regulators

SUPPLIER PART NUMBER

Texas Instruments TPS767D301

NOTE

The GPIO pins are undefined until VDD= 1 V and V

DDIO

SGUS062A–JUNE 2009–REVISED APRIL 2010

= 2.5 V.

Figure 6-4. F2812 Typical Power-Up and Power-Down Sequence – Option 2

6.8 Signal Transition Levels

Note that some of the signals use different reference voltages, see the recommended operating conditions table. Output levels are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of

0.4 V.

Figure 6-5 shows output levels.

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0.4 V (VOL)

20%

2.4 V (VOH) 80%

0.8 V (VIL)

10%

2.0 V (VIH) 90%

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Output transition times are specified as follows:

• For a high-to-low transition, the level at which the output is said to be no longer high is below 80% of the total voltage range and lower and the level at which the output is said to be low is 20% of the total voltage range and lower.

• For a low-to-high transition, the level at which the output is said to be no longer low is 20% of the total voltage range and higher and the level at which the output is said to be high is 80% of the total voltage range and higher.

Figure 6-6 shows the input levels.

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Figure 6-5. Output Levels

Figure 6-6. Input Levels

Input transition times are specified as follows:

• For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is 90% of the total voltage range and lower and the level at which the input is said to be low is 10% of the total voltage range and lower.

• For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is 10% of the total voltage range and higher and the level at which the input is said to be high is 90% of the total voltage range and higher.

See the individual timing diagrams for levels used for testing timing parameters.

6.9 Timing Parameter Symbology

Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows:

Lowercase subscripts and their meanings: Letters and symbols and their meanings: a access time H High c cycle time (period) L Low d delay time V Valid f fall time X Unknown, changing, or don’t care level h hold time Z High impedance r rise time su setup time t transition time v valid time w pulse duration (width)

NOTE

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Transmission Line

4.0 pF 1.85 pF

Z0 = 50 Ω (see note)

Tester Pin Electronics

Data Sheet Timing Reference Point

Output Under Test

NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must

be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.

42 Ω 3.5 nH

Device Pin (see note)

Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.

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6.10 General Notes on Timing Parameters

All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.

The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For actual cycle examples, see the appropriate cycle description section of this document.

6.11 Test Load Circuit

This test load circuit is used to measure all switching characteristics provided in this document.

SGUS062A–JUNE 2009–REVISED APRIL 2010

Figure 6-7. 3.3-V Test Load Circuit

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6.12 Device Clock Table

This section provides the timing requirements and switching characteristics for the various clock options available on the F2812 DSP. Table 6-3 lists the cycle times of various clocks.

Table 6-3. Clock Table and Nomenclature

MIN NOM MAX UNIT

, Cycle time 28.6 50 ns

On-chip oscillator clock

XCLKIN

SYSCLKOUT

XCLKOUT

HSPCLK

LSPCLK

ADC clock

SPI clock

McBSP

XTIMCLK

(1) This is the default reset value if SYSCLKOUT = 150 MHz. (2) The maximum value for ADCCLK frequency is 25 MHz. For SYSCLKOUT values of 25 MHz or lower, ADCCLK has to be

SYSCLKOUT/2 or lower. ADCCLK = SYSCLKOUT is not a valid mode for any value of SYSCLKOUT.

c(OSC)

Frequency 20 35 MHz t

, Cycle time 6.67 250 ns

c(CI)

Frequency 4 150 MHz t

, Cycle time 6.67 500 ns

c(SCO)

Frequency 2 150 MHz t

, Cycle time 6.67 2000 ns

c(XCO)

Frequency 0.5 150 MHz t

, Cycle time 6.67 13.3

c(HCO)

Frequency 75 t

, Cycle time 13.3 26.6

c(LCO)

Frequency 37.5 t

c(ADCCLK)

, Cycle time

(2)

40 ns

(1) (1) (1) (1)

150 MHz

Frequency 25 MHz t

, Cycle time 50 ns

c(SPC)

Frequency 20 MHz t

, Cycle time 50 ns

c(CKG)

Frequency 20 MHz t

, Cycle time 6.67 ns

c(XTIM)

Frequency 150 MHz

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75 MHz

6.13 Clock Requirements and Characteristics

6.13.1 Input Clock Requirements

The clock provided at the XCLKIN pin generates the internal CPU clock cycle.

Table 6-4. Input Clock Frequency

PARAMETER MIN TYP MAX UNIT

Resonator

Input clock frequency Crystal

XCLKIN 4 150

Limp mode clock frequency 2 MHz

(1) Not production tested. (2) Not guaranteed for TA> 125°C.

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(2)

(1)

20 35 20 35 MHz

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Table 6-5. XCLKIN Timing Requirements – PLL Bypassed or Enabled

SGUS062A–JUNE 2009–REVISED APRIL 2010

(1)

NO. MIN MAX UNIT

C8 t

C9 t

C10 t

C11 t C12 t

c(CI)

f(CI)

r(CI)

w(CIL) w(CIH)

Cycle time, XCLKIN 6.67 250 ns

Fall time, XCLKIN ns

Rise time, XCLKIN ns

Pulse duration, X1/XCLKIN low as a percentage of t Pulse duration, X1/XCLKIN high as a percentage of t

c(CI)

Up to 30 MHz 6 30 MHz to 150 MHz 2 Up to 30 MHz 6 30 MHz to 150 MHz 2

40 60 % 40 60 %

(1) Not production tested.

Table 6-6. XCLKIN Timing Requirements – PLL Disabled

(1)

NO. MIN MAX UNIT

C8 t

C9 t

C10 t

C11 t

C12 t

c(CI)

f(CI)

r(CI)

w(CIL)

w(CIH)

Cycle time, XCLKIN 6.67 250 ns

Fall time, XCLKIN ns

Rise time, XCLKIN ns

Pulse duration, X1/XCLKIN low as a percentage of t

Pulse duration, X1/XCLKIN high as a percentage of t

c(CI)

Up to 30 MHz 6 30 MHz to 150 MHz 2 Up to 30 MHz 6 30 MHz to 150 MHz 2 XCLKIN ≤ 120 MHz 40 60

c(CI)

120 < XCLKIN ≤ 150 MHz 45 55 XCLKIN ≤ 120 MHz 40 60 120 < XCLKIN ≤ 150 MHz 45 55

(1) Not production tested.

Table 6-7. Possible PLL Configuration Modes

(1)

PLL MODE REMARKS SYSCLKOUT

PLL Disabled XCLKIN

Invoked by tying XPLLDIS pin low upon reset. PLL block is completely disabled. Clock input to the CPU (CLKIN) is directly derived from the clock signal present at the X1/XCLKIN pin.

Default PLL configuration upon power-up, if PLL is not disabled. The PLL itself is bypassed.

PLL Bypassed However, the /2 module in the PLL block divides the clock input at the X1/XCLKIN pin by two before XCLKIN/2

feeding it to the CPU.

PLL Enabled (XCLKIN × n)/2

Achieved by writing a non-zero value n into PLLCR register. The /2 module in the PLL block now divides the output of the PLL by two before feeding it to the CPU.

(1) Not production tested.

6.13.2 Output Clock Characteristics

Table 6-8. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)

NO. PARAMETER MIN TYP MAX UNIT

C1 t

(4)

c(XCO)

f(XCO)

r(XCO)

w(XCOL)

w(XCOH)

Cycle time, XCLKOUT 6.67 Fall time, XCLKOUT 2 ns Rise time, XCLKOUT 2 ns Pulse duration, XCLKOUT low H–2 H+2 ns Pulse duration, XCLKOUT high H–2 H+2 ns PLL lock time

(5)

(1) A load of 40 pF is assumed for these parameters. (2) H = 0.5t (3) The PLL must be used for maximum frequency operation.

c(XCO)

(4) Not production tested.. (5) This parameter has changed from 4096 XCLKIN cycles in the earlier revisions of the silicon.

(3)

(1) (2)

131 072t

c(CI)

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SeeNote A

SeeNoteB

SM320F2812-HT

SGUS062A–JUNE 2009–REVISED APRIL 2010

A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown in

Figure 6-8 is intended to illustrate the timing parameters only and may differ based on configuration.

B. XCLKOUT configured to reflect SYSCLKOUT.

Figure 6-8. Clock Timing

6.14 Reset Timing

Table 6-9. Reset (XRS) Timing Requirements

w(RSL1)

w(RSL2)

w(WDRS)

d(EX)

(3)

OSCST

su(XPLLDIS)

h(XPLLDIS)

h(XMP/MC)

h(boot-mode)

(1) If external oscillator/clock source isused, reset time has to be low at least for 1 ms after VDDreaches 1.5 V. (2) Not production tested. (3) Dependent on crystal/resonator and board design. (4) The boot ROM reads the password locations. Therefore, this timing requirement includes the wakeup time for flash. See the

TMS320x281x Boot ROM Reference Guide (literature number SPRU095) and TMS320x281x System Control and Interrupts Reference Guide (literature number SPRU078) for further information.

Pulse duration, stable XCLKIN to XRS high 8t Pulse duration, XRS low Warm reset 8t

WD-initiated reset 512t

Pulse duration, reset pulse generated by watchdog

Delay time, address/data valid after XRS high 32t Oscillator start-up time 1 10 ms Setup time for XPLLDIS pin 16t Hold time for XPLLDIS pin 16t Hold time for XMP/MC pin 16t Hold time for boot-mode pins 2520t

(1) (2)

MIN NOM MAX UNIT

c(CI) c(CI)

c(CI)

512t

c(CI)

c(CI) c(CI) c(CI)

(4)

c(CI)

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cycles cycles

cycles cycles cycles cycles

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w(RSL1)

h(XPLLDIS)

h(XMP/MC)

h(boot-mode)

(See Note D)

DDIO

, V

DD3VFL

DDAn

, V

DDAIO

(3.3 V)

(See Note B)

XCLKIN

2.5 V

0.3 V

XRS

XF/XPLLDIS

XMP/MC

Boot-Mode Pins

VDD, V

DD1

(1.8 V (or 1.9 V))

XCLKOUT

I/O Pins

User-Code Dependent

Boot-ROM Execution Starts

Peripheral/GPIO Function Based on Boot Code

GPIO Pins as Input

XPLLDIS

Sampling

GPIOF14

XCLKIN/8 (See Note C)

GPIO Pins as Input (State Depends on Internal PU/PD)

OSCST

(Don’t Care)

User-Code Dependent

Address/Data/

Control

Address/Data Valid. Internal Boot-ROM Code Execution Phase

User-Code Execution Phase

NOTES: A. The state of the GPIO pins is undefined (i.e., they could be input or output) until the 1.8-V (or 1.9-V) supply reaches at least 1 V

and 3.3-V supply reaches 2.5 V.

B. V

DDAn

− V

DDA1/VDDA2

and AV

DDREFBG

C. Upon power up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the XINTCNF2

register come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why XCLKOUT = XCLKIN/8 during this phase.

D. After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) and then

samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function in ROM. The BOOT Mode pins should be held high/low for at least 2520 XCLKIN cycles from boot ROM execution time for proper selection of Boot modes. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT is based on user environment and could be with or without PLL enabled.

d(EX)

See Note A

su(XPLLDIS)

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Figure 6-9. Power-on Reset in Microcomputer Mode (XMP/MC = 0) (See Note A)

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w(RSL)

h(XPLLDIS)

h(XMP/MC)

OSCST

DDIO

, V

DD3VFL

DDAn

, V

DDAIO

(3.3 V)

XCLKIN

XRS

XF/XPLLDIS

XMP/MC

VDD, V

DD1

(1.8 V (or

1.9 V))

I/O Pins

XPLLDIS

Sampling

Address/Data/

Control

XCLKOUT

(Don’t Care)

GPIOF14/XF (User-Code Dependent)

XCLKIN/8 (See Note A)

(Don’t Care)

Input Configuration (State Depends on Internal PU/PD)

User-Code Dependent

Address/Data/Control Valid Execution

Begins From External Boot Address 0x3FFFC0

User-Code Dependent

2.5 V

0.3 V

d(EX)

NOTES: A. Upon power up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the XINTCNF2

register come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why XCLKOUT = XCLKIN/8 during this phase.

B. The state of the GPIO pins is undefined (i.e., they could be input or output) until the 1.8-V (or 1.9-V) supply reaches at least 1 V

and 3.3-V supply reaches 2.5 V ..

See Note B

su(XPLLDIS)

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Figure 6-10. Power-on Reset in Microprocessor Mode (XMP/MC = 1)

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XCLKIN/8

(XCLKIN * 5)

h(XPLLDIS)

h(XMP/MC)

h(boot-mode)

(see Note A)

w(RSL2)

XCLKIN

XRS

XF/XPLLDIS

XMP/MC

Boot-Mode Pins

XCLKOUT

I/O Pins

Address/Data/

Control

Boot-ROM Execution Starts

User-Code Execution Starts

User-Code Dependent

User-Code Execution Phase

(Don’t Care)

User-Code Dependent

User-Code Execution

Peripheral/GPIO Function

User-Code Dependent

GPIO Pins as Input (State Depends on Internal PU/PD)

GPIO Pins as Input

GPIOF14/XF

XPLLDIS

Sampling

GPIOF14

Peripheral/GPIO Function

d(EX)

su(XPLLDIS)

X1/XCLKIN

SYSCLKOUT

Write to PLLCR

XCLKIN x 2

(Current CPU

Frequency)

XCLKIN/2

(CPU Frequency While PLL is Stabilizing

With the Desired Frequency. This Period

(PLL Lock-up Time, tp) is

131072 XCLKIN Cycles Long.)

XCLKIN x 4

(Changed CPU Frequency)

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SGUS062A–JUNE 2009–REVISED APRIL 2010

A. After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) and

then samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function in ROM. The BOOT Mode pins should be held high/low for at least 2520 XCLKIN cycles from boot ROM execution time for proper selection of Boot modes. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT is based on user environment and could be with or without PLL enabled.

Figure 6-11. Warm Reset in Microcomputer Mode

Figure 6-12. Effect of Writing Into PLLCR Register

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WAKE INT

(see Note B)

XCLKOUT

(see Note A)

A0−A15

d(WAKE−IDLE)

w(WAKE−INT)

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6.15 Low-Power Mode Wakeup Timing

Table 6-10 is also the IDLE Mode Wake-Up Timing Requirements table.

c(SCO)

+ IQT

c(SCO)

+ IQT

c(SCO)

+ IQT

c(SCO)

+ IQT

(1)

Cycles

(2)

Cycles

(2)

Cycles

(2)

Cycles Cycles

(2)

Cycles

Table 6-10. IDLE Mode Switching Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

w(WAKE-INT)

Pulse duration, external wake-up signal

Delay time, external wake signal to program execution resume

–Wake-up from Flash –Flash module in active state

– Wake-up from Flash –Flash module in active state

d(WAKE-IDLE)

–Wake-up from Flash –Flash module in sleep state

–Wake-up from SARAM Without input qualifier 8 × t –Wake-up from SARAM With input qualifier 8 × t

(1) Not production tested. (2) Input Qualification Time (IQT) = [5 × QUALPRD × 2] × t (3) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered

by the wake-up) signal involves additional latency.

Without input qualifier 2 x t With input qualifier 1 × t

(3)

Without input qualifier 8 × t

With input qualifier 8 × t

Without input qualifier 1050 × t

With input qualifier 1050 × t

c(SCO)

A. XCLKOUT = SYSCLKOUT B. WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.

Figure 6-13. IDLE Entry and Exit Timing

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Texas Instruments SM320F2812-HT User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Features

1.1 SUPPORTS EXTREME TEMPERATURE APPLICATIONS

2 Introduction

2.1 Description

2.2 Device Summary

2.3 Die Layout

2.4 Pin Assignments

2.5 Signal Descriptions

3 Functional Overview

3.1 Memory Map

3.2 Brief Descriptions

3.2.1 C28x CPU

3.2.2 Memory Bus (Harvard Bus Architecture)

3.2.3 Peripheral Bus

3.2.4 Real-Time JTAG and Analysis

3.2.5 External Interface (XINTF)

3.2.6 Flash

3.2.7 L0, L1, H0 SARAMs

3.2.8 Boot ROM

3.2.9 Security

3.2.10 Peripheral Interrupt Expansion (PIE) Block

3.2.11 External Interrupts (XINT1, XINT2, XINT13, XNMI)

3.2.12 Oscillator and PLL

3.2.13 Watchdog

3.2.14 Peripheral Clocking

3.2.15 Low-Power Modes

3.2.16 Peripheral Frames 0, 1, 2 (PFn)

3.2.17 General-Purpose Input/Output (GPIO) Multiplexer

3.2.18 32-Bit CPU Timers (0, 1, 2)

3.2.19 Control Peripherals

3.2.20 Serial Port Peripherals

3.3 Register Map

3.4 Device Emulation Registers

3.5 External Interface, XINTF

3.5.1 Timing Registers

3.5.2 XREVISION Register

3.6 Interrupts

3.6.1 External Interrupts

3.7 System Control

3.8 OSC and PLL Block

3.8.1 Loss of Input Clock

3.9 PLL-Based Clock Module

3.10 External Reference Oscillator Clock Option

3.11 Watchdog Block

3.12 Low-Power Modes Block

4 Peripherals

4.1 32-Bit CPU-Timers 0/1/2

4.2 Event Manager Modules (EVA, EVB)

4.2.1 General-Purpose (GP) Timers

4.2.2 Full-Compare Units

4.2.3 Programmable Deadband Generator

4.2.4 PWM Waveform Generation

4.2.5 Double Update PWM Mode

4.2.6 PWM Characteristics

4.2.7 Capture Unit

4.2.8 Quadrature-Encoder Pulse (QEP) Circuit

4.2.9 External ADC Start-of-Conversion

4.3 Enhanced Analog-to-Digital Converter (ADC) Module

4.4 Enhanced Controller Area Network (eCAN) Module

4.5 Multichannel Buffered Serial Port (McBSP) Module

4.6 Serial Communications Interface (SCI) Module

4.7 Serial Peripheral Interface (SPI) Module

4.8 GPIO MUX

5 Development Support

5.1 Device and Development Support Tool Nomenclature

5.2 Documentation Support

6 Electrical Specifications

6.1 Absolute Maximum Ratings

6.2 Recommended Operating Conditions

6.3 Electrical Characteristics

6.4 Current Consumption by Power-Supply Pins Over Recommended Operating Conditions During Low-Power Modes at 150-MHz SYSCLKOUT

6.5 Current Consumption Graphs

6.6 Reducing Current Consumption

6.7 Power Sequencing Requirements

6.8 Signal Transition Levels

6.9 Timing Parameter Symbology