TEXAS INSTRUMENTS SM320F2810-EP Technical data
查询SM320C2810-EP供应商查询SM320C2810-EP供应商
SM320F2810-EP, SM320F2811-EP,
SM320C2810-EP, SM320C2811-EP,
SM320F2812-EP
SM320C2812-EP
Digital Signal Processors
Data Manual
Literature Number: SGUS051A
March 2004 − Revised October 2004
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Contents
Contents
Section Page
1 Features 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Introduction 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Description 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Device Summary 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Pin Assignments 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1 Terminal Assignments for the GHH Package 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2 Pin Assignments for the PGF Package 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.3 Pin Assignments for the PBK Package 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Signal Descriptions 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Functional Overview 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Memory Map 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Brief Descriptions 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 C28x CPU 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 Memory Bus (Harvard Bus Architecture) 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3 Peripheral Bus 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.4 Real-Time JTAG and Analysis 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.5 External Interface (XINTF) (2812 Only) 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.6 Flash (F281x Only) 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.7 ROM (C281x Only) 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.8 M0, M1 SARAMs 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.9 L0, L1, H0 SARAMs 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.10 Boot ROM 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.11 Security 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.12 Peripheral Interrupt Expansion (PIE) Block 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.13 External Interrupts (XINT1, 2, 13, XNMI) 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.14 Oscillator and PLL 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.15 Watchdog 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.16 Peripheral Clocking 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.17 Low-Power Modes 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.18 Peripheral Frames 0, 1, 2 (PFn) 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.19 General-Purpose Input/Output (GPIO) Multiplexer 37. . . . . . . . . . . . . . . . . . . . . . . .
3.2.20 32-Bit CPU-Timers (0, 1, 2) 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.21 Control Peripherals 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.22 Serial Port Peripherals 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Register Map 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Device Emulation Registers 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 External Interface, XINTF (2812 Only) 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1 Timing Registers 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.2 XREVISION Register 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Interrupts 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1 External Interrupts 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 System Control 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8 OSC and PLL Block 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.1 Loss of Input Clock 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9 PLL-Based Clock Module 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10 External Reference Oscillator Clock Option 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11 Watchdog Block 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
March 2004 − Revised October 2004 SGUS051A
3
Contents
3.12 Low-Power Modes Block 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Peripherals 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 32-Bit CPU-Timers 0/1/2 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Event Manager Modules (EVA, EVB) 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1 General-Purpose (GP) Timers 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2 Full-Compare Units 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.3 Programmable Deadband Generator 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.4 PWM Waveform Generation 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.5 Double Update PWM Mode 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.6 PWM Characteristics 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.7 Capture Unit 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.8 Quadrature-Encoder Pulse (QEP) Circuit 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.9 External ADC Start-of-Conversion 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Enhanced Analog-to-Digital Converter (ADC) Module 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Enhanced Controller Area Network (eCAN) Module 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Multichannel Buffered Serial Port (McBSP) Module 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 Serial Communications Interface (SCI) Module 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 Serial Peripheral Interface (SPI) Module 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8 GPIO MUX 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Development Support 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Device and Development Support Tool Nomenclature 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 Documentation Support 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Electrical Specifications 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 Absolute Maximum Ratings 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Recommended Operating Conditions† 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Electrical Characteristics Over Recommended Operating Conditions
(Unless Otherwise Noted) 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4 Current Consumption by Power-Supply Pins Over Recommended Operating Conditions
During Low-Power Modes at 150-MHz SYSCLKOUT (320F281x) 91. . . . . . . . . . . . . . . . . . . . . . .
6.5 Current Consumption by Power-Supply Pins Over Recommended Operating Conditions
During Low-Power Modes at 150-MHz SYSCLKOUT (320C281x) 92. . . . . . . . . . . . . . . . . . . . . .
6.6 Current Consumption Graphs 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7 Reducing Current Consumption 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8 Power Sequencing Requirements 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9 Signal Transition Levels 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10 Timing Parameter Symbology 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.11 General Notes on Timing Parameters 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12 Test Load Circuit 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13 Device Clock Table 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14 Clock Requirements and Characteristics 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.1 Input Clock Requirements 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.2 Output Clock Characteristics 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.15 Reset Timing 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.16 Low-Power Mode Wakeup Timing 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17 Event Manager Interface 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17.1 PWM Timing 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17.2 Interrupt Timing 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.18 General-Purpose Input/Output (GPIO) − Output Timing 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.19 General-Purpose Input/Output (GPIO) − Input Timing 112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.20 SPI Master Mode Timing 113. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.21 SPI Slave Mode Timing 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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March 2004 − Revised October 2004SGUS051A
Contents
6.22 External Interface (XINTF) Timing 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.23 XINTF Signal Alignment to XCLKOUT 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.24 External Interface Read Timing 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.25 External Interface Write Timing 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.26 External Interface Ready-on-Read Timing With One External Wait State 126. . . . . . . . . . . . . . . .
6.27 External Interface Ready-on-Write Timing With One External Wait State 129. . . . . . . . . . . . . . . .
6.28 XHOLD
and XHOLDA 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.29 XHOLD/XHOLDA Timing 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.30 On-Chip Analog-to-Digital Converter 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.30.1 ADC Absolute Maximum Ratings† 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.30.2 ADC Electrical Characteristics Over Recommended Operating Conditions 136. .
6.30.3 Current Consumption for Different ADC Configurations
(at 25-MHz ADCCLK) 137. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.30.4 ADC Power-Up Control Bit Timing 138. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.30.5 Detailed Description 139. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.30.6 Sequential Sampling Mode (Single-Channel) (SMODE = 0) 139. . . . . . . . . . . . . . .
6.30.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) 141. . . . . . . . . . . . . .
6.30.8 Definitions of Specifications and Terminology 142. . . . . . . . . . . . . . . . . . . . . . . . . . .
6.31 Multichannel Buffered Serial Port (McBSP) Timing 143. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.31.1 McBSP Transmit and Receive Timing 143. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.31.2 McBSP as SPI Master or Slave Timing 146. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.32 Flash Timing (F281x Only) 150. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.32.1 Recommended Operating Conditions 150. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 Mechanical Data 151. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Ball Grid Array (BGA) 151. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Plastic Ball Grid Array 152. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 Low-Profile Quad Flatpacks (LQFPs) 153. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision History 155. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
March 2004 − Revised October 2004 SGUS051A
5
Figures
List of Figures
Figure Page
2−1. 320F2812 and 320C2812 179-Ball GHH MicroStar BGA (Bottom View) 14. . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2. 320F2812 and 320C2812 176-Pin PGF LQFP (Top View) 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−3. 320F2810, 320F2811, 320C2810, and 320C2811 128-Pin PBK
LQFP (Top View) 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1. Functional Block Diagram 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2. F2812/C2812 Memory Map 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3. F2811/C2811 Memory Map 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4. F2810/C2810 Memory Map 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5. External Interface Block Diagram 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6. Interrupt Sources 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−7. Multiplexing of Interrupts Using the PIE Block 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−8. Clock and Reset Domains 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−9. OSC and PLL Block 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−10. Recommended Crystal/Clock Connection 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−11. Watchdog Module 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1. CPU-Timers 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−2. CPU-Timer Interrupts Signals and Output Signal 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−3. Event Manager A Functional Block Diagram 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4. Block Diagram of the F281x and C281x ADC Module 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−5. ADC Pin Connections With Internal Reference 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−6. ADC Pin Connections With External Reference 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−7. eCAN Block Diagram and Interface Circuit 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−8. eCAN Memory Map 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−9. McBSP Module With FIFO 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−10. Serial Communications Interface (SCI) Module Block Diagram 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−11. Serial Peripheral Interface Module Block Diagram (Slave Mode) 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−12. Modes of Operation 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−1. TMS320x28x Device Nomenclature 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−1. FIT Rate vs Operating Junction Temperature 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−2. Package Lifetime vs Operating Junction Temperature 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−3. F2812/F2811/F2810 Typical Current Consumption (With Peripheral Clocks Enabled) 93. . . . . . . . . . . . . . . .
6−4. F2812/F2811/F2810 Typical Power-Up and Power-Down Sequence − Option 2 95. . . . . . . . . . . . . . . . . . . . .
6−5. Output Levels 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−6. Input Levels 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−7. 3.3-V Test Load Circuit 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−8. Clock Timing 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−9. Power-on Reset in Microcomputer Mode (XMP/MC = 0) 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−10. Power-on Reset in Microprocessor Mode (XMP/MC = 1) 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−11. Warm Reset in Microcomputer Mode 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−12. Effect of Writing Into PLLCR Register 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−13. IDLE Entry and Exit Timing 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
March 2004 − Revised October 2004SGUS051A
6−14. STANDBY Entry and Exit Timing 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−15. HALT Wakeup Using XNMI 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−16. PWM Output Timing 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−17. TDIRx Timing 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−18. EVASOC
Timing 109. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−19. EVBSOC Timing 109. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−20. External Interrupt Timing 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−21. General-Purpose Output Timing 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−22. GPIO Input Qualifier − Example Diagram for QUALPRD = 1 112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−23. General-Purpose Input Timing 112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−24. SPI Master Mode External Timing (Clock Phase = 0) 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−25. SPI Master External Timing (Clock Phase = 1) 116. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−26. SPI Slave Mode External Timing (Clock Phase = 0) 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−27. SPI Slave Mode External Timing (Clock Phase = 1) 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−28. Relationship Between XTIMCLK and SYSCLKOUT 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−29. Example Read Access 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−30. Example Write Access 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−31. Example Read With Synchronous XREADY Access 127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−32. Example Read With Asynchronous XREADY Access 128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−33. Write With Synchronous XREADY Access 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−34. Write With Asynchronous XREADY Access 131. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−35. External Interface Hold Waveform 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−36. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) 134. . . . . . . . . . . . . . . . . . . . . . . . . . .
6−37. ADC Analog Input Impedance Model 138. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−38. ADC Power-Up Control Bit Timing 138. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−39. Sequential Sampling Mode (Single-Channel) Timing 140. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−40. Simultaneous Sampling Mode Timing 141. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−41. McBSP Receive Timing 145. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−42. McBSP Transmit Timing 145. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−43. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 146. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−44. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 147. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−45. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 148. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−46. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 149. . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−1. 320F2812 and 320C2812 179-Ball GHH MicroStar BGA 151. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−2. 320F2812 and 320C2812 176-Pin PGF LQFP 152. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−3. TMS320F2810, TMS320F2811, TMS320C2810, and TMS320C2811 128-Pin PBK LQFP 153. . . . . . . . . . .
Figures
March 2004 − Revised October 2004 SGUS051A
7
Tables
List of Tables
Table Page
2−1. Hardware Features 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2. Signal Descriptions 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1. Addresses of Flash Sectors in F2812 and F2811 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2. Addresses of Flash Sectors in F2810 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3. Wait States 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4. Peripheral Frame 0 Registers 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5. Peripheral Frame 1 Registers 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6. Peripheral Frame 2 Registers 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−7. Device Emulation Registers 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−8. XINTF Configuration and Control Register Mappings 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−9. XREVISION Register Bit Definitions 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−10. PIE Peripheral Interrupts 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−11. PIE Configuration and Control Registers 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−12. External Interrupts Registers 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−13. PLL, Clocking, Watchdog, and Low-Power Mode Registers 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−14. PLLCR Register Bit Definitions 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−15. Possible PLL Configuration Modes 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−16. F281x and C281x Low-Power Modes 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1. CPU-Timers 0, 1, 2 Configuration and Control Registers 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−2. Module and Signal Names for EVA and EVB 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−3. EVA Registers 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4. ADC Registers 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−5. 3.3-V eCAN Transceivers for the 320F281x and 320C281x DSPs 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−6. CAN Registers Map 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−7. McBSP Register Summary 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−8. SCI-A Registers 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−9. SCI-B Registers 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−10. SPI Registers 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−11. GPIO Mux Registers 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−12. GPIO Data Registers 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−1. Typical Current Consumption by Various Peripherals (at 150 MHz) 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−2. Recommended “Low-Dropout Regulators” 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−3. 320F281x and 320C281x Clock Table and Nomenclature 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−4. Input Clock Frequency 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−5. XCLKIN Timing Requirements − PLL Bypassed or Enabled 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−6. XCLKIN Timing Requirements − PLL Disabled 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−7. Possible PLL Configuration Modes 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−8. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−9. Reset (XRS) Timing Requirements 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−10. IDLE Mode Switching Characteristics 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−11. STANDBY Mode Switching Characteristics 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−12. HALT Mode Switching Characteristics 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−13. PWM Switching Characteristics 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−14. Timer and Capture Unit Timing Requirements 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−15. External ADC Start-of-Conversion − EVA − Switching Characteristics 109. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−16. External ADC Start-of-Conversion − EVB − Switching Characteristics 109. . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
March 2004 − Revised October 2004SGUS051A
6−17. Interrupt Switching Characteristics 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−18. Interrupt Timing Requirements 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−19. General-Purpose Output Switching Characteristics 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−20. General-Purpose Input Timing Requirements 112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−21. SPI Master Mode External Timing (Clock Phase = 0) 113. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−22. SPI Master Mode External Timing (Clock Phase = 1) 115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−23. SPI Slave Mode External Timing (Clock Phase = 0) 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−24. SPI Slave Mode External Timing (Clock Phase = 1) 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−25. Relationship Between Parameters Configured in XTIMING and Duration of Pulse 120. . . . . . . . . . . . . . . . .
6−26. XINTF Clock Configurations 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−27. External Memory Interface Read Switching Characteristics 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−28. External Memory Interface Read Timing Requirements 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−29. External Memory Interface Write Switching Characteristics 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−30. External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State) 126. . . . . . . . .
6−31. External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) 126. . . . . . . . . . . .
6−32. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) 126. . . . . . . . . . . . . . . . . . . . .
6−33. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) 126. . . . . . . . . . . . . . . . . . . .
6−34. External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) 129. . . . . . . .
6−35. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) 129. . . . . . . . . . . . . . . . . . . . .
6−36. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) 129. . . . . . . . . . . . . . . . . . . .
6−37. XHOLD
/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−38. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) 134. . . . . . . . . . . . . . . . . . . . . . . . . . .
6−39. DC Specifications 136. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−40. AC Specifications 137. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−41. ADC Power-Up Delays 138. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−42. Sequential Sampling Mode Timing 140. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−43. Simultaneous Sampling Mode Timing 141. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−44. McBSP Timing Requirements 143. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−45. McBSP Switching Characteristics 144. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−46. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) 146. . . . . . . . . . . . . . .
6−47. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) 146. . . . . . . . . . .
6−48. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) 147. . . . . . . . . . . . . . .
6−49. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) 147. . . . . . . . . . .
6−50. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) 148. . . . . . . . . . . . . . .
6−51. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) 148. . . . . . . . . . .
6−52. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) 149. . . . . . . . . . . . . . .
6−53. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) 149. . . . . . . . . . .
6−54. Flash Parameters at 150-MHz SYSCLKOUT 150. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−55. Flash/OTP Access Timing 150. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−56. Minimum Required Wait-States at Different Frequencies 150. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−1. Thermal Resistance Characteristics for 179-GHH 151. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−2. Thermal Resistance Characteristics for 179-ZHH 152. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−3. Thermal Resistance Characteristics for 176-PGF 153. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−4. Thermal Resistance Characteristics for 128-PBK 154. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
March 2004 − Revised October 2004 SGUS051A
9
This page intentionally left blank.
10
March 2004 − Revised October 2004SGUS051A
1 Features
Controlled Baseline
D
− One Assembly/Test/Fabrication Site
D Extended Temperature Performance of
−55°C to 125°C
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree
†
D High-Performance Static CMOS Technology
− 150 MHz (6.67-ns Cycle Time)
− Low-Power (1.8-V Core @135 MHz, 1.9-V
Core @150 MHz, 3.3-V I/O) Design
D JTAG Boundary Scan Support
‡
D High-Performance 32-Bit CPU (320C28x)
− 16 x 16 and 32 x 32 MAC Operations
− 16 x 16 Dual MAC
− Harvard Bus Architecture
− Atomic Operations
− Fast Interrupt Response and Processing
− Unified Memory Programming Model
− 4M Linear Program/Data Address Reach
− Code-Efficient (in C/C++ and Assembly)
− 320F24x/LF240x Processor Source Code
Compatible
D On-Chip Memory
− Flash Devices: Up to 128K x 16 Flash
(Four 8K x 16 and Six 16K x 16 Sectors)
− ROM Devices: Up to 128K x 16 ROM
− 1K x 16 OTP ROM
− L0 and L1: 2 Blocks of 4K x 16 Each
Single-Access RAM (SARAM)
− H0: 1 Block of 8K x 16 SARAM
− M0 and M1: 2 Blocks of 1K x 16 Each
SARAM
D Boot ROM (4K x 16)
− With Software Boot Modes
− Standard Math Tables
D External Interface (2812)
− Up to 1M Total Memory
− Programmable Wait States
− Programmable Read/Write Strobe Timing
− Three Individual Chip Selects
Features
D Clock and System Control
− Dynamic PLL Ratio Changes Supported
− On-Chip Oscillator
− Watchdog Timer Module
D Three External Interrupts
D Peripheral Interrupt Expansion (PIE) Block
That Supports 45 Peripheral Interrupts
D Three 32-Bit CPU-Timers
D 128-Bit Security Key/Lock
− Protects Flash/ROM/OTP and L0/L1
SARAM
− Prevents Firmware Reverse Engineering
D Motor Control Peripherals
− Two Event Managers (EVA, EVB)
− Compatible to 240xA Devices
D Serial Port Peripherals
− Serial Peripheral Interface (SPI)
− Two Serial Communications Interfaces
(SCIs), Standard UART
− Enhanced Controller Area Network
(eCAN)
− Multichannel Buffered Serial Port
(McBSP)
D 12-Bit ADC, 16 Channels
− 2 x 8 Channel Input Multiplexer
− Two Sample-and-Hold
− Single/Simultaneous Conversions
− Fast Conversion Rate: 80 ns/12.5 MSPS
D Up to 56 General Purpose I/O (GPIO) Pins
D Advanced Emulation Features
− Analysis and Breakpoint Functions
− Real-Time Debug via Hardware
D Development Tools Include
− ANSI C/C++ Compiler/Assembler/Linker
− Code Composer Studio IDE
− DSP/BIOS
D Low-Power Modes and Power Savings
− IDLE, STANDBY, HALT Modes Supported
− Disable Individual Peripheral Clocks
D Package Options
− 179-Ball MicroStar BGA (GHH), (2812)
− 176-Pin Low-Profile Quad Flatpack
(LQFP) (PGF) (2812)
TMS320C24x, Code Composer Studio, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments.
†
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range.
This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this
component beyond specified performance and environmental limits.
‡
IEEE Standard 1149.1−1990, IEEE Standard Test-Access Port
March 2004 − Revised October 2004 SGUS051A
11
Introduction
−55°C to 125°C
2 Introduction
This section provides a summary of each device’s features, lists the pin assignments, and describes the
function of each pin. This document also provides detailed descriptions of peripherals, electrical
specifications, parameter measurement information, and mechanical data about the available packaging.
2.1 Description
The SM320F2810-EP, SM320F2811-EP, SM320F2812-EP, SM320C2810-EP, SM320C2811-EP, and
SM320C2812-EP devices, members of the TMS320C28x DSP generation, are highly integrated,
high-performance solutions for demanding control applications. The functional blocks and the memory maps
are described in Section 3, Functional Overview.
Throughout this document, SM320F2810-EP, SM320F2811-EP, and SM320F2812-EP are abbreviated as
F2810, F2811, and F2812, respectively. F281x denotes all three Flash devices. SM320C2810-EP,
SM320C2811-EP, and SM320C2812-EP are abbreviated as C2810, C2811, and C2812, respectively . C281x
denotes all three ROM devices. 2810 denotes both F2810 and C2810 devices; 2811 denotes both F2811 and
C2811 devices; and 2812 denotes both F2812 and C2812 devices.
ORDERING INFORMATION
T
A
†
Package drawings, standard packing quantities, thermal data,
symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡
All other combinations are Product Preview.
PACKAGE
µstar CSP − GHH SM320F2812GHHMEP
LQFP − PGF SM320F2812PGFMEP
†
ORDERABLE
PART NUMBER
‡
TMS320C28x is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12
March 2004 − Revised October 2004SGUS051A
Introduction
2.2 Device Summary
Table 2−1 provides a summary of each device’s features.
Table 2−1. Hardware Features
FEATURE F2810 F2811 F2812 C2810 C2811 C2812
Instruction Cycle (at 150 MHz) 6.67 ns 6.67 ns 6.67 ns 6.67 ns 6.67 ns 6.67 ns
Single-Access RAM (SARAM)
(16-bit word)
3.3-V On-Chip Flash (16-bit word) 64K 128K 128K — — —
On-Chip ROM (16-bit word) — — — 64K 128K 128K
Code Security for
On-Chip Flash/SARAM/OTP/ROM
Boot ROM Yes Yes Yes Yes Yes Yes
OTP ROM (1K X 16) Yes Yes Yes Yes
External Memory Interface — — Yes — — Yes
Event Managers A and B
(EVA and EVB)
S General-Purpose (GP) Timers 4 4 4 4 4 4
S Compare (CMP)/PWM 16 16 16 16 16 16
S Capture (CAP)/QEP Channels 6/2 6/2 6/2 6/2 6/2 6/2
Watchdog Timer Yes Yes Yes Yes Yes Yes
12-Bit ADC Yes Yes Yes Yes Yes Yes
S Channels 16 16 16 16 16 16
32-Bit CPU Timers 3 3 3 3 3 3
SPI Yes Yes Yes Yes Yes Yes
SCIA, SCIB SCIA, SCIB SCIA, SCIB SCIA, SCIB SCIA, SCIB SCIA, SCIB SCIA, SCIB
CAN Yes Yes Yes Yes Yes Yes
McBSP Yes Yes Yes Yes Yes Yes
Digital I/O Pins (Shared) 56 56 56 56 56 56
External Interrupts 3 3 3 3 3 3
Supply Voltage 1.8-V Core, (135 MHz) 1.9-V Core (150 MHz), 3.3-V I/O
Packaging 128-pin PBK 128-pin PBK
M: −55°C to
Temperature Options
Product Status
†
The TMS320F2810, TMS320F2811, and TMS320F2812 Digital Signal Processors Silicon Errata (literature number SPRZ193) has been posted
on the Texas Instruments (TI) website. It will be updated as needed.
‡
On C281x devices, OTP is replaced by a 1K X 16 block of ROM.
§
M stands for −55°C to 125°C military range.
¶
See Section 5.1, Device and Development Support Nomenclature for descriptions of TMS and TMX stages.
#
PP: Product Preview. Electrical specifications of F2810/11/12 devices are to be considered as advance information for C2810/11/12 devices.
||
TMX: The status of each device is indicated on the page(s) specifying its electrical characteristics and is not necessarily representative of the
final device’s electrical specifications.
§
125°C
¶
18K 18K 18K 18K 18K 18K
Yes Yes Yes Yes Yes Yes
EVA, EVB EVA, EVB EVA, EVB EVA, EVB EVA, EVB EVA, EVB
179-ball GHH
176-pin PGF
No No Yes No No No
PP
#
PP
#
†
128-pin PBK 128-pin PBK
SM TMX
‡
||
Yes
TMX
‡
||
‡
Yes
179-ball GHH
176-pin PGF
||
TMX
March 2004 − Revised October 2004 SGUS051A
13
Introduction
2.3 Pin Assignments
Figure 2−1 illustrates the ball locations for the 179-ball GHH ball grid array (BGA) package. Figure 2−2 shows
the pin assignments for the 176-pin PGF low-profile quad flatpack (LQFP) and Figure 2−3 shows the pin
assignments for the 128-pin PBK LQFP. Table 2−2 describes the function(s) of each pin.
2.3.1 Terminal Assignments for the GHH Package
See Table 2−2 for a description of each terminal’s function(s).
P
N
M
XZCS0AND1
SPISOMIA PWM9 XR/W
SPISIMOA XA[1] XRD
L
K
J
MCLKXA MFSRA XD[3]
H
G
F
E
MDXA MDRA XD[0]
XMP/MC
AVDD-
REFBG
PWM8
PWM10
PWM7 TEST2
V
DD
V
SPICLKA
SS
V
MCLKRA XD[1] MFSXA XD[2]
DD
RESEXT
ADCREFP
XD[6] PWM11 XD[7] C5TRIP
V
SS
XD[4]
ADC-
V
AVSS-
REFBG
V
PWM12
SPISTEA
V
DDIO
V
V
SSA1
DDA1
ADCREFM ADCINA5
SS
T4PWM
_T4CMP
_QEP3
T3PWM
_T3CMP
SS
ADCINB7 C3TRIP
CAP6
V
DD
_QEPI2
C4TRIP
CAP4
CAP5
_QEP4
XD[5] XD[13]
XA[0]
ADC-
BGREFIN
XD[8]
TEST1 XD[9] X2
V
V
C6TRIP
SS
XHOLD
DDIO
V
SS
V
DD3VFL
TDIRB XD[10]
TCLKINB
XNMI
_XINT13
T3CTRIP
V
DD
_PDPINTB
XD[11] XA[2] XWE
X1/
XHOLDA
XCLKIN
T2CTRIP
V
DDIO
T4CTRIP/
EVBSOC
V
SS
V
DDIOVSS
PWM5
T1PWM
_T1CMP
CAP1
_QEP1
EVASOC
XA[13] C2TRIP XA[8] C1TRIP
CAP2
_QEP2
/
V
XCLKOUT XA[7] TCLKINA TDIRA
V
DD
CANTXA CANRXA
XA[3] PWM1
PWM3 PWM4 XD[12]
V
DD
XA[4]
CAP3
_QEPI1
V
DDIO
DD
XZCS2
SCIRXDB
V
SS
T2PWM
_T2CMP
XA[5]
V
SS
SCITXDB
V
DDIO
PWM2
PWM6
V
SS
T1CTRIP
_PDPINTA
XA[6]
V
SS
14
D
C
B
A
ADCINB6 ADCINB5 ADCINB4 ADCINA1 ADCINA6 XRS
ADCINB3 ADCINB0 ADCINB1 ADCINA2
ADCINB2
V
DDAIO
V
ADCINA0 ADCINA4 V
SSAIO
ADCLO ADCINA3 ADCINA7 XREADY XA[17]
V
SSA2VSS1
DDA2VDD1
XA[18]
SCITXDA
SCIRXDA XA[16] XD[15] TESTSEL XA[11]
XINT2
_ADCSOC
XINT1
_XBIO
V
EMU1
DD
XA[15]
V
SS
V
EMU0 TDO TMS XA[9]
SS
V
XA[12] XA[10] TDI
SS
XD[14] TRST
V
DD
XA[14]
XF
_XPLLDIS
TCK
XZCS6AND7
V
DD
V
SS
1412 1310 1189563412 7
Figure 2−1. 320F2812 and 320C2812 179-Ball GHH MicroStar BGA (Bottom View)
March 2004 − Revised October 2004SGUS051A
2.3.2 Pin Assignments for the PGF Package
The 320F2812 and 320C2812 176-pin PGF low-profile quad flatpack (LQFP) pin assignments are shown in
Figure 2−2. See Table 2−2 for a description of each pin’s function(s).
Introduction
XZCS6AND7
TESTSEL
TRST
TCK
EMU0
XA[12]
XD[14]
XF_XPLLDIS
XA[13]
V
V
XA[14]
V
DDIO
EMU1
XD[15]
XA[15]
XINT1_XBIO
XNMI_XINT13
XINT2_ADCSOC
XA[16]
V
V
DD
SCITXDA
XA[17]
SCIRXDA
XA[18]
XHOLD
XRS
XREADY
V
DD1
V
SS1
ADCBGREFIN
V
SSA2
V
DDA2
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCLO
V
SSAIO
SS
VDDV
XA[11]
TDI
XA[10]
TDO
TMS
XA[9]
132 89
SS
DD
SS
133
176
131
130
129
128
127
126
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
23456789101112131415161718192021222324252627282930313233343536373839404142
125
C2TRIP
C3TRIP
124
123
C1TRIP
XA[8]
121
122
SS
V
XCLKOUT
120
119
XA[7]
TCLKINA
118
117
T2CTRIP / EVASOC
TDIRA
116
115
DDIO
114
T1CTRIP_PDPINTA
VDDVSSV
XA[6]
111
113
112
110
SS
CAP3_QEPI1
XA[5]
CAP2_QEP2
CAP1_QEP1
V
109
108
107
106
105
DD
T2PWM_T2CMP
XA[4]
T1PWM_T1CMP
PWM6
VSSV
99989796959493
101
104
103
102
100
PWM5
XD[13]
XD[12]
PWM4
PWM3
PWM2
PWM1
929190
SCIRXDB
SCITXDB
CANRXA
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
43
88
XZCS2
CANTXA
V
SS
XA[3]
XWE
T4CTRIP/EVBSOC
XHOLDA
V
DDIO
XA[2]
T3CTRIP_PDPINTB
V
SS
X1/XCLKIN
X2
V
DD
XD[11]
XD[10]
TCLKINB
TDIRB
V
SS
V
DD3VFL
XD[9]
TEST1
TEST2
XD[8]
V
DDIO
C6TRIP
C5TRIP
C4TRIP
CAP6_QEPI2
CAP5_QEP4
V
SS
CAP4_QEP3
V
DD
T4PWM_T4CMP
XD[7]
T3PWM_T3CMP
V
SS
XR/W
PWM12
PWM11
PWM10
PWM9
PWM8
PWM7
45
1
DDAIO
V
ADCINB0
ADCINB1
ADCINB2
ADCINB3
ADCINB4
ADCINB5
ADCINB6
ADCINB7
ADCREFP
ADCREFM
SSA1
DDA1
V
V
AVSSREFBG
AVDDREFBG
SS
MCXMP/
V
XA[0]
MDRA
ADCRESEXT
XD[0]
MDXA
DD
V
XD[1]
MCLKRA
XD[2]
MFSXA
XD[3]VDDIO
MFSRA
MCLKXA
SS
V
XD[4]
SPICLKA
DD
V
XD[5]
SPISTEA
SS
V
XD[6]
SPISIMOA
XRD
XA[1]
SPISOMIA
44
XZCS0AND1
Figure 2−2. 320F2812 and 320C2812 176-Pin PGF LQFP (Top View)
March 2004 − Revised October 2004 SGUS051A
15
Introduction
2.3.3 Pin Assignments for the PBK Package
The 320F2810, 320F2811, 320C2810, and 320C2811 128-pin PBK low-profile quad flatpack (LQFP) pin
assignments are shown in Figure 2−3. See Table 2−2 for a description of each pin’s function(s).
TESTSEL
TRST
TCK
EMU0
XF_XPLLDIS
V
DD
V
SS
V
DDIO
EMU1
XINT1_XBIO
XNMI_XINT13
XINT2_ADCSOC
ADCBGREFIN
V
SS
V
DD
SCITXDA
SCIRXDA
XRS
V
DD1
V
SS1
V
SSA2
V
DDA2
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCLO
V
SSAIO
97
128
SS
TDI
TDO
TMS
VDDV
96 65
93
9291908988
95
94
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
2345678
C1TRIP
C2TRIP
C3TRIP
SS
XCLKOUT
V
878685
9
101112
TCLKINA
TDIRA
T2CTRIP/ EVASOC
84
131415
DDIO
VDDV
83
82
T1CTRIP_PDPINTA
CAP1_QEP1
CAP2_QEP2
CAP3_QEPI1
81
79
78
80
16
18
19
17
DD
T2PWM_T2CMP
T1PWM_T1CMP
76
77
21
20
PWM6
757473
222324
VSSV
PWM5
72
25
PWM4
PWM3
71
70
27
26
PWM1
PWM2
69
68
28
29
SCIRXDB
SCITXDB
CANRXA
66
67
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
31
30
64
CANTXA
V
DD
V
SS
T4CTRIP
T3CTRIP_PDPINTB
V
SS
X1/XCLKIN
X2
V
DD
TCLKINB
TDIRB
V
SS
V
DD3VFL
TEST1
TEST2
V
DDIO
C6TRIP
C5TRIP
C4TRIP
CAP6_QEPI2
CAP5_QEP4
CAP4_QEP3
V
DD
T4PWM_T4CMP
T3PWM_T3CMP
V
SS
PWM12
PWM11
PWM10
PWM9
PWM8
PWM7
33
/EVBSOC
16
1
DDAIO
V
ADCINB0
ADCINB1
ADCINB2
ADCINB3
ADCINB4
ADCINB5
ADCINB6
ADCINB7
ADCREFP
ADCREFM
AVSSREFBG
AVDDREFBG
SSA1
DDA1
V
V
ADCRESEXT
V
SS
MDRA
MDXA
DD
V
MCLKRA
MFSXA
MFSRA
MCLKXA
DDIO
V
SS
V
SPICLKA
SPISTEA
DD
V
V
SS
32
SPISIMOA
SPISOMIA
Figure 2−3. 320F2810, 320F2811, 320C2810, and 320C2811 128-Pin PBK LQFP
(Top View)
March 2004 − Revised October 2004SGUS051A
2.4 Signal Descriptions
‡
§
19-bit XINTF Address Bus
Table 2−2 specifies the signals on the F281x and C281x devices. All digital inputs are TTL-compatible. All
outputs are 3.3 V with CMOS levels. Inputs are not 5-V tolerant. A 100-µA (or 20-µA) pullup/pulldown is used.
Introduction
Table 2−2. Signal Descriptions
PIN NO.
NAME
XA[18] D7 158 − O/Z −
XA[17] B7 156 − O/Z −
XA[16] A8 152 − O/Z −
XA[15] B9 148 − O/Z −
XA[14] A10 144 − O/Z −
XA[13] E10 141 − O/Z −
XA[12] C11 138 − O/Z −
XA[11] A14 132 − O/Z
XA[10] C12 130 − O/Z −
XA[9] D14 125 − O/Z −
XA[8] E12 121 − O/Z −
XA[7] F12 118 − O/Z −
XA[6] G14 111 − O/Z −
XA[5] H13 108 − O/Z −
XA[4] J12 103 − O/Z −
XA[3] M11 85 − O/Z −
XA[2] N10 80 − O/Z −
XA[1] M2 43 − O/Z −
XA[0] G5 18 − O/Z
XD[15] A9 147 − I/O/Z PU
XD[14] B11 139 − I/O/Z PU
XD[13] J10 97 − I/O/Z PU
XD[12] L14 96 − I/O/Z PU
XD[11] N9 74 − I/O/Z PU
XD[10] L9 73 − I/O/Z PU
XD[9] M8 68 − I/O/Z PU
XD[8] P7 65 − I/O/Z PU
XD[7] L5 54 − I/O/Z PU
XD[6] L3 39 − I/O/Z PU
XD[5] J5 36 − I/O/Z PU
XD[4] K3 33 − I/O/Z PU
XD[3] J3 30 − I/O/Z PU
XD[2] H5 27 − I/O/Z PU
XD[1] H3 24 − I/O/Z PU
XD[0] G3 21 − I/O/Z PU
†
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
‡
I = Input, O = Output, Z = High impedance
§
PU = pin has internal pullup; PD = pin has internal pulldown
179-PIN
GHH
176-PIN
PGF
128-PIN
PBK
I/O/Z
XINTF SIGNALS (2812 ONLY)
PU/PD
19-bit XINTF Address Bus
16-bit XINTF Data Bus
†
DESCRIPTION
March 2004 − Revised October 2004 SGUS051A
17
Introduction
Table 2−2. Signal Descriptions
PIN NO.
‡
NAME DESCRIPTIONPU/PD
NAME DESCRIPTIONPU/PD
XMP/MC F1 17 − I PD
XHOLD E7 159 − I PU
XHOLDA K10 82 − O/Z −
XZCS0AND1 P1 44 − O/Z −
XZCS2 P13 88 − O/Z −
XZCS6AND7 B13 133 − O/Z −
XWE N11 84 − O/Z −
XRD M3 42 − O/Z −
XR/W N4 51 − O/Z −
†
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
‡
I = Input, O = Output, Z = High impedance
§
PU = pin has internal pullup; PD = pin has internal pulldown
179-PIN
GHH
176-PIN
PGF
128-PIN
PBK
XINTF SIGNALS (2812 ONLY) (CONTINUED)
I/O/Z
I/O/Z
‡
†
(Continued)
§
§
Microprocessor/Microcomputer Mode Select. Switches
between microprocessor and microcomputer mode. When
high, Zone 7 is enabled on the external interface. When low,
Zone 7 is disabled from the external interface, and on-chip
boot ROM may be accessed instead. This signal is latched
into the XINTCNF2 register on a reset and the user can modify
this bit in software. The state of the XMP/MC
after reset.
External Hold Request. XHOLD, when active (low), requests
the XINTF to release the external bus and place all buses and
strobes into a high-impedance state. The XINTF will release
the bus when any current access is complete and there are no
pending accesses on the XINTF.
External Hold Acknowledge. XHOLDA is driven active (low)
when the XINTF has granted a XHOLD
buses and strobe signals will be in a high-impedance state.
XHOLDA is released when the XHOLD signal is released.
External devices should only drive the external bus when
XHOLDA
XINTF Zone 0 and Zone 1 Chip Select. XZCS0AND1 is active
(low) when an access to the XINTF Zone 0 or Zone 1 is
performed.
XINTF Zone 2 Chip Select. XZCS2 is active (low) when an
access to the XINTF Zone 2 is performed.
XINTF Zone 6 and Zone 7 Chip Select. XZCS6AND7 is active
(low) when an access to the XINTF Zone 6 or Zone 7 is
performed.
Write Enable. Active-low write strobe. The write strobe
waveform is specified, per zone basis, by the Lead, Active,
and Trail periods in the XTIMINGx registers.
Read Enable. Active-low read strobe. The read strobe
waveform is specified, per zone basis, by the Lead, Active,
and Trail periods in the XTIMINGx registers. NOTE: The XRD
and XWE signals are mutually exclusive.
Read Not Write Strobe. Normally held high. When low, XR/W
indicates write cycle is active; when high, XR/W indicates read
cycle is active.
is active (low).
pin is ignored
request. All XINTF
18
March 2004 − Revised October 2004SGUS051A
Introduction
Table 2−2. Signal Descriptions
PIN NO.
‡
NAME DESCRIPTIONPU/PD
NAME DESCRIPTIONPU/PD
XREADY B6 161 − I PU
X1/XCLKIN K9 77 58 I
X2 M9 76 57 O Oscillator Output
XCLKOUT F11 119 87 O −
TESTSEL A13 134 97 I PD Test Pin. Reserved for TI. Must be connected to ground.
179-PIN
GHH
176-PIN
PGF
128-PIN
PBK
XINTF SIGNALS (2812 ONLY) (CONTINUED)
JTAG AND MISCELLANEOUS SIGNALS
I/O/Z
I/O/Z
‡
†
(Continued)
§
§
Ready Signal. Indicates peripheral is ready to complete the
access when asserted to 1. XREADY can be configured to be
a synchronous or an asynchronous input. See the timing
diagrams for more details.
Oscillator Input − input to the internal oscillator. This pin is also
used to feed an e x t e r n a l clock. The 28x can be operated with
an external clock source, provided that the proper voltage
levels be driven on the X1/XCLKIN pin. It should be noted that
the X1/XCLKIN pin is referenced to the 1.8-V (or 1.9-V) core
digital power supply (VDD), rather than the 3.3-V I/O supply
(V
). A clamping diode may be used to clamp a buffered
DDIO
clock signal to ensure that the logic-high level does not
exceed VDD (1.8 V or 1.9 V) or a 1.8-V oscillator may be used.
Output clock derived from SYSCLKOUT to be used for
external wait-state generation and as a general-purpose clock
source. XCLKOUT is either the same frequency, 1/2 the
frequency, or 1/4 the frequency of SYSCLKOUT. At reset,
XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be
turned of f by setting bit 3 (CLKOFF) of the XINTCNF2 register
to 1.
Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution.
The PC will point to the address contained at the location
0x3FFFC0. When XRS
begins at the location pointed to by the PC. This pin is driven
XRS D6 160 113 I/O PU
TEST1 M7 67 51 I/O −
TEST2 N7 66 50 I/O −
†
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
‡
I = Input, O = Output, Z = High impedance
§
PU = pin has internal pullup; PD = pin has internal pulldown
low by the DSP when a watchdog reset occurs. During
watchdog reset, the XRS
watchdog reset duration of 512 XCLKIN cycles.
The output buffer of this pin is an open-drain with an internal
pullup (100 µA, typical). It is recommended that this pin be
driven by an open-drain device.
Test Pin. Reserved for TI. On F281x devices, TEST1 must be
left unconnected. On C281x devices, this pin is a “no connect
(NC)” (i.e., this pin is not connected to any circuitry internal
to the device).
Test Pin. Reserved for TI. On F281x devices, TEST2 must be
left unconnected. On C281x devices, this pin is a “no connect
(NC)” (i.e., this pin is not connected to any circuitry internal
to the device).
is brought to a high level, execution
pin will be driven low for the
March 2004 − Revised October 2004 SGUS051A
19
Introduction
pins should not be driven before V
, V
, and V
pins have been fully powered up.
Table 2−2. Signal Descriptions
PIN NO.
‡
NAME DESCRIPTIONPU/PD
NAME DESCRIPTIONPU/PD
TRST B12 135 98 I PD
TCK A12 136 99 I PU JTAG test clock with internal pullup
TMS D13 126 92 I PU
TDI C13 131 96 I PU
TDO D12 127 93 O/Z −
EMU0 D11 137 100 I/O/Z PU
EMU1 C9 146 105 I/O/Z PU
ADCINA7 B5 167 119 I
ADCINA6 D5 168 120 I
ADCINA5 E5 169 121 I
ADCINA4 A4 170 122 I
ADCINA3 B4 171 123 I
ADCINA2 C4 172 124 I
ADCINA1 D4 173 125 I
ADCINA0 A3 174 126 I
†
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
‡
I = Input, O = Output, Z = High impedance
§
PU = pin has internal pullup; PD = pin has internal pulldown
179-PIN
GHH
176-PIN
PGF
128-PIN
PBK
ADC ANALOG INPUT SIGNALS
I/O/Z
I/O/Z
‡
JTAG
†
(Continued)
§
§
JTAG test reset with internal pulldown. TRST, when driven
high, gives the scan system control of the operations of the
device. If this signal is not connected or driven low , the device
operates in its functional mode, and the test reset signals are
ignored.
NOTE: Do not use pullup resistors on TRST
pulldown device. In a low-noise environment, TRST
left floating. In a high-noise environment, an additional
pulldown resistor may be needed. The value of this resistor
should be based on drive strength of the debugger pods
applicable to the design. A 2.2-kΩ resistor generally offers
adequate protection. Since this is application-specific, it is
recommended that each target board is validated for proper
operation of the debugger and the application.
JTAG test-mode select (TMS) with internal pullup. This serial
control input is clocked into the TAP controller on the rising
edge of TCK.
JTAG test data input (TDI) with internal pullup. TDI is clocked
into the selected register (instruction or data) on a rising e dg e
of TCK.
JTAG scan out, test data output (TDO). The contents of the
selected register (instruction or data) is shifted out of TDO on
the falling edge of TCK.
Emulator pin 0. When TRST is driven high, this pin is used
as an interrupt to or from the emulator system and is
defined as input/output through the JTAG scan.
Emulator pin 1. When TRST is driven high, this pin is used
as an interrupt to or from the emulator system and is
defined as input/output through the JTAG scan.
8-Channel analog inputs for Sample-and-Hold A. The ADC
DDA1
; it has an internal
DDA2
can be
DDAIO
20
March 2004 − Revised October 2004SGUS051A
Introduction
pins should not be driven before the V
, V
, and
V
DDAIO
pins have been fully powered up.
Table 2−2. Signal Descriptions
PIN NO.
‡
NAME DESCRIPTIONPU/PD
NAME DESCRIPTIONPU/PD
ADCINB7 F5 9 9 I
ADCINB6 D1 8 8 I
ADCINB5 D2 7 7 I
ADCINB4 D3 6 6 I
ADCINB3 C1 5 5 I
ADCINB2 B1 4 4 I
ADCINB1 C3 3 3 I
ADCINB0 C2 2 2 I
ADCREFP E2 11 11 I/O
ADCREFM E4 10 10 I/O
ADCRESEXT F2 16 16 O ADC External Current Bias Resistor (24.9 kΩ ±5%)
ADCBGREFIN E6 164 116 I Test Pin. Reserved for TI. Must be left unconnected.
AVSSREFBG E3 12 12 I ADC Analog GND
AVDDREFBG E1 13 13 I ADC Analog Power (3.3-V)
ADCLO B3 175 127 I Common Low Side Analog Input. Connect to analog ground.
V
SSA1
V
SSA2
V
DDA1
V
DDA2
V
SS1
V
DD1
V
DDAIO
V
SSAIO
†
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
‡
I = Input, O = Output, Z = High impedance
§
PU = pin has internal pullup; PD = pin has internal pulldown
179-PIN
GHH
F3 15 15 I ADC Analog GND
C5 165 117 I ADC Analog GND
F4 14 14 I ADC Analog 3.3-V Supply
A5 166 118 I ADC Analog 3.3-V Supply
C6 163 115 I ADC Digital GND
A6 162 114 I ADC Digital 1.8-V (or 1.9-V) Supply
B2 1 1 3.3-V Analog I/O Power Pin
A2 176 128 Analog I/O Ground Pin
176-PIN
PGF
128-PIN
PBK
ADC ANALOG INPUT SIGNALS (CONTINUED)
I/O/Z
I/O/Z
‡
†
(Continued)
§
§
8-Channel Analog Inputs for Sample-and-Hold B. The ADC
DDA1
ADC Voltage Reference Output (2 V). Requires a low ESR
(50 mΩ − 1.5 Ω) ceramic bypass capacitor of 10 µF to analog
ground. (Can accept external reference input (2 V) if the
software bit is enabled for this mode. 1−10 µF low ESR
capacitor can be used in the external reference mode.)
ADC Voltage Reference Output (1 V). Requires a low ESR
(50 mΩ − 1.5 Ω) ceramic bypass capacitor of 10 µF to analog
ground. (Can accept external reference input (1 V) if the
software bit is enabled for this mode. 1−10 µF low ESR
capacitor can be used in the external reference mode.)
DDA2
March 2004 − Revised October 2004 SGUS051A
21
Introduction
,
Recommended Operating Conditions, for voltage
requirements.
Table 2−2. Signal Descriptions
PIN NO.
‡
NAME DESCRIPTIONPU/PD
NAME DESCRIPTIONPU/PD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDIO
V
DDIO
V
DDIO
V
DDIO
V
DDIO
V
DDIO
V
DD3VFL
†
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
‡
I = Input, O = Output, Z = High impedance
§
PU = pin has internal pullup; PD = pin has internal pulldown
179-PIN
GHH
H1 23 20
L1 37 29
P5 56 42
P9 75 56
P12 − 63
K12 100 74
G12 112 82
C14 128 94
B10 143 102
C8 154 110
G4 19 17
K1 32 26
L2 38 30
P4 52 39
K6 58 −
P8 70 53
M10 78 59
L11 86 62
K13 99 73
J14 105 −
G13 113 −
E14 120 88
B14 129 95
D10 142 −
C10 − 103
B8 153 109
J4 31 25
L7 64 49
L10 81 −
N14 − −
G11 114 83
E9 145 104
N8 69 52
176-PIN
PGF
128-PIN
PBK
‡
I/O/Z
I/O/Z
POWER SIGNALS
†
(Continued)
§
§
1.8-V or 1.9-V Core Digital Power Pins. See Section 6.2
Core and Digital I/O Ground Pins
3.3-V I/O Digital Power Pins
3.3-V Flash Core Power Pin. This pin should be connected to
3.3 V at all times after power-up sequence requirements have
been met. This pin is used as VDDIO in ROM parts and must
be connected to 3.3 V in ROM parts as well.
22
March 2004 − Revised October 2004SGUS051A
Table 2−2. Signal Descriptions† (Continued)
§
PIN NO.
GPIO PERIPHERAL SIGNAL
GPIOA0 PWM1 (O) M12 92 68 I/O/Z PU GPIO or PWM Output Pin #1
GPIOA1 PWM2 (O) M14 93 69 I/O/Z PU GPIO or PWM Output Pin #2
GPIOA2 PWM3 (O) L12 94 70 I/O/Z PU GPIO or PWM Output Pin #3
GPIOA3 PWM4 (O) L13 95 71 I/O/Z PU GPIO or PWM Output Pin #4
GPIOA4 PWM5 (O) K11 98 72 I/O/Z PU GPIO or PWM Output Pin #5
GPIOA5 PWM6 (O) K14 101 75 I/O/Z PU GPIO or PWM Output Pin #6
GPIOA6 T1PWM_T1CMP (I) J11 102 76 I/O/Z PU GPIO or Timer 1 Output
GPIOA7 T2PWM_T2CMP (I) J13 104 77 I/O/Z PU GPIO or Timer 2 Output
GPIOA8 CAP1_QEP1 (I) H10 106 78 I/O/Z PU GPIO or Capture Input #1
GPIOA9 CAP2_QEP2 (I) H11 107 79 I/O/Z PU GPIO or Capture Input #2
GPIOA10 CAP3_QEPI1 (I) H12 109 80 I/O/Z PU GPIO or Capture Input #3
GPIOA11 TDIRA (I) F14 116 85 I/O/Z PU GPIO or Timer Direction
GPIOA12 TCLKINA (I) F13 117 86 I/O/Z PU GPIO or Timer Clock Input
GPIOA13 C1TRIP (I) E13 122 89 I/O/Z PU GPIO or Compare 1 Output Trip
GPIOA14 C2TRIP (I) E11 123 90 I/O/Z PU GPIO or Compare 2 Output Trip
GPIOA15 C3TRIP (I) F10 124 91 I/O/Z PU GPIO or Compare 3 Output Trip
GPIOB0 PWM7 (O) N2 45 33 I/O/Z PU GPIO or PWM Output Pin #7
GPIOB1 PWM8 (O) P2 46 34 I/O/Z PU GPIO or PWM Output Pin #8
GPIOB2 PWM9 (O) N3 47 35 I/O/Z PU GPIO or PWM Output Pin #9
GPIOB3 PWM10 (O) P3 48 36 I/O/Z PU GPIO or PWM Output Pin #10
GPIOB4 PWM11 (O) L4 49 37 I/O/Z PU GPIO or PWM Output Pin #11
GPIOB5 PWM12 (O) M4 50 38 I/O/Z PU GPIO or PWM Output Pin #12
GPIOB6 T3PWM_T3CMP (I) K5 53 40 I/O/Z PU GPIO or Timer 3 Output
GPIOB7 T4PWM_T4CMP (I) N5 55 41 I/O/Z PU GPIO or Timer 4 Output
GPIOB8 CAP4_QEP3 (I) M5 57 43 I/O/Z PU GPIO or Capture Input #4
GPIOB9 CAP5_QEP4 (I) M6 59 44 I/O/Z PU GPIO or Capture Input #5
GPIOB10 CAP6_QEPI2 (I) P6 60 45 I/O/Z PU GPIO or Capture Input #6
GPIOB11 TDIRB (I) L8 71 54 I/O/Z PU GPIO or Timer Direction
GPIOB12 TCLKINB (I) K8 72 55 I/O/Z PU GPIO or Timer Clock Input
GPIOB13 C4TRIP (I) N6 61 46 I/O/Z PU GPIO or Compare 4 Output Trip
GPIOB14 C5TRIP (I) L6 62 47 I/O/Z PU GPIO or Compare 5 Output Trip
GPIOB15 C6TRIP (I) K7 63 48 I/O/Z PU GPIO or Compare 6 Output Trip
†
Typical drive strength of the output buffer for all pins [except TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins] is 4 mA typical.
‡
I = Input, O = Output, Z = High impedance
§
PU = pin has internal pullup; PD = pin has internal pulldown
179-PIN
GHH
176-PIN
PGF
GPIO OR PERIPHERAL SIGNALS
GPIOA OR EVA SIGNALS
GPIOB OR EVB SIGNALS
128-PIN
PBK
I/O/Z‡PU/PD
DESCRIPTION
Introduction
March 2004 − Revised October 2004 SGUS051A
23
Introduction
§
Table 2−2. Signal Descriptions† (Continued)
PIN NO.
GPIO PERIPHERAL SIGNAL
GPIOD0 T1CTRIP_PDPINTA (I) H14 110 81 I/O/Z PU Timer 1 Compare Output Trip
GPIOD1 T2CTRIP/EVASOC (I) G10 115 84 I/O/Z PU
GPIOD5 T3CTRIP_PDPINTB (I) P10 79 60 I/O/Z PU Timer 3 Compare Output Trip
GPIOD6 T4CTRIP/EVBSOC (I) P11 83 61 I/O/Z PU
GPIOE0 XINT1_XBIO (I) D9 149 106 I/O/Z − GPIO or XINT1 or XBIO input
GPIOE1 XINT2_ADCSOC (I) D8 151 108 I/O/Z − GPIO or XINT2 or ADC start of conversion
GPIOE2 XNMI_XINT13 (I) E8 150 107 I/O/Z PU GPIO or XNMI or XINT13
GPIOF0 SPISIMOA (O) M1 40 31 I/O/Z − GPIO or SPI slave in, master out
GPIOF1 SPISOMIA (I) N1 41 32 I/O/Z − GPIO or SPI slave out, master in
GPIOF2 SPICLKA (I/O) K2 34 27 I/O/Z − GPIO or SPI clock
GPIOF3 SPISTEA (I/O) K4 35 28 I/O/Z − GPIO or SPI slave transmit enable
GPIOF4 SCITXDA (O) C7 155 111 I/O/Z PU
GPIOF5 SCIRXDA (I) A7 157 112 I/O/Z PU
GPIOF6 CANTXA (O) N12 87 64 I/O/Z PU GPIO or eCAN transmit data
GPIOF7 CANRXA (I) N13 89 65 I/O/Z PU GPIO or eCAN receive data
GPIOF8 MCLKXA (I/O) J1 28 23 I/O/Z PU GPIO or transmit clock
GPIOF9 MCLKRA (I/O) H2 25 21 I/O/Z PU GPIO or receive clock
GPIOF10 MFSXA (I/O) H4 26 22 I/O/Z PU GPIO or transmit frame synch
GPIOF11 MFSRA (I/O) J2 29 24 I/O/Z PU GPIO or receive frame synch
GPIOF12 MDXA (O) G1 22 19 I/O/Z − GPIO or transmitted serial data
GPIOF13 MDRA (I) G2 20 18 I/O/Z PU GPIO or received serial data
†
Typical drive strength of the output buffer for all pins [except TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins] is 4 mA typical.
‡
I = Input, O = Output, Z = High impedance
§
PU = pin has internal pullup; PD = pin has internal pulldown
179-PIN
GHH
176-PIN
PGF
GPIOD OR EVA SIGNALS
GPIOD OR EVB SIGNALS
GPIOE OR INTERRUPT SIGNALS
GPIOF OR SPI SIGNALS
GPIOF OR SCI-A SIGNALS
GPIOF OR CAN SIGNALS
GPIOF OR McBSP SIGNALS
128-PIN
PBK
I/O/Z‡PU/PD
DESCRIPTION
Timer 2 Compare Output Trip or External
ADC Start-of-Conversion EV-A
Timer 4 Compare Output Trip or External
ADC Start-of-Conversion EV-B
GPIO or SCI asynchronous serial port TX
data
GPIO or SCI asynchronous serial port RX
data
24
March 2004 − Revised October 2004SGUS051A
Table 2−2. Signal Descriptions† (Continued)
§
PIN NO.
GPIO PERIPHERAL SIGNAL
GPIOF14 XF_XPLLDIS (O) A11 140 101 I/O/Z PU
GPIOG4 SCITXDB (O) P14 90 66 I/O/Z −
GPIOG5 SCIRXDB (I) M13 91 67 I/O/Z −
†
Typical drive strength of the output buffer for all pins [except TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins] is 4 mA typical.
‡
I = Input, O = Output, Z = High impedance
§
PU = pin has internal pullup; PD = pin has internal pulldown
179-PIN
GHH
176-PIN
PGF
GPIOF OR XF CPU OUTPUT SIGNAL
GPIOG OR SCI-B SIGNALS
128-PIN
PBK
I/O/Z‡PU/PD
DESCRIPTION
This pin has three functions:
1. XF − General-purpose output pin.
2. XPLLDIS − This pin will be sampled
during reset to check if the PLL needs
to be disabled. The PLL will be
disabled if this pin is sensed low. HALT
and STANDBY modes cannot be used
when the PLL is disabled.
3. GPIO − GPIO function
GPIO or SCI asynchronous serial port
transmit data
GPIO or SCI asynchronous serial port
receive data
NOTE:
Other than the power supply pins, no pin should be driven before the 3.3-V rail has reached
recommended operating conditions. However , i t i s acceptable for an I/O pin to ramp along with
the 3.3-V supply.
Introduction
March 2004 − Revised October 2004 SGUS051A
25
Functional Overview
3 Functional Overview
Memory Bus
GPIO Pins
TINT0
TINT1
G
P
I
O
M
U
X
XINT13
XNMI
CPU-Timer 0
CPU-Timer 1
CPU-Timer 2
TINT2
PIE
(96 interrupts)
External Interrupt
Control
(XINT1/2/13, XNMI)
SCIA/SCIB
SPI FIFO
McBSP
eCAN
EVA/EVB
†
FIFO
FIFO
INT14
INT[12:1]
INT13
NMI
C28x CPU
Real-Time JTAG
External
Interface
‡
(XINTF)
M0 SARAM
1K x 16
M1 SARAM
1K x 16
L0 SARAM
4K x 16
L1 SARAM
4K x 16
Flash
128K x 16 (F2812)
128K x 16 (F2811)
64K x 16 (F2810)
Control
Address(19)
Data(16)
XRS
X1/XCLKIN
X2
XF_XPLLDIS
†
45 of the possible 96 interrupts are used on the devices.
‡
XINTF is available on the F2812 and C2812 devices only.
§
On C281x devices, the OTP is replaced with a 1K X 16 block of ROM
16 Channels
(Oscillator and PLL
Peripheral Clocking
Protected by the code-security module.
12-Bit ADC
System Control
+
+
Low-Power
Modes
+
WatchDog)
Figure 3−1. Functional Block Diagram
RS
CLKIN
Memory Bus
Peripheral Bus
ROM
128K x 16 (C2812)
128K x 16 (C2811)
64K x 16 (C2810)
§
OTP
1K x 16
H0 SARAM
8K × 16
Boot ROM
4K × 16
26
March 2004 − Revised October 2004SGUS051A
3.1 Memory Map
Block
Start Address
Functional Overview
On-Chip Memory External Memory XINTF
0x00 0000
0x00 0040
0x00 0400
0x00 0800
0x00 0D00
Low 64K
(24x/240x Equivalent Data Space)
0x00 0E00
0x00 2000
0x00 6000
0x00 7000
0x00 8000
0x00 9000
0x00 A000
Data Space Prog Space
M0 Vector − RAM (32 × 32)
(Enabled if VMAP = 0)
M0 SARAM (1K × 16)
M1 SARAM (1K × 16)
Peripheral Frame 0
(2K × 16)
PIE Vector - RAM
(256 × 16)
(Enabled if VMAP
= 1, ENPIE = 1)
Reserved
Reserved
Peripheral Frame 1
(4K × 16, Protected)
Peripheral Frame 2
(4K × 16, Protected)
L0 SARAM (4K × 16, Secure Block)
L1 SARAM (4K × 16, Secure Block)
Reserved
Reserved
Reserved
Data Space Prog Space
Reserved
XINTF Zone 0 (8K × 16, XZCS0AND1
XINTF Zone 1 (8K × 16, XZCS0AND1) (Protected)
Reserved
XINTF Zone 2 (0.5M × 16, XZCS2
XINTF Zone 6 (0.5M × 16, XZCS6AND7)
)
)
0x00 2000
0x00 4000
0x08 0000
0x10 0000
0x18 0000
High 64K
Program Space)
(24x/240x Equivalent
LEGEND:
0x3D 7800
0x3D 7C00
0x3D 8000
0x3F 7FF8
0x3F 8000
0x3F A000
0x3F F000
0x3F FFC0
OTP (or ROM) (1K × 16, Secure Block)
Flash (or ROM) (128K × 16, Secure Block)
H0 SARAM (8K × 16)
(Enabled if MP/MC
BROM Vector - ROM (32 × 32)
(Enabled if VMAP = 1, MP/MC
Only one of these vector maps—M0 vector, PIE vector, BROM vector, XINTF vector—should be enabled at a time.
NOTES: A. Memory blocks are not to scale.
B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Boot ROM and Zone 7 memory maps are active either in on-chip or XINTF zone depending on MP/MC
D. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
cannot access these memory maps in program space.
E. “Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
F. Certain memory ranges are EALLOW protected against spurious writes after configuration.
G. Zones 0 and 1 and Zones 6 and 7 share the same chip select; hence, these memory blocks have mirrored locations.
Figure 3−2. F2812/C2812 Memory Map (See Notes A through E)
Reserved (1K)
128-Bit Password
Reserved
Boot ROM (4K × 16)
= 0)
= 0, ENPIE = 0)
Reserved
XINTF Zone 7 (16K × 16, XZCS6AND7
(Enabled if MP/MC
XINTF Vector - RAM (32 × 32)
(Enabled if VMAP = 1, MP/MC
= 1)
= 1, ENPIE = 0)
0x3F C000
)
, not in both.
March 2004 − Revised October 2004 SGUS051A
27
Functional Overview
Block
Start Address
0x00 0000
0x00 0040
0x00 0400
0x00 0800
0x00 0D00
Low 64K
(24x/240x Equivalent Data Space)
0x00 0E00
0x00 2000
0x00 6000
0x00 7000
0x00 8000
0x00 9000
0x00 A000
On-Chip Memory
Data Space Prog Space
M0 Vector − RAM (32 × 32)
(Enabled if VMAP = 0)
M0 SARAM (1K × 16)
M1 SARAM (1K × 16)
Peripheral Frame 0
(2K × 16)
PIE Vector - RAM
(256 × 16)
(Enabled if VMAP
= 1, ENPIE = 1)
Reserved
Reserved
Peripheral Frame 1
(4K × 16, Protected)
Peripheral Frame 2
(4K × 16, Protected)
L0 SARAM (4K × 16, Secure Block)
L1 SARAM (4K × 16, Secure Block)
Reserved
Reserved
High 64K
Program Space)
(24x/240x Equivalent
LEGEND:
Only one of these vector maps—M0 vector, PIE vector, BROM vector, XINTF vector—should be enabled at a time.
NOTES: A. Memory blocks are not to scale.
B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
cannot access these memory maps in program space.
D. “Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
E. Certain memory ranges are EALLOW protected against spurious writes after configuration.
0x3D 7800
0x3D 7C00
0x3D 8000
0x3F 7FF8
0x3F 8000
0x3F A000
0x3F F000
0x3F FFC0
Reserved
OTP (or ROM) (1K × 16, Secure Block)
Reserved (1K)
Flash (or ROM) (128K × 16, Secure Block)
128-Bit Password
H0 SARAM (8K × 16)
Reserved
Boot ROM (4K × 16)
(Enabled if MP/MC
BROM Vector - ROM (32 × 32)
(Enabled if VMAP = 1, MP/MC
= 0)
= 0, ENPIE = 0)
28
Figure 3−3. F2811/C2811 Memory Map (See Notes A through E)
March 2004 − Revised October 2004SGUS051A
Functional Overview
Block
Start Address
0x00 0000
0x00 0040
0x00 0400
0x00 0800
0x00 0D00
Low 64K
(24x/240x Equivalent Data Space)
0x00 0E00
0x00 2000
0x00 6000
0x00 7000
0x00 8000
0x00 9000
0x00 A000
Peripheral Frame 0
Peripheral Frame 1
(4K × 16, Protected)
Peripheral Frame 2
(4K × 16, Protected)
On-Chip Memory
Data Space Prog Space
M0 Vector − RAM (32 × 32)
(Enabled if VMAP = 0)
M0 SARAM (1K × 16)
M1 SARAM (1K × 16)
(2K × 16)
PIE Vector - RAM
(256 × 16)
(Enabled if VMAP
= 1, ENPIE = 1)
Reserved
Reserved
L0 SARAM (4K × 16, Secure Block)
L1 SARAM (4K × 16, Secure Block)
Reserved
Reserved
High 64K
Program Space)
(24x/240x Equivalent
LEGEND:
Only one of these vector maps—M0 vector, PIE vector, BROM vector—should be enabled at a time.
NOTES: A. Memory blocks are not to scale.
B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
cannot access these memory maps in program space.
D. “Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
E. Certain memory ranges are EALLOW protected against spurious writes after configuration.
0x3D 7800
0x3D 7C00
0x3E 8000
0x3F 7FF8
0x3F 8000
0x3F A000
0x3F F000
0x3F FFC0
Reserved
OTP (or ROM) (1K × 16, Secure Block)
Reserved
Flash (or ROM) (64K × 16, Secure Block)
128-Bit Password
H0 SARAM (8K × 16)
Reserved
Boot ROM (4K × 16)
(Enabled if MP/MC
BROM Vector - ROM (32 × 32)
(Enabled if VMAP = 1, MP/MC
= 0)
= 0, ENPIE = 0)
Figure 3−4. F2810/C2810 Memory Map (See Notes A through E)
March 2004 − Revised October 2004 SGUS051A
29
Functional Overview
Table 3−1. Addresses of Flash Sectors in F2812 and F2811
ADDRESS RANGE PROGRAM AND DATA SPACE
0x3D 8000
0x3D 9FFF
0x3D A000
0x3D BFFF
0x3D C000
0x3D FFFF
0x3E 0000
0x3E 3FFF
0x3E 4000
0x3E 7FFF
0x3E 8000
0x3E BFFF
0x3E C000
0x3E FFFF
0x3F 0000
0x3F 3FFF
0x3F 4000
0x3F 5FFF
0x3F 6000 Sector A, 8K x 16
0x3F 7F80
0x3F 7FF5
0x3F 7FF6
0x3F 7FF7
0x3F 7FF8
0x3F 7FFF
Program to 0x0000 when using the
Boot-to-Flash (or ROM) Entry Point
Sector J, 8K x 16
Sector I, 8K x 16
Sector H, 16K x 16
Sector G, 16K x 16
Sector F, 16K x 16
Sector E, 16K x 16
Sector D, 16K x 16
Sector C, 16K x 16
Sector B, 8K x 16
Code Security Module
(program branch instruction here)
Security Password (128-Bit)
(Do not program to all zeros)
Table 3−2. Addresses of Flash Sectors in F2810
ADDRESS RANGE PROGRAM AND DATA SPACE
0x3E 8000
0x3E BFFF
0x3E C000
0x3E FFFF
0x3F 0000
0x3F 3FFF
0x3F 4000
0x3F 5FFF
0x3F 6000 Sector A, 8K x 16
0x3F 7F80
0x3F 7FF5
0x3F 7FF6
0x3F 7FF7
0x3F 7FF8
0x3F 7FFF
Sector E, 16K x 16
Sector D, 16K x 16
Sector C, 16K x 16
Sector B, 8K x 16
Program to 0x0000 when using the
Code Security Module
Boot-to-Flash (or ROM) Entry Point
(program branch instruction here)
Security Password (128-Bit)
(Do not program to all zeros)
30
March 2004 − Revised October 2004SGUS051A
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