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SM320C6455-EP
User Manual
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Texas Instruments SM320C6455-EP User Manual

SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR
Data Manual
JANUARY 2008
SPRS462B
SM320C6455-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
Data Manual
Literature Number: SPRS462B
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
SM320C6455-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
Contents
1 Features .............................................................................................................................. 7
1.1 ZTZ/GTZ BGA Package (Bottom View) ................................................................................... 8
1.2 Description .................................................................................................................... 8
1.3 Functional Block Diagram ................................................................................................. 10
2 Device Overview ................................................................................................................. 11
2.1 Device Characteristics ..................................................................................................... 11
2.2 CPU (DSP Core) Description ............................................................................................. 12
2.3 Memory Map Summary .................................................................................................... 15
2.4 Boot Sequence ............................................................................................................. 17
2.4.1 Boot Modes Supported ......................................................................................... 17
2.4.2 2nd-Level Bootloaders .......................................................................................... 19
2.5 Pin Assignments ............................................................................................................ 20
2.5.1 Pin Map ........................................................................................................... 20
2.6 Signal Groups Description ................................................................................................ 24
2.7 Terminal Functions ......................................................................................................... 30
2.8 Development ................................................................................................................ 55
2.8.1 Development Support ........................................................................................... 55
2.8.2 Device Support .................................................................................................. 55
2.8.2.1 Device and Development-Support Tool Nomenclature ........................................ 55
2.8.2.2 Documentation Support ............................................................................. 56
3 Device Configuration .......................................................................................................... 59
3.1 Device Configuration at Device Reset ................................................................................... 59
3.2 Peripheral Configuration at Device Reset ............................................................................... 61
3.3 Peripheral Selection After Device Reset ................................................................................ 63
3.4 Device State Control Registers ........................................................................................... 65
3.4.1 Peripheral Lock Register Description ......................................................................... 66
3.4.2 Peripheral Configuration Register 0 Description ............................................................ 67
3.4.3 Peripheral Configuration Register 1 Description ............................................................ 69
3.4.4 Peripheral Status Registers Description ...................................................................... 70
3.4.5 EMAC Configuration Register (EMACCFG) Description ................................................... 73
3.4.6 Emulator Buffer Powerdown Register (EMUBUFPD) Description ........................................ 74
3.5 Device Status Register Description ...................................................................................... 75
3.6 JTAG ID (JTAGID) Register Description ................................................................................ 77
3.7 Pullup/Pulldown Resistors ................................................................................................. 78
3.8 Configuration Examples ................................................................................................... 78
4 System Interconnect ........................................................................................................... 81
4.1 Internal Buses, Bridges, and Switch Fabrics ........................................................................... 81
4.2 Data Switch Fabric Connections ......................................................................................... 82
4.3 Configuration Switch Fabric ............................................................................................... 84
4.4 Bus Priorities ................................................................................................................ 86
5 C64x+ Megamodule ............................................................................................................ 87
5.1 Memory Architecture ....................................................................................................... 87
5.2 Memory Protection ......................................................................................................... 90
5.3 Bandwidth Management ................................................................................................... 90
5.4 Power-Down Control ....................................................................................................... 91
5.5 Megamodule Resets ....................................................................................................... 91
5.6 Megamodule Revision ..................................................................................................... 92
5.7 C64x+ Megamodule Register Description(s) ........................................................................... 93
6 Device Operating Conditions ............................................................................................. 101
6.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted) .......... 101
Contents 3
SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
6.2 Recommended Operating Conditions .................................................................................. 101
6.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case
Temperature (Unless Otherwise Noted) ............................................................................... 103
7 C64x+ Peripheral Information and Electrical Specifications ................................................... 105
7.1 Parameter Information ................................................................................................... 105
7.1.1 3.3-V Signal Transition Levels ............................................................................... 105
7.1.2 3.3-V Signal Transition Rates ................................................................................ 105
7.1.3 Timing Parameters and Board Routing Analysis .......................................................... 106
7.2 Recommended Clock and Control Signal Transition Behavior ..................................................... 107
7.3 Power Supplies ........................................................................................................... 107
7.3.1 Power-Supply Sequencing .................................................................................... 107
7.3.2 Power-Supply Decoupling .................................................................................... 107
7.3.3 Power-Down Operation ....................................................................................... 107
7.3.4 Preserving Boundary-Scan Functionality on RGMII and DDR2 Memory Pins ......................... 108
7.4 Enhanced Direct Memory Access (EDMA3) Controller .............................................................. 109
7.4.1 EDMA3 Device-Specific Information ........................................................................ 110
7.4.2 EDMA3 Channel Synchronization Events .................................................................. 110
7.4.3 EDMA3 Peripheral Register Description(s) ................................................................. 111
7.5 Interrupts ................................................................................................................... 124
7.5.1 Interrupt Sources and Interrupt Controller .................................................................. 124
7.5.2 External Interrupts Electrical Data/Timing .................................................................. 127
7.6 Reset Controller ........................................................................................................... 128
7.6.1 Power-on Reset ( POR Pin) ................................................................................... 128
7.6.2 Warm Reset ( RESET Pin) .................................................................................... 129
7.6.3 Max Reset ....................................................................................................... 130
7.6.4 System Reset ................................................................................................... 130
7.6.5 CPU Reset ...................................................................................................... 130
7.6.6 Reset Priority ................................................................................................... 131
7.6.7 Reset Controller Register ..................................................................................... 132
7.6.7.1 Reset Type Status Register Description ......................................................... 132
7.6.8 Reset Electrical Data/Timing ................................................................................. 133
7.7 PLL1 and PLL1 Controller ............................................................................................... 136
7.7.1 PLL1 Controller Device-Specific Information ............................................................... 137
7.7.1.1 Internal Clocks and Maximum Operating Frequencies ......................................... 137
7.7.1.2 PLL1 Controller Operating Modes ................................................................ 138
7.7.1.3 PLL1 Stabilization, Lock, and Reset Times ...................................................... 138
7.7.2 PLL1 Controller Memory Map ................................................................................ 139
7.7.3 PLL1 Controller Register Descriptions ...................................................................... 140
7.7.3.1 PLL1 Control Register .............................................................................. 140
7.7.3.2 PLL Multiplier Control Register .................................................................... 141
7.7.3.3 PLL Pre-Divider Control Register ................................................................. 142
7.7.3.4 PLL Controller Divider 4 Register ................................................................. 143
7.7.3.5 PLL Controller Divider 5 Register ................................................................. 144
7.7.3.6 PLL Controller Command Register ............................................................... 145
7.7.3.7 PLL Controller Status Register .................................................................... 146
7.7.3.8 PLL Controller Clock Align Control Register ..................................................... 147
7.7.3.9 PLLDIV Ratio Change Status Register ........................................................... 148
7.7.3.10 SYSCLK Status Register ......................................................................... 149
7.7.4 PLL1 Controller Input and Output Clock Electrical Data/Timing ......................................... 150
7.8 PLL2 and PLL2 Controller ............................................................................................... 151
7.8.1 PLL2 Controller Device-Specific Information ............................................................... 152
7.8.1.1 Internal Clocks and Maximum Operating Frequencies ......................................... 152
7.8.1.2 PLL2 Controller Operating Modes ................................................................ 152
Contents 4 Submit Documentation Feedback
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FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
7.8.2 PLL2 Controller Memory Map ................................................................................ 153
7.8.3 PLL2 Controller Register Descriptions ...................................................................... 153
7.8.3.1 PLL Controller Divider 1 Register ................................................................. 154
7.8.3.2 PLL Controller Command Register ............................................................... 155
7.8.3.3 PLL Controller Status Register .................................................................... 156
7.8.3.4 PLL Controller Clock Align Control Register ..................................................... 156
7.8.3.5 PLLDIV Ratio Change Status Register ........................................................... 157
7.8.3.6 SYSCLK Status Register ........................................................................... 158
7.8.4 PLL2 Controller Input Clock Electrical Data/Timing ....................................................... 159
7.9 DDR2 Memory Controller ................................................................................................ 160
7.9.1 DDR2 Memory Controller Device-Specific Information ................................................... 160
7.9.2 DDR2 Memory Controller Peripheral Register Description(s) ............................................ 161
7.9.3 DDR2 Memory Controller Electrical Data/Timing .......................................................... 161
7.10 External Memory Interface A (EMIFA) ................................................................................. 162
7.10.1 EMIFA Device-Specific Information .......................................................................... 162
7.10.2 EMIFA Peripheral Register Description(s) .................................................................. 163
7.10.3 EMIFA Electrical Data/Timing ................................................................................ 164
7.10.3.1 Asynchronous Memory Timing .................................................................. 165
7.10.3.2 Programmable Synchronous Interface Timing ................................................ 168
7.10.4 HOLD/ HOLDA Timing ......................................................................................... 171
7.10.5 BUSREQ Timing ............................................................................................... 172
7.11 I2C Peripheral ............................................................................................................. 173
7.11.1 I2C Device-Specific Information .............................................................................. 173
7.11.2 I2C Peripheral Register Description(s) ...................................................................... 175
7.11.3 I2C Electrical Data/Timing .................................................................................... 176
7.11.3.1 Inter-Integrated Circuits (I2C) Timing .......................................................... 176
7.12 Host-Port Interface (HPI) Peripheral ................................................................................... 179
7.12.1 HPI Device-Specific Information ............................................................................. 179
7.12.2 HPI Peripheral Register Description(s) ...................................................................... 179
7.12.3 HPI Electrical Data/Timing .................................................................................... 180
7.13 Multichannel Buffered Serial Port (McBSP) ........................................................................... 190
7.13.1 McBSP Device-Specific Information ......................................................................... 191
7.13.1.1 McBSP Peripheral Register Description(s) ..................................................... 191
7.13.2 McBSP Electrical Data/Timing ............................................................................... 193
7.13.2.1 Multichannel Buffered Serial Port (McBSP) Timing ......................................... 193
7.14 Ethernet MAC (EMAC) ................................................................................................... 200
7.14.1 EMAC Device-Specific Information .......................................................................... 201
7.14.2 EMAC Peripheral Register Description(s) .................................................................. 204
7.14.3 EMAC Electrical Data/Timing ................................................................................. 208
7.14.3.1 EMAC MII and GMII Electrical Data/Timing .................................................. 208
7.14.3.2 EMAC RMII Electrical Data/Timing .............................................................. 211
7.14.3.3 EMAC RGMII Electrical Data/Timing ............................................................ 213
7.14.4 Management Data Input/Output (MDIO) ................................................................... 216
7.14.4.1 MDIO Device-Specific Information .............................................................. 216
7.14.4.2 MDIO Peripheral Register Description(s) ....................................................... 216
7.14.4.3 MDIO Electrical Data/Timing ..................................................................... 217
7.15 Timers ...................................................................................................................... 218
7.15.1 Timers Device-Specific Information .......................................................................... 218
7.15.2 Timers Peripheral Register Description(s) .................................................................. 218
7.15.3 Timers Electrical Data/Timing ................................................................................ 219
7.16 Enhanced Viterbi-Decoder Coprocessor (VCP2) ..................................................................... 220
7.16.1 VCP2 Device-Specific Information ........................................................................... 220
7.16.2 VCP2 Peripheral Register Description(s) ................................................................... 220
Contents 5
SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
7.17 Enhanced Turbo Decoder Coprocessor (TCP2) ...................................................................... 221
7.17.1 TCP2 Device-Specific Information ........................................................................... 221
7.17.2 TCP2 Peripheral Register Description(s) ................................................................... 222
7.18 Peripheral Component Interconnect (PCI) ............................................................................ 223
7.18.1 PCI Device-Specific Information ............................................................................. 223
7.18.2 PCI Peripheral Register Description(s) ...................................................................... 224
7.18.3 PCI Electrical Data/Timing .................................................................................... 229
7.19 UTOPIA .................................................................................................................... 230
7.19.1 UTOPIA Device-Specific Information ........................................................................ 230
7.19.2 UTOPIA Peripheral Register Description(s) ................................................................ 230
7.19.3 UTOPIA Electrical Data/Timing .............................................................................. 231
7.20 Serial RapidIO (SRIO) Port .............................................................................................. 234
7.20.1 Serial RapidIO Device-Specific Information ................................................................ 234
7.20.2 Serial RapidIO Peripheral Register Description(s) ........................................................ 234
7.20.3 Serial RapidIO Electrical Data/Timing ....................................................................... 244
7.21 General-Purpose Input/Output (GPIO) ................................................................................. 246
7.21.1 GPIO Device-Specific Information ........................................................................... 246
7.21.2 GPIO Peripheral Register Description(s) ................................................................... 246
7.21.3 GPIO Electrical Data/Timing .................................................................................. 247
7.22 Emulation Features and Capability ..................................................................................... 248
7.22.1 Advanced Event Triggering (AET) ........................................................................... 248
7.22.2 Trace ............................................................................................................. 248
7.22.3 IEEE 1149.1 JTAG ............................................................................................. 249
7.22.3.1 JTAG Device-Specific Information ............................................................... 249
7.22.4 JTAG Peripheral Register Description(s) ................................................................... 249
7.22.5 JTAG Electrical Data/Timing ................................................................................. 249
Revision History ........................................................................................................................ 250
8 Mechanical Data ............................................................................................................... 251
8.1 Thermal Data .............................................................................................................. 251
8.2 Packaging Information ................................................................................................... 251
Contents 6 Submit Documentation Feedback
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FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

1 Features

• Controlled Baseline
– One Assembly Site – Test Site – One Fabrication Site
• Enhanced Diminishing Manufacturing Sources
(DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree
(1)
• High-Performance Fixed-Point DSP (C6455)
– 1.39 ns, 1.17 ns, 1 ns, and 0.83 ns
Instruction Cycle Time – 1 GHz Clock Rate – Eight 32 Bit Instructions/Cycle – 9600 MIPS/MMACS (16 Bits) – Commercial Temperature (0 ° C to 90 ° C) – Extended Temperature (–40 ° C to 105 ° C) – S-Temp (–55 ° C to 105 ° C)
• C64x+™ DSP Core
– Dedicated SPLOOP Instruction – Compact Instructions (16 Bit) – Instruction Set Enhancements – Exception Handling
• C64x+ Megamodule L1/L2 Memory
Architecture: – 256K Bit (32K Byte) L1P Program Cache
(Direct Mapped) – 256K Bit (32K Byte) L1D Data Cache
[2-Way Set-Associative] – 16M Bit (2096K Byte) L2 Unified Mapped
RAM/Cache (Flexible Allocation) – 256K Bit (32K Byte) L2 ROM – Time Stamp Counter
• Enhanced VCP2
– Supports Over 694 7.95 Kbps AMR – Programmable Code Parameters
• Enhanced Turbo Decoder Coprocessor (TCP2)
– Supports up to Eight 2 Mbps 3GPP
(6 Iterations) – Programmable Turbo Code and Decoding Configurable as Four 32 Bit Timers
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
Parameters
• Endianess: Little Endian, Big Endian
• 64 Bit External Memory Interface (EMIFA)
– Glueless Interface to Asynchronous
Memories (SRAM, Flash, and EEPROM) and Synchronous Memories (SBSRAM, ZBT SRAM)
– Supports Interface to Standard Sync
Devices and Custom Logic (FPGA, CPLD, ASICs, etc.)
– 32M Byte Total Addressable External
Memory Space
• Four 1x Serial RapidIO® Links (or One 4x),
v1.2 Compliant – 1.25/2.5/3.125 Gbps Link Rates – Message Passing, DirectIO Support, Error
Management Extensions, and Congestion Control
– IEEE 1149.6 Compliant I/Os
• DDR2 Memory Controller
– Interfaces to DDR2-533 SDRAM – 32 Bit/16 Bit, 533 MHz (data rate) Bus – 512M Byte Total Addressable External
Memory Space
• EDMA3 Controller (64 Independent Channels)
• 32/16 Bit Host-Port Interface (HPI)
• 32 Bit 33/66 MHz, 3.3 V Peripheral Component
Interconnect (PCI) Master/Slave Interface Conforms to PCI Local Bus Specification (version 2.3)
• One Inter-Integrated Circuit (I2C) Bus
• Two McBSPs
• 10/100/1000 Mb/s Ethernet MAC (EMAC)
– IEEE 802.3 Compliant – Supports Multiple Media Independent
Interfaces (MII, GMII, RMII, and RGMII)
– Eight Independent Transmit (TX) and
Eight Independent Receive (RX) Channels
• Two 64 Bit General-Purpose Timers,
• UTOPIA
– UTOPIA Level 2 Slave ATM Controller – 8 Bit Transmit and Receive Operations up
to 50 MHz per Direction
– User-Defined Cell Format up to 64 Bytes
• 16 General-Purpose I/O (GPIO) Pins
SM320C6455-EP
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document.
C64x+, JTAG, C64x+, VelociTI, C6000, Code Composer Studio, DSP/BIOS, XDS are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2007–2008, Texas Instruments Incorporated
www.ti.com
ZTZ/GTZ 697-PIN BALL GRID ARRAY (BGA) PACKAGE
(BOTTOM VIEW)
A
2
B
1 345678910111213141516171819202122232425
26
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
272829
AG
AH
AJ
NOTE: The ZTZ mechanical package designator represents the version of the GTZ package with lead-free balls. For more detailed information,
see the Mechanical Data section of this document.
SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
• System PLL and PLL Controller Boundary-Scan-Compatible
• Secondary PLL and PLL Controller, Dedicated • 697-Pin Ball Grid Array (BGA) Package
to EMAC and DDR2 Memory Controller (ZTZ or GTZ Suffix), 0.8 mm Ball Pitch
• Advanced Event Triggering (AET) Compatible • 0.09 µ m/7-Level Cu Metal Process (CMOS)
• Trace-Enabled Device • 3.3/1.8/1.5/1.25/1.2 V I/Os, 1.25/1.2 V Internal
• IEEE-1149.1 ( JTAG™)

1.1 ZTZ/GTZ BGA Package (Bottom View)

Figure 1-1 shows the SM320C6455-EP device 697-pin ball grid array package (bottom view).
Figure 1-1. ZTZ/GTZ BGA Package (Bottom View)

1.2 Description

The C64x+™ DSPs (including the SM320C6455-EP device) are the highest-performance fixed-point DSP
generation in the C6000™ DSP platform. The C6455 device is based on the third-generation
high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by
Texas Instruments (TI), making these DSPs an excellent choice for applications including video and
telecom infrastructure, imaging/medical, and wireless infrastructure (WI). The C64x+™ devices are
upward code-compatible from previous devices that are part of the C6000™ DSP platform.
Based on 90-nm process technology and with performance of up to 9600 million instructions per second
(MIPS) [or 9600 16 bit MMACs per cycle] at a 1.2-GHz clock rate, the C6455 device offers cost-effective
solutions to high-performance DSP programming challenges. The C6455 DSP possesses the operational
flexibility of high-speed controllers and the numerical capability of array processors.
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SM320C6455-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier
C6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ .M unit doubles
the multiply throughput versus the C64x core by performing four 16 bit x 16 bit multiply-accumulates
(MACs) every clock cycle. Thus, eight 16 bit x 16 bit MACs can be executed every cycle on the C64x+
core. At a 1.2-GHz clock rate, this means 9600 16 bit MMACs can occur every second. Moreover, each
multiplier on the C64x+ core can compute one 32 bit x 32 bit MAC or four 8 bit x 8 bit MACs every clock
cycle.
The C6455 device includes Serial RapidIO. This high bandwidth peripheral dramatically improves system
performance and reduces system cost for applications that include multiple DSPs on a board, such as
video and telecom infrastructures and medical/imaging.
The C6455 DSP integrates a large amount of on-chip memory organized as a two-level memory system.
The level-1 (L1) program and data memories on the C6455 device are 32KB each. This memory can be
configured as mapped RAM, cache, or some combination of the two. When configured as cache, L1
program (L1P) is a direct mapped cache where as L1 data (L1D) is a two-way set associative cache. The
level 2 (L2) memory is shared between program and data space and is 2096KB in size. L2 memory also
can be configured as mapped RAM, cache, or some combination of the two. The C64x+ Megamodule also
has a 32 bit peripheral configuration (CFG) port, an internal DMA (IDMA) controller, a system component
with reset/boot control, interrupt/exception control, a power-down control, and a free-running 32 bit timer
for time stamp.
The peripheral set includes: an inter-integrated circuit bus module (I2C); two multichannel buffered serial
ports (McBSPs); an 8 bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode
(ATM) Slave [UTOPIA Slave] port; two 64 bit general-purpose timers (also configurable as four 32 bit
timers); a user-configurable 16 bit or 32 bit host-port interface (HPI16/HPI32); a peripheral component
interconnect (PCI); a 16-pin general-purpose input/output port (GPIO) with programmable interrupt/event
generation modes; an 10/100/1000 Ethernet media access controller (EMAC), which provides an efficient
interface between the C6455 DSP core processor and the network; a management data input/output
(MDIO) module (also part of the EMAC) that continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system; a glueless external memory interface (64 bit EMIFA), which is
capable of interfacing to synchronous and asynchronous peripherals; and a 32 bit DDR2 SDRAM
interface.
The I2C ports on the C6455 allow the DSP to easily control peripheral devices and communicate with a
host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to
communicate with serial peripheral interface (SPI) mode peripheral devices.
The C6455 device has two high-performance embedded coprocessors [enhanced Viterbi Decoder
Coprocessor (VCP2) and enhanced Turbo Decoder Coprocessor (TCP2)] that significantly speed up
channel-decoding operations on-chip. The VCP2 operating at CPU clock divided-by-3 can decode over
694 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP2 supports constraint
lengths K = 5, 6, 7, 8, and 9, rates R = 3/4, 1/2, 1/3, 1/4, and 1/5 and flexible polynomials, while
generating hard decisions or soft decisions. The TCP2 operating at CPU clock divided-by-3 can decode
up to fifty 384-Kbps or eight 2-Mbps turbo encoded channels (assuming 6 iterations). The TCP2
implements the max*log-map algorithm and is designed to support all polynomials and rates required by
Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and
turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also
programmable. Communications between the VCP2/TCP2 and the CPU are carried out through the
EDMA3 controller.
The C6455 has a complete set of development tools which includes: a new C compiler, an assembly
optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into
source code execution.
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L2 Memory Controller
(Memory Protect/
Bandwidth Mgmt)
Serial Rapid
I/O
DDR2
Mem Ctlr
System
(B)
C64x+ DSP Core
Data Path B
B Register File
B31−B16
B15−B0
Instruction Fetch
Data Path A
A Register File
A31−A16
A15−A0
Device
Configuration
Logic
.L1 .S1
.M1
xx xx
.D1 .D2
.M2
xx xx
.S2 .L2
64
SBSRAM
SRAM
L1P Cache Direct-Mapped
32K Bytes
L1D Cache
2-Way Set-Associative 32K Bytes Total
C6455
Primary Switched Central Resource
PLL1 and
PLL1
Controller
EMIFA
ZBT SRAM
HI
Boot Configuration
ROM/FLASH
I/O Devices
VCP2
I2C
GPIO16
(B)
16
McBSP0
(A)
Internal DMA
(IDMA)
M e g a m o d u
l
e
L2
Cache
Memory
2096K
Bytes
L1P Memory Controller (Memory Protect/Bandwidth Mgmt)
TCP2
McBSP1
(A)
HPI (32/16)
(B)
Instruction
Decode
16-/32-bit
Instruction Dispatch
Control Registers
In-Circuit Emulation
DDR2 SDRAM
32
LO
Timer1
(C)
HI
LO
Timer0
(C)
PLL2 and
PLL2
Controller
(D)
EMAC
10/100/1000
SPLOOP Buffer
Power Control
L1D Memory Controller (Memory Protect/Bandwidth Mgmt)
Interrupt and Exception Controller
EDMA 3.0
L2 ROM
32K
Bytes
(E)
Secondary
Switched Central
Resource
A. McBSPs: Framing Chips − H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs B. The PCI peripheral pins are muxed with some of the HPI peripheral pins and the UTOPIA address pins. For more detailed information, see the Device
Configuration section of this document.
C. Each of the TIMER peripherals (TIMER1 and TIMER0) is configurable as either two 64-bit general-purpose timers or two 32-bit general-purpose
timers or a watchdog timer. D. The PLL2 controller also generates clocks for the EMAC. E. When accessing the internal ROM of the DSP, the CPU frequency must always be less than 750 MHz.
MDIO
RMGII
(D)
GMII
RMII
MII
UTOPIA
(B)
PCI66
(B)
SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

1.3 Functional Block Diagram

Figure 1-2 shows the functional block diagram of the C6455 device.
Figure 1-2. Functional Block Diagram
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FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

2 Device Overview

2.1 Device Characteristics

Table 2-1 , provides an overview of the C6455 DSP. The tables show significant features of the C6455
device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count.
Table 2-1. Characteristics of the C6455 Processor
HARDWARE FEATURES C6455
EMIFA (64 bit bus width) (clock source = AECLKIN or SYSCLK4)
DDR2 Memory Controller (32 bit bus width) [1.8 V I/O] (clock source = CLKIN2)
EDMA3 (64 independent channels) [CPU/3 clock rate] 1
High-speed 1x/4x Serial Rapid IO Port 1 Peripherals Not all peripherals pins
are available at the same time (For more detail, see the Device Configuration section).
Decoder Coprocessors
On-Chip Memory
C64x+ Megamodule Megamodule Revision ID Register (address location: Revision ID 0181 2000h)
JTAG BSDL_ID JTAGID register (address location: 0x02A80008) Frequency MHz 720, 850, 1000 (1 GHz), and 1200 (1.2 GHz)
Cycle Time ns 1 ns (C6455 A-1000, -1000) [1-GHz CPU]
Voltage
PLL1 and PLL1 Controller Options
PLL2 x20
BGA Package 24 x 24 mm
I2C 1
HPI (32- or 16 bit user selectable) 1 (HPI16 or HPI32)
PCI (32 bit), [66-MHz or 33-MHz] 1 (PCI66 or PCI33)
McBSPs (internal CPU/6 or external clock source up
to 100 Mbps)
UTOPIA (8 bit mode, 50-MHz, Slave-only) 1
10/100/1000 Ethernet MAC (EMAC) 1
Management Data Input/Output (MDIO) 1
64 Bit Timers (Configurable)
(internal clock source = CPU/6 clock frequency)
General-Purpose Input/Output Port (GPIO) 16
VCP2 (clock source = CPU/3 clock frequency) 1
TCP2 (clock source = CPU/3 clock frequency) 1
Size (Bytes) 2192K
32K-Byte (32KB) L1 Program Memory Controller
Organization 32KB Data Memory Controller [SRAM/Cache]
See Section 5.6 , Megamodule Revision
See Section 3.6 , JTAG ID (JTAGID) Register
1.39 ns (C6455-720), 1.17 ns (C6455-850),
0.83 ns (C6455-1200) [1.2-GHz CPU]
Core (V)
I/O (V) 1.5/1.8 [EMAC RGMII], and
CLKIN1 frequency multiplier Bypass (x1), x15, x20, x25, x30, x32
CLKIN2 frequency multiplier
[DDR2 Memory Controller and EMAC support only]
697-Pin Flip-Chip Plastic BGA (ZTZ) 697-Pin Flip-Chip Plastic BGA (GTZ)
2 64 bit or 4 32 bit
2096KB L2 Unified Memory/Cache
1.25 V (A-1000/-1000/-1200)
1.25/1.2 [RapidIO],
1.8 and 3.3 V [I/O Supply Voltage]
1
1
2
[SRAM/Cache]
32KB L2 ROM
Description
1.2 V (-850/-720)
(1)
(1) The extended temperature device's (A-1000) electrical characteristics and ac timings are the same as those for the corresponding
commercial temperature devices (-1000).
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
Table 2-1. Characteristics of the C6455 Processor (continued)
HARDWARE FEATURES C6455
Process Technology µ m 0.09 µ m Product Status
Device Part Numbers TMS320C6455ZTZ8,
(2) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
(2)

2.2 CPU (DSP Core) Description

The C64x+ Central Processing Unit (CPU) consists of eight functional units, two register files, and two data paths as shown in Figure 2-1 . The two general-purpose register files (A and B) each contain thirty-two 32 bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types supported include packed 8 bit data, packed 16 bit data, 32 bit data, 40 bit data, and 64 bit data. Values larger than 32 bits, such as 40 bit-long or 64 bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register).
The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and store results from the register file into memory.
Product Preview (PP), Advance Information (AI),
or Production Data (PD)
(For more details on the C64x+™ DSP part
numbering, see Figure 2-13 )
PD
TMS320C6455ZTZ7,
TMS320C6455ZTZ
The C64x+ CPU extends the performance of the C64x core through enhancements and new features. Each C64x+ .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, two
16 x 16 bit multiplies, two 16 x 32 bit multiplies, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four 16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for Galois field multiplication for 8 bit and 32 bit data. Many communications algorithms such as FFTs and modems require complex multiplication. The complex multiply (CMPY) instruction takes for 16 bit inputs and produces a 32 bit real and a 32 bit imaginary output. There are also complex multiplies with rounding capability that produces one 32 bit packed output that contain 16 bit real and 16 bit imaginary values. The 32 x 32 bit multiply instructions provide the extended precision necessary for audio and other high-precision algorithms on a variety of signed and unsigned 32 bit data types.
The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a pair of common inputs. Versions of this instruction exist to work on 32 bit data or on pairs of 16 bit data performing dual 16 bit add and subtracts in parallel. There are also saturated forms of these instructions.
The C64x+ core enhances the .S unit in several ways. In the C64x core, dual 16 bit MIN2 and MAX2 comparisons were available only on the .L units. On the C64x+ core they also are available on the .S unit, which increases the performance of algorithms that do searching and sorting. Finally, to increase data packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8 bit/16 bit and dual 16 bit instructions. Unpack instructions prepare 8 bit data for parallel 16 bit operations. Pack instructions return parallel results to output precision including saturation support.
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SM320C6455-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
Other new features include:
• SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.
• Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+ compiler can restrict the code to use certain registers in the register file. This compression is performed by the code generation tools.
• Instruction Set Enhancements - As noted above, there are new instructions such as 32 bit multiplications, complex multiplications, packing, sorting, bit manipulation, and 32 bit Galois field multiplication.
• Exception Handling - Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and from system events (such as a watchdog time expiration).
• Privilege - Defines user and supervisor modes of operation, allowing the operating system to give
a basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with read, write, and execute permissions.
• Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.
For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following documents:
• TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732 )
• TMS320C64x+ DSP Cache User's Guide (literature number SPRU862 )
• TMS320C64x+ Megamodule Reference Guide (literature number SPRU871 )
• TMS320C6455 Technical Reference (literature number SPRU965 )
• TMS320C64x to TMS320C64x+ CPU Migration Guide (literature number SPRAA84 )
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src2
src2
.D1
.M1
.S1
.L1
long src
odd dst
src2
src1
src1
src1
src1
even dst
even dst
odd dst
dst1
dst
src2
src2
src2
long src
DA1
ST1b
LD1b LD1a
ST1a
Data path A
Odd
register
file A
(A1, A3,
A5...A31)
Odd
register
file B
(B1, B3,
B5...B31)
.D2
src1
dst
src2
DA2
LD2a LD2b
src2
.M2
src1
dst1
.S2
src1
even dst
long src
odd dst
ST2a ST2b
long src
.L2
even dst
odd dst
src1
Data path B
Control Register
32 MSB 32 LSB
dst2
(A)
32 MSB 32 LSB
2x
1x
32 LSB
32 MSB
32 LSB
32 MSB
dst2
(B)
(B) (A)
8
8
8
8
32
32
32
32
(C)
(C)
Even
register
file A
(A0, A2,
A4...A30)
Even
register
file B
(B0, B2,
B4...B30)
(D)
(D)
(D)
(D)
A. On .M unit, dst2 is 32 MSB. B. On .M unit, dst1 is 32 LSB. C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits. D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.
SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
Figure 2-1. C64x+™ CPU (DSP Core) Data Paths
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FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

2.3 Memory Map Summary

Table 2-2 shows the memory map address ranges of the C6455 device. The external memory
configuration register address ranges in the C6455 device begin at the hex address location 0x7000 0000 for EMIFA and hex address location 0x7800 0000 for DDR2 Memory Controller.
Table 2-2. C6455 Memory Map Summary
MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE
Reserved 1024K 0000 0000 - 000F FFFF Internal ROM 32K 0010 0000 - 0010 7FFF Reserved 7M - 32K 0010 8000 - 007F FFFF Internal RAM (L2) [L2 SRAM] 2M 0080 0000 - 009F FFFF Reserved 4M 00A0 0000 - 00DF FFFF L1P SRAM 32K 00E0 0000 - 00E0 7FFF Reserved 1M - 32K 00E0 8000 - 00EF FFFF L1D SRAM 32K 00F0 0000 - 00F0 7FFF Reserved 1M - 32K 00F0 8000 - 00FF FFFF Reserved 8M 0100 0000 - 017F FFFF C64x+ Megamodule Registers 4M 0180 0000 - 01BF FFFF Reserved 12.5M 01C0 0000 - 0287 FFFF HPI Control Registers 256K 0288 0000 - 028B FFFF McBSP 0 Registers 256K 028C 0000 - 028F FFFF McBSP 1 Registers 256K 0290 0000 - 0293 FFFF Timer 0 Registers 256K 0294 0000 - 0297 FFFF Timer 1 Registers 128K 0298 0000 - 0299 FFFF PLL1 Controller (including Reset Controller) Registers 512 029A 0000 - 029A 01FF Reserved 256K - 512 029A 0200 - 029B FFFF PLL2 Controller Registers 512 029C 0000 - 029C 01FF Reserved 64K 029C 0200 - 029C FFFF EDMA3 Channel Controller Registers 32K 02A0 0000 - 02A0 7FFF Reserved 96K 02A0 8000 - 02A1 FFFF EDMA3 Transfer Controller 0 Registers 32K 02A2 0000 - 02A2 7FFF EDMA3 Transfer Controller 1 Registers 32K 02A2 8000 - 02A2 FFFF EDMA3 Transfer Controller 2 Registers 32K 02A3 0000 - 02A3 7FFF EDMA3 Transfer Controller 3 Registers 32K 02A3 8000 - 02A3 FFFF Reserved 256K 02A4 0000 - 02A7 FFFF Chip-Level Registers 256K 02A8 0000 - 02AB FFFF Device State Control Registers 256K 02AC 0000 - 02AF FFFF GPIO Registers 16K 02B0 0000 - 02B0 3FFF I2C Data and Control Registers 256K 02B0 4000 - 02B3 FFFF UTOPIA Control Registers 512 02B4 0000 - 02B4 01FF Reserved 256K - 512 02B4 0200 - 02B7 FFFF VCP2 Control Registers 128K 02B8 0000 - 02B9 FFFF TCP2 Control Registers 128K 02BA 0000 - 02BB FFFF Reserved 256K 02BC 0000 - 02BF FFFF PCI Control Registers 256K 02C0 0000 - 02C3 FFFF Reserved 256K 02C4 0000 - 02C7 FFFF EMAC Control 4K 02C8 0000 - 02C8 0FFF EMAC Control Module Registers 2K 02C8 1000 - 02C8 17FF MDIO Control Registers 2K 02C8 1800 - 02C8 1FFF
SM320C6455-EP
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
Table 2-2. C6455 Memory Map Summary (continued)
MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE
EMAC Descriptor Memory 8K 02C8 2000 - 02C8 3FFF Reserved 496K 02C8 4000 - 02CF FFFF RapidIO Control Registers 256K 02D0 0000 - 02D3 FFFF Reserved 768K 02D4 0000 - 02DF FFFF RapidIO CPPI RAM 16K 02E0 0000 - 02E0 3FFF Reserved 2M - 16K 02E0 4000 - 02FF FFFF Reserved 16M 0300 0000 - 03FF FFFF Reserved 192M 0400 0000 - 0FFF FFFF Reserved 256M 1000 0000 - 1FFF FFFF Reserved 256M 2000 0000 - 2FFF FFFF McBSP 0 Data 256 3000 0000 - 3000 00FF Reserved 64M - 256 3000 0100 - 33FF FFFF McBSP 1 Data 256 3400 0000 - 3400 00FF Reserved 64M - 256 3400 0100 - 37FF FFFF UTOPIA Receive (Rx) Data Queue 1K 3C00 0000 - 3C00 03FF UTOPIA Transmit (Tx) Data Queue 1K 3C00 0400 - 3C00 07FF Reserved 16M - 2K 3C00 0800 - 3CFF FFFF Reserved 48M 3D00 0000 - 3FFF FFFF PCI External Memory Space 256M 4000 0000 - 4FFF FFFF TCP2 Data Registers 128M 5000 0000 - 57FF FFFF VCP2 Data Registers 128M 5800 0000 - 5FFF FFFF Reserved 256M 6000 0000 - 6FFF FFFF EMIFA (EMIF64) Configuration Registers 128M 7000 0000 - 77FF FFFF DDR2 Memory Controller Configuration Registers 128M 7800 0000 - 7FFF FFFF Reserved 256M 8000 0000 - 8FFF FFFF Reserved 256M 9000 0000 - 9FFF FFFF EMIFA CE2 - SBSRAM/Async Reserved 256M - 8M A080 0000 - AFFF FFFF EMIFA CE3 - SBSRAM/Async Reserved 256M - 8M B080 0000 - BFFF FFFF EMIFA CE4 - SBSRAM/Async Reserved 256M - 8M C080 0000 - CFFF FFFF EMIFA CE5 - SBSRAM/Async Reserved 256M - 8M D080 0000 - DFFF FFFF DDR2 Memory Controller CE0 - DDR2 SDRAM 512M E000 0000 - FFFF FFFF
(1) The EMIFA CE0 and CE1 are not functionally supported on the C6455 device, and therefore, are not pinned out.
(1)
(1)
(1)
(1)
8M A000 0000 - A07F FFFF
8M B000 0000 - B07F FFFF
8M C000 0000 - C07F FFFF
8M D000 0000 - D07F FFFF
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SM320C6455-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

2.4 Boot Sequence

The boot sequence is a process by which the DSP's internal memory is loaded with program and data sections and the DSP's internal registers are programmed with predetermined values. The boot sequence is started automatically after each power-on reset, warm reset, max reset, and system reset. For more details on the initiators of these resets, see Section 7.6 , Reset Controller.
There are several methods by which the memory and register initialization can take place. Each of these methods is referred to as a boot mode. The boot mode to be used is selected at reset through the BOOTMODE[3:0] pins.
Each boot mode can be classified as a hardware boot mode or as a software boot mode. Software boot modes require the use of the on-chip bootloader. The bootloader is DSP code that transfers application code from an external source into internal or external program memory after the DSP is taken out of reset. The bootloader is permanently stored in the internal ROM of the DSP starting at byte address 0010 0000h. Hardware boot modes are carried out by the boot configuration logic. The boot configuration logic is actual hardware that does not require the execution of DSP code. Section 2.4.1 , Boot Modes Supported, describes each boot mode in more detail.
When accessing the internal ROM of the DSP, the CPU frequency must always be less than 750 MHz. Therefore, when using a software boot mode, care must be taken such that the CPU frequency does not exceed 750 MHz at any point during the boot sequence. After the boot sequence has completed, the CPU frequency can be programmed to the frequency required by the application.

2.4.1 Boot Modes Supported

The C6455 has six boot modes:
• No boot (BOOTMODE[3:0] = 0000b)
• Host boot (BOOTMODE[3:0] = 0001b and BOOTMODE[3:0] = 0111b)
With no boot, the CPU executes directly from the internal L2 SRAM located at address 0x80 0000. Note: device operations are undefined if invalid code is located at address 0x80 0000. This boot mode is a hardware boot mode.
If host boot is selected, after reset, the CPU is internally "stalled" while the remainder of the device is released. During this period, an external host can initialize the CPU's memory space as necessary through Host Port Interface (HPI) or the Peripheral Component Interconnect (PCI) interface. Internal configuration registers, such as those that control the EMIF also can be initialized by the host with two exceptions: Device State Control registers (Section 3.4 ), PLL1 and PLL2 Controller registers (Section 7.7 and Section 7.8 ) cannot be accessed through any host interface, including HPI and PCI.
Once the host is finished with all necessary initialization, it must generate a DSP interrupt (DSPINT) to complete the boot process. This transition causes boot configuration logic to bring the CPU out of the "stalled" state. The CPU then begins execution from the internal L2 SRAM located at 0x80 0000. Note that the DSP interrupt is registered in bit 0 (channel 0) of the EDMA Event Register (ER). This event must be cleared by software before triggering transfers on DMA channel 0.
All memory, with the exceptions previously described, may be written to and read by the host. This allows for the host to verify what it sends to the DSP if required. After the CPU is out of the "stalled" state, the CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received.
As previously mentioned, for the C6455 device, the Host Port Interface (HPI) and the Peripheral Component Interconnect (PCI) interface can be used for host boot. To use the HPI for host boot, the PCI_EN pin (Y29) must be low [default] (enabling the HPI peripheral) and BOOTMODE[3:0] must be set to 0001b at device reset. Conversely, to use the PCI interface for host boot, the PCI_EN pin (Y29) must be high (enabling the PCI peripheral) and BOOTMODE[3:0] must be set to 0111b at device reset. For the HPI host boot, the DSP interrupt can be generated through the use of the DSPINT bit in the HPI Control (HPIC) register.
For the HPI host boot, the CPU is actually held in reset until a DSP interrupt is generated by the host. The DSP interrupt can be generated through the use of the DSPINT bit in the HPI Control (HPIC) register. Because the CPU is held in reset during HPI host boot, it does not respond to emulation
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software such as Code Composer Studio. For the PCI host boot, the CPU is out of reset, but it executes an IDLE instruction until a DSP interrupt
is generated by the host. The host can generate a DSP interrupt through the PCI peripheral by setting the DSPINT bit in the Back-End Application Interrupt Enable Set Register (PCIBINTSET) and the Status Set Register (PCISTATSET).
Note that the HPI host boot is a hardware boot mode while the PCI host boot is a software boot mode. If PCI boot is selected, the on-chip bootloader configures the PLL1 Controller such that CLKIN1 is
multiplied by 15. More specifically, PLLM is set to 0Eh (x15) and RATIO is set to 0 ( ÷ 1) in the PLL1 Multiplier Control Register (PLLM) and PLL1 Pre-Divider Register (PREDIV), respectively. The CLKIN1 frequency must not be greater than 50 MHz so that the maximum speed of the internal ROM, 750 MHz, is not violated. The CFGGP[2:0] pins must be set to 000b during reset for proper operation of the PCI boot mode.
As mentioned previously, a DSP interrupt must be generated at the end of the host boot process to begin execution of the loaded application. Because the DSP interrupt generated by the HPI and PCI is mapped to the EDMA event DSP_EVT (DMA channel 0), it will get recorded in bit 0 of the EDMA Event Register (ER). This event must be cleared by software before triggering transfers on DMA channel 0.
• EMIFA 8 bit ROM boot (BOOTMODE[3:0] = 0100b) After reset, the device will begin executing software out of an Asynchronous 8 bit ROM located in
EMIFA CE3 space using the default settings in the EMIFA registers. This boot mode is a hardware boot mode.
• Master I2C boot (BOOTMODE[3:0] = 0101b) After reset, the DSP can act as a master to the I2C bus and copy data from an I2C EEPROM or a
device acting as an I2C slave to the DSP using a predefined boot table format. The destination address and length are contained within the boot table. This boot mode is a software boot mode.
• Slave I2C boot (BOOTMODE[3:0] = 0110b) A Slave I2C boot is also implemented, which programs the DSP as an I2C Slave and simply waits for a
Master to send data using a standard boot table format. Using the Slave I2C boot, a single DSP or a device acting as an I2C Master can simultaneously boot
multiple slave DSPs connected to the same I2C bus. Note that the Master DSP may require booting via an I2C EEPROM before acting as a Master and booting other DSPs.
The Slave I2C boot is a software boot mode.
• Serial RapidIO boot (BOOTMODE[3:0] = 1000b through 1111b) After reset, the following sequence of events occur: – The on-chip bootloader configures device registers, including SerDes, and EDMA3 – The on-chip bootloader resets the peripheral's state machines and registers – RapidIO ports send idle control symbols to initialize SerDes ports – The host explores the system with RapidIO maintenance packets – The host identifies, enumerates, and initializes the RapidIO device – The host controller configures DSP peripherals through maintenance packets – The application software is sent from the host controller to DSP memory – The DSP CPU is awakened by interrupt such as a RapidIO DOORBELL packet – The application software is executed and normal operation follows For Serial RapidIO boot, BOOTMODE2 (L26 pin) is used in conjunction with CFGGP[2:0] (T26, U26,
and U25 pins, respectively) to determine the device address within the RapidIO network. BOOTMODE2 is the MSB of the address, while CFGGP[2:0] are used as the three LSBs–giving the user the opportunity to have up to 16 unique device IDs.
BOOTMODE[1:0] (L25 and P26, respectively) denote the configuration of the RapidIO peripheral; i.e., "00b" refers to RapidIO Configuration 0. For exact device RapidIO Configurations, see the
TMS320C645xx Bootloader User's Guide (literature number SPRUEC6 ).
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2.4.2 2nd-Level Bootloaders

SM320C6455-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
The SRIO boot is a software boot mode.
Any of the boot modes can be used to download a 2nd-level bootloader. A 2nd-level bootloader allows for any level of customization to current boot methods as well as definition of a completely customized boot. TI offers a few second-level bootloaders, such as an EMAC bootloader and a UTOPIA bootloader, which can be loaded using the Master I2C boot.
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AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
13121110987654321
13121110987654321
CLKR1/
GP[0]
HD15/
AD15
HD2/
AD2
URADDR0/
PGNT/ GP[12]
HD22/
AD22
DV
DD33
RSV15
UXADDR1/
PIDSEL
RSV16
HDS1/
PSERR
HINT/
PFRAME
DV
DD33
HHWIL/
PCLK
V
SS
HD12/
AD12
HD24/
AD24
RSV03
HD20/
AD20
HD18/
AD18
HD6/
AD6
HD16/ AD16
V
SS
HD28/
AD28
HD17/
AD17
HD31/ AD31
HD14/
AD14
HCNTL1/
PDEVSEL
HR/W/
PCBE2
HRDY/ PIRDY
URADDR1/
PRST/
GP[13]
HD21/
AD21
DV
DD33
V
SS
EMU8
RSV36
EMU11
EMU1
EMU10
EMU12
RSV37
EMU15
EMU4
EMU13
DV
DD33
DV
DD33
V
SS
EMU0
V
SS
DV
DD33
RSV38EMU6
CLKX1/
GP[3]
DV
DD33
V
SS
EMU18
DV
DD33
EMU5
V
SS
DV
DD33
HD9/
AD9
HD23/ AD23
HD3/
AD3
HD10/ AD10
GP[6]
V
SS
EMU14
GP[7]
RSV02
HD4/
AD4
HD30/
AD30
CV
DD
HD27/
AD27
V
SS
V
SS
V
SS
DV
DD33
V
SS
CV
DD
CV
DD
V
SS
DV
DD33
DV
DD33
V
SS
V
SS
DV
DD33
V
SS
V
SS
HD19/
AD19
HD13/
AD13
HD29/
AD29
DV
DD33
DV
DD33
HD25/
AD25
DV
DD33
HD0/
AD0
V
SS
HD11/ AD11
TOUTL0
EMU3
EMU7
TOUTL1
V
SS
DV
DD33
V
SS
DV
DD33
V
SS
HDS2/
PCBE1
HCNTL0/
PSTOP
HCS/
PPERR
V
SS
HD8/
AD8
V
SS
HD26/
AD26
V
SS
HD7/
AD7
HD1/
AD1
EMU2 RSV39
V
SS
DV
DD33
HAS/
PPAR
HD5/
AD5
AH
TINPL0 EMU17TDONMI EMU16GP[4]V
SS
TRST
TDI
RSV27 EMU9
AJ
TINPL1 TMSV
SS
CLKS RSV40
GP[5]DV
DD33
DV
DD33
TCK
RSV26
SYSCLK4/
GP[1]
14
V
SS
DV
DD33
RESETSTAT
POR
V
SS
CV
DD
CV
DD
RESET
DV
DD33
V
SS
15
AV
DDA
V
SS
DV
DD33
RIOCLK
CV
DD
V
SS
V
SS
RIOCLK
V
SS
DV
DD33
14 15
V
SS
CV
DD
CV
DD
CV
DD
V
SS
V
SS
V
SS
CV
DD
DV
DDRM
V
SS
V
SS
CV
DD
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
AH
AJFSX0 DR0
FSR0
DR1/
GP[8]
CLKR0
FSX1/
GP[11]
DX1/ GP[9]
CLKX0
DX0
FSR1/
GP[10]
SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

2.5 Pin Assignments

2.5.1 Pin Map

Figure 2-2 through Figure 2-5 show the C6455 pin assignments in four quadrants (A, B, C, and D).
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Figure 2-2. C6455 Pin Map (Bottom View) [Quadrant A]
www.ti.com
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
17 18 19 20 21 22 23 24 25 26 27 28 29
17 18 19 20 21 22 23 24 25 26 27 28 29
SDA
AED27
V
SS
ASADS/
ASRE
AED17
AHOLD
PLLV1
AEA13/
LENDIAN
AEA4/
SYSCLKOUT
_EN
AEA5/
MCBSP1
_EN
AEA6/ PCI66
AECLKOUTACE5 ACE4
ABA0/
DDR2_EN
ABE7ACE2 RSV41
AAOE/ ASOE
RSV42 RSV44
ABE2ABE0
AED29
AED31
ACE3
AEA1/
CFGGP1
AEA11
AEA2/
CFGGP2
AEA14/
HPI_
WIDTH
AED21
DV
DD33
V
SS
V
SS
V
SS
DV
DD33
AV
DDT
DV
DDR
V
SS
V
SS
RSV17
V
SS
DV
DD33
V
SS
V
SS
AV
DDT
RIOTX0
DV
DD33
V
SS
DV
DD33
V
SS
AED3V
SS
RIOTX1
AED7
AED1
SCL
AV
DDA
V
SS
AV
DDT
RIOTX2
V
SS
DV
DD33
V
SS
AED25
AED28
AED11
AED4
AED9
AED15RIOTX3
AED16
ABA1/
EMIFA_EN
RSV43
ABE1
DV
DD12
AED24DV
DD33
V
SS
V
SS
AED19
DV
DD33
CV
DD
CV
DD
DV
DD33
V
SS
V
SS
DV
DD33
DV
DD33
V
SS
V
SS
V
SS
DV
DD33
V
SS
AED26V
SS
DV
DD33
AED22AED0
AED13AED12
AED10RIOTX0AV
DDT
RIOTX3
AED30DV
DD33
AEA12/
UTOPIA_EN
V
SS
V
SS
V
SS
V
SS
RSV20
AEA0/
CFGGP0
V
SS
DV
DD33
AR/WDV
DD33
PCI_ENDV
DD33
AED23
AAWE/ ASWE
RIOTX1RIOTX2DV
DD33
ABE3
AEA3
AED8
AH
DV
DD33
V
SS
AV
DDT
RIORX0 AED14RIORX3 AED2 AED18
V
SS
RIORX0VSSV
SS
V
SS
RIORX3
AJ
V
SS
DV
DD33
V
SS
RIORX1 AED5RIORX2 AED6 AED20 DV
DD33
AV
DDT
RIORX1RIORX2AV
DDT
16
V
SS
AV
DDA
V
SS
DV
DD33
V
SS
DV
DD12
CV
DD
V
SS
DV
DD33
V
SS
16
V
SS
CV
DD
CV
DD
DV
DDRM
V
SS
V
SS
V
SS
DV
DDRM
V
SS
CV
DD
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
AH
AJ
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
SM320C6455-EP
Submit Documentation Feedback Device Overview 21
Figure 2-3. C6455 Pin Map (Bottom View) [Quadrant B]
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C
D
E
F
G
H
J
K
L
M
N
P
17 18 19 20 21 22 23 24 25 26 27 28 29
17 18 19 20 21 22 23 24 25 26 27 28 29
RSV09
AED52
DV
DD33
V
SS
V
SS
V
SS
AECLKIN
AEA9/
MACSEL0
CLKIN1
DV
DD33
AEA15/
AECLKIN
_SEL
AED40AED44 AED42
AED34
ABE6
AED32
ABE4
AEA18/
BOOT
MODE2
AED37
ABUSREQ
AED46
AEA16/
BOOT
MODE0
AEA19/
BOOT
MODE3
AHOLDA
AEA10/
MACSEL1
V
SS
V
SS
DV
DD18
DED19
V
SS
CV
DD
VSSDSDDQS2
DSDDQ
GATE2
DED23
DV
DD18
DV
DD33
DSDDQS3
DSDDQS3
V
SS
DV
DD18
RSV11
RSV12 RSV33DSDDQM2 DED26
V
SS
RSV32
RSV23
V
SS
V
SS
DEA4
DEA1
AV
DLL2
DV
DD33
DV
DD33
AED56
AED50
AED45
AED59
AED61
AED58DEA5
AED60
AED33
AEA17/
BOOT
MODE1
DSDDQ
GATE3
RSV19
AED55V
SS
DV
DD18
DV
DD18
AED39
DV
DD33
V
SS
V
SS
RSV30
DV
DD33
V
SS
V
SS
DV
DD18
V
SS
DV
DD18
DV
DD18
AED35AED48AED54DV
DD18
V
SS
DV
DD33
AED47
DV
DD33
DV
DD33
AED57DED27DSDDQS2DEA0
AED41DSDDQM3
DV
DD33
V
SS
CV
DD
V
SS
CV
DD
V
SS
AEA8/
PCI_EEAI
RSV31
AED38
V
SS
AARDY
V
SS
AED36AED63
V
SS
DED22DED18DEA6
ABE5
AEA7
AED43
B
DED29 DED31DV
DD18
DED25
RSV22
DEA2 AED49 AED51
V
SS
DV
DD18
DED21DED16DEA7
A
DED28 DED30V
SS
DED24 DV
DD18MON
DEA3 AED62 AED53 DV
DD33
V
SS
DED20DED17DEODT1
16
DV
DD18
CV
DD
DEODT0
DEA8
CV
DD
V
SS
V
SS
DEA9
DEA10
DEA11
16
CV
DD
V
SS
V
SS
CV
DD
V
SS
CV
DD
C
D
E
F
G
H
J
K
L
M
N
P
B
A
SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
Figure 2-4. C6455 Pin Map (Bottom View) [Quadrant C]
Device Overview22 Submit Documentation Feedback
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A
D
E
F
G
H
J
K
L
M
N
P
13121110987654321
13121110987654321
RGRXD2
RGTXD3
DV
DD33
UXDATA2/
MTXD2
V
SS
UXDATA0/
MTXD0/
RMTXD0
CV
DDMON
UXDATA6/
MTXD6
V
SS
URADDR3/
PREQ/ GP[15]
URADDR2/
PINTA/ GP[14]
URDATA2/
MRXD2
URDATA3/
MRXD3
URDATA0/
MRXD0/
RMRXD0
V
SS
UXDATA3/
MTXD3
UXSOC/
MCOL
URDATA5/
MRXD5
UXDATA1/
MTXD1/
RMTXD1
DV
DD15
UXDATA4/
MTXD4
URCLAV/
MCRS/
RMCRSDV
UXADDR0/
PTRDY
UXDATA7/
MTXD7
UXCLK/ MTCLK/
RMREFCLK
UXADDR4/
MDCLK
RGRXD3
DV
DD18
DED1
DSDDQS0
DSDDQM0 DED2
DSDDQS0
DED6
DED7
DED8
DED9
DED10
DSDDQM1
DSDDQS1
DED15
DED14
V
SS
RSV25
RSV35
RSV34
V
SS
DV
DD15
V
SS
V
SS
DV
DD15
V
SS
V
SS
DSDWE
DSDRAS
DSDCAS
V
SS
DED3
RSV29
DV
DD33
RGTXD0
RGTXD1
RGREFCLK
RGTXCTL
DV
DD15MON
RGRXD1 RSV18
RSV13
UXCLAV/ GMTCLK
UXDATA5/
MTXD5
DSDDQ
GATE0
DED0
DV
DD15
DED12 DV
DD18
DED5
RGRXD0
DV
DD33
V
SS
V
SS
V
SS
DV
DD33MONVSS
RSV21 DED13 DED4 V
SS
AV
DLL1
V
SSVREFHSTL
RGMDCLK RSV24
DSDDQ
GATE1
RGRXCTL V
SS
DV
DD15
RGTXC
RGRXC DSDDQS1 DV
DD18
DV
DD18
RSV14
DV
DD18
URDATA7/
MRXD7
V
SS
CV
DD
RSV28 CV
DD
URADDR4/
PCBE0/
GP[2]
UXADDR2/
PCBE3
DV
DD33
UXENB/ MTXEN/
RMTXEN
V
SS
DV
DD33
V
SS
RGMDIO PLLV2 V
SS
DED11
DV
DD18
DV
DD18
URDATA4/
MRXD4
UXADDR3/
MDIO
RGTXD2
B
DV
DD15
V
SS
DV
DD18
DV
DD18
RSV07 DV
DD18
CLKIN2DV
DD33
V
SS
V
SS
V
SS
V
SS
V
SS
C
V
SS
URENB/ MRXDV
URSOC/ MRXER/
RMRXER
CV
DD
URDATA1/
MRXD1/
RMRXD1
URDATA6/
MRXD6
URCLK/ MRCLK
DV
DD15
V
SS
V
SS
14
DDR2
CLKOUT
V
REFSSTL
DSDCKE
DCE0
CV
DD
DDR2
CLKOUT
V
SS
V
SS
DV
DD18
CV
DD
15
DEA13
DBA0
DBA1
DBA2
V
SS
DEA12
CV
DD
DV
DD18
V
SS
V
SS
14 15
CV
DD
RSV04
V
SS
CV
DD
V
SS
CV
DD
RSV05
F
D
E
A
G
H
J
K
L
M
N
P
B
C
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
SM320C6455-EP
Figure 2-5. C6455 Pin Map (Bottom View) [Quadrant D]
Submit Documentation Feedback Device Overview 23
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•
TRST
IEEE Standard
1149.1
(JTAG)
Emulation
Reserved
Reset and Interrupts
Control/Status
TDI
TDO
TMS
TCK
NMI
RESET
RSV03 RSV04
Clock/PLL1
and
PLL Controller
CLKIN1
EMU0 EMU1
SYSCLK4/GP[1]
(A)
EMU14 EMU15 EMU16
EMU17
RSV02
EMU18
RSV07 RSV09
RSV05
RSV43 RSV44
RSV42
•
•
•
•
•
RESETSTAT
CLKIN2
POR
PCI_EN
Peripheral
Enable/Disable
Clock/PLL2
PLLV2
PLLV1
A. This pin functions as GP[1] by default. For more details, see the Device Configuration section of this document.
SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

2.6 Signal Groups Description

Figure 2-6. CPU and Peripheral Signals
Device Overview24 Submit Documentation Feedback
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A. This pin functions as GP[1] by default. For more details, see the Device Configuration section of this document. B. These McBSP1 peripheral pins are muxed with the GPIO peripheral pins and by default these signals function as GPIO peripheral pins. For
more details, see the Device Configuration section of this document.
C. These UTOPIA and PCI peripheral pins are muxed with the GPIO peripheral pins and by default these signals function as GPIO peripheral
pins. For more details, see the Device Configuration section of this document.
GPIO
General-Purpose Input/Output 0 (GPIO) Port
CLKX1/GP[3]
(B)
URADDR4/PCBE0/GP[2]
(C)
SYSCLK4/GP[1]
(A)
URADDR3/PREQ/GP[15]
(C)
URADDR2/PINTA/GP[14]
(C)
URADDR1/PRST/GP[13]
(C)
URADDR0/PGNT/GP[12]
(C)
FSX1/GP[11]
(B)
FSR1/GP[10]
(B)
DX1/GP[9]
(B)
DR1/GP[8]
(B)
GP[7] GP[6] GP[5] GP[4]
CLKR1/GP[0]
(B)
Timers (64-Bit)
TINPL1
Timer 1
Timer 0
TOUTL1
TINPL0
TOUTL0
RIOCLK
Clock
RIOTX[3:0]
RAPID IO
Transmit
Receive
RIOCLK
4
4
4
4
RIOTX[3:0]
RIORX[3:0] RIORX[3:0]
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
SM320C6455-EP
Figure 2-7. Timers/GPIO/RapidIO Peripheral Signals
Submit Documentation Feedback Device Overview 25
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ACE4
(A)
AECLKOUT
AED[63:0]
ACE3
(A)
ACE2
(A)
AEA[19:0]
AARDY
Data
Memory Map
Space Select
Address
Byte Enables
64
20
External
Memory I/F
Control
EMIFA (64-bit Data Bus)
AECLKIN
AHOLD AHOLDA ABUSREQ
Bus
Arbitration
ABE3 ABE2 ABE1 ABE0
ASWE/AAWE
DDR2CLKOUT
DED[31:0]
DCE0
DEA[13:0]
Data
Memory Map
Space Select
Address
Byte Enables
32
14
External
Memory I/F
Control
DDR2 Memoty Controller (32-bit Data Bus)
DSDCAS
DSDCKE
DDR2CLKOUT
DSDDQS[3:0]
DSDRAS DSDWE
DSDDQS[3:0]
ABE7 ABE6 ABE5
ABE4
ACE5
(A)
Bank Address
ABA[1:0]
AR/W AAOE/ASOE ASADS/ASRE
Bank Address
DBA[2:0]
DEODT[1:0]
DSDDQGATE[0]
DSDDQM3 DSDDQM2
DSDDQM1 DSDDQM0
A. The EMIFA ACE0 and ACE1 are not functionally supported on the C6455 device.
DSDDQGATE[1] DSDDQGATE[2] DSDDQGATE[3]
SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
Figure 2-8. EMIFA/DDR2 Memory Controller Peripheral Signals
Device Overview26 Submit Documentation Feedback
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McBSPs
(Multichannel Buffered Serial Ports)
(B)
CLKX0 FSX0 DX0
CLKR0 FSR0
DR0
Transmit
McBSP0
Receive
Clock
CLKX1/GP[3]
FSX1/GP[11]
DX1/GP[9]
CLKR1/GP[0]
FSR1/GP[10]
DR1/GP[8]
Transmit
McBSP1
Receive
Clock
HHWIL/PCLK
HCNTL0/PSTOP
HCNTL1/PDEVSEL
Data
Register Select
Half-Word
Select
Control
HPI
(A)
(Host-Port Interface)
32
HAS/PPAR
HR/W/PCBE2 HCS/PPERR
HDS1/PSERR HDS2/PCBE1 HRDY/PIRDY
HINT/PFRAME
(HPI16 ONL Y)
HD[15:0]/AD[15:0]
HD[31:16]/AD[31:16]
SCL
I2C
SDA
A. These HPI pins are muxed with the PCI peripheral. By default, these pins function as HPI. When the HPI is enabled, the number of HPI pins
used depends on the HPI configuration (HPI16 or HPI32). For more details on these muxed pins, see the Device Configuration section of this document.
B. These McBSP1 peripheral pins are muxed with the GPIO peripheral pins and by default these signals function as GPIO peripheral pins. For
more details, see the Device Configuration section of this document.
CLKS
(SHARED)
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SM320C6455-EP
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
Figure 2-9. HPI/McBSP/I2C Peripheral Signals
Submit Documentation Feedback Device Overview 27
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RGTXCTL, RGRXCTL
URSOC/MRXER/RMRXER,
URENB/MRXDV,
URCLAV/MCRS/RMCRSDV,
UXSOC/MCOL,
UXENB/MTXEN/RMTXEN
Ethernet MAC (EMAC) and MDIO
(B)
UXADDR3/MDIO
UXADDR4/MDCLK
MDIO
Clock
Clocks
Error Detect and Control
Input/Output
Receive
RGMDIO
RGMDCLK
RGTXD[3:0]
A. RGMII signals are mutually exclusive to all other EMAC signals. B. These EMAC pins are muxed with the UTOPIA peripheral. By default, these signals function as EMAC. For more details on these
muxed pins, see the Device Configuration section of this document.
RGTXC, RGRXC,
RGREFCLK
UXDATA[7:2]/MTXD[7:2],
UXDATA[1:0]/MTXD[1:0]/RMTXD[1:0]
Transmit
RGMII
(A)
GMII
RMII
MII
RGRXD[3:0]
URDATA[7:2]/MRXD[7:2],
URDATA[1:0]/MRXD[1:0]/RMRXD[1:0]
RGMII
(A)
GMII
RMII
MII
RGMII
(A)
GMII
RMII
MII
RGMII
(A)
GMII
RMII
MII
RGMII
(A)
GMII
RMII
MII
GMII
RMII
MII
RGMII
(A)
UXCLK/MTCLK/RMREFCLK,
URCLK/MRCLK,
UXCLAV/GMTCLK
Ethernet MAC
(EMAC)
SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
Figure 2-10. EMAC/MDIO [MII/RMII/GMII/RGMII] Peripheral Signals
Device Overview28 Submit Documentation Feedback
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URADDR2/PINTA/GP[14]
Control/Status
URADDR4/PCLK/GP[2]
URDATA0/MRXD0/RMRXD0
URDATA1/MRXD1/RMRXD1
URADDR3/PREQ/GP[15]
URADDR1/PRST/GP[13]
URADDR0/PGNT/GP[12]
Receive
URDATA7/MRXD7
URDATA4/MRXD4 URDATA3/MRXD3 URDATA2/MRXD2
URCLAV/MCRS/RMCRSDV
URENB/MRXDV
URDATA5/MRXD5
URDATA6/MRXD6
URSOC/MRXER/RMRXER
URCLK/MRCLK
Clock
Control/Status
Transmit
Clock
UXADDR2/PCBE3
UXADDR4/GMDCLK
UXDATA0/MTXD0/RMTXD0
UXDATA1/MTXD1/RMTXD1
UXADDR3/GMDIO
UXADDR1/PIDSEL UXADDR0/PTRDY
UXDATA7/MTXD7
UXDATA4/MTXD4 UXDATA3/MTXD3 UXDATA2/MTXD2
UXCLAV/GMTCLK
UXENB/MTXEN/RMTXEN
UXDATA5/MTXD5
UXDATA6/MTXD6
UXSOC/MCOL/TCLKRISE
UXCLK/MTCLK/REFCLK
UTOPIA (SLAVE)
(A)
A. These UTOPIA pins are muxed with the PCI or EMAC or GPIO peripherals. By default, these signals function as GPIO or EMAC peripheral
pins or have no function. For more details on these muxed pins, see the Device Configuration section of this data sheet.
HD[15:0]/AD[15:0]
HR/W/PCBE2 HDS2/PCBE1
UXADDR4/PCBE0/GP[2]
HHWIL/PCLK
HINT/PFRAME URADDR2/PINTA/GP[14]
Data/Address
Arbitration
32
Clock
Control
PCI Interface
(A)
HAS/PPAR URADDR1/PRST/GP[13]
HRDY/PIRDY HCNTL0/PSTOP
UXADDR0/PTRDY
UXADDR2/PCBE3
UXADDR1/PIDSEL
HCNTL1/PDEVSEL
HDS1/PSERR
Error
Command
Byte Enable
HCS/PPERR
URADDR0/PGNT/GP[12] URADDR3/PREQ/GP[15]
HD[31:16]/AD[31:16]
A. These PCI pins are muxed with the HPI or UTOPIA or GPIO peripherals. By default, these signals function as HPI or GPIO or EMAC. For more
details on these muxed pins, see the Device Configuration section of this document.
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
SM320C6455-EP
Figure 2-11. UTOPIA Peripheral Signals
Figure 2-12. PCI Peripheral Signals
Submit Documentation Feedback Device Overview 29
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

2.7 Terminal Functions

The terminal functions table (Table 2-3 ) identifies the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors, and a functional pin description. For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and pullup/pulldown resistors, see
Section 3 , Device Configuration.
Table 2-3. Terminal Functions
SIGNAL
NAME NO.
CLKIN1 N28 I IPD Clock Input for PLL1. CLKIN2 G3 I IPD Clock Input for PLL2. PLLV1 T29 A 1.8-V I/O supply voltage for PLL1 PLLV2 A5 A 1.8-V I/O supply voltage for PLL2
SYSCLK4/GP[1]
TMS AJ10 I IPU JTAG test-port mode select TDO AH8 O/Z IPU JTAG test-port data out TDI AH9 I IPU JTAG test-port data in TCK AJ9 I IPU JTAG test-port clock
TRST AH7 I IPD
(4)
EMU0
(4)
EMU1 EMU2 AG9 I/O/Z IPU Emulation pin 2 EMU3 AF10 I/O/Z IPU Emulation pin 3 EMU4 AF9 I/O/Z IPU Emulation pin 4 EMU5 AE12 I/O/Z IPU Emulation pin 5 EMU6 AG8 I/O/Z IPU Emulation pin 6 EMU7 AF12 I/O/Z IPU Emulation pin 7 EMU8 AF11 I/O/Z IPU Emulation pin 8 EMU9 AH13 I/O/Z IPU Emulation pin 9 EMU10 AD10 I/O/Z IPU Emulation pin 10 EMU11 AD12 I/O/Z IPU Emulation pin 11 EMU12 AE10 I/O/Z IPU Emulation pin 12 EMU13 AD8 I/O/Z IPU Emulation pin 13 EMU14 AF13 I/O/Z IPU Emulation pin 14 EMU15 AE9 I/O/Z IPU Emulation pin 15 EMU16 AH12 I/O/Z IPU Emulation pin 16 EMU17 AH10 I/O/Z IPU Emulation pin 17 EMU18 AE13 I/O/Z IPU Emulation pin 18
(3)
AJ13 I/O/Z IPD
AF7 I/O/Z IPU Emulation pin 0
AE11 I/O/Z IPU Emulation pin 1
(1)
TYPE
(2)
IPD/IPU
CLOCK/PLL CONFIGURATIONS
SYSCLK4 is the clock output at 1/8 of the device speed ( O/Z) or this pin can be programmed as the GP1 pin ( I/O/Z) [default].
JTAG EMULATION
JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE
1149.1 JTAG compatibility statement portion of this document.
DESCRIPTION
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (2) IPD = Internal pulldown, IPU = Internal pullup. For most systems, a 1-k Ω resistor can be used to oppose the IPU/IPD. For more detailed
information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.7 ,
Pullup/Pulldown Resistors. (3) These pins are multiplexed pins. For more details, see Section 3 , Device Configuration. (4) The C6455 DSP does not require external pulldown resistors on the EMU0 and EMU1 pins for normal or boundary-scan operation.
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