Texas Instruments SLVP089 User Manual

SLVP089 Synchronous Buck

Converter Evaluation Module

User’s Guide

1998 Mixed-Signal Linear Products

Printed in U.S.A.
07/98

SLVU001A

SLVP089 Synchronous Buck

Converter Evaluation Module

User’s Guide

Literature Number: SLVU001A

July 1998

Printed on Recycled Paper

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Copyright  1998, Texas Instruments Incorporated

About This Manual

Related Documentation From Texas Instruments

Preface

Read This First

This user’s guide is a reference manual for the SLVP089 Synchronous Buck
Converter Evaluation Module used to evaluate the performance of the TL5001
PWM Controller. This document provides information to assist managers and
hardware engineers in application development.

How to Use This Manual

This manual provides the information and instructions necessary to design,
construct, operate, and understand the SLVP089. Chapter 1 describes and
lists the hardware requirements; Chapter 2 describes design considerations
and procedures; and Appendix A contains the data sheet for the TL5001 PWM
Controller

Related Documentation From Texas Instruments

The following books describe the TL5001 and related support tools. T o obtain
a copy of any of these TI documents, call the T exas Instruments Literature Re­sponse Center at (800) 477–8924. When ordering, please identify the book by
its title and literature number.

TL5001 Pulse-Width-Modulation Control Circuits Data Sheet (Literature

number SL VS084C). It contains electrical specifications, available tem­perature options, general overview of the device, and application in­formation.

Designing with the TL5001C PWM Controller Application Report

(Literature number SLVA034).

Read This First

iii

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for compliance with the limits of computing devices pursuant to subpart J of
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Trademarks

TI is a trademark of Texas Instruments Incorporated.

iv

Running Title—Attribute Reference

Contents

1 Hardware 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Introduction 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Schematic 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Input/Output Connections 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Board Layout 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Bill of Materials 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.6 Test Results 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Design Procedure 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Introduction 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Operating Specifications 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Design Procedures 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.1 Duty Cycle Estimate 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.2 Output Filter 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.3 Power Switch 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.4 Synchronous Switch and Rectifier 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.5 Snubber Network 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.6 Controller Functions 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.7 Loop Compensation 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter Title—Attribute Reference

v

Running Title—Attribute Reference

Figures

1–1 Typical Synchronous Buck Converter 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–2 Schematic Diagram 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–3 Input/Output Connections 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–4 Board Layout 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–5 Efficiency Vs Load 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–6 Power Switch Turn-On and Delay from Q2 Off 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–7 Power Switch Turn-Off and Delay to Q2 On 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–8 Inductor and Output Ripple 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–1 Power Stage Bode Plot 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 Compensation Network 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 Bode Plot 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–4 Output Response 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tables

1–1 Bill of Materials 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–2 Line/Load Regulation, 3.3-V (Total Variation) 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–3 Load Regulation and Ripple, 3.3-V (9-V Input) 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–1 Operating Specifications 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi

Chapter 1

Hardware

The SLVP089 Synchronous Buck Converter Evaluation Module (SLVP089)
provides a method for evaluating the performance of the TL5001 pulse-width­modulation (PWM) controller. The device contains all of the circuitry necessary
to control a switch-mode power supply in a voltage-mode configuration. This
manual explains how to construct basic power conversion circuits including
the design of the control chip functions and the basic loop. This chapter in­cludes the following topics:

Topic Page

1.1 Introduction 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Schematic 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Input/Output Connections 1–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Board Layout 1–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Bill of Materials 1–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.6 Test Results 1–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter Title—Attribute Reference

1-1

Introduction

1.1 Introduction

Synchronous buck converters provide the smaller size and higher efficiency
required by electronic equipment, particularly portable battery-operated
equipment. The synchronous buck converter reduces power losses
associated with a standard buck converter by substituting a power MOSFET
for the commutating diode. This reduces the typical 0.5-V to 1-V diode drop
to 0.3 V or less and increases system efficiency by up to 10 percent.
Continuous-current mode is desirable and is used in this EVM for the low
peak-to-average current ratio. Figure 1–1 shows a typical synchronous buck
converter.

Figure 1–1.Typical Synchronous Buck Converter

V

I

R3

R1

R2

Controller
FB

R4

Q1

Q2

+
C1

CR1

L1

+
C2

V

O

Transistor Q1 is the power switch and Q2 is the synchronous switch. A diode
in parallel with Q2 allows inductor current flow during the dead time when both
transistors are turned off. If dead time is not present in this configuration, high
transient shoot-through currents will flow during the transition when one tran­sistor is turning on and the other is turning off, usually resulting in destruction
of the power stage switches.

The SL VP089 evaluation module will supply a nominal 3.3-V output over a load
range from 0 to 3 A using a dc input voltage of 5.5 V to 12 V . Full load efficiency
is typically 90 percent.

1-2

1.2 Schematic

Figure 1–2.Schematic Diagram

Hardware

C3

0.0022

GND
GND

V

I

V

I

µF

1.00 kΩ

J1

C9 0.22

R2

1.6 kΩ

R9

1
2

3
4

R8

121 kΩ

0.033

5.5 V to 12 V

C15

µ1.0 F

µF

6

C2

3

µF

4

7

R9

90.9 kΩ

R6

15 Ω

DTC

TL5001

COMP

FB

RT

V

U1

GND

CC

2

8

OUT

SCP

R10

1 kΩ

100 µF

R12 10 kΩ

R11 30 kΩ

1

5

+

+

C10

CR3

BAS16ZX

BAS16ZX

C1

µ1F

CR2

100 µF

2

4

+

1IN

2IN

C11

0.47 µF

C14

0.1 µF

U2
TPS2812

61

V

V

DD

CC

8

REG

7

1OUT

5

2OUT

GND

10 kΩ

3

IRF7201

NMOS

R13

C4

R4

2.32 kΩ

µ0.022 F

R5

10 kΩ

Q2

180 Ω

Q1
IRF7406
PMOS

L1

µH

27

C7

C12

100 µF

+

+

R7

CR1

30BQ015

R3

3.3 Ω

C6
1000 pF

100

C13
10 µFµF

J2

1
2

3
4

C5

Note: Frequency is set to 100 kHz by R9. See TL5001 data sheet for the curve of oscillator frequency versus timing resistance.

3.3 V

3.3 V
RTN
RTN

1-3

Schematic

Input/Output Connections

1.3 Input/Output Connections

Figure 1–3 shows the input/output connections to the SLVP089.

Figure 1–3.Input/Output Connections

–

+

C5 Q1

C11

C10

U2

J1

R12

1

TEXAS INSTRUMENTS

CR3

R11

CR2

+3.3V, 3 AMP

SYNC. RECT BUCK

TL5001

Power Supply

R5

R7

R13

C6

C14

R6

R10

C4

CR1

JMP1

R4

R2

Q2

C12

R3

C3

C2

C15

U1

R1

C8

SLVP089

R9

EVAL BOARD

R8

REV2

C9
C1

L1

C13

J2

1

–

LOAD

+

Notes: 1) Source power should be able to supply a minimum of 2.5 A at 5.5-V input and/or 1.1-A at 12-V input.

2) Load should be able to sink up to 3A with adequate power rating. Resistive loads with adequate ratings may be used.

1-4

1.4 Board Layout

Figure 1–4 shows the SLVP089 board layout.

Figure 1–4.Board Layout

Board Layout

C5 Q1

Q2

C11

C10

U2

J1

TEXAS INSTRUMENTS

R12

1

CR3

CR2R11

+3.3V, 3 AMP

SYNC. RECT BUCK

R5

R13

C14

TL5001

R10

R7

C6

R6

C4

CR1

JMP1

C12

R4

R2

C2

R3

C3

C15

U1

R1

R9
R8

C9

C1

L1

J2

1

C13

C8

SLVP089
EVAL BOARD
REV2

Hardware

1-5

Bill of Materials

1.5 Bill of Materials

Table 1–1 lists materials required for the SLVP089.

Table 1–1.Bill of Materials

Qty Reference Part Number Mfr Description

1 C1 ECS-T1CY105R Panasonic Capacitor, Tant, 1 mF, 20%, A Case
1 C1 1 Standard Capacitor, Cer, 0.47 mF, 10%, X7R, 1210
1 C13 C3225Y5V1C106Z TDK Capacitor, Cer, 10 mF, 10 V, Y5V,3225
1 C14 Standard Capacitor, Cer, 0.1 mF, 10%, X7R, 1206
1 C2 Standard Capacitor, Cer, 0.033 mF, 10%, X7R, 1206
1 C3 Standard Capacitor, Cer, 0.0022 mF, 10%, X7R, 0805
1 C4 Standard Capacitor, Cer, 0.022 mF, 10%, X7R, 0805
4 C5, C7,

C10, C12
1 C6 Standard Capacitor, Cer, 1000 pF, 5%, NPO, 0805
1 C9 Standard Capacitor, Cer, 0.22 mF, 10%, X7R, 1210
1 CR1 30BQ015 IR Rectifier, Schottky, 3 A, 15 V
2 CR2, CR3 BAS16ZXCT Zetex Diode, Signal, SOT-23
2 J1, J2 Standard Connector, 4-pin header, 25 Mil, 0.1′′ Sp. Gold
1 L1 NOVA 1 Nova Mag Inductor, 27 mH
1 Q1 IRF7406 IR Transistor, P-CH FET, 30 V, 0.04 W, 4.7 A, SO-8
1 Q2 IRF7201 IR Transistor, N-CH FET, 30 V, 0.03 W, 7 A, SO-8
1 R1 Standard Resistor, 1.00 k
2 R12, R13 Standard Resistor, 10 k
1 R2 Standard Resistor, 1.6 k
1 R3 Standard Resistor, 180
1 R4 Standard Resistor, 2.32 k
1 R5 Standard Resistor, 10 k
1 R6 Standard Resistor, 15
1 R7 Standard Resistor, 3.3
1 R8 Standard Resistor, 121 k
1 U1 TL5001CD TI IC, PWM, SO-8
1 U2 TPS2812D TI IC, dual MOSFET driver, SO-8
1

TPSD107M010R0100 AVX Capacitor, Tant, 100 mF, 10 V, D Case

, 20%, 3

W, 5%, 0805

W, 5%, 0805

W, 5%, 0805

W, 1%, 0805

W, 5%, 0805

W, 5%, 0805

W, 1%, 0805

SLVP089 PWB

A

W, 1%, 0805

W, 1%, 0805

1-6

Test Results

1.6 Test Results

T ables 1–2 and 1–3, along with Figures 1–5 through 1–8, show the test results
for the SLVP089.

Table 1–2.Line/Load Regulation, 3.3-V (Total Variation)

Line/Load 0.3 A 0.9 A 1.5 A 3.0 A 5.0 A Load Reg.

5.5 V Vo(V) 3.330 3.329 3.328 3.324 3.320 0.18%

6.0 V Vo(V) 3.330 3.329 3.328 3.324 3.320 0.18%

7.0 V Vo(V) 3.330 3.328 3.328 3.325 3.321 0.15%

8.0 V Vo(V) 3.330 3.329 3.328 3.325 3.321 0.15%

9.0 V Vo(V) 3.331 3.330 3.328 3.325 3.321 0.18%
10 V Vo(V) 3.331 3.330 3.328 3.325 3.321 0.18%
11 V Vo(V) 3.331 3.330 3.328 3.325 3.321 0.18%
12 V Vo(V) 3.331 3.330 3.329 3.325 3.321 0.18%

Line Reg.

Note: The calculation for load regulation only accounts for the worst case of load variation under the normal voltage condition

(i.e., 3.3 V at 3 A). All voltages were measured at the PCB header pins.

0.03% 0.06% 0.03% 0.03% 0.03%

Table 1–3.Load Regulation and Ripple, 3.3-V (9-V Input)

Load No Load 0.50 A 1.0 A 2.0 A 3.0 A 5.0 A Reg.

Vo(V) 3.331 3.330 3.329 3.327 3.325 3.321 0.18%
Vo Ripple (mV P–P) 16 16 18 24 24 32
Vo Spikes (mV P–P) 0 24 24 34 48 60

Figure 1–5.Efficiency Vs Load

EFFICIENCY

vs

LOAD CURRENT

100

Efficiency – %

95

VI = 9 V

90

85

80

VI = 5.5 V

VI = 12 V

75

70

0123

Load Current – A

45

Hardware

1-7

Test Results

Figure 1–6.Power Switch Turn-On and Delay from Q2 Off

VCC = 12 V
IO = 1.5 A

Q1 DRAIN
5 V/DIV

Q2 GATE
5 V/DIV

Figure 1–7.Power Switch Turn-Off and Delay to Q2 On

1

2

20 ns/Div

VCC = 12 V
IO = 1.5 A

Q2 Gate

5 V/Div

Q1 Drain

5 V/Div

1

2

20 ns/Div

1-8

Figure 1–8.Inductor and Output Ripple

Test Results

VCC = 12 V
IO = 1.5 A

Inductor
Ripple
1 A/Div

1–DC

Output
Ripple
20 mV/Div

2–AC

2 µs/Div

Hardware

1-9

1-10

Chapter 2

Design Procedure

There are many possible ways to proceed when designing power supplies.
This chapter shows the procedure used in the design of the SLVP089. The
chapter includes the following topics:

Topic Page

2.1 Introduction 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Operating Specifications 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Design Procedures 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter Title—Attribute Reference

2-1

Introduction

2.1 Introduction

The SL VP089 is a dc-dc synchronous buck converter module that provides a

3.3-V output at up to 3 A with an input voltage range of 5.5 V to 12 V . The PWM
controller is a TL5001 operating at a nominal frequency of 100 kHz. The
TL5001 is configured for a maximum duty cycle of 100 percent and has short­circuit protection built in. The synchronous power stage consists of a PMOS
switch and an NMOS synchronous rectifier.

2-2

2.2 Operating Specifications

Table 2–1 lists the operating specifications for the SLVP089.

Table 2–1.Operating Specifications

Specification Min Typ Max Units

Input Voltage Range 5.5 12 V
Output Voltage Range 3.10 3.30 3.50 V
Output Current Range 0 3 A
Operating Frequency 100 kHz
Output Ripple 50 mV

Operating Specifications

Efficiency (V

= 9 V, IO = 3 A) 85% 90%

i

Design Procedure

2-3

Design Procedures

2.3 Design Procedures

Detailed steps in the design of a buck-mode converter may be found in
Designing With the TL5001C PWM Controller (literature number SLVA034)
from TI. This section shows the basic steps involved in this design.

2.3.1 Duty Cycle Estimate

The duty cycle for a continuous-mode step-down converter is approximately:

D

+

Assuming the diode or synchronous switch forward voltage Vd = 0.12 V and
the power-switch-on voltage V
12 V is 0.64, 0.39, and 0.29, respectively.

2.3.2 Output Filter

A synchronous buck converter uses a single-stage LC filter. Choose an induc­tor to maintain continuous-mode operation down to 15 percent of the rated out­put load:

)

V

O

VI– V

V

d

SAT

= 0.15 V , the duty cycle for VI = 5.5, 9, and

SAT

D

IO+2

The inductor value is:

ǒ

VI– V

L

+

(12 – 0.15 – 3.3) 0.29

+

Assuming that all of the inductor ripple current flows through the capacitor and
the effective series resistance (ESR) is zero, the capacitance needed is:

C

+

8 f

Assuming the capacitance is very large, the ESR needed to limit the ripple to
50 mV is:

ESR

+

The output filter capacitor should be rated at least ten times the calculated ca­pacitance and 30–50 percent lower than the calculated ESR. This design used
two 100-mF capacitors in parallel with a multilayer ceramic to reduce ESR.

0.15 IO+2

– V

SAT

D

I

O

ǒD

D

V

O

+

D

I

O

D

I

O

V

O

0.05

0.9

O

Ǔ

Ǔ

D

0.9

+

8

+

0.056

0.15 3

ǒ

100 10

t

ǒ

10 10

W

0.9

+

0.9 A

–6

Ǔ

+

27.6mH

+

3

Ǔ

0.05

22.5mF

2.3.3 Power Switch

2-4

Based on the preliminary estimate, r
= 50 mW. The IRF7406 is a 30-V p-channel MOSFET with r

DS(ON)

should be less than 0.015 V  3A

DS(ON)

= 40 m

W.

Design Procedures

The power dissipation (conduction + switching losses) can be approximated
as:

P

D

Assuming total switching time, t
perature, and r

P

D

The thermal impedance for Q1 R
a one-inch-square pattern, thus:

T

J

2

+ǒI

+

r

DS(ON)

O

DS(ON)

+ƪ32

)ƪ0.5 5.5 3

TA)ǒR

(0.04 1.6) 0.64

q

JA

adjustment factor = 1.6, then:

2.3.4 Synchronous Switch and Rectifier

The synchronous switch calculations follow the same path as the power switch
except that the duty cycle is 1–D. Then r
3A = 40 mW. Selecting an IRF7201 with an r

+ƪ32

P

D

)ƪ0.5 5.5 3

+

T

J

(0.03 1.6) 0.36

TA)ǒR

q

JA

DǓ)ǒ0.5 VI

, = 100 ns, a 55°C maximum ambient tem-

r+f

ǒ0.1 10

= 90°C/W for FR-4 with 2-oz. copper and

q

JA

Ǔ

P

+55)

D

ǒ0.1 10

Ǔ

P

+

D

55)(90 0.238)+76°C

ƫ

–6

Ǔ ǒ

(90 0.45)

DS(ON)

DS(ON)

ƫ

–6

Ǔ ǒ

Ǔ

Ǔ

ƫ

ƫ

+

+

Ǔ

f

0.45 W

0.238 W

IO

t

r)f

+

3

96°C

3

100 10

should be less than 0.012 V

= 30 mW, then:

100 10



The catch rectifier serves as a backup device for the synchronous switch and
conducts during the time interval when both devices are off. The 30BQ015 is
a 3-A, 15-V rectifier in an SMC power surface-mount package. If the synchro­nous switch were not used, the power dissipation for the catch diode would be:

P

D

However, since the catch diode actually conducts only during the deadtime
and switching time, the power dissipation is:

P

D

2.3.5 Snubber Network

A snubber network is usually needed to suppress the ringing at the node where
the power switch drain, output inductor, and synchronous switch drain con­nect. This is usually a trial-and-error sequence of steps to optimize the net­work, but as a starting point, select a snubber capacitor with a value that is
4–10 times larger than the estimated capacitance of the synchronous switch
and catch rectifier. Then, measuring a ringing time constant of 3 ns, R is:

R

+

IO

+

IO

+3

3 10

+

0.7

C

V

D

VD

–9

ǒ

1 – D

Min

t

f

r)f

ǒ0.1 10

3 10

+

1000 10

Ǔ

+3

–6

Ǔ ǒ

–9

–12

0.7 0.71+1.491 W

3

100 10

+3W

Ǔ

+

2.1 mW

Design Procedure

2-5

Design Procedures

2.3.6 Controller Functions

The controller functions, oscillator frequency, soft-start, dead-time-control,
short-circuit protection, and sense-divider-network are discussed in this sec­tion.

The oscillator frequency is set by selecting the resistance value from the graph
in figure 6 of the TL5001 data sheet. For 100 kHz, a value of 90.9 kWis se­lected.

Dead-time control provides a minimum off-time for the power switch in each
cycle. Set this time by connecting a resistor between DTC and GND. For this
design, a maximum duty cycle of 100% is chosen. Then R8 is calculated as:

R8

+

+
+

Soft-start is added to reduce power-up transients. This is implemented by ad­ding a capacitor across the dead-time resistor. In this design, a soft-start time
of 25 ms is used:

C

+

The TL5001 has short circuit protection instead of a current sense circuit. If not
used, the SCP terminal must be connected to ground to allow the converter
to start up. If a timing capacitor is connected to SCP, it should have a time
constant that is greater than the soft-start time constant. This time constant is
chosen to be 75 ms:

C(mF)+12.46 t

2.3.7 Loop Compensation

Loop compensation is necessary to stabilize the converter over the full range
of load, line, and gain conditions. A buck-mode converter has a two-pole LC
output filter with a 40-dB-per-decade rolloff. The total closed-loop response
needed for stability is a 20-dB-per-decade rolloff with a minimum phase margin
of 30 degrees over the full bandwidth for all conditions. In addition, sufficient
bandwidth must be designed into the circuit to assure that the converter will
have good transient response. Both of these requirements are achieved by ad­ding compensation components around the error amplifier to modify the total
loop response.

121 k

W

SCP

3

+

+

W

0.21mF

(R9)1.25) 10

(90.9)1.25) 103

119.8 KWå

t

R

R

DT

+

0.025 s
121 k

ƪDǒV

12.46 0.075 s+0.93mF

O(100%)

[1(1.3 – 0.65))0.65]

– V

O(0%)

Ǔ

)

V

O(0%)

ƫ

2-6

The first step in design of the loop compensation network is the design of the
output sense divider. This sets the output voltage and the top resistor deter­mines the relative size of the rest of the compensation design. Since the
TL5001 input bias current is 0.5 mA (worst case), the divider current should be
at least 0.5 mA. Using a 1-kW resistor for the bottom of the divider gives a divid­er current of 1 mA. The top of the divider is calculated as:

ǒ

VO– 1

R

+

1 mA

Ǔ

+

(

3.3 –1

0.001

)

+

2.3 k

W

Design Procedures

Calculating the pulse-width-modulator gain as the change in output voltage
divided by the change in PWM input voltage gives:

A

PWM

+

D

V

V

COMP

O

9 – 0

+

1.3 – 0.65

+

13.85

å

22.8 db

D

The LC filter has a double pole at:

1

+

Ǹ

2pLC

2p21.6mH 168mF

(worst case values) and rolls off at 40-dB per decade after that until the ESR
zero is reached at:

1

2pRC

+

2p(0.025)

This information is enough to calculate the required compensation values.
Figure 2–1 shows the power stage gain and phase plots.

Figure 2–1.Power Stage Bode Plot

50

40

30

20

10

1

Ǹ

1

ǒ

210 10

FREQUENCY RESPONSE

–6

+

Ǔ

+

2.64 kHz

38 kHz

0

–45

–90

–135

–180

Gain – Solid

0

–10

–20

–30

10 10

2

3

10

Frequency

10

4

10

–225

–270

–315

–360

5

Phase – Dashed

This response must be corrected by addition of the following:

-

A pole at zero to give high dc gain

-

Two zeroes at approximately 2.6 kHz to cancel the LC poles

-

A pole at approximately 38 kHz to cancel the ESR zero

-

A final pole to roll off high-frequency gain

The compensation circuit shown in figure 2–2 can be used to implement the
above conditions.

Design Procedure

2-7

Design Procedures

Figure 2–2.Compensation Network

C3

R4

R3

V

I

The transfer function for this circuit is:

V

V

The desired output regulation is ±6 percent total deviation. The PWM control­ler tolerance is ±5 percent, and the divider resistors are 1 percent; therefore,
the control loop must be very precise. A minimum dc gain of 1000 (60 dB) gives
a 0.1 percent tolerance. The integrator (R4, C2) sets the gain of the compensa­tion network. The minimum modulator gain is 18 dB, therefore the compensa­tion network must have a gain of at least 42 dB. With a desired crossover fre­quency of 20 kHz and a desired slope of 20 dB per decade, choose an integra­tor frequency of 2 kHz. This gives a gain of 46 dB at 10 Hz, which is sufficient
for this application. If more gain is needed, increase the integrator frequency .
R4 is already known, so C2 is calculated as:.

[1)sR2(C2)C3)] [1)sC4(R3)R4)]

O

+

I

C4

sC2R4 [1)sC3R2][1)sC4R3]

R2

_

ref

+

V

C2

V

O

ǒ

Ǔǒ

Ǔ

f

Z2

Ǔ

ǒ

f

P2

Ǔ

f

P3

+

f

Z1

Ǔǒ

ǒ

f

P1

C2

+

Setting f
C4

+

Now R3 can be calculated using f
R3

+

The other LC filter compensator uses R2 and C2:
R2

+

The final rolloff pole (selected at 50 kHz) uses C3 and R2:
C3

+

1

ǒ

f

2

p

P1

= 3 kHz to compensate for one of the LC poles gives:

Z2

1

ǒ

2

p

f

Z2

ǒ

2

p

f

P3

1

ǒ

f

2

p

Z1

ǒ

2

p

f

P2

Ǔ

(R4)

Ǔ

(R4)

1

Ǔ

Ǔ

(C2)

1

Ǔ

+

2p(2 kHz)(2.32 kW)

+

2p(3 kHz)(2.32 kW)

+

(C4)

(R2)

2p(40 kHz)(0.022mF)

+

2p(3 kHz)(0.033mF)

+

2p(50 kHz)(1.6 kW)

1

1

P3

1

1

1

+

0.034mF

+

0.023mFå0.022mF

(40 kHz), the ESR compensator:

+

+

1.6 k

+

å

181Wå

W

0.002mF

0.033mF

180

å

0.0022mF

W

2-8

Figure 2–3.Bode Plot

Design Procedures

Figure 2–3 shows the bode plot for the compensation network.

45

90

40

35

30

25

20

Gain – dB (Solid)

15

10

5
0

10 10

Note from the output response shown in Figure 2–4 that the minimum phase
margin is 40 degrees and the bandwidth is 18 kHz under nominal operating
conditions.

Figure 2–4.Output Response

70

2

Frequency – Hz

10

3

OUTPUT RESPONSE

10

70

50

30

10

–10

–30

Phase – Degrees (Dashed)

–50

–70

4

10

–90

5

–180

60

50

40

30

20

Gain – dB (Solid)

10

0

–10
–20

10 10

2

Frequency – Hz

10

–225

–270

Phase – Degrees (Dashed)

–315

–360

3

10

4

10

5

Design Procedure

2-9

2-10