Texas Instruments SLAU081 User Manual

 

User’s Guide

January 2002 AAP Data Acquisition (Dallas)

SLAU081

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty . Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty . Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. T o minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third–party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party , or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Mailing Address:

Texas Instruments Post Office Box 655303 Dallas, Texas 75265

Copyright  2002, Texas Instruments Incorporated

EVM IMPORTANT NOTICE

Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING

DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety measures typically found in the end product incorporating the goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may not meet the technical requirements of the directive.

Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide, the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.

The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products received may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge.

EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.

TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.

TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein.

Please read the EVM User’s Guide and, specifically, the EVM W arnings and Restrictions notice in the EVM User’s Guide prior to handling the product. This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact the TI application engineer.

Persons handling the product must have electronics training and observe good laboratory practice standards.

No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or combination in which such TI products or services might be or are used.

Mailing Address:

Texas Instruments Post Office Box 655303 Dallas, Texas 75265

Copyright  2002, Texas Instruments Incorporated

EVM WARNINGS AND RESTRICTIONS

It is important to operate this EVM within the input voltage range of ±12 V and the output voltage range of ±12 V.

Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power.

Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.

During normal operation, some circuit components may have case temperatures greater than 60°C. The EVM is designed to operate properly with certain components above 60°C as long as the input and output ranges are maintained. These components include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified using the EVM schematic located in the EVM User’s Guide. When placing measurement probes near these devices during operation, please be aware that these devices may be very warm to the touch.

Mailing Address:

Texas Instruments Post Office Box 655303 Dallas, Texas 75265

Copyright  2002, Texas Instruments Incorporated

Running Title—Attribute Reference

Figures

2–1 SAM Configuration 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tables

2–1 Default Switch Settings 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 Default Jumper Settings 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 Jumper/Function Reference 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi

Chapter 1

Introduction

This chapter contains an overview of the features and functions of the EVM.

Topic Page

1.1 EVM Modes 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Analog Input Conditioning 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Analog Output Conditioning 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Prototype Area 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1

EVM Modes

This user’s guide has been written to help you get the most from your evaluation module (EVM). The TLC4541 EVM is a member of the multipurpose (MP) family of serial EVMs. It provides a platform to demonstrate the performance and functionality of the TLC4541 ADC and the TLV5636 DAC.

TI’s websites are regularly updated. They present the latest software additions, development information, troubleshooting help, general background, as well as all applicable data sheets.

For specific questions related to this EVM or device send an email to the Analog Applications Team at dataconvapps@list.ti.com and reference the orderable tool description – TLC4541 EVM.

This user’s guide is divided into the following chapters:

- Chapter 1 offers an overview of the EVM and introduces the general

features and functions of the system.

- Chapter 2 describes the operation of the EVM from a user’s view . It details

options that can be modified, connectors used, and pinout details.

- Appendix A details the bill of materials (BOM) and the schematic, along

with explanations of certain EVM features.

1.1 EVM Modes

This EVM has been designed, tested, and shipped in a condition that enables the user to begin evaluation with minimal effort.

There are basically two operating modes for the EVM. These modes are mutually exclusive. They are:

- Stand-Alone Mode (SAM)

Stand-alone mode enables the user to check the system without the support of a signal generator, pattern generator , or DSP. In this mode, the digital output from the ADC is fed into the companion DAC and reconstructed.

User mode is deselected if SAM is selected. The DSP will be unable to communicate with either the ADC or the DAC.

- User Mode

The EVM typically operates via a DSP or a microprocessor. In this mode the user is responsible for generating all the control signals. If user mode is selected, SAM is deselected.

1-2

1.1.1 Stand-Alone Mode

A unique feature of this EVM is the facility it offers the user to closely couple the ADC and DAC with a minimum of user intervention. This feature allows the serial bit stream from the digitized analog output to be fed directly to the DAC. Therefore, the signal that is fed into the ADC can be reconstructed via the DAC. No DSP need be present.

SAM is selected by:

- Switching SW1-1 to the on position, LED is on.

1.1.2 User Mode

The user can connect the ADC to a DSP or to a microprocessor in two ways:

- Via IDC ribbon cable

- Via daughterboard connectors J16 and J17

User mode is selected by:

- Switching SW1-1 to the of f position, LED is off.

Analog Input Conditioning

For example, TI’s range of DSP starter kits (DSK modules) provides a simple low-cost solution, offering a range of DSK modules for most needs. The EVM also supports the TMS320C6000 daughtercard specification (SPRA711), in addition to providing support for the Motorola specification for data transfer (SPI).

1.2 Analog Input Conditioning

There are a number of methods to connect analog input signals to the EVM. Chapter 2 discusses these alternatives.

1.3 Analog Output Conditioning

There are a number of methods to connect analog output signals to the EVM. Chapter 2 discusses these alternatives.

1.4 Prototype Area

An area of the PWB has been set aside if none of the signal conditioning options provided are suitable.

The prototype area has the following features:

- A matrix of plated-through holes (PTH)

- SMT pads in a standard 14-pin JEDEC footprint

- Convenient points to pick up all power options

Introduction

1-3

Chapter 2

Getting Started

This chapter describes how the user can modify the various options of this EVM.

Topic Page

2.1 Shipping (Default Configuration) 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Jumpers 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Switches 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Connectors 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 ADC and DAC Direct Access 2-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Host Communication 2-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Getting Started

2-1

Shipping (Default Configuration)

It is very important that users feel comfortable with the EVM from the beginning. To achieve this, each unit is manufactured and shipped in a predetermined condition. This allows the user to begin evaluation of the system immediately and to have confidence that the EVM is working.

To confirm that the EVM is working properly, follow the steps below:

1) Apply power to the system. The green LED will illuminate.

2) Ensure stand-alone mode (SAM) LED is on.

3) Check TP7 via oscilloscope. This will be a sine wave.

4) Press the reset button SW3.

5) Press the start button SW2.

6) Check TP20 with an oscilloscope. If the system is working properly, the signal at TP20 will also be a sine wave.

The system works as illustrated below. Any analog input supplied to the ADC will be digitized and reconstructed by the DAC.

Figure 2–1.SAM Configuration

TP7

ADC

DAC

TP20

The user may probe the data and control signals to observe the signals that allow stand-alone mode to function.

2.1 Shipping (Default Configuration)

The EVM is tested and shipped with jumpers and switches in a predetermined arrangement. This arrangement enables users to verify at once that the EVM is working. The tables below list switch and jumper settings that the EVM should be set to upon receipt.

Data

Control

Electronics

DSP / Micro

Interface

2-2

Shipping (Default Configuration)

Th

clock. This has been designed to be as flexible as ossible to

Table 2–1.Default Switch Settings

Switch Settings

Default

Configuration

SW1-1 On Stand-alone mode is selected, LED is on SW1-2 Off Reserved SW1-3 Off Reserved SW1-4 Off Reserved

Description

Table 2–2.Default Jumper Settings

Jumper Settings

Default Configuration Description

Pins 1–2 Pins 2–3 W1 Inserted Not inserted Input for channel 0 is via BNC connector J1. W2 Not inserted Inserted Sine wave test signal is selected for channel 0. W3 Not inserted Inserted Sine wave test signal is output for channel 0. W4 Not inserted Inserted Onboard conditioned input for channel 0 is selected. W5 Not populated Not populated W6 Not populated Not populated W7 Not populated Not populated W8 Not populated Not populated W9 Not inserted Disables onboard sine and triangle wave generator W10 Inserted Not inserted SCLK routed to ADC W11 Not inserted Inserted Signal conditioning output selected for channel 0 W12 Inserted Not inserted FS routed to ADC W13 Not Inserted 5-V analog W14 Inserted EVM reference or DAC’s on-chip reference selected. W15 Not populated Not populated W16 Inserted Not inserted Selects internal or external reference W17 Inserted Not inserted Determines EVM reference voltage W18 Not inserted Inserted FS routed to DAC W19 Inserted Not inserted Selects source of signal conditioning output from DAC W20 Not inserted

W21 Inserted Not inserted W22 Inserted Not inserted W23 Inserted Not inserted W24 Not inserted W25 Not populated Not populated

ese jumpers determine various options for supplying system clock. This has been designed to be as flexible as possible to accommodate many potential options.

p

pp

The hardware that can be reconfigured falls into one of the following sections:

- Jumpers

- Switches

- Connectors

Getting Started

2-3

Jumpers

2.2 Jumpers

The table below lists the functions that users can reconfigure along with the shipping condition.

Table 2–3.Jumper/Function Reference

Function Reference Designator Subsection

Channel 0 Analog input W1, W1 1, W4, W2, W3 3.2.3 Analog output W14, W19, W18 3.2.4 Disable onboard signal generator W9 3.2.7 Voltage reference W16, W17 3.2.8

3.3-V/5-V analog supply select W13 3.2.9 Clock/timer routing W20, W21, W22, W23, W24 3.2.10

2.2.1 Analog I/O Signal Conditioning

The TLC4541 supports various signal conditioning configurations. The user has the following options:

- Bypass signal conditioning

- Use the onboard signal conditioning. This consists of an operational

amplifier for each input channel configured with a gain of 1.

- Use the prototype area for signal conditioning.

- Use the expansion connector via a TI universal operational amplifier

evaluation module (such as SLOP224/SLOP249).

2.2.2 Channel 0 Analog Input

This is the primary analog input and can always be connected externally.

Analog Input Configuration Channel 0

Reference

Designator

W1 W1 allows the user to select between an analog input via BNC – J1 or IDC – J4 pin 1.

W11 W1 1 allows selection of either the conditioned or nonconditioned analog input signal.

W4 W4 allows the user to select either the prototype area output or the output from W1 1. W2 W2 enables the user to select either the output from the expansion connector or the output

from the onboard signal generator.

W3 W3 completes the selection choices for channel 0 by determining if the output from W2 or W4

is chosen to be presented to the ADC.

Functional Description

2-4

2.2.3 Channel 0 Analog Output

With a one-channel DAC installed, this signal is the primary analog output (output A).

With a two-channel DAC installed, the pinout of these devices effectively resolves this channel to be the secondary analog output (output B).

Analog Input Configuration Channel 0

Reference

Designator

W19 This jumper selects the source for the analog output on channel 0.

When a jumper is installed between pins 1 and 2, the output from the expansion connector’s B-channel is routed out.

When the jumper is installed between pins 2 and 3, the output from the onboard signal conditioning is directed through channel 0.

Functional Description

2.2.4 Signal Generator

Signal Generator

Reference

Designator

W9 W9 controls the generation of both onboard test signals. A jumper installed between pins 1 and 2

disables the waveform generator.

Functional Description

Jumpers

2.2.5 Voltage Reference

V oltage Reference

Reference

Designator

W16 W16 selects either the onboard reference or an external reference supplied by the user. W17 W17 allows the user to vary the reference voltage. W14 There are a number of possible DACs that a user can install on this EVM. Some have an internal

reference that the user can select via software, and some do not have an internal reference. For the DACs that support an internal reference, it is important to have the facility to remove the external reference supplied by the EVM (or user) to avoid conflicts between the DAC’s internal reference and the external reference.

Functional Description

2.2.6 ADC Supply Voltage

ADC Supply Voltage

Reference

Designator

W13 This jumper controls the analog supply voltage.

When the jumper is installed, the supply voltage to the ADC is 3.3 V. When the jumper is not installed, the supply voltage to the ADC is 5 V.

Functional Description

Getting Started

2-5

Switches

2.2.7 Clock/Timer Routing

A variety of options are available to the user. Be careful about altering these.

Clock/Timer Routing

Reference

Designator

W21 This jumper defines the clock that the ADC and DAC use for all their timing. The user can select

either the output from W23 or the output from W22 to be the base clock for the system.

W23 This jumper allows the user to select either an external clock, or the onboard 20-MHz oscillator for

conversion. In addition, this signal is fed to W20. W20 W20 provides a route for the EVM to generate CLKS for a DSP if so desired. W22 This jumper enables the user to select either the transmit clock from a DSP, or the output

from W24. W24 W24 connects or isolates the timer output from a DSP.

Functional Description

2.3 Switches

There are three switches present on the EVM:

- One 8-pin DIL switch which houses four individual switches; these are

denoted SW1-1, SW1-2, SW1-3, and SW1-4.

- Two momentary push-button switches

Features and functions of each switch:

Reference

Designator

SW1-1 Selects either stand-alone mode (SAM) or user mode SAM SW1-2 Reserved

SW1-3 Reserved SW1-4 Reserved

2.3.1 Stand-Alone-Mode, SW1-1

SW1-1 chooses either stand-alone mode or user mode. If the switch is set to the off position, SAM is selected and the EVM ignores all signals generated by a DSP. In addition, the EVM will not output any signals to a DSP or microprocessor.

In this mode, SW2 and SW3 are used to reset the EVM’s logic and initiate automatic conversions from the ADC, in addition to automatically routing the serial bit stream from the ADC to the DAC for reconstruction.

Function

Default

Condition

2-6

Reference

Designator

SW2 Initiates ADC and DAC conversions in SAM SW3 Forces the EVM’s control logic into a known state

Function

2.4 Connectors

g

lifi

evaluation board, SIL

Connectors

If SW1-1 is set to the on position, user mode is selected. In this case the user has absolute control of the data and control signals for the ADC and DAC. With SW1-1 in the on position, the logic that generates the control for SAM is disabled and plays no active part in the process.

In addition to jumpers and switches, the user also has access to various connectors. This section details the pinout of each connector.

Reference

Designator

J1 Analog input option for channel 0, miniature BNC

Description

Cells in grey are not supported (tracked) directly by this EVM.

Reference

Designator

J3 Analog input option

Description

for universal

p

operational-amp evaluation board, SIL PTH not installed.

Number

1 Noninverting input signal to dual operational amplifier, (2)

p

er

2 Noninverting input signal to dual operational amplifier, (2) 3 Inverting input signal to dual operational amplifier, (2) 4 Inverting input signal to dual operational amplifier, (2) 5 Nonfiltered output from dual operational amplifier, (2) 6 Filtered output from dual operational amplifier, (2) 7 +V supply 8 Operational amplifier (2) shutdown signal

9 Reference voltage 10 Analog ground 11 Operational amplifier (1) shutdown signal 12 –V supply 13 Nonfiltered output from dual operational amplifier, (1) 14 Filtered output from dual operational amplifier, (1) 15 Noninverting input signal to dual operational amplifier, (1) 16 Noninverting input signal to dual operational amplifier, (1) 17 Inverting input signal to dual operational amplifier, (1) 18 Inverting input signal to dual operational amplifier, (1)

Function

Getting Started

2-7

Connectors

g,

Reference

Designator

J4 Analog input option, 26-pin

DIL header

Description

Number

1 Channel 0 input 2 AGND 3 Channel 1 input 4 AGND 5 Not connected 6 AGND 7 Not connected 8 AGND

9 Not connected 10 AGND 11 Not connected 12 AGND 13 Not connected 14 AGND 15 Not connected 16 AGND 17 Not connected 18 AGND 19 Not connected 20 AGND 21 Not connected 22 AGND 23 Not connected 24 AGND 25 External reference voltage 26 AGND

Function

Reference

Designator

J5 Analog output for one-channel DAC

2-8

Description

Connectors

g,

Reference

Designator

J7 EVM power

J8 Analog output option,

26-pin DIL header

Description

Number

1 5 V 2 –12 V 3 0 V 4 12 V 1 No output 2 AGND 3 Analog output for one-channel DAC 4 AGND 5 Not connected 6 AGND 7 Not connected 8 AGND

9 Not connected 10 AGND 11 Not connected 12 AGND 13 Not connected 14 AGND 15 Not connected 16 AGND 17 Not connected 18 AGND 19 Not connected 20 AGND 21 Not connected 22 AGND 23 Not connected 24 AGND 25 Not connected 26 AGND

Function

Getting Started

2-9

Connectors

g

lifi

evaluation board, SIL

Reference

Designator

J9 Analog input option

Description

for universal

p

operational-amp evaluation board, SIL PTH not installed.

Number

1 Noninverting input signal to dual operational amplifier, (2)

p

er

2 Noninverting input signal to dual operational amplifier, (2) 3 Inverting input signal to dual operational amplifier, (2) 4 Inverting input signal to dual operational amplifier, (2) 5 Nonfiltered output from dual operational amplifier, (2) 6 Filtered output from dual operational amplifier, (2) 7 +V supply 8 Operational amplifier (2) shutdown signal

9 Reference voltage 10 Analog ground 11 Operational amplifier (1) shutdown signal 12 –V supply 13 Nonfiltered output from dual operational amplifier, (1) 14 Filtered output from dual operational amplifier, (1) 15 Noninverting input signal to dual operational amplifier, (1) 16 Noninverting input signal to dual operational amplifier, (1) 17 Inverting input signal to dual operational amplifier, (1) 18 Inverting input signal to dual operational amplifier, (1)

Function

2-10

2.5 ADC and DAC Direct Access

gg

J10 and J1 1 offer users the facility to directly inspect the digital signals coming from and going to the ADC and DAC.

ADC and DAC Direct Access

Reference

Designator

J10 Allows the user direct access to all digital signals for the ADC

J11 Allows the user direct access to all digital signals for the DAC

Description

Number

1 Digital ground 2 SDO 3 Digital ground 4 SCLK 5 Digital ground 6 CS or CS/FS 7 Digital ground 8 FS 1 Digital ground 2 SDI 3 Digital ground 4 SCLK 5 Digital ground 6 CS 7 Digital ground 8 FS

Signal

2.6 Host Communication

There are two ways to connect a host system (DSP/microprocessor):

- Texas Instruments’ new DSKs provide two dedicated 80-pin connectors.

The EVM can be plugged directly onto these DSKs. This connector standard is referred to as the common connector.

- Legacy DSKs not equipped with the 80-pin common connectors will

communicate via the daisy-chained legacy header.

The following sections discuss each connection method.

Getting Started

2-11

Host Communication

y

2.6.1 Common Connector

Reference

Designator

J16 80-pin memory interface connector for ’C5000 and ’C6000 DSK

EVMs. Pins unused by this EVM are omitted for clarity .

Description

Number

1 5 V 2 5 V

11 PCI ground 12 PCI ground 21 5 V 22 5 V 29 PCI ground 30 PCI ground 31 PCI ground 32 PCI ground 41 3.3 V 42 3.3 V 51 PCI ground 52 PCI ground 61 PCI ground 62 PCI ground 71 PCI ground 72 PCI ground 79 PCI ground 80 PCI ground

Function

2-12

Host Communication

Reference

Designator

J17 80-pin peripheral and control connector for ’C5000 and ’C6000

DSK EVMs. Pins unused by this EVM are omitted for clarity.

Description

Number

1 12 V 2 –12 V 3 PCI ground 4 PCI ground 5 5 V 6 5 V 7 PCI ground 8 PCI ground

9 5 V 10 5 V 35 FSX 33 CLKX 36 DX 25 PCI ground 26 PCI ground 39 CLKR 41 FSR 42 DR 31 PCI ground 32 PCI ground 37 PCI ground 38 PCI ground 43 PCI ground 44 PCI ground 45 TOUT 49 XF 51 PCI ground 52 PCI ground 61 PCI ground 62 PCI ground 76 PCI ground 77 PCI ground 79 PCI ground 80 PCI ground

Function

Getting Started

2-13

Host Communication

2.6.2 Legacy Connector

J12, J13, and J15 are three 2x20 headers daisy-chained together and are collectively referred to as the legacy connector. The principle behind this arrangement is to eliminate the confused and untidy custom cabling that is typically present when connecting a legacy DSP to an EVM. This daisy-chained connector method is flexible, robust, and makes it possible to use a standard flat signal-cable assembly, improving reliability of communications between host and EVM.

Two shorting bars are inserted in J12 and J15; these bars permit alternate pins on J13 to be DGND. If the user has complete discretion over signal routing at the host end, it is recommended that the host-end connector should reflect the same pinout as J13.

However, if the host-end connector does not (or cannot) mirror the pinout for J13, then some degree of signal-twisting is necessary. This is accomplished on the EVM by removing the shorting bars on J12 and J15 and typically wire-wrapping directly onto the appropriate header.

For example, if the host connector on the DSP has the pin assignment described in the following table, then a 1:1 mapping is possible and the user should plug a flat 20-way ribbon cable into J13.

Host Connector EVM Connector – J13

Pin No. Signal Pin No. Signal Pin No. Signal Pin No. Signal

1 XF 2 DGND 1 XF 2 DGND 3 CLKX 4 DGND 3 CLKX 4 DGND 5 CLKR 6 DGND 5 CLKR 6 DGND 7 DX 8 DGND 7 DX 8 DGND

9 DR 10 DGND 9 DR 10 DGND 11 FSX 12 DGND 11 FSX 12 DGND 13 FSR 14 DGND 13 FSR 14 DGND 15 Resvd 16 DGND 15 Resvd 16 DGND 17 CLKS 18 DGND 17 CLKS 18 DGND 19 TOUT 20 DGND 19 TOUT 20 DGND

However, if the host connector has a different signal pinout, the user should remove the shorting bars from J12 and J15. A flat 20-way IDC ribbon cable can still be used; in this case, the user should plug the connector into J12 of the EVM. Since the cable is now plugged into J12, and all the signals on both sides of the J12 pins are routed to adjacent connector pins (J13 and J15), the user can typically wire-wrap the associated host signal to the relevant EVM signal.

2-14

The example shown below demonstrates the steps that must be taken to reassign the connector and wire-wrap the correct signals.

Host Communication

Consider a host cable signal assignment as shown below:

Host Connector

Pin No. Signal Pin No. Signal

1 NA 2 DGND 3 NA 4 DGND 5 CLKX 6 CLKR 7 TOUT 8 DGND

9 DX 10 DR 11 FSX 12 FSR 13 NA 14 DGND 15 XF 16 DGND 17 NA 18 NA 19 NA 20 CLKS

The host connector mates with J12. Signals on either side of J12 are available on J13 and J15.

J13 Host Connector Plugged into J12 J15

Pin No. Pin No. Signal Pin No. Signal Pin No.

2 1 N/A 2 DGND 1 4 3 N/A 4 DGND 3 6 5 CLKX 6 CLKR 5

8 7 TOUT 8 DGND 7 10 9 DX 10 DR 9 12 11 FSX 12 FSR 11 14 13 N/A 14 DGND 13 16 15 XF 16 DGND 15 18 17 N/A 18 N/A 17 20 19 N/A 20 CLKS 19

Getting Started

2-15

Host Communication

For clarity, the above table can be redrawn with J12 removed.

J13 J15

Pin No. Signal Pin No. Signal

2 NA 1 DGND 4 NA 3 DGND 6 CLKX 5 CLKR

8 TOUT 7 DGND 10 DX 9 DR 12 FSX 11 FSR 14 NA 13 DGND 16 XF 15 DGND 18 NA 17 NA 20 NA 19 CLKS

The table below shows the signal names and pin assignments that the composite connector shown above must be mapped onto.

J13

Pin No. Signal

1 XF

3 CLKX

5 CLKR

7 DX

9 DR 11 FSX 13 FSR 15 Resvd 17 CLKS 19 TOUT

2-16

Host Communication

All of the signals required to interface the EVM to the host are now available on either J13 or J15. This is simply a matter of wire-wrapping in the following way:

J13

Pin No. Signal Pin No. Signal

2 NA 4 NA 6 CLKX 3 CLKX

8 TOUT 19 TOUT 10 DX 7 DX 12 FSX 11 FSX 14 NA 16 XF 1 XF 18 NA 20 NA

J15

Pin No. Signal Pin No. Signal

1 DGND YES 2 DGND

3 DGND YES 4 DGND

Wire Wrap

J13

Jumper

Between

J15

Pin No. Signal

5 CLKR YES 5 CLKR 6 DGND

7 DGND YES 8 DGND

9 DR YES 9 DR 10 DGND 11 FSR YES 13 FSR 12 DGND

13 DGND YES 14 DGND 15 DGND YES 16 DGND 17 NA 18 DGND 19 CLKS YES 17 CLKS 20 DGND

Getting Started

2-17

Host Communication

All of these connectors are shown below:

Reference

Designator

J12 20-pin connector

Description

Number

1 J13 pin 2 2 J15 pin 1 3 J13 pin 4 4 J15 pin 3 5 J13 pin 6 6 J15 pin 5 7 J13 pin 8 8 J15 pin 7

9 J13 pin 10 10 J15 pin 9 11 J13 pin 12 12 J15 pin 1 1 13 J13 pin 14 14 J15 pin 13 15 J13 pin 16 16 J15 pin 15

Signal Name/Function

17 J13 pin 18 18 J15 pin 17 19 J13 pin 20 20 J15 pin 19

2-18

Host Communication

Reference

Designator

J13 20-pin signal connector

Description

Number

1 ADC select signal 2 J12 pin 1 3 CLKX/transmit clock 4 J12 pin 3 5 CLKR receive clock 6 J12 pin 5 7 DX/data transmit 8 J12 pin 7

9 DR/data receive 10 J12 pin 9 11 FSX/frame sync transmit 12 J12 pin 1 1 13 FSR/frame sync receive 14 J12 pin 13 15 Reserved 16 J12 pin 15

Signal Name/Function

17 CLKS/sync clock 18 J12 pin 17 19 TOUT/host timer output 20 J12 pin 19

Getting Started

2-19

Host Communication

Reference

Designator

J15 20-Pin connector

Description

Number

1 J12 pin 2 2 DGND 3 J12 pin 4 4 DGND 5 J12 pin 6 6 DGND 7 J12 pin 8 8 DGND

9 J12 pin 10 10 DGND 11 J12 pin 12 12 DGND 13 J12 pin 14 14 DGND 15 J12 pin 16 16 DGND

Signal Name/Function

17 J12 pin 18 18 DGND 19 J12 pin 20 20 DGND

2-20

Appendix A

Bill of Materials, Board Layout, and

Schematics

This appendix contains the bill of materials, board layouts, and the EVM schematics.

Bill of Materials, Board Layout, and Schematics

A-1

321

5(9 (&11XPEHU $SSURYHG

4

5HYLVLRQ+LVWRU\

D

C

B

J1

J2

J4

12 34 56 78

910 1112 1314 1516 1718 1920 2122 2324 2526

Input Config

BNC_0

BNC_1

IDC_0 IDC_1

Channel_0 Channel_1

J8

12 34 56 78

910 1112 1314 1516 1718 1920 2122 2324 2526

J6

J5

SENSE

VREFP

ADC

ADC_Data_out

SENSE VREFP

LCL_CS_ADC*

LCL_CLKX

In_0 In_1

DAC

LCL_CLKX

LCL_CS_DAC*

DAC_Data_in

DAC_Write*

VREFP

AOUT

AOUT_A

Interface

ADC_Data_out

FS

FS LCL_CS_ADC* LCL_CLKX

LCL_CS_DAC* DAC_Data_in DAC_Write*

DSP_CLKS

DSP_TOUT

DSP_FSX

DSP_FSR

DSP_DX

DSP_DR

DSP_XF

DSP_CLKX

DSP_CLKR

User connectors

DSP_CLKS DSP_TOUT

DSP_FSX DSP_FSR

DSP_DX DSP_DR

DSP_XF

DSP_CLKX DSP_CLKR

PCI_+5v PCI_+12V PCI_GND PCI_-12V

D

C

B

J7

+Supply

4

Ground

3

-Supply

A

2

+5V_IN1

1 2 34

Power & Reference

+Supply

Ground

-Supply

+5V_IN

VREFPEXT_VREFP

SENSE

PCI_+5v PCI_+12V PCI_GND PCI_-12V

VREFP

SENSE



12500 TI Boulevard. Dallas, Texas 75243

TITLE:

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Block Diagram DATE: 28-Nov-2001

Block Diagram

DOCUMENT CONTR O L #:

6430333

A4

SHEET: OF:

114

A

REV:

321

5(9 (&11XPEHU $SSURYHG

2 040500

4

5HYLVLRQ+LVWRU\

D

FL2

GND

1

2

GND

FL3

1

2

GND

FL4

1

2

GND

FB13

SM_FB_27--044447

SENSE

+Supply

PCI_+12V

Ground

PCI_GND

C

-Supply

PCI_-12V

+5V_IN

PCI_+5v

B

R70 0

R68 0

R69 0

R58 0

3

Power

+VIN

REF_IN

-VIN

+DVdd +DVdd

Reference

+VIN

SENSE

+Vs

VREFP

-Vs

+

VREFP

+VS

C11

+

10uF

C10 10uF

C57

+

10uF

-VS

C56

+

10uF

+DVdd

D

C

B

EXT_VREFP

1

2

3

EXT_REFP

FL1



A

Engineer:

Joe Purvis

Drawn By:

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Power & Reference DATE: 28-Nov-2001

FILE: SIZE:

1 2 34

12500 TI Boulevard. Dallas, Texas 75243

TITLE:

Power & Reference

DOCUMENT CONTR O L #:

6430333

A4

SHEET: OF:

214

A

REV:

321

5(9 (&11XPEHU $SSURYHG

TP16

+DVdd

D

C51

+

4.7uF

C53

C50

0.1uF

0.01uF

D2

C58

TP18

C59

0.1uF

+DVdd

C44

+

10uF

+

10uF

F 040500

4

5HYLVLRQ+LVWRU\

D

TP12

TP9

C29

0.1uF

0.01uF

TP11

C42

+

10uF



12500 TI Boulevard. Dallas, Texas 75243

Power

6430333

A4

+Vs

+AVdd

C20

+

10uF

SHEET: OF:

314

C

B

A

REV:

BLM11A121SGPB

8

PG

6

OUT

5

OUT

7

FB3

R63 357K

R64 110K

W13

R24 590K

+

C31

4.7uF

FB2

BLM11A121SGPB

C34

0.1uF

C24

Engineer:

Joe Purvis

Drawn By:

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Power DATE: 28-Nov-2001

FILE: SIZE:

+

C28

4.7uF

TITLE:

DOCUMENT CONTR O L #:

C

U6 TPS77801D

R18 20K

R62 0

TP13

3

IN

4

IN

2

/ENA

1

GND

SENSE / FB

-Vs

+VIN

D1

+

C25

B

REF_IN

-VIN

A

10uF

1 2 34

+

Green

C26

4.7uF

C33

+

10uF

BLM11A121SGPB

R17 1K

FB1

R14 0

C27

0.1uF

321

5(9 (&11XPEHU $SSURYHG

F 040500

R25

Trim

1

R23 0

Not Installed

C46

0.1uF

RV10 100K

U11 TLE2081

Trim

5

R20 0

Vout

6

W17

RV9 10k

D

SENSE

C

3

6

Temp

Vout

+VIN

U7 VRE3050

2

+Vin

+Vs

7

2

V+

-In

3

+In

V-

4

5HYLVLRQ+LVWRU\

D

C

TP10

R50

C30

+

8

NR

2.2uF

B

REF GND

7

GND

4

TRIM

5

RV7 10k

+

C38

2.2uF

R66 4k

R65 6k

R67 10K

-Vs

C45

0.1uF

5K

R29 10K

EXT_REFP

VREFPW16

B



A

Engineer:

Joe Purvis

Drawn By:

Joe Purvis

Reference DATE: 28-Nov-2001

FILE: SIZE:

1 2 34

12500 TI Boulevard. Dallas, Texas 75243

TITLE:

Reference

DOCUMENT CONTR O L #:

6430333

A4

SHEET: OF:

414

A

REV:

C22

+AVdd

321

0405002

5(9 (&11XPEHU $SSURYHG

4

5HYLVLRQ+LVWRU\

ADC_REF

0.1uF C19

10uF

6

3

2

Vref

AGND

FS or SCLK

1

7

C47

0.01uF

ADC_REF

2

3

6

AIN0

AIN1

U5

VDD

8

SDO

CS* or CS*/FS

4 5

MSOP ADC

7

U501

8

+DVdd

1

J10

1 2 3 4 5 6 7 8

R10 10K

C1 100pF

ADC_Data_out

LCL_CLKX

LCL_CS_ADC*

D

C

B

D

C23 10uF

AIN0

R19 0

C14

0.1uF

4

AIN or AI N0 or AIN(+)

SENSE

VREFP

C

In_0

SOCKETED ADC

5

AIN1

B

In_1

W10

SCLK or AIN1 or AIN(-)

FS

W12



A

Engineer:

Joe Purvis

Drawn By:

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ADC DATE: 28-Nov-2001

FILE: SIZE:

1 2 34

12500 TI Boulevard. Dallas, Texas 75243

TITLE:

ADC

DOCUMENT CONTR O L #:

6430333

A4

SHEET: OF:

514

A

REV:

DAC Out

321

C43

+AVdd

4

5(9 (&11XPEHU $SSURYHG

2 040500

5HYLVLRQ+LVWRU\

D

C

B

AOUT W19

AOUT_A

W15

J9

A2_FLT14A204+

13

A2_OUT

6

B2_FLT

5

B2_OUT

DAC_OUT

DAC Out

OUT/OUTB

GND

VREF2

V2-

V2+

A203+

A202A201-

A2/SD

B2/SD

B201-

B202B203+ B204+

10

-VS

9 12 7

+VS

15 16 17 18 11

8 4 3 2 1

7

REF +AVdd

TP20

DAC SOP(D)

3

4

TP21

7

658

2

OUT/OUTB

U801

1

0.1uF C41

10uF

5

AGND

SOCKETED DAC

FS/OUTA

4

8

Vcc

C21

0.1uF

R54 10K

W14

REF

R55

1 2 3 4 5 6 7 8

10K

C32

0.1uF

6

REF

CS*

3

U8

1

DIN

SCLK

2

J11

VREFP

DAC_Data_in

LCL_CLKX

LCL_CS_DAC*

DAC_Write*

D

C

B

OUTA

A

1 2 34

DAC_OUTA

W18

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DAC DATE: 28-Nov-2001

FILE: SIZE:

DAC

DOCUMENT CONTR O L #:

6430333

A4

SHEET: OF:

614

A

REV:

321

-Vs

R33 0

RV11

D

U12 TLE2081

DAC_OUTA

R35

4.7K

C52

C

B

R26

DAC_OUT

4.7K

C36

6

Vout

U9

6

Vout

100K

R30

0

5

Trim

R34 0

R27

0

5

Trim

RV8

100K

C48

0.1uF

R51 5K

R32

0

4

1

Trim

R28

0

1

Trim

+Vs

-Vs

3

V-

+In

2

-In

V+

7

4

3

V-

+In

2

-In

V+

7

C49

0.1uF

R31 NI

C39

0.1uF

R22 NI

OUTA

OUT/OUTB

5(9 (&11XPEHU $SSURYHG

2

040500

4

5HYLVLRQ+LVWRU\

D

C

B

C40

A

R21 0

1 2 34

0.1uF

+Vs

TITLE:

Engineer:

Joe Purvis

Drawn By:

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Output conditioning DATE: 28-Nov-2001

FILE: SIZE:

DOCUMENT CONTR O L #:



12500 TI Boulevard. Dallas, Texas 75243

DAC Output

6430333

A4

SHEET: OF:

714

A

REV:

321

Peripheral & Control ConnectorMemory Interfac e Connector

DSP_CLKX

D

C

B

DSP_CLKR

DSP_FSX

DSP_FSR

DSP_DX

DSP_DR

DSP_XF

DSP_TOUT

DSP_CLKS

FB12 BLM11A121SGPB

FB11 BLM11A121SGPB

FB5 BLM11A121SGPB

FB4 BLM11A121SGPB

FB6

BLM11A121SGPB FB7

BLM11A121SGPB

FB9

BLM11A121SGPB

FB10

BLM11A121SGPB

FB8

BLM11A121SGPB

CLKX

CLKR

FSX

FSR

DX

DR

XF

TOUT

CLKS

+3.3v

+5v

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

+5v

+3.3v

CLKX FSX

CLKR FSR

TOUT XF

PCI_-12V

PCI_+12V

PCI_+5V

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

5(9 (&11XPEHU $SSURYHG

F 040500

CLKS DX

DR

4

5HYLVLRQ+LVWRU\

D

C

B

J13

XF

1 2

CLKX

3 4

CLKR

5 6

DX

7 8

DR

9 10

FSX

11 12

FSR

13 14 15 16

CLKS

17 18

A

TOUT

19 20

1 2 34

J12

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

J15

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

J16

PCI_GND

Engineer:

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User connectors DATE: 28-Nov-2001

FILE: SIZE:

J17

TITLE:

DOCUMENT CONTR O L #:



12500 TI Boulevard. Dallas, Texas 75243

User Connectors

6430333

A4

SHEET: OF:

814

A

REV:

321

5(9 (&11XPEHU $SSURYHG

4

5HYLVLRQ+LVWRU\

TO / FROM USER

CONNECTIONS

FS

DAC_Data_in

DAC_Write*

DSP_TOUT DSP_CLKS DSP_CLKX DSP_CLKR DSP_DX DSP_DR DSP_FSX DSP_FSR DSP_XF

C64

0.01uF

Stand Al one Mode

FS

LCL_CS_ADC* LCL_CLKX

ADC_Data_out

DAC_Data_in

LCL_CS_DAC* DAC_Write*

+DVdd

8

C65

0.1uF

SYSCLK

EVM_CLKX

DSP_XF

DSP_FSX

DSP_DX DSP_DR

MOM

DAC_Type

SAM*

X1

VCC

GND4OUT

OE

MOM* DAC_Type

SAM*

1

5

R56

430

SYSCLK

SYSCLK EVM_CLKX

DSP_XF

DSP_FSX

DSP_DX DSP_DR

+DVdd

R37 1K

D

C

DSP_TOUT

DSP_CLKS

DSP_CLKX DSP_CLKR

DSP_DX

DSP_DR DSP_FSX

DSP_FSR

DSP_XF

LCL_CS_ADC*

LCL_CLKX

ADC_Data_out

TO / FROM ADC

B

LCL_CS_DAC*

TO DAC

D3

1

SW1D

4

A

1 2 34

Out5In

In

SW1A

Out

8

SYSCLK EVM_CLKX

DSP_FSR

DSP_FSX

DSP_TOUT

DSP_CLKX

DSP_CLKR

DSP_CLKS

R57 430

D4

+DVdd

2

7

In

Out

SW1B

R38 1K

R40

33

W24

R45

33

R43

33

+DVdd

R6 430

D5

3

6

In

Out

SW1C

W20

R11 1K

W22

W21

J14

R44 33

R46

49.9K

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Digital Interface DATE: 28-Nov-2001

FILE: SIZE:

EVM-0309R2.DDB

Digital Interface

DOCUMENT CONTR O L #:

6430333

A4

R71 33

W23

SHEET: OF:

914

D

C

B

A

REV:

321

I12/O0/Q0 I13/O1/Q1

I14/O2/Q2

I15/O3/Q3 I16/O4/Q4

I17/O5/Q5

I18/O6/Q6 I19/O7/Q7

I20/O8/Q8

I21/O9/Q9

NC NC NC NC

U13A

I11 I10

CLK/I0

5(9 (&11XPEHU $SSURYHG

16

13

ADC_Data_n3

12

I9

I8 I7

I6

I5 I4

I3

I2 I1

ADC_Data_out

11

DSP_DX

10

ADC_TC*

9

START*

7

SAM* DSP_DX

6

DAC_Type

5

DSP_FSX

4

DSP_XF

3

RESET

2

SYSCLK

MOM EVM_CLKX SYSCLK DSP_FSX

DSP_XF SAM* DAC_Type ADC_Data_out START*

MOM

EVM_CLKX

SYSCLK

DSP_FSX

DSP_DX DSP_XF

SAM*

DAC_Type

ADC_Data_out

START

U16B

14

GND

D

U13B

14

GND

U14B

14

C

GND

Vcc

+DVdd

28

C63

0.1uF

+DVdd

28

C55

0.1uF

+DVdd

28

C54

0.1uF

DSP_DR

LCL_CS_ADC*

DAC_Data_in

TP14

DSP_DR MOM ADC_CS* DAC_Data_in

TP15

Q0 Q1 Q2 Q3 INIT*

17

18

19 20

21

23 24

25

26 27

1

8 15 22

4

5HYLVLRQ+LVWRU\

+DVdd

R39 10K

SW2

D

C

+DVdd

C62

U10

3

OUT

8

VCC

5

CONT

1

GND

NE555D

TITLE:

DOCUMENT CONTR O L #:

RESET

DISCH

THRES

TRIG

4

7

6

2

R42 10K

C61

R41 10K

RESET

SW3



12500 TI Boulevard. Dallas, Texas 75243

Stand Alone

6430333

A4

SHEET: OF:

B

A

REV:

10 14

U16A

FS

LCL_CS_DAC*

LCL_CLKX

ADC_Data_n3

B

ADC_Data_out

A

DAC_Write*

1 2 34

TP19

TP17

17

I12/O0/Q0

18

I13/O1/Q1

19

I14/O2/Q2

20

I15/O3/Q3

21

I16/O4/Q4

23

I17/O5/Q5

24

I18/O6/Q6

25

I19/O7/Q7

26

I20/O8/Q8

27

I21/O9/Q9

1

NC

8

NC

15

NC

22

NC

CLK/I0

16

I11

13

12

11 10

9

7 6

5 4

3

2

Q0 Q1 Q2 Q3 MOM DAC_Type EVM_CLKX DSP_FSX DSP_XF RESET SYSCLK

I10

I9

I8

I7 I6

I5

I4 I3

I2

I1

ADC_TC*

17 18

19

20 21

23

24 25

26 27

1

8 15 22

I12/O0/Q0

I13/O1/Q1 I14/O2/Q2

I15/O3/Q3

I16/O4/Q4 I17/O5/Q5

I18/O6/Q6

I19/O7/Q7 I20/O8/Q8

I21/O9/Q9

NC NC NC NC

U14A

CLK/I0

16

I11

13

12

11 10

9

7 6

5 4

3

2

Q0 Q1 Q2 Q3

DAC_Type INIT* DSP_FSX DSP_XF RESET SYSCLK

I10

I9

I8

I7 I6

I5

I4 I3

I2

I1

RESET

+DVdd

C60

0.1uF

Engineer:

Joe Purvis

Drawn By:

Joe Purvis

Stand Alone Mode DATE: 28-Nov-2001

FILE: SIZE:

321

5(9 (&11XPEHU $SSURYHG

2 040500

4

5HYLVLRQ+LVWRU\

Signal Conditioning

D

BNC_0

W1

C

B

IDC_0

BNC_1

W5

IDC_1

IN_0 OUT_0

J3

1

B204+

2

B203+

3

B202-

4

B201-

8

B2/SD

11

A2/SD

18

A201-

17

A202-

16

A203+

15

+Vs

-Vs

A204+

7

V2+

12

V2-

9

VREF2

10

GND

B2_OUT

B2_FLT

A2_OUT

A2_FLT

W11

5

6

13

14

Prototype Ar e a

IN_0

Signal Generator

BB_Output_0

Test signal 0

Test signal 1

W2

W6

W4

W7

W3

R12

D

6800pF

TP7

TP6

Channel_0

Channel_1

C

B

R9

33

C8

33

C9

Signal Conditioning

OUT_1

A

1 2 34

IN_1

W25

Prototype Ar e a

IN_1

BB_Output_1

W8



12500 TI Boulevard. Dallas, Texas 75243

TITLE:

Engineer:

Joe Purvis

Drawn By:

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Input configuration DATE: 28-Nov-2001

FILE: SIZE:

Input Configuration

DOCUMENT CONTR O L #:

6430333

A4

SHEET: OF:

11 14

A

REV:

+Vs

321

5(9 (&11XPEHU $SSURYHG

2 040500

4

5HYLVLRQ+LVWRU\

-Vs

8 4

+Vs

R8

4.7K

U4A

TLE2082D

U4B

TLE2082D

C13

0.1uF

1

C12

0.1uF

7

Test Signal 0

Test Signal 1



12500 TI Boulevard. Dallas, Texas 75243

TITLE:

Engineer:

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Drawn By:

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Signal Generator DATE: 28-Nov-2001

FILE: SIZE:

Signal Generator

DOCUMENT CONTR O L #:

6430333

A4

SHEET: OF:

12 14

D

C

B

A

REV:

D

C6

+

10uF

R60

49.9K

R72

C

W9

B

A

C17 1nF

-Vs

49.9K

+

1 2 34

C18 10uF

0.1uF

6

5

4

12

1

10

8 7

14

13 11

C5

U3

V+ Duty adj.

Duty Adj.

Sine Adj Sine Adj

Timing Cap.

FM Sweep Input

FM Bias

Not Connected

Not connected

V- / GND

ICL8038

C15

0.1uF

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Prototype Area DATE: 28-Nov-2001

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Prototype Area

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12500 TI Boulevard. Dallas, Texas 75243

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Engineer:

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Signal Conditioning DATE: 28-Nov-2001

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REV:

Texas Instruments SLAU081 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

IMPORTANT NOTICE

EVM IMPORTANT NOTICE

EVM WARNINGS AND RESTRICTIONS

Contents

Figures

Tables

Introduction

EVM Modes

1.1.1 Stand-Alone Mode

1.1.2 User Mode

Analog Input Conditioning

1.3 Analog Output Conditioning

1.4 Prototype Area

Getting Started

Shipping (Default Configuration)

Jumpers

2.2.1 Analog I/O Signal Conditioning

2.2.2 Channel 0 Analog Input

2.2.3 Channel 0 Analog Output

Signal Generator

V oltage Reference

ADC Supply Voltage

Switches

Clock/Timer Routing

2.3.1 Stand-Alone-Mode, SW1-1

Connectors

ADC and DAC Direct Access

2.6 Host Communication

2.6.1 Common Connector

2.6.2 Legacy Connector

Bill of Materials, Board Layout, and Schematics