TEXAS INSTRUMENTS SBAS306F Technical data

SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

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 

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FEATURES

D 105kSPS Data Rate D AC Performance:

51kHz Bandwidth 109dB SNR (High-Resolution Mode)

−108dB THD

D DC Accuracy:

1.8µV/°C Offset Drift 2ppm/°C Gain Drift

D Selectable Operating Modes:

High-Speed: 105kSPS Data Rate High-Resolution: 109dB SNR Low-Power: 35mW Dissipation

D Power-Down Control D Digital Filter:

Linear Phase Response Passband Ripple: ±0.005dB Stop Band Attenuation: 100dB

D Internal Offset Calibration On Command D Selectable SPIt or Frame Sync Serial In terface D Designed for Multichannel Systems:

Daisy-Chainable Serial Interface Easy Synchronization

D Simple Pin-Driven Control D Modulator Output Option D Specified fro m −40°C to +105°C D Analog Supply: 5V D Digital Supply: 1.8V to 3.3V

DESCRIPTION

The ADS1271 is a 24-bit, delta-sigma analog-to-digital converter (ADC) with a data rate up to 105kSPS. It offers a unique combination of excellent DC accuracy and outstanding AC performance. The high-order, chopper-stabilized modulator achieves very low drift with low in-band noise. The onboard decimation filter suppresses modulator and signal out-of-band noise. The ADS1271 provides a usable signal bandwidth up to 90% of the Nyquist rate with less than 0.005dB of ripple.

Traditionally, industrial delta-sigma ADCs offering good drift performance use digital filters with large passband droop. As a result, they have limited signal bandwidth and are mostly suited for DC measurements. High-resolution ADCs in audio applications offer larger usable bandwidths, but the offset and drift specification are significantly weaker than their industrial counterparts. The ADS1271 combines these converters, allowing high-precision industrial measurement with excellent DC and AC specifications ensured over an extended industrial temperature range.

Three operating modes allow for optimization of speed, resolution, and power. A selectable SPI or a frame-sync serial interface provides for convenient interfacing to microcontrollers or DSPs. The output from the modulator is accessible for external digital filter applications. All operations, including internal offset calibration, are controlled directly by pins; there are no registers to program.

VREFP VREFN AVDD DVDD

APPLICATIONS

D Vibration/Modal Analysis

Control

Logic

D Acoustics D Dynamic Strain Gauges D Pressure Sensors D Test and Measurement

semiconductor products and disclaimers thereto appears at the end of this data sheet.

SPI is a trademark of Motorola Inc. All other trademarks are the property of their respective owners.

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AINP

AINN

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∆Σ

Modulator

Copyright  2004−2007, Texas Instruments Incorporated

Digital

Filter

Serial

Interface

DGNDAGND

SYNC/PDWN MODE

CLK DRDY/FSYNC

SCLK DOUT DIN FORMAT



Input Current

SBAS306F − NOVEMBER 2004 − REVISED OCT OBER 2007

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ABSOLUTE MAXIMUM RATINGS

over opera t i n g f r e e - a i r t e m p e r a t ure range u n l e s s o t h e r w i s e n o t e d

ADS1271 UNIT

AVDD to AGND −0.3 to +6.0 V DVDD to DGND −0.3 to +3.6 V AGND to DGND −0.3 to +0.3 V

100, Momentary mA

10, Continuous mA Analog Input to AGND −0.3 to AVDD + 0 .3 V Digital Input or Output to DGND −0.3 to DVDD + 0.3 V Maximum Junction Tem perature +150 °C Operating Temperature Range −40 to +105 °C Storage Temperature Range −60 to +150 °C

(1)

Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only , an d functional operation of the device at these or any other conditions beyond those specified is not implied.

(1)

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe

proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to

complete device failure. Precision integrated circuits may be more susceptible t o damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or refer to our web site at www.ti.com.

2

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Differential

input (f

)

Noise Power-supply

Power-supply Signal-to-noise

Signal-to-noise

)

ratio (SNR)

Stop band Group delay

Group delay

(latency)

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SBAS306F − NOVEMBER 2004 − REVISED OCT OBER 2007

ELECTRICAL CHARACTERISTICS

All specifications at TA = −40°C to +105°C, AVDD = +5V, DVDD = +1.8V, f

Specified values for ADS1271 and ADS1271B (high-grade version) are the same, except where shown in BOLDFACE type.

PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

Analog Inputs

Full-scale input voltage (FSR Absolute input voltage AINP or AINN to AGND AGND – 0.1 AVDD + 0.1 AGND – 0.1 AVDD + 0.1 V Common-mode input voltage VCM = (AINP + AINN)/2 2.5 2.5 V

High-Speed mode 16.4 16.4 kΩ

input impedance

High-Resolution mode 16.4 16.4 kΩ Low-Power mode 32.8 32.8 kΩ

DC Performance

Resolution No missing codes 24 24 Bits

Data rate

DATA

High-Speed mode 105,469 105,469 SPS High-Resolution mode 52,734 52,734 SPS Low-Power mode 52,734 52,734 SPS

Integral nonlinearity (INL)

Offset error

High-Speed mode Without calibration 0.150 1 0.150 1 mV

Offset drift 1.8 1.8 µV/_C Gain error 0.1 0.5 0.1 0.5 %FSR Gain error drift 2 2 ppm/°C

High-Speed mode Shorted input 9.0 20 9.0 16 µV, rms

Noise

High-Resolution mode 6.5 6.5 12 µV, rms Low-Power mode 9.0 9.0 16 µV, rms

Common-mode rejection fCM = 60Hz 90 100 95 110 dB

AVDD

rejection

DVDD

AC Performance

High-Speed mode 99 106 101 106 dB

(2

ratio (SNR) (unweighted)

High-Resolution mode 109 103 109 dB Low-Power mode 106 101 106 dB

Total harmonic distortion (THD) Spurious-free dynamic range −108 −109 dB Passband ripple ±0.005 ±0.005 dB Passband 0.453 f

−3dB Bandwidth 0.49 f Stop band attenuation 100 100 dB

High-Speed mode 0.547 f

Stop band

High-Resolution mode 0.547 f Low-Power mode 0.547 f High-Speed and

Low-Power modes High-Resolution mode 39/f

Settling time

High-Speed and Low-Power modes

High-Resolution mode Complete settling 78/f

(1)

FSR = full-scale range = 2V

(2)

Minimum SNR is ensured by the limit of the DC noise specification.

(3)

THD includes the first nine harmonics of the input signal.

(4)

MODE and FORMAT pins excluded.

(5)

See the text for more details on SCLK.

(1)

) VIN = (AINP – AINN) ±V

Differential input,

= 2.5V

V

CM

With calibration On the level of the noise

f = 60Hz

(3)

VIN = 1kHz, −0.5dBFS −105 −95 −108 −100 dB

Complete settling 76/f

.

REF

= 27MHz, VREFP = 2.5V , and VREFN = 0V, unless otherwise noted.

CLK

ADS1271 ADS1271B

REF

±V

REF

± 0.0006 ± 0.0015 ± 0.0006 ± 0.0015 %FSR

80 80 dB 80 80 dB

DATA DATA DATA

38/f

DATA DATA

DATA

63.453 f

127.453 f

63.453 f

DAT A DAT A DAT A

0.547 f

DATA DATA DATA

0.453 f

0.49 f

38/f 39/f 76/f 78/f

DATA DATA

63.453 f

127.453 f

63.453 f

DATA

DAT A DATA DAT A

V

Hz Hz

Hz Hz Hz

s s s s

(1)

3



Reference

Input

Serial clock

SCLK

Frame-Sync format

AVDD current Power-Down mode

DVDD current Power-Down mode

dissipation

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SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007

ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA = −40°C to +105°C, AVDD = +5V, DVDD = +1.8V, f

Specified values for ADS1271 and ADS1271B (high-grade version) are the same, except where shown in BOLDFACE type.

PARAMETER UNITSMAXTYPMINMAXTYPMINTEST CONDITIONS

Voltage Reference Inputs

Reference input voltage (V Negative reference input (VREFN) AGND − 0.1 VREFP − 2.0 AGND − 0.1 VREFP − 0.5 V Positive reference input (VREFP) VREFN + 2.0 AVDD − 0.5 VREF N + 0.5 A VDD + 0.1 V

High-Speed mode 4.2 4.2 kΩ

Input impedance

High-Resolution mode 4.2 4.2 kΩ Low-Power mode 8.4 8.4 kΩ

Digital Input/Output

V

IH

V

IL

V

OH

V

OL

Input leakage Master clock rate (f

(4)

CLK

SPI format 24 f

Serial clock rate (f

SCLK

(5)

)

Frame-Sync format

Power Supply

AVDD 4.75 5 5.25 4.75 5 5.25 V DVDD 1.65 3.6 1.65 3.6 V

High-Speed mode 17 25 17 25 mA High-Resolution mode 17 25 17 25 mA

AVDD current

Low-Power mode 6.3 9.5 6.3 9.5 mA

High-Speed mode 3.5 6 3.5 6 mA High-Resolution mode 2.5 5 2.5 5 mA

DVDD current

Low-Power mode 1.8 3.5 1.8 3.5 mA

High-Speed mode 92 136 92 136 mW

Power

High-Resolution mode 90 134 90 134 mW Low-Power mode 35 54 35 54 mW

Temperature Range

Specified −40 +105 −40 +105 _C Operating −40 +105 −40 +105 _C Storage −60 +150 −60 +150 _C (1)

FSR = full-scale range = 2V

(2)

Minimum SNR is ensured by the limit of the DC noise specification.

(3)

THD includes the first nine harmonics of the input signal.

(4)

MODE and FORMAT pins excluded.

(5)

See the text for more details on SCLK.

) V

REF

= VREFP – VREFN 2.0 2.5 2.65 0.5 2.5 2.65 V

REF

0.7 DVDD DVDD 0.7 DVDD DVDD V

IOH = 5mA 0.8 DVDD DVDD 0.8 DVDD DVDD V IOL = 5mA DGND 0.2 DVDD DGND 0.2 DVDD V 0 < V

IN DIGITAL

< DVDD ±10 ±10 µA

) 0.1 27 0.1 27 MHz

High-Speed mode 64 f High-Resolution mode 128 f Low-Power mode 64 f

T > 85°C 1 70 1 70 µA T ≤ 85°C 1 10 1 10 µA

T > 85°C, DVDD = 3.3V 1 70 1 70 µA T ≤ 85°C, DVDD = 3.3V 1 20 1 20 µA

.

REF

= 27MHz, VREFP = 2.5V , and VREFN = 0V, unless otherwise noted.

CLK

ADS1271BADS1271

DGND 0.3 DVDD DGND 0.3 DVDD V

f

DATA DATA DATA DATA

64 f

128 f

64 f

CLK DATA DATA DATA

24 f 64 f

128 f

64 f

DATA DATA DATA DATA

64 f

128 f

64 f

f

CLK

DATA DATA DATA

MHz MHz MHz MHz

4

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MODE5Digital Input

FORMAT

6

Digital Input

PIN ASSIGNMENTS



SBAS306F − NOVEMBER 2004 − REVISED OCT OBER 2007

PW P ACKAGE

TSSOP-16

(TOP VIEW)

AINP AINN

AGND

AVDD

MODE

FORMAT

SYNC/PDWN

DIN

1 2 3 4

ADS1271

5 6 7 8

16

VREFP

15

VREFN

14

DGND

13

DVDD

12

CLK

11

SCLK

10

DRDY/FSYNC

9

DOUT

Terminal Functions

NAME NO. FUNCTION DESCRIPTION

AINP 1 Analog Input Positive analog input AINN 2 Analog Input Negative analog input AGND 3 Analog Input Analog ground AVDD 4 Analog Input Analog supply MODE 5 Digital Input MODE = 0: High-Speed mode

MODE = float: High-Resolution mode MODE = 1: Low-Power mode

FORMAT 6 Digital Input FORMAT = 0 : SPI

FORMAT = float: Modulator output (ADS1271B only)

FORMAT = 1: Frame-Sync SYNC/PDWN 7 Digital Input Synchronize/Power-down input, active low DIN 8 Digital Input Data input for daisy-chain operation DOUT 9 Digital Output ADC data output, modulator output (modulator mode) DRDY/FSYNC 10 Digital

Input/Output SCLK 11 Digital Input Serial clock for ADC data retrieval, modulator clock output (modulator mode) CLK 12 Digital Input Master clock DVDD 13 Digital Input Digital supply DGND 14 Digital Input Digital ground VREFN 15 Analog Input Negative reference input VREFP 16 Analog Input Positive reference input

If FORMAT = 0 (SPI), then pin 10 = DRDY output If FORMAT = 1 (Frame-Sync), then pin 10 = FSYNC input

5



CONV

DATA

t

CONV

Conversion period (1/f

DATA

)

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SBAS306F − NOVEMBER 2004 − REVISED OCT OBER 2007

TIMING CHARACTERISTICS: SPI FORMAT

t

CLK

t

CD

DRDY

t

DS

SCLK

t

DDO

DOUT

DIN

Bit 23 (MSB) Bit 22 Bit 21

TIMING REQUIREMENTS: SPI FORMAT

For TA = −40°C to +105°C and DVDD = 1.65V to 3.6V.

SYMBOL PARAMETER MIN TYP MAX UNIT

t

CLK

t

CPW

t

(1)

t

CD

(1)

t

DS

(1)

t

DDO

(1)

t

SD

(2)

t

S

t

SPW

t

DOHD

t

DOPD

t

DIST

(3)

t

DIHD

(1)

Load on DRDY and DOUT = 20pF.

(2)

For best performance, limit f

(3)

t

DOHD

temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is 4nS.

CLK period (1/f

) 37 10,000 ns

CLK

CLK positive or negative pulse width 15 ns

High-Speed mode 256 CLK periods

Conversion period (1/f

High-Resolution mode 512 CLK periods

)

Low-Power mode 512 CLK periods Falling edge of CLK to falling edge of DRDY 8 ns Falling edge of DRDY to rising edge of first SCLK to retrieve data 5 ns Valid DOUT to falling edge of DRDY 0 ns Falling edge of SCLK to rising edge of DRDY 8 ns SCLK period t SCLK positive or negative pulse width 12 ns

(1)(3)

SCLK falling edge to old DOUT invalid (hold time) 5 ns

(1)

SCLK falling edge to new DOUT valid (propagation delay) 12 ns New DIN valid to falling edge of SCLK (setup time) 6 ns Old DIN valid to falling edge of SCLK (hold time) 6 ns

(DOUT hold time) and t

SCLK/fCLK

to ratios of 1, 1/2, 1/4, 1/8, etc.

(DIN Hold time) are specified under opposite worst case conditions (digital supply voltage and ambient

DIHD

t

SPW

CPW

t

SD

t

•••

CPW

t

DIST

t

CONV

t

S

t

DOHD

t

DIHD

t

SPW

t

DOPD

CLK

ns

6

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FRAME

DATA

t

FRAME

Frame period (1/f

DATA

)

S

t

S

be continuously running)

TIMING CHARACTERISTICS: FRAME-SYNC FORMAT



SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007

t

CPW

t

CPW

t

SPW

t

DIST

t

FRAME

t

FPW

t

S

t

DOHD

t

DIHD

t

SPW

t

DOPD

t

SF

CLK

FSYNC

SCLK

DOUT

DIN

t

CLK

t

CF

t

FPW

t

FS

t

DDO

Bit 23(MSB) Bit22 Bit 21

TIMING REQUIREMENTS: FRAME-SYNC FORMAT

for TA = −40°C to +105°C and DVDD = 1.65V to 3.6V.

SYMBOL PARAMETER MIN TYP MAX UNIT

t

CLK

t

CPW

t

CF

t

FPW

t

FS

t

SF

t

SPW

t

DOHD

t

DOPD

t

DDO

t

DIST

t

DIHD

(1)

The ADS1271 automatically detects either frame period (only 256 or 512 allowed).

(2)

Load on DOUT = 20pF.

(3)

t

DOHD

temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is 4nS.

CLK period (1/f

) 37 10,000 ns

CLK

CLK positive or negative pulse width 15 ns Falling edge of CLK to falling edge of SCLK −0.35 t

CLK

0.35 t

CLK

High-Speed mode 256 CLK periods

Frame period (1/f

High-Resolution mode 256 or 512

)

Low-Power mode 256 or 512

(1) (1)

FSYNC positive or negative pulse width 1 SCLK periods Rising edge of FSYNC to rising edge of SCLK 5 ns Rising edge of SCLK to rising edge of FSYNC 5 ns

SCLK period (SCLK must

High-Resolution mode τ

FRAME

Low-Power mode τ

High-Speed mode τ

SCLK positive or negative pulse width 0.4t

(2)(3 )

SCLK falling edge to old DOUT invalid (hold time) 5 ns

(2)

SCLK falling edge to new DOUT valid (propagation delay) 12 ns

(2)

Valid DOUT to rising edge of FSYNC 0 ns

SCLK

/64 τ

FRAME

/128 τ

/64 τ

FRAME

0.6t

SCLK

New DIN valid to falling edge of SCLK (setup time) 6 ns

(3)

Old DIN valid to falling edge of SCLK (hold time) 6 ns

(DOUT hold time) and t

(DIN Hold time) are specified under opposite worst case conditions (digital supply voltage and ambient

DIHD

CLK periods CLK periods

FRAME FRAME FRAME

ns

periods periods periods

ns

7



OUTPUT SPECTRUM

Amplitude (dB)

OUTPUT SPECTRUM

Amplitude (dB)

OUTPUT SPECTRUM

Amplitude (dB)

NOISE HISTOGRAM

OUTPUT SPECTRUM

Amplitude (dB)

OUTPUT SPECTRUM

Amplitude (dB)

SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007

TYPICAL CHARACTERISTICS

TA = 25°C, AVDD = 5V, DVDD = 1.8V, f

= 27MHz, VREFP = 2.5V , VREFN = 0V, unless otherwise noted.

CLK

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0

High−Speed Mode

= 1kHz,−0.5dBFS

f

−

20

IN

32,768 Points

−

40

−

60

−

80

−

100

−

120

−

140

−

160

10 100 1k

Frequency (Hz)

Figure 1

0

High−Speed Mode

−

Shorted Input

20

2,097,152 Points

−

40

−

60

−

80

−

100

−

120

−

140

−

160

−

180

0.1 1 10 100 1k Frequency (Hz)

10k 100k

0

High−Speed Mode

=1kHz,−20dBFS

f

−

20

IN

32,768 Points

−

40

−

60

−

80

−

100

−

120

−

140

−

160

10 100 1k

420k

High−Speed Mode Shorted Input

360k

2,097,152 Points

300k

240k

180k

120k

Number of Occurrences

60k

0

−50−45−40−35−30−25−20−15−

Frequency (Hz)

Figure 2

5

0

5

10

−

Output (µV)

10k 100k

101520253035404550

Figure 3

0

High−Resolution Mode

=1kHz,−0.5dBFS

f

−

20

IN

32,768 Points

−

40

−

60

−

80

−

100

−

120

−

140

−

160

10 100 1k

Frequency (Hz)

Figure 5

10k 100k

0

High−Resolution Mode

= 1kHz,−20dBFS

f

−

20

IN

32,768 Points

−

40

−

60

−

80

−

100

−

120

−

140

−

160

10 100 1k

Figure 4

10k 100k

Frequency (Hz)

Figure 6

8

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OUTPUT SPECTRUM

Amplitude (dB)

NOISE HISTOGRAM

OUTPUT SPECTRUM

Amplitude (dB)

OUTPUT SPECTRUM

Amplitude (dB)

OUTPUT SPECTRUM

Amplitude (dB)

NOISEH ISTOGRAM

TYPICAL CHARACTERISTICS (continued)

TA = 25°C, AVDD = 5V, DVDD = 1.8V, f

= 27MHz, VREFP = 2.5V , VREFN = 0V, unless otherwise noted.

CLK



SBAS306F − NOVEMBER 2004 − REVISED OCT OBER 2007

0

High−Resolution Mode

−

20

Shorted Input 1,048,576 Points

−

40

−

60

−

80

−

100

−

120

−

140

−

160

−

180

0.1 1 10 100 1k Frequency (Hz)

Figure 7

0

Low−Power Mode

=1kHz,−0.5dBFS

f

−

20

IN

32,768 Points

−

40

−

60

−

80

−

100

−

120

−

140

−

160

10 100 1k

Frequency (Hz)

10k 100k

210k

High−ResolutionMode Shorted Input

180k

1,048,576 Points

150k

120k

90k

60k

Number ofOccurrences

30k

0

−30−28−26−24−22−20−18−16−14−12−

0

Low−Power Mode

=1kHz,−20dBFS

f

−

20

IN

32,768 Points

−

40

−

60

−

80

−

100

−

120

−

140

−

160

10 100 1k

2

−8−6−4−

Output (µV)

02468

10

Figure 8

Frequency (Hz)

1012141618202224262830

10k 100k

Figure 9

0

Low−Power Mode

−

Shorted Input

20

1,048,576 Points

−

40

−

60

−

80

−

100

−

120

−

140

−

160

−

180

0.1 1 10 100 1k Frequency (Hz)

Figure 11

10k 100k

200k

Low−Power Mode

180k

Shorted Input 1,048,576 Points

160k 140k 120k 100k

80k 60k

Number of Occurrences

40k 20k

0

−50−45−40−35−30−25−20−15−

Figure 10

5

0

5

10

−

Output (µV)

Figure 12

101520253035404550

9



TOTAL HARMONIC DISTORTION

THD, THD+NAmplitude (dB)

TOTAL HARMONIC DISTORTION

THD, THD+NAmplitude (dB)

TOTAL HARMONIC DISTORTION

THD, THD+NAmplitude (dB)

TOTAL HARMONIC DISTORTION

THD, THD+NAmplitude (dB)

TOTAL HARMONIC DISTORTION

THD, THD+NAmplitude (dB)

TOTAL HARMONIC DISTORTION

THD, THD+NAmplitude (dB)

SBAS306F − NOVEMBER 2004 − REVISED OCT OBER 2007

TYPICAL CHARACTERISTICS (continued)

TA = 25°C, AVDD = 5V, DVDD = 1.8V, f

= 27MHz, VREFP = 2.5V , VREFN = 0V, unless otherwise noted.

CLK

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0

High−Speed Mode

=−0.5dBFS

V

IN

−

20

−

40

−

60

−

80

−

100

−

120

10 100 1k

0

High−Resolution Mode

=−0.5dBFS

V

IN

−

20

−

40

−

60

−

80

−

100

−

120

10 100 1k

vs FREQUENCY

THD+N

THD

Frequency (Hz)

Figure 13

vs FREQUENCY

THD+N

THD

Frequency (Hz)

Figure 15

10k 100k

0

High−Speed Mode

=1kHz

f

IN

−

20

−

40

−

60

−

80

−

100

−

120

−

140

−

120−100

0

High−Resolution Mode

=1kHz

f

IN

−

20

−

40

−

60

−

80

−

100

−

120

−

140

−

120−100

vs INPUT LEVEL

THD+N

THD

−

80

Input Amplitude (dBFS)

−

60

Figure 14

vs INPUT LEVEL

THD+N

THD

−

80

Input Amplitude (dBFS)

−

60

Figure 16

−

40

20 0

−

20 0

0

Low−Power Mode

=−0.5dBFS

V

IN

−

20

−

40

−

60

−

80

−

100

−

120

10 100 1k

vs FREQUENCY

THD+N

THD

Frequency (Hz)

10k 100k

0

−

20

−

40

−

60

−

80

−

100

−

120

−

140

−

120−100

Low−Power Mode

=1kHz

f

IN

Figure 17

vs INPUT LEVEL

THD+N

THD

−

80

Input Amplitude (dBFS)

−

60

Figure 18

−

40

20 0

10

www.ti.com

ABSOLUTE OFFSET DRIFT HISTOGRAM

GAIN DRIFT HISTOGRAM

OFFSETPOWER−ON WARMUP

GAIN ERROR POWER−ON WARMUP

UNCALIBRATED OFFSET HISTOGRAM

GAIN ERRORHISTOGRAM

TYPICAL CHARACTERISTICS (continued)

TA = 25°C, AVDD = 5V, DVDD = 1.8V, f

= 27MHz, VREFP = 2.5V , VREFN = 0V, unless otherwise noted.

CLK



SBAS306F − NOVEMBER 2004 − REVISED OCT OBER 2007

60

50

40

30

20

Occurrences (%)

10

0

13579111315171921

30 units, based on 20_C intervals

overthe range−40_C to +105_C

outliers:T <−20_C

Absolute Offset Drift (µV/_C)

Figure 19

40 30

V)

20

µ

10

0

−

10

−

20

Normalized Offset (

−

30

−

40

0102030405060

Response

Band

Time After Power−On (s)

High−SpeedMode DVDD = 3.3V

15

10

5

Occurrences (%)

0

6.0−5.5−5.0−4.5−4.0−3.5−3.0−2.5−2.0−1.5−1.0−0.5

−

Gain Drift (ppm/_C)

30units, based on 20_C

intervals over the range

−40_

Cto+105_C

0

0.5

1.0

1.5

2.0

2.5

Figure 20

10

8 6 4 2 0

−

2

−

4

−

6

Normalized Gain Error (ppm)

−

8

−

10

0102030405060

Response

Band

Time AfterPower−On (s)

High−Speed Mode DVDD = 3.3V

3.0

3.5

4.0

Figure 21

30

High−Speed Mode 30 Units

20

Units (%)

10

0

500−450−400−350−300−250−200−150−100

−

Uncalibrated Offset (µV)

Figure 23

50

−

Figure 22

50

High−SpeedMode 30 Units

40

30

Units (%)

20

10

0

50

100

150

200

250

300

0

2350−2300−2250−2200−2150−2100−2050−2000−1950−1900−1850−1800−1750−1700−1650−1600

−

Gain Error(ppm)

Figure 24

11