Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
FEATURES
D105kSPS Data Rate
DAC Performance:
51kHz Bandwidth
109dB SNR (High-Resolution Mode)
−108dB THD
DDC Accuracy:
1.8µV/°C Offset Drift
2ppm/°C Gain Drift
DSelectable Operating Modes:
High-Speed: 105kSPS Data Rate
High-Resolution: 109dB SNR
Low-Power: 35mW Dissipation
DPower-Down Control
DDigital Filter:
Linear Phase Response
Passband Ripple: ±0.005dB
Stop Band Attenuation: 100dB
DInternal Offset Calibration On Command
DSelectable SPIt or Frame Sync Serial In terface
DDesigned for Multichannel Systems:
Daisy-Chainable Serial Interface
Easy Synchronization
DSimple Pin-Driven Control
DModulator Output Option
DSpecified fro m −40°C to +105°C
DAnalog Supply: 5V
DDigital Supply: 1.8V to 3.3V
DESCRIPTION
The ADS1271 is a 24-bit, delta-sigma analog-to-digital
converter (ADC) with a data rate up to 105kSPS. It offers
a unique combination of excellent DC accuracy and
outstanding AC performance. The high-order,
chopper-stabilized modulator achieves very low drift with
low in-band noise. The onboard decimation filter
suppresses modulator and signal out-of-band noise. The
ADS1271 provides a usable signal bandwidth up to 90%
of the Nyquist rate with less than 0.005dB of ripple.
Traditionally, industrial delta-sigma ADCs offering good
drift performance use digital filters with large passband
droop. As a result, they have limited signal bandwidth and
are mostly suited for DC measurements. High-resolution
ADCs in audio applications offer larger usable bandwidths,
but the offset and drift specification are significantly
weaker than their industrial counterparts. The ADS1271
combines these converters, allowing high-precision
industrial measurement with excellent DC and AC
specifications ensured over an extended industrial
temperature range.
Three operating modes allow for optimization of speed,
resolution, and power. A selectable SPI or a frame-sync
serial interface provides for convenient interfacing to
microcontrollers or DSPs. The output from the modulator
is accessible for external digital filter applications. All
operations, including internal offset calibration, are
controlled directly by pins; there are no registers to
program.
VREFP VREFNAVDDDVDD
APPLICATIONS
DVibration/Modal Analysis
Control
Logic
DAcoustics
DDynamic Strain Gauges
DPressure Sensors
DTest and Measurement
semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI is a trademark of Motorola Inc. All other trademarks are the property of their respective owners.
over opera t i n g f r e e - a i r t e m p e r a t ure range u n l e s s o t h e r w i s e n o t e d
ADS1271UNIT
AVDD to AGND−0.3 to +6.0V
DVDD to DGND−0.3 to +3.6V
AGND to DGND−0.3 to +0.3V
100, MomentarymA
10, ContinuousmA
Analog Input to AGND−0.3 to AVDD + 0 .3V
Digital Input or Output to DGND−0.3 to DVDD + 0.3V
Maximum Junction Tem perature+150°C
Operating Temperature Range−40 to +105°C
Storage Temperature Range−60 to +150°C
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only , an d
functional operation of the device at these or any other conditions
beyond those specified is not implied.
(1)
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible t o damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current package and ordering information,
see the Package Option Addendum located at the end of
this data sheet, or refer to our web site at www.ti.com.
2
Differential
Differential
input
(f
)
Noise
Power-supply
Power-supply
Signal-to-noise
Signal-to-noise
)
ratio (SNR)
Stop band
Group delay
Group delay
(latency)
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SBAS306F − NOVEMBER 2004 − REVISED OCT OBER 2007
ELECTRICAL CHARACTERISTICS
All specifications at TA = −40°C to +105°C, AVDD = +5V, DVDD = +1.8V, f
Specified values for ADS1271 and ADS1271B (high-grade version) are the same, except where shown in BOLDFACE type.
PARAMETERTEST CONDITIONSMINTYPMAXMINTYPMAXUNITS
Analog Inputs
Full-scale input voltage (FSR
Absolute input voltageAINP or AINN to AGNDAGND – 0.1AVDD + 0.1 AGND – 0.1AVDD + 0.1V
Common-mode input voltageVCM = (AINP + AINN)/22.52.5V
If FORMAT = 0 (SPI), then pin 10 = DRDY output
If FORMAT = 1 (Frame-Sync), then pin 10 = FSYNC input
5
CONV
DATA
t
CONV
Conversion period (1/f
DATA
)
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SBAS306F − NOVEMBER 2004 − REVISED OCT OBER 2007
TIMING CHARACTERISTICS: SPI FORMAT
t
CLK
CLK
t
CD
DRDY
t
DS
SCLK
t
DDO
DOUT
DIN
Bit 23 (MSB)Bit 22Bit 21
TIMING REQUIREMENTS: SPI FORMAT
For TA = −40°C to +105°C and DVDD = 1.65V to 3.6V.
SYMBOLPARAMETERMINTYPMAXUNIT
t
CLK
t
CPW
t
(1)
t
CD
(1)
t
DS
(1)
t
DDO
(1)
t
SD
(2)
t
S
t
SPW
t
DOHD
t
DOPD
t
DIST
(3)
t
DIHD
(1)
Load on DRDY and DOUT = 20pF.
(2)
For best performance, limit f
(3)
t
DOHD
temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is 4nS.
CLK period (1/f
)3710,000ns
CLK
CLK positive or negative pulse width15ns
High-Speed mode256CLK periods
Conversion period (1/f
High-Resolution mode512CLK periods
)
Low-Power mode512CLK periods
Falling edge of CLK to falling edge of DRDY8ns
Falling edge of DRDY to rising edge of first SCLK to retrieve data5ns
Valid DOUT to falling edge of DRDY0ns
Falling edge of SCLK to rising edge of DRDY8ns
SCLK periodt
SCLK positive or negative pulse width12ns
(1)(3)
SCLK falling edge to old DOUT invalid (hold time)5ns
(1)
SCLK falling edge to new DOUT valid (propagation delay)12ns
New DIN valid to falling edge of SCLK (setup time)6ns
Old DIN valid to falling edge of SCLK (hold time)6ns
(DOUT hold time) and t
SCLK/fCLK
to ratios of 1, 1/2, 1/4, 1/8, etc.
(DIN Hold time) are specified under opposite worst case conditions (digital supply voltage and ambient
DIHD
t
t
SPW
CPW
t
SD
t
•••
CPW
t
DIST
t
CONV
t
S
t
DOHD
t
DIHD
t
SPW
t
DOPD
CLK
ns
6
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FRAME
DATA
t
FRAME
Frame period (1/f
DATA
)
S
t
S
be continuously running)
TIMING CHARACTERISTICS: FRAME-SYNC FORMAT
SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007
t
CPW
t
CPW
t
SPW
t
DIST
t
FRAME
t
FPW
t
S
t
DOHD
t
DIHD
t
SPW
t
DOPD
t
SF
CLK
FSYNC
SCLK
DOUT
DIN
t
CLK
t
CF
t
FPW
t
FS
t
DDO
Bit 23(MSB)Bit22Bit 21
TIMING REQUIREMENTS: FRAME-SYNC FORMAT
for TA = −40°C to +105°C and DVDD = 1.65V to 3.6V.
SYMBOLPARAMETERMINTYPMAXUNIT
t
CLK
t
CPW
t
CF
t
t
FPW
t
FS
t
SF
t
t
SPW
t
DOHD
t
DOPD
t
DDO
t
DIST
t
DIHD
(1)
The ADS1271 automatically detects either frame period (only 256 or 512 allowed).
(2)
Load on DOUT = 20pF.
(3)
t
DOHD
temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is 4nS.
CLK period (1/f
)3710,000ns
CLK
CLK positive or negative pulse width15ns
Falling edge of CLK to falling edge of SCLK−0.35 t
CLK
0.35 t
CLK
High-Speed mode256CLK periods
Frame period (1/f
High-Resolution mode256 or 512
)
Low-Power mode256 or 512
(1)
(1)
FSYNC positive or negative pulse width1SCLK periods
Rising edge of FSYNC to rising edge of SCLK5ns
Rising edge of SCLK to rising edge of FSYNC5ns
SCLK period (SCLK must
High-Resolution modeτ
FRAME
Low-Power modeτ
High-Speed modeτ
SCLK positive or negative pulse width0.4t
(2)(3 )
SCLK falling edge to old DOUT invalid (hold time)5ns
(2)
SCLK falling edge to new DOUT valid (propagation delay)12ns
(2)
Valid DOUT to rising edge of FSYNC0ns
SCLK
/64τ
FRAME
/128τ
/64τ
FRAME
0.6t
SCLK
New DIN valid to falling edge of SCLK (setup time)6ns
(3)
Old DIN valid to falling edge of SCLK (hold time)6ns
(DOUT hold time) and t
(DIN Hold time) are specified under opposite worst case conditions (digital supply voltage and ambient
The ADS1271 is a 24-bit, delta-sigma ADC. It offers the
combination of outstanding DC accuracy and superior AC
performance. Figure 43 shows the block diagram for the
ADS1271. The ADS1271 converter is comprised of an
advanced, 6th-order, chopper-stabilized, delta-sigma
modulator followed by a low-ripple, linear phase FIR filter.
The modulator measures the differential input signal,
V
= (AINP – AINN), against the differential reference,
IN
= (VREFP – VREFN). The digital filter receives the
V
REF
modulator signal and provides a low-noise digital output.
To allow tradeoffs among speed, resolution, and power,
three modes of operation are supported on the ADS1271:
High-Speed, High-Resolution, and Low-Power. Table 1
summarizes the performance of each mode.
VREFP
VREFN
SBAS306F − NOVEMBER 2004 − REVISED OCT OBER 2007
In High-Speed mode, the data rate is 105kSPS; in
High-Resolution mode, the SNR = 109dB; and in
Low-Power mode, the power dissipation is only 35mW.
The digital filter can be bypassed, enabling direct access
to the modulator output.
The ADS1271 is configured by simply setting the
appropriate IO pins—there are no registers to program.
Data is retrieved over a serial interface that supports both
SPI and Frame-Sync formats. The ADS1271 has a
daisy-chainable output and the ability to synchronize
externally, so it can be used conveniently in multichannel
systems.
SYNC/PDWN
MODE
CLK
DRDY/FSYNC
SCLK
DOUT
DIN
FORMAT
AINP
AINN
Σ
V
REF
V
Σ
IN
∆Σ
Modulator
Digital
Filter
SPI
or
Frame−
Sync
Serial
Interface
Figure 43. Block Diagram
Table 1. Operating Mode Performance Summary
MODEDATA RATE (SPS)PASSBAND (Hz)SNR (dB)NOISE (µV
High-Speed105,46947,7771069.092
High-Resolution52,73423,8891096.590
Low-Power52,73423,8891069.035
)POWER (mW)
RMS
15
High-Resolution
Low-Power
SBAS306F − NOVEMBER 2004 − REVISED OCT OBER 2007
ANALOG INPUTS (AINP, AINN)
The ADS1271 measures the differential input signal
V
= (AINP – AINN) against the differential reference
IN
= (VREFP – VREFN). The most positive measurable
V
REF
differential input is +V
positive digital output code of 7FFFFFh. Likewise, the
most negative measurable differential input is −V
which produces the most negative digital output code of
800000h.
While the ADS1271 measures the differential input signal,
the absolute input voltage is also important. This is the
voltage on either input (AINP or AINN) with respect to
AGND. The range for this voltage is:
−0.1V < (AINN or AINP) < AVDD +0.1V
, which produces the most
REF
REF
t
=1/f
ON
S1
OFF
ON
,
S2
OFF
SAMPLE
MOD
Figure 45. S1 and S2 Switch Timing for Figure 44
Table 2. Modulator Frequency for the Different
Mode and Format Settings
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If either input is taken below –0.4V or above (AVDD + 0.4),
ESD protection diodes on the inputs may turn on.
If these conditions are possible, external Schottky clamp
diodes or series resistors may be required to limit the input
current to safe values (see Absolute Maximum Ratings).
The ADS1271 uses switched-capacitor circuitry to
measure the input voltage. Internal capacitors are charged
by the inputs and then discharged. Figure 44 shows a
conceptual diagram of these circuits. Switch S2
represents the net effect of the modulator circuitry in
discharging the sampling capacitor; the actual
implementation is di fferent. The timing for switches S1 and
S2 is shown in Figure 45. The sampling time (t
the inverse of modulator sampling frequency (f
SAMPLE
MOD
) is
) and is
a function of the mode, format, and frequency of CLK, as
shown in Table 2. When using the Frame-Sync format with
High-Resolution or Low-Power modes, the ratio between
f
MOD
and f
depends on the frame period that is set by the
CLK
FSYNC input.
AGND
AVDD
INTERFACE
MODE
High-SpeedSPI or Frame-Syncf
FORMAT
SPIf
Frame-Syncf
SPIf
Frame-Syncf
CLK
CLK
f
MOD
CLK
CLK
/4 or f
CLK
/8 or f
/4
/4
/8
CLK
CLK
/2
/4
The average load presented by the switched capacitor
input can be modeled with an effective differential
impedance, as shown in Figure 46. Note that the effective
impedance is a function of f
AINP
Zeff = 16.4kΩ×(6.75MHz/f
AINN
MOD
.
)
MOD
Figure 44. Equivalent Analog Input Circuitry
16
AINP
AINN
AVDDAGND
ESD Protection
S
1
S
9pF
2
Figure 46. Effective Input Impedances
S
1
The ADS1271 is a very high-performance ADC. For
optimum performance, it is critical that the appropriate
circuitry be used to drive the ADS1271 inputs. See the
Application Information section for the recommended
circuits.
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SBAS306F − NOVEMBER 2004 − REVISED OCT OBER 2007
VOLTAGE REFERENCE INPUTS (VREFP,
VREFN)
The voltage reference for the ADS1271 ADC is the
differential voltage between VREFP and VREFN:
V
= (VREFP−VREFN). The reference inputs use a
REF
structure similar to that of the analog inputs with the
equivalent circuitry on the reference inputs shown in
Figure 47. As with the analog inputs, the load presented by
the switched capacitor can be modeled with an effective
impedance, as shown in Figure 48.
VREFP
Figure 47. Equivalent Reference Input Circuitry
VREFN
AVDDAVDD
ESD
Protection
VREFPVREFN
Zeff = 4.2kΩ×(6.75MHz/f
MOD
)
Figure 48. Effective Reference Impedance
ESD diodes protect the reference inputs. To keep these
diodes from turning on, make sure the voltages on the
reference pins do not go below AGND by more than 0.4V,
and likewise do not exceed AVDD by 0.4V. If these
conditions are possible, external Schottky clamp diodes or
series resistors may be required to limit the input current
to safe values (see Absolute Maximum Ratings).
Note that the valid operating range of the reference inputs
is limited to the following:
A high-quality reference voltage wi th the appropriate drive
strength is essential for achieving the b est p erformance f rom
the ADS1271. Noise and drift on the reference degrade
overall system performance. See the Applica tion I n forma tion
section for example reference circuits.
17
High-Resolution
Low-Power
SBAS306F − NOVEMBER 2004 − REVISED OCT OBER 2007
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CLOCK INPUT (CLK)
data rate. When High-Speed mode is used, each
conversion takes 256 CLK periods. When
The ADS1271 requires an external clock signal to be
applied to the CLK input pin. As with any high-speed data
High-Resolution or Low-Power modes are selected, the
conversions take 512 CLK periods.
converter, a high-quality, low-jitter clock is essential for
optimum performance. Crystal clock oscillators are the
recommended clock source. Make sure to avoid excess
ringing on the clock input; keeping the clock trace as short
as possible using a 50Ω series resistor will help.
The ratio between the clock frequency and output data rate
is a function of the mode and format. Table 3 shows the
ratios when the SPI format is selected. Also included in this
table is the typical CLK frequency and the corresponding
Table 4 shows the ratios when the Frame-Sync format is
selected. When using the Frame-Sync format in either
High-Resolution or Low-Power mode, the f
can be 256 or 512. The ADS1271 automatically detects
which ratio is being used. Using a ratio of 256 allows the
CLK frequency to be reduced by a factor of two while
maintaining the same data rate. The output data rate
scales with the clock frequency. See the Serial Interface
section for more details on the Frame-Sync operation.
The ADS1271 supports three modes of operation:
High-Speed, High-Resolution, and Low-Power. The mode
selection is determined by the status of the digital input
MODE pin, as shown in Table 5. A high impedance, or
floating, condition allows the MODE pin to support a third
state. The ADS1271 constantly monitors the status of the
MODE pin during operation and responds to a change in
status after 12,288 CLK periods. When floating the MODE
pin, keep the total capacitance on the pin less than 100pF
and the resistive loading greater than 10MΩ to ensure
proper operation. Changing the mode clears the internal
offset calibration value. If onboard offset calibration is
being used, be sure to recalibrate after a mode change.
When daisy-chaining multiple ADS1271s together and
operating in High-Resolution mode (MODE pin floating), the
MODE pin of e ach d evice m ust be isolated f r om o ne a nother;
this ensures p roper d evice operation. T he MODE p ins can b e
tied together for High-Speed and Low-Power modes.
Table 5. Mode Selection
MODE PIN ST ATUSMODE SELECTION
Logic Low (DGND)High-Speed
(1)
Float
Logic High (DVDD)Low-Power
(1)
Load on MODE: C < 100pF, R > 10MΩ.
High-Resolution
When using the SPI format, DRDY is held high after a
mode change occurs until settled (or valid) data is ready,
as shown in Figure 49.
In Frame-Sync format, the DOUT pin is held low after a
mode change occurs until settled data is ready, as shown
in Figure 49. Data can be read from the device to detect
when DOUT changes to logic 1, indicating valid data.
FORMAT SELECTION (FORMAT)
To help connect easily to either microcontrollers or DSPs,
the ADS1271 supports two formats for the serial interface:
an SPI-compatible interface and a Frame-Sync interface.
The format is selected by the FORMAT pin, as shown in
Table 6. If the status of this pin changes, perform a sync
operation afterwards to ensure proper operation. The
modulator output mode does not require a sync operation.
Table 6. Format Selection
FORMAT PIN STATUSSERIAL INTERFACE FORMAT
Logic Low (DGND)SPI
(1)
Float
Logic High (DVDD)Frame-Sync
(1)
Load on FORMAT: C < 100pF, R > 10MΩ.
(2)
See Modulator Output section.
Modulator Output
(2)
SPI
Format
Frame−Sync
Format
SYMBOL
MODE
Pin
CLK
ADS1271
Mode
DRDY
DOUT
t
MD
t
NDR
High−Speed
t
MD
Time to register MODE changes
Time for new data to be ready
Figure 49. Mode Change Timing
MINTYPMAXUNITSDESCRIPTION
12,288
Low−Power
t
NDR
Low−Power Mode
ValidData Ready
t
NDR
Low−Power Mode
ValidDataonDOUT
128
CLK periods
Conversions
)
(1/f
DATA
19
SBAS306F − NOVEMBER 2004 − REVISED OCT OBER 2007
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SYNCHRONIZATION
The SYNC/PDWN pin has two functions. When pulsed, it
synchronizes the start of conversions and, if held low for
more than 219 CLK cycles (t
Power-Down mode. The SYNC
for continuous data acquisition. See the Power-Down andOffset Calibration section for more details.
The ADS1271 can be synchronized by pulsing the
SYNC
/PDWN pin low and then returning the pin high.
When the pin goes low, the conversion process is stopped,
and the internal counters used by the digital filter are reset.
When the SYNC
/PDWN pin is returned high, the
conversion process is restarted. Synchronization allows
the conversion to be aligned with an external event; for
example, the changing of an external multiplexer on the
analog inputs, or by a reference timing pulse.
The SYNC
/PDWN pin is capable of synchronizing multiple
ADS1271s to within the same CLK cycle. Figure 50 shows
the timing requirement of SYNC/PDWN and CLK in SPI
format.
), places the ADS1271 in
SYN
/PDWN pin can be left high
CLK
t
SYNC/PDWN
DRDY
SYN
Figure 51 shows the timing requirement for Frame-Sync
format.
After synchronization, indication of valid data depends on
the whether SPI or Frame-Sync format was used.
In the SPI format, DRDY
/PDWN is taken low, as shown in Figure 50. After
SYNC
SYNC
/PDWN is returned high, DRDY stays high while the
goes high as soon as
digital filter is settling. Once valid data is ready for retrieval,
DRDY goes low.
In the Frame-Sync format, DOUT goes low as soon as
SYNC
/PDWN is taken low, as shown in Figure 51. After
SYNC
/PDWN is returned high, DOUT stays low while the
digital filter is settling. Once valid data is ready for retrieval,
DOUT begins to output valid data. For proper
synchronization, FSYNC, SCLK, and CLK must be
established before taking SYNC
/PDWN high, and must
then remain running.
t
CSHD
t
SCSU
t
NDR
SYMBOL
t
SCSU
t
CSHD
t
SYN
t
NDR
SYNC/PWDN to CLK setup time
CLK to SYNC/PWDN hold time
Synchronize pulse width
Time for new data to be ready128
Figure 50. Synchronization Timing for SPI format
CLK
SYNC/PDWN
FSYNC
DOUT
SYMBOL
t
SCSU
t
CSHDCLK to SYNC/PWDN hold time
t
t
SYNC/PWDN to CLK setup timens
Synchronize pulse width
SYN
Time for new data to be ready
NDR
MINTYPMAXUNITSDESCRIPTION
5
10
1
t
CSHD
t
t
SYN
SCSU
t
NDR
MINTYPMAXUNITSDESCRIPTION
5
10
1
128129
18
2
Valid Data
18
2
ns
ns
CLK periods
Conversions (1/f
ns
CLK periods
Conversions (1/f
DATA
DATA
)
)
20
Figure 51. Synchronization Timing for Frame-Sync Format
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SBAS306F − NOVEMBER 2004 − REVISED OCT OBER 2007
POWER-DOWN AND OFFSET CALIBRATION
In addition to controlling synchronization, the
SYNC
/PDWN pin also serves as the control for
Power-Down mode and offset calibration. To enter this
mode, hold the SYNC/PDWN pin low for at least 219 CLK
periods. While in Power-Down mode, both the analog and
digital circuitry are completely deactivated. The digital
inputs are internally disabled so that is not necessary to
shut down CLK and SCLK. To exit Power-Down mode,
return SYNC
The ADS1271 uses a chopper-stabilized modulator to
provide inherently very low offset drift. To further minimize
offset, the ADS1271 automatically performs an offset
self-calibration when exiting Power-Down mode. When
power down completes, the offset self-calibration begins
with the inputs AINP and AINN automatically
disconnected from the signal source and internally shorted
together. There is no need to modify the signal source
applied to the analog inputs during this calibration.
It is critical for the reference voltage to be stable when
exiting Power-Down mode; otherwise, the calibration will
be corrupted.
/PDWN high on the rising edge of CLK.
CLK
t
SYNC/PDWN
DRDY
PDWN
The offset self- calib r at ion on ly removes offset errors internal
to the device, not offset errors due to external sources.
NOTE: When an offset self-calibration is performed, the
resulting offset value will vary each time within the
peak-to-peak noise range of the converter. In High-Speed
mode, this is typically 178 LSBs.
The offset calibration value is cleared whenever the device
mode is changed (for example, from High-Speed mode to
High-Resolution mode).
When using the SPI format, DRDY
will stay high after
exiting Power-Down mode while the digital filter settles, as
shown in Figure 52.
When using the Frame-Sync format, DOUT will stay low
after exiting Power-Down mode while the digital filter
settles, as shown in Figure 53.
NOTE: In Power-Down mode, the inputs of the ADS1271
must be driven (do not float) and the device drives the
outputs driven to a DC level.
Figure 53. Power-Down Timing for Frame-Sync Format
21
SBAS306F − NOVEMBER 2004 − REVISED OCT OBER 2007
POWER-UP SEQUENCE
The analog and digital supplies should be applied before
any analog or digital input is driven. The power supplies
may be sequenced in any order. Once the supplies and the
voltage reference inputs have stabilized, data can be read
from the device.
FREQUENCY RESPONSE
The digital f ilter s ets t he o verall f requency r esponse. T he f ilter
uses a multi-stage FIR topology to provide linear phase with
minimal passband ripple a nd h igh stopband attenuation. T he
oversampling ratio of the digital filter (that is, the ratio of the
modulator sampling to the output data rate: f
MOD/fDATA
function of the selected mode, as shown in Table 7. f
CLK/2, CLK/4, or CLK/8, depending on the mode.
) is a
MOD
is
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0
−
20
−
40
−
60
−
80
Amplitude (dB)
−
100
−
120
−
140
00.20.60.81.0
Normalized Input Frequency (f
0.4
IN/fDATA
)
Table 7. Oversampling Ratio versus Mode
MODEOVERSAMPLING RATIO (f
High-Speed64
High-Resolution128
Low-Power64
MOD/fDATA
)
High-Speed and Low-Power Modes
The digital filter configuration is the same in both
High-Speed and Low-Power modes with the oversampling
ratio set to 64. Figure 54 shows the frequency response in
High-Speed and Low-Power modes normalized to f
DATA
Figure 55 shows the passband ripple. The transition from
passband to stop band is illustrated in Figure 56. The
overall frequency response repeats at 64x multiples of the
modulator frequency f
, as shown in Figure 57. These
MOD
image frequencies, if present in the signal and not
externally filtered, will fold back (or alias) into the
passband, causing errors. The stop-band of the ADS1271
provides 100dB attenuation of frequencies that begin just
beyond the passband and continue out to f
. Placing an
MOD
antialiasing, low-pass filter in front of the ADS1271 inputs
is recommended to limit possible high-amplitude
out-of-band signals and noise.
Figure 54. Frequency Response for High-Speed
and Low-Power Modes
0.02
0
−
0.02
−
0.04
−
Amplitude (dB)
.
0.06
−
0.08
−
0.10
00.10.30.40.50.6
0.2
Normalized Input Frequency (f
IN/fDATA
)
Figure 55. Passband Response for High-Speed
and Low-Power Modes
22
www.ti.com
0
−
1
−
2
−
3
−
4
−
5
−
6
Amplitude (dB)
−
7
−
8
−
9
−
10
0.450.470.490.510.530.55
Normalized Input Frequency (f
IN/fDATA
)
SBAS306F − NOVEMBER 2004 − REVISED OCT OBER 2007
High-Resolution Mode
The oversampling ratio is 128 in High-Resolution mode.
Figure 58 shows the frequency response in
High-Resolution mode normalized to f
shows the passband ripple, and the transition from
passband to stop band is illustrated in Figure 60. The
overall frequency response repeats at multiples of the
modulator frequency f
MOD
, (128 × f
DATA
Figure 61. The stop band of the ADS1271 provides 100dB
attenuation of frequencies that begin just beyond the
passband and continue out to f
MOD
antialiasing, low-pass filter in front of the ADS1271 inputs
is recommended to limit possible high-amplitude
out-of-band signals and noise.
. Figure 59
DATA
), as shown in
. Placing an
Figure 56. Transition Band Response for
High-Speed and Low-Power Modes
20
0
−
20
−
40
−
60
−
80
Gain (dB)
−
100
−
120
−
140
−
160
016324864
Input Frequency (f
IN/fDATA
)
Figure 57. Frequency Response Out to f
High-Speed and Low-Power Modes
MOD
for
0
−
20
−
40
−
60
−
80
Amplitude (dB)
−
100
−
120
−
140
00.250.751
Normalized Input Frequency (f
0.50
IN/fDATA
)
Figure 58. Frequency Response for
High-Resolution Mode
0.02
0
−
0.02
−
0.04
−
Amplitude (dB)
0.06
−
0.08
−
0.10
00.10.30.40.50.6
0.2
Normalized Input Frequency (f
Figure 59. Passband Response for
High-Resolution Mode
IN/fDATA
)
23
ANTIALIASING
SBAS306F − NOVEMBER 2004 − REVISED OCT OBER 2007
www.ti.com
0
−
1
−
2
−
3
−
4
−
5
−
6
Amplitude (dB)
−
7
−
8
−
9
−
10
0.450.470.490.510.530.55
Normalized Input Frequency (f
IN/fDATA
)
Figure 60. Transition Band Response for
High-Resolution Mode
20
0
−
20
−
40
−
60
−
80
Gain (dB)
−
100
−
120
−
140
−
160
0326496128
Normalized Input Frequency (fIN/f
DATA
)
PHASE RESPONSE
The ADS1271 incorporates a multiple stage, linear phase
digital filter. Linear phase filters exhibit constant delay time
versus input frequency (constant group delay). This
means the time delay from any instant of the input signal
to the same instant of the output data is constant and is
independent of input signal frequency. This behavior
results in essentially zero phase errors when analyzing
multi-tone signals.
SETTLING TIME
As with frequency and phase response, the digital filter
also determines settling time. Figure 62 shows the output
settling behavior after a step change on the analog inputs
normalized to conversion periods. The X axis is given in
units of conversion. Note that after the step change on the
input occurs, the output data changes very little prior to 30
conversion periods. The output data is fully settled after 76
conversion periods for High-Speed and Low-Power
modes, and 78 conversions for High-Resolution mode.
100
% Settling
Initial Value
0
Final Value
Fully Settled Data
at 76 Conversions
(78 Conversions for
High−Resolution mode)
Figure 61. Frequency Response out to f
Table 8. Antialiasing Filter Order Image Rejection
FIL TER ORDER
24
High-Resolution Mode
MOD
IMAGE REJECTION (dB)
(f
−3dB
at f
DATA
)
HS, LPHR
13945
27587
3111129
for
02010403060508070
Conversions (1/f
DATA
)
Figure 62. Settling Time for All Power Modes
www.ti.com
SBAS306F − NOVEMBER 2004 − REVISED OCT OBER 2007
DATA FORMAT
The ADS1271 outputs 24 bits of data in two’s complement
format.
A positive full-scale input produces an output code of
7FFFFFh, and the negative full-scale input produces an
output code of 800000h. The output clips at these codes
for signals exceeding full-scale. Table 9 summarizes the
ideal output codes for different input signals.
Table 9. Ideal Output Code versus Input Signal
INPUT SIGNAL V
(AINP − AINN)
w +V
+V
223* 1
0000000h
−V
223* 1
REF
ǒ
v −V
(1)
Excludes effects of noise, INL, offset and gain errors.
REF
REF
REF
23
2
223* 1
IN
Ǔ
IDEAL OUTPUT CODE
7FFFFFh
000001h
FFFFFFh
800000h
(1)
rising edge. Even though the SCLK input has hysteresis,
it is recommended to keep SCLK as clean as possible to
prevent glitches from accidentally shifting the data. SCLK
should be held low after data retrieval. SCLK may be run
as fast as the CLK frequency. SCLK may be either in
free-running or stop-clock operation between
conversions. For best performance, limit f
SCLK/fCLK
to ratios
of 1, 1/2, 1/4, 1/8, etc. When the device is configured for
modulator output, SCLK becomes the modulator clock
output (see the Modulator Output section).
For the f
SCLK/fCLK
ratio of 1, care must be observed that
these signals are not tied together. After Power On, SCLK
remains an output until a few clocks have been received
on the CLK input.
DRDY/FSYNC
In the SP I format, this pin functions as the DRDY output. It
goes low when data is ready for retrieval and then returns
high on the falling edge o f t he first subsequent SCLK. If data
is not retrieved (that is, SCLK is held low), DRDY
will pulse
high just before the next conversion data is ready, as shown
in Figure 63. T he n ew d ata i s l oaded within t he A DS1271 one
CLK cycle before DRDY
goes low. All data must be shifted
out before this time to avoid being overwritten.
SERIAL INTERFACE
Data is retrieved from the ADS1271 using the serial
interface. To provide easy connection to either
microcontrollers or DSPs, two formats are available for the
interface: SPI and Frame-Sync. The FORMA T pin selects
the interface. The same pins are used for both interfaces
(SCLK, DRDY
/FSYNC, DOUT and DIN), though their
respective functionality depends on the particular interface
selected.
SPI SERIAL INTERFACE
The SPI-compatible format is a simple read-only interface.
Data ready for retrieval is indicated by the DRDY
and is shifted out on the falling edge of SCLK, MSB first.
The interface can be daisy-chained using the DIN input
when using multiple ADS1271s. See the Daisy-Chaining
section for more information.
SCLK (SPI Format)
The serial clock (SCLK) features a Schmitt-triggered input
and shifts out data on DOUT on the falling edge. It also
shifts in data on the falling edge on DIN when this pin is
being used for daisy-chaining. The device shifts data out
on the falling edge and the user shifts this data in on the
output
1/f
CLK
DRDY
SCLK
1/f
DATA
Figure 63. DRDY Timing with No Readback
DOUT
The conversion data is shifted out on DOUT. The MSB
data is valid on DOUT when DRDY
goes low. The
subsequent bits are shifted out with each falling edge of
SCLK. If daisy-chaining, the data shifted in using DIN will
appear on DOUT after all 24 bits have been shifted out.
When the device is configured for modulator output, DOUT
becomes the modulator data output (see the ModulatorOutput section).
DIN
This input is used when multiple ADS1271s are to be
daisy-chained together. The DOUT pin of the first device
connects to the DIN pin of the next, etc. It can be used with
either the SPI or Frame-Sync formats. Data is shifted in on
the falling edge of SCLK. When using only one ADS1271,
tie DIN low. See the Daisy-Chaining section for more
information.
25
SBAS306F − NOVEMBER 2004 − REVISED OCT OBER 2007
www.ti.com
FRAME-SYNC SERIAL INTERFACE
Frame-Sync format is similar to the interface often used on
audio ADCs. It operates in slave fashion—the user must
supply framing signal FSYNC (similar to the left/right clock
on stereo audio ADCs) and the serial clock SCLK (similar
to the bit clock on audio ADCs). The data is output MSB
first or left-justified. When using Frame-Sync format, the
CLK, FSYNC and SCLK inputs must be synchronized
together, as described in the following sub-sections.
SCLK (Frame-Sync Format)
The serial clock (SCLK) features a Schmitt-triggered input
and shifts out data on DOUT on the falling edge. It also
shifts in data on the falling edge on DIN when this pin is
being used for daisy-chaining. Even though SCLK has
hysteresis, it is recommended to keep SCLK as clean as
possible to prevent glitches from accidentally shifting the
data. When using Frame-Sync format, SCLK must run
continuously. If it is shut down, the data readback will be
corrupted. Frame-Sync format requires a specific
relationship between SCLK and FSYNC, determined by
the mode shown in Table 10. When the device is
configured for modulator output, SCLK becomes the
modulator clock output (see the Modulator Output
section).
Table 10. SCLK Period When Using Frame-Sync
MODEREQUIRED SCLK PERIOD
High-Speedτ
High-Resolutionτ
Low-Powerτ
Format
FRAME
FRAME
FRAME
/64
/128
/64
DRDY/FSYNC
In Frame-Sync format, this pin is used as the FSYNC input.
The frame-sync input (FSYNC) sets the frame period. The
required FSYNC periods are shown in Table 11. For
High-Speed mode, the FSYNC period must be 256 CLK
periods. For both High-Resolution and Low-Power modes,
the FSYNC period can be either 512 or 256 CLK periods;
the ADS1271 will automatically detect which is being
used. If the FSYNC period is not the proper value, data
readback will be corrupted. It is recommended that
FSYNC be aligned with the falling edge of SCLK.
Table 11. FSYNC Period
MODEREQUIRED FSYNC PERIOD
High-Speed256 CLK Periods
High-Resolution256 or 512 CLK periods
Low-Power256 or 512 CLK periods
DOUT
The conversion data is shifted out on DOUT. The MSB
data becomes valid on DOUT on the CLK rising edge prior
to FSYNC going high. The subsequent bits are shifted out
with each falling edge of SCLK. If daisy-chaining, the data
shifted in using DIN will appear on DOUT after all 24 bits
have been shifted out. When the device is configured for
modulator output, DOUT becomes the modulator data
output (see the Modulator Output section).
DIN
This input is used when multiple ADS1271s are to be
daisy-chained together. It can be used with either SPI or
Frame-Sync formats. Data is shifted in on the falling edge
of SCLK. When using only one ADS1271, tie DIN low.See
the Daisy-Chaining section for more information.
26
www.ti.com
SBAS306F − NOVEMBER 2004 − REVISED OCT OBER 2007
DAISY-CHAINING
Multiple ADS1271s can be daisy-chained together to
simplify the serial interface connections. The DOUT of one
ADS1271 is connected to the DIN of the next ADS1271.
The first DOUT provides the output data and the last DIN
in the chain is connected to ground. A common SCLK is
used for all the devices in the daisy chain. Figure 64 shows
an example of a daisy chain with four ADS1271s.
Figure 65 shows the timing diagram when reading back in
the SPI format. It takes 96 SCLKs to shift out all the data.
In SPI format, it is recommended to tie all the
SYNC
/PDWN inputs together, which forces
synchronization of all the devices. It is only necessary to
monitor the DRDY output of one device when multiple
devices are configured this way.
In Frame-Sync format, all of the devices are driven to
synchronization by the FSYNC and SCLK inputs. However,
to ensure synchronization to the same f
recommended to tie all SYNC
The device clocks the SYNC
. To ensure exact synchronization, the SYNC/PDWN
of f
CLK
/PDWN inputs together.
/PDWN pin on the falling edge
pin should transition on the rising edge of f
cycle, it is
CLK
CLK
Since DOUT and DIN are both shifted on the falling edge
of SCLK, the propagation delay on DOUT creates the
setup time on DIN. Minimize the skew in SCLK to avoid
timing violations. See Mode Selection section for MODE
pin use when daisy-chaining.
The SPI format offers the most flexibility when
daisy-chaining because there is more freedom in setting
the SCLK frequency. The maximum number of ADS1271s
that can be daisy-chained is determined by dividing the
conversion time (1/f
all 24 bits (24 × 1/f
) by the time needed to read back
DATA
).
SCLK
Consider the case where:
f
= 27MHz
CLK
mode = High-Resolution (52,734SPS)
format = SPI
f
= 27MHz
SCLK
The maximum length of the daisy-chain is:
27MHz/(24 × 52,734SPS) = 21.3
Rounding down gives 21 as the maximum number of
ADS1271s that can be daisy-chained.
Daisy-chaining also works in Frame-Sync format, but the
maximum number of devices that can be daisy-chained is
less than when using the SPI format. The ratio between the
frame period and SCLK period is fixed, as shown in
Table 10. Using these values, the maximum number of
devices is two for High-Speed and Low-Power modes, and
five for High-Resolution mode.
SYNC
SCLK
ADS1271
SYNC
DIN
SCLK
4
DOUT
ADS1271
SYNC
DIN
SCLK
3
DOUT
ADS1271
SYNC
DIN
SCLK
2
DOUT
ADS1271
SYNC
DIN
SCLK
1
DRDY
DOUT
Figure 64. Example of SPI-Format, Daisy-Chain Connection for Multiple ADS1271s
DRDY
SCLK1
DOUT
ADS1271
Bit 23 (MSB)
1
24257396
ADS1271
Bit 0 (LSB)
1
Bit 23 (MSB)
ADS1271
2
ADS1271
Bit 2 3 (MSB)
4
ADS1271
Bit 0(LSB)
4
Figure 65. Timing Diagram for Example in Figure 64 (SPI Format)
27
SBAS306F − NOVEMBER 2004 − REVISED OCT OBER 2007
www.ti.com
MODULATOR OUTPUT
The ADS1271 incorporates a 6th-order, single-bit,
chopper-stabilized modulator followed by a multi-stage
digital filter, which yields the conversion results. The data
stream output of the modulator is available directly,
bypassing the internal digital filter. In this mode, an
external digital filter implemented in an ASIC, FPGA, or
similar device is required. To invoke the modulator output,
float the FORMAT pin and tie DIN to DVDD. DOUT then
becomes the modulator data stream output and SCLK
becomes the modulator clock output. The DRDY
pin becomes an unused output and can be ignored. The
normal operation of the Frame-Sync and SPI interfaces is
disabled, and the functionality of SCLK changes from an
input to an output, as shown in Figure 66. Note that
modulator output mode is specified for the B grade device
only.
DVDD
Modulator Data Output
Modulator Clock Output
(Float)
DIN
FORMAT
DOUT
SCLK
/FSYNC
In modulator output mode, the frequency of the SCLK
clock output depends on the mode selection of the
ADS1271. Table 12 lists the modulator clock output
frequency versus device mode.
Table 12. Modulator Output Clock Frequencies
MODULATOR CLOCK OUTPUT
MODE PIN
0f
Floatf
1f
(SCLK)
/4
CLK
/4
CLK
/8
CLK
Figure 67 shows the timing relationship of the modulator
clock and data outputs.
Modulator
Clock Output
Modulator
Data Output
SCLK
DOUT
(10ns max)
Figure 66. Modulator Output (B-Grade Device)
28
Figure 67. Modulator Output Timing
www.ti.com
SBAS306F − NOVEMBER 2004 − REVISED OCT OBER 2007
APPLICATION INFORMATION
To obtain the specified performance from the ADS1271,
the following layout and component guidelines should be
considered.
1.Power Supplies: The device requires two power
supplies for operation: DVDD and A VDD. The allowed
range for DVDD is 1.65V to 3.6V, and AVDD is
restricted to 4.75V to 5.25V. Best performance is
achieved when DVDD = 1.8V. For both supplies, use
a 10µF tantalum capacitor, bypassed with a 0.1µF
ceramic capacitor, placed close to the device pins.
Alternatively, a single 10µF ceramic capacitor can be
used. The supplies should be relatively free of noise
and should not be shared with devices that produce
voltage spikes (such as relays, LED display drivers,
etc.). If a switching power supply source is used, the
voltage ripple should be low (< 2mV). The power
supplies may be sequenced in any order.
2.Ground Plane: A single ground plane connecting both
AGND and DGND pins can be used. If separate digital
and analog grounds are used, connect the grounds
together at the converter.
3.Digital Inputs: It is recommended to source terminate
the digital inputs to the device with 50Ω series
resistors. The resistors should be placed close to the
driving end of digital source (oscillator, logic gates,
DSP, etc.) This helps to reduce ringing on the digital
lines, which may lead to degraded ADC performance.
4.Analog/Digital Circuits: Place analog circuitry (input
buffer, reference) and associated tracks together,
keeping them away from digital circuitry (DSP,
microcontroller, logic). Avoid crossing digital tracks
across analog tracks to reduce noise coupling and
crosstalk.
5.Reference Inputs: It is recommended to use a
minimum 10µF tantalum with a 0.1µF ceramic
capacitor directly across the reference inputs, VREFP
and VREFN. The reference input should be driven by
a low-impedance source. For best performance, the
reference should have less than 3µV
broadband
RMS
noise. For references with noise higher than this,
external reference filtering may be necessary.
6.Analog Inputs: The analog input pins must be driven
differentially to achieve specified performance. A true
differential driver or transformer (AC applications) can
be used for this purpose. Route the analog inputs
tracks (AINP, AINN) as a pair from the buffer to the
converter using short, direct tracks and away from
digital tracks.
A 1nF to 10nF capacitor should be used directly
across the analog input pins, AINP and AINN. A low-k
dielectric (such as COG or film type) should be used to
maintain low THD. Capacitors from each analog input
to ground should be used. They should be no larger
than 1/10 the size of the difference capacitor (typically
100pF) to preserve the AC common-mode
performance.
7.Component Placement: Place the power supply,
analog input, and reference input bypass capacitors
as close as possible to the device pins. This is
particularly important for the small-value ceramic
capacitors. Surface-mount components are
recommended to avoid the higher inductance of
leaded components.
Figure 68 to Figure 70 illustrate basic connections and
interfaces that can be used with the ADS1271.
(1) Bypass with 10µFand0.1µF capacitors.
(2) 2.7nF for Low−Power mode.
Figure 69. Basic Differential Input Signal Interface
Ω
V
1k
IN
5.6nF
+15V
V
REF
V
OCM
OPA1632
0.1µF
−
15V
5.6nF
Ω
1k
(1) Bypasswith 10µF and 0.1µF capacitors.
NOTES:
Ω
249
(2)
(1)
Ω
49.9
AINP
Ω
49.9
AINN
(1)
(2)
Ω
249
V
ODIFF
V
OCOMM=VREF
(2) 10nF forLow−Power mode.
Figure 70. Basic Single-Ended Input Signal
Interface
=0.25×V
IN
30
www.ti.com
7
Timing Characteristics:
16
Analog Inputs (AINP, AINN)
17
Voltage ReferFence Inputs
7/06
D
20
Synchronization
29
Application Information
SBAS306F − NOVEMBER 2004 − REVISED OCT OBER 2007
Revision History
DATEREVPAGESECTIONDESCRIPTION
10/07F25SCLK (SPI Format)Added final paragraph to section.
9/07E20SynchronizationAdded sentence to 1st paragraph regarding SYNC/PDWN left high.
2Absolute Maximum RatingsDeleted lead temperature.
Timing Characteristics:
Frame-Sync Format
Voltage ReferFence Inputs
(VREFP, VREFN)
20Synchronization
22Frequency ResponseAdded “or CLK/8” to last sentence of 2nd paragraph.
26DOUTChanged “SCLK” to “CLK” in 2nd sentence of 3rd paragraph.
Changed t
Added “(only 256 or 512 allowed)” to Note 1.
Changed “0.1V” to “0.4V” in 3rd paragraph
Added 4th paragraph about clamp diode and series resistor requirements.
Changed “0.1V” to “0.4V” in 1st paragraph of right column.
Added sentence about clamp diode and series resistor requirements.
Changed text from 2nd paragraph through end of section.
Changed Figure 50.
Changed Figure 51.
Changed “REFP” to “VREFP” in part 5.
Changed “REFN” to “VREFN” in part 5.
parameter from “falling edge” to “rising edge.”
DDO
NOTE:Page numbers for previous revisions may differ from page numbers in the current version.
31
PACKAGE OPTION ADDENDUM
www.ti.com
12-Oct-2007
PACKAGING INFORMATION
Orderable DeviceStatus
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
ADS1271IBPWACTIVETSSOPPW1690Green (RoHS &
no Sb/Br)
ADS1271IBPWG4ACTIVETSSOPPW1690Green (RoHS &
no Sb/Br)
ADS1271IBPWRACTIVETSSOPPW162000 Green (RoHS &
no Sb/Br)
ADS1271IBPWRG4ACTIVETSSOPPW162000 Green (RoHS &
no Sb/Br)
ADS1271IPWACTIVETSSOPPW1690Green (RoHS &
no Sb/Br)
ADS1271IPWG4ACTIVETSSOPPW1690Green (RoHS &
no Sb/Br)
ADS1271IPWRACTIVETSSOPPW162500 Green (RoHS &
no Sb/Br)
ADS1271IPWRG4ACTIVETSSOPPW162500 Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
(3)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153