Texas Instruments QFN Layout Manuallines

PlasticMold Compound

ExposedThermalPadLocated

UnderneaththePackage

Die Attach(Epoxy)

IC(Silicon)

Leadframe(Copper Alloy)

Application Report

QFN Layout Guidelines

Yang Boon Quek ........................................................................................ HPL Audio Power Amplifiers

1 Introduction

Board layout and stencil information for most Texas Instruments (TI) Quad Flat No-Lead (QFN) devices is
provided in their data sheets. This document helps printed-circuit board (PCB) designers understand and
better use this information for optimal designs.

The QFN package is a thermally enhanced standard size IC package designed to eliminate the use of
bulky heat sinks and slugs. This package can be easily mounted using standard PCB assembly
techniques and can be removed and replaced using standard repair procedures.

The QFN package is designed so that the lead frame die pad (or thermal pad) is exposed on the bottom
of the IC (see Figure 1 ). This provides an extremely low thermal resistance ( θJC) path between the die and
the exterior of the package.

SLOA122 – July 2006

SLOA122 – July 2006 QFN Layout Guidelines 1

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Figure 1. Section View of a QFN Package

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SolderMaskDefinedThermalPad,seeFigure4

FingerPads,seeFigure3

Board Layout

2 Board Layout

Figure 2 shows an example of the recommended board layout for an RGZ package.

Figure 2. Board Layout for an RGZ Package Finger Pads

TI recommends the use of rounded finger pads to prevent solder bridging. Surround each pad with a
0,07-mm wide solder mask. The recommended dimensions are shown in Figure 3 .

2.1 Solder Mask Defined Thermal Pad

The solder mask defined thermal pad is the exposed copper area not covered by solder mask. It must be
soldered directly to the thermal pad on the bottom of the IC. Figure 2 shows an example of the
recommended dimensions.

2.1.1 Copper Areas

Copper areas on and in a PCB act as heat sinks for the QFN device. Top copper areas should be covered
with solder mask leaving only the solder mask defined thermal pad exposed. The top copper areas should
be made as large as possible.

2 QFN Layout Guidelines SLOA122 – July 2006

Figure 3. Finger Pads Layout

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ThermalVia

WeborSpokeVia

NOTRecommended

Solid Via

Recommended

Exposed Copper–

0,05mm AroundVia

Inner or bottom layer copper planes also can be connected to thermal pad using vias and should be made
as large as possible. The thermal pad is usually tied to ground, and designers should verify the electrical
correctness when connecting the copper planes to the thermal pad.

Designers may leave the bottom copper plane exposed. However, studies have shown that this has
minimal impact on thermal performance.

2.1.2 Thermal Vias

TI recommends placing thermal vias in the solder mask defined thermal pad to transfer effectively the heat
from the top copper layer of the PCB to the inner or bottom copper layers.

TI provides the recommended layout of the thermal vias in most data sheets. The recommended via
diameter is 0,3 mm or less, and the recommended via spacing is 1 mm (see Figure 4 ).

Board Layout

Figure 4. Solder Mask Defined Thermal Pad

The thermal vias should make their connection to the internal ground plane with a complete connection
around the entire circumference of the plated through hole. Place a ring of exposed copper (0,05 mm
wide) around the vias at the bottom of the copper plane.

Do not cover the vias with solder mask which causes excessive voiding.
Do not use a thermal relief web or spoke connection which impedes the conduction path into the inner

copper layer(s) (see Figure 5 ).

Figure 5. Via Connection at the Bottom of the Copper Plane

SLOA122 – July 2006 QFN Layout Guidelines 3

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