Texas Instruments q25601 Service Manual

VBUS SW

BTST

SYS
BAT

I2C Bus

TS

USB

QON

REGN

+

I

CHG

Host

Host Control

Optional

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bq25601

SLUSCK5 –MARCH 2017

bq25601 I2C Controlled 3-A Single-Cell Battery Charger

for High Input Voltage and Narrow Voltage DC (NVDC) Power Path Management

1 Features

1

• High-Efficiency, 1.5-MHz, Synchronous Switch­Mode Buck Charger

– 92% Charge Efficiency at 2 A from 5-V Input
– Optimized for USB Voltage Input (5 V)
– Selectable Low Power Pulse Frequency

Modulation (PFM) Mode for Light Load
Operations

• Supports USB On-The-Go (OTG)
– Boost Converter With Up to 1.2-A Output
– 92% Boost Efficiency at 1-A Output
– Accurate Constant Current (CC) Limit
– Soft-Start Up To 500-µF Capacitive Load
– Output Short Circuit Protection
– Selectable Low Power PFM Mode for Light

Load Operations

• Single Input to Support USB Input and High
Voltage Adapters

– Support 3.9-V to 13.5-V Input Voltage Range

With 22-V Absolute Maximum Input Voltage
Rating

– Programmable Input Current Limit (100 mA to

3.2 A With 100-mA Resolution) to Support
USB 2.0, USB 3.0 Standards and High Voltage
Adaptors (IINDPM)

– Maximum Power Tracking by Input Voltage

Limit Up to 5.4 V (VINDPM)

– VINDPM Threshold Automatically Tracks

Battery Voltage

– Auto Detect USB SDP, DCP and Non-

Standard Adaptors

• High Battery Discharge Efficiency With 19.5-mΩ
Battery Discharge MOSFET

• Narrow VDC (NVDC) Power Path Management
– Instant-On Works with No Battery or Deeply

Discharged Battery

– Ideal Diode Operation in Battery Supplement

Mode

• BATFET Control to Support Ship Mode, Wake Up
and Full System Reset

• Flexible Autonomous and I2C Mode for Optimal

System Performance

• High Integration Includes All MOSFETs, Current
Sensing and Loop Compensation

• High Accuracy
– ±0.5% Charge Voltage Regulation
– ±5% at 1.5-A Charge Current Regulation

• Create a Custom Design Using the bq25601 With
the WEBENCH®Power Designer

2 Applications

• Smart Phones

• Portable Internet Devices and Accessory

3 Description

The bq25601 device is a highly-integrated 3-A switch­mode battery charge management and system power
path management device for single cell Li-Ion and Li­polymer battery. The low impedance power path
optimizes switch-mode operation efficiency, reduces
battery charging time and extends battery life during
discharging phase. The I2C serial interface with
charging and system settings makes the device a
truly flexible solution.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)

bq25601 WQFN (24) 4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Simplified Application

(1)

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

bq25601

SLUSCK5 –MARCH 2017

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Description (continued)......................................... 3

6 Pin Configuration and Functions......................... 4

7 Specifications......................................................... 6

7.1 Absolute Maximum Ratings ...................................... 6

7.2 ESD Ratings.............................................................. 6

7.3 Recommended Operating Conditions....................... 6

7.4 Thermal information .................................................. 7

7.5 Electrical Characteristics........................................... 7

7.6 Typical Characteristics............................................ 12

8 Detailed Description............................................ 14

8.1 Overview ................................................................. 14

8.2 Functional Block Diagram ....................................... 15

4 Revision History

DATE REVISION NOTES

March 2017 * Initial release.

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8.3 Feature Description................................................. 16

8.4 Register Maps......................................................... 31

9 Application and Implementation ........................ 42

9.1 Application information............................................ 42

9.2 Typical Application Diagram .................................. 43

10 Power Supply Recommendations ..................... 45

11 Layout................................................................... 46

11.1 Layout Guidelines ................................................. 46

11.2 Layout Example .................................................... 46

12 Device and Documentation Support ................. 48

12.1 Documentation Support ....................................... 48

12.2 Community Resources.......................................... 48

12.3 Trademarks........................................................... 48

12.4 Electrostatic Discharge Caution............................ 48

12.5 Glossary................................................................ 48

13 Mechanical, Packaging, and Orderable

Information........................................................... 49

2

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5 Description (continued)

The bq25601 is a highly-integrated 3.0-A switch-mode battery charge management and system power path
management device for single cell Li-Ion and Li-polymer battery. It features fast charging with high input voltage
support for a wide range of smart phones, tablets and portable devices. Its low impedance power path optimizes
switch-mode operation efficiency, reduces battery charging time and extends battery life during discharging
phase. Its input voltage and current regulation deliver maximum charging power to battery. The solution is highly
integrated with input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2), low-side
switching FET (LSFET, Q3), and battery FET (BATFET, Q4) between system and battery. It also integrates the
bootstrap diode for the high-side gate drive for simplified system design. The I2C serial interface with charging
and system settings makes the device a truly flexible solution.

The device supports a wide range of input sources, including standard USB host port, USB charging port, and
USB compliant high voltage adapter. The device sets default input current limit based on the built-in USB
interface. To set the default input current limit, the device takes the result from detection circuit in the system,
such as USB PHY device. The device is compliant with USB 2.0 and USB 3.0 power spec with input current and
voltage regulation. The device also meets USB On-the-Go (OTG) operation power rating specification by
supplying 5.15 V on VBUS with constant current limit up to 1.2A.

The power path management regulates the system slightly above battery voltage but does not drop below 3.5 V
minimum system voltage (programmable). With this feature, the system maintains operation even when the
battery is completely depleted or removed. When the input current limit or voltage limit is reached, the power
path management automatically reduces the charge current to zero. As the system load continues to increase,
the power path discharges the battery until the system power requirement is met. This Supplement Mode
prevents overloading the input source.

The device initiates and completes a charging cycle without software control. It senses the battery voltage and
charges the battery in three phases: pre-conditioning, constant current and constant voltage. At the end of the
charging cycle, the charger automatically terminates when the charge current is below a preset limit and the
battery voltage is higher than recharge threshold. If the fully charged battery falls below the recharge threshold,
the charger automatically starts another charging cycle.

The charger provides various safety features for battery charging and system operations, including battery
negative temperature coefficient thermistor monitoring, charging safety timer and overvoltage and overcurrent
protections. The thermal regulation reduces charge current when the junction temperature exceeds 110°C
(programmable). The STAT output reports the charging status and any fault conditions. Other safety features
include battery temperature sensing for charge and boost mode, thermal regulation and thermal shutdown and
input UVLO and overvoltage protection. The VBUS_GD bit indicates if a good power source is present. The INT
output Immediately notifies host when fault occurs.

The device also provides QON pin for BATFET enable and reset control to exit low power ship mode or full
system reset function.

The device is available in 24-pin, 4 mm × 4 mm x 0.75 mm thin WQFN package.

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3

18 GND
17 GND
16 SYS
15
14 BAT
13

SYS

BAT

(Not to scale)

Thermal

Pad

1VAC
2PSEL
3PG
4STAT
5SCL
6SDA

22

PMID21REGN20BTST19SW

SW

24

23

VBUS

INT

NC

NC

TS

CE

7 8 11 129 10

bq25601

SLUSCK5 –MARCH 2017

6 Pin Configuration and Functions

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RTW Package

24-Pin WQFN

Top View

Pin Functions

Pin

NAME NO.

BAT

BTST 21 P
CE 9 DI Charge enable pin. When this pin is driven low, battery charging is enabled.

GND

INT 7 DO

NC

PG 3 DO

PMID 23 DO

PSEL 2 DI

QON 12 DI

REGN 22 P

SCL 5 DI
SDA 6 DIO

13
14

17
18

8

10

(1) AI = Analog input, AO = Analog Output, AIO = Analog input Output, DI = Digital input, DO = Digital Output, DIO = Digital input Output, P

= Power

4

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(1)

TYPE

Battery connection point to the positive terminal of the battery pack. The internal BATFET and current sensing is

P

connected between SYS and BAT. Connect a 10 µF close to the BAT pin.
PWM high side driver positive supply. Internally, the BTST pin is connected to the cathode of the boost-strap

diode. Connect the 0.047-μF bootstrap capacitor from SW to BTST.

— Ground pins.

Open-drain interrupt Output. Connect the INT to a logic rail through 10-kΩ resistor. The INT pin sends an active
low, 256-µs pulse to host to report charger device status and fault.

— No Connect. Keep the pins float.

Open drain active low power good indicator. Connect to the pull up rail through 10-kΩ resistor. LOW indicates a
good input source if the input voltage is between UVLO and ACOV, above SLEEP mode threshold, and current
limit is above 30 mA.

Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET. Put 10 μF ceramic
capacitor on PMID to GND.

Power source selection input. Set 500 mA input current limit by pulling this pin high and set 2.4A input current limit
by pulling this pin low. Once the device gets into host mode, the host can program different input current limits to
IINDPM register.

BATFET enable/reset control input. When BATFET is in ship mode, a logic low of t
BATFET to exit shipping mode. When VBUS is not pluggeD–in, a logic low of t
resets SYS (system power) by turning BATFET off for t
to provide full system power reset. The pin contains an internal pull-up to maintain default high logic.

LSFET driver and internal supply output. Internally, REGN is connected to the anode of the boost-strap diode.
Connect a 4.7-μF (10-V rating) ceramic capacitor from REGN to GND. The capacitor should be placed close to the
IC.

I2C interface clock. Connect SCL to the logic rail through a 10-kΩ resistor.
I2C interface data. Connect SDA to the logic rail through a 10-kΩ resistor.

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DESCRIPTION

BATFET_RST

(minimum 250 ms) and then re-enable BATFET

QON_RST

duration turns on

SHIPMODE

(minimum 8 s) duration

bq25601

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Pin Functions (continued)

Pin

NAME NO.

STAT 4 DO

SW

SYS

TS 11 AI

VAC 1 AI Charge input voltage sense. This pin must be connected to VBUS pin.
VBUS 24 P

Thermal Pad — P

19
20
15
16

(1)

TYPE

Open-drain charge status output. Connect the STAT pin to a logic rail via 10-kΩ resistor. The STAT pin indicates
charger status. Collect a current limit resister and a LED from a rail to this pin.
Charge in progress: LOW
Charge complete or charger in SLEEP mode: HIGH
Charge suspend (fault response): 1-Hz, 50% duty cycle Pulses
This pin can be disabled via EN_ICHG_MON[1:0] register bits.

P Switching node output. Connected to output inductor. Connect the 0.047-μF bootstrap capacitor from SW to BTST.

Converter output connection point. The internal current sensing network is connected between SYS and BAT.

P

Connect a 20 µF capacitor close to the SYS pin.
Temperature qualification voltage input to support JEITA profile. Connect a negative temperature coefficient

thermistor. Program temperature window with a resistor divider from REGN to TS to GND. Charge suspends when
TS pin is out of range. When TS pin is not used, connect a 10-kΩ resistor from REGN to TS and connect a 10-kΩ
resistor from TS to GND. It is recommended to use a 103AT-2 thermistor.

Charger input. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID
pins. Place a 1-uF ceramic capacitor from VBUS to GND close to device.

Thermal pad and ground reference. This pad is ground reference for the device and it is also the thermal pad used
to conduct heat from the device. This pad should be tied externally to a ground plane through PCB vias under the
pad.

DESCRIPTION

SLUSCK5 –MARCH 2017

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SLUSCK5 –MARCH 2017

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

Voltage Range (with respect to
GND)

Voltage Range (with respect to
GND)

Voltage Range (with respect to
GND)

Voltage Range (with respect to
GND)

Voltage Range (with respect to
GND)

Voltage Range (with respect to
GND)

Output Sink Current STAT 6 mA
Voltage Range (with respect to

GND)
Voltage Range (with respect to

GND)
Output Sink Current INT 6 mA
Operating junction temperature, T
Storage temperature, T

stg

(1) Stresses beyond those listed under Absolute maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.

(2) VBUS is specified up to 22 V for a maximum of one hour at room temperature

VAC, VBUS (converter not switching)

BTST, PMID (converter not switching)

SW –2 16 V
BTST to SW –0.3 7 V

PSEL –0.3 7 V
REGN, TS, CE, PG, BAT, SYS (converter not switching) –0.3 7 V

SDA, SCL, INT, /QON, STAT –0.3 7 V

PGND to GND (QFN package only) –0.3 0.3 V

J

(1)

MIN MAX UNIT

(2)

(2)

–2 22 V

–0.3 22 V

–40 150 °C
–65 150 °C

7.2 ESD Ratings

VALUE UNIT

V

(ESD)

Electrostatic discharge

Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins

(1)

Charged device model (CDM), per
JEDEC specification JESD22-C101, all

(2)

pins

±2000

V

±250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT

V

BUS

I

in

I

SWOP

V

BATOP

I

BATOP

I

BATOP

T

A

Input voltage 3.9 13.5
Input current (VBUS) 3.25 A
Output current (SW) 3.25 A
Battery voltage 4.624 V
Fast charging current 3.0 A
Discharging current (continuous) 6 A
Operating ambient temperature –40 85 °C

(1) The inherent switching noise voltage spikes should not exceed the absolute maximum voltage rating on either the BTST or SW pins. A

tight layout minimizes switching noise.

(1)

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SLUSCK5 –MARCH 2017

7.4 Thermal information

bq25601

THERMAL METRIC

(1)

UNITRTW (WQFN)

24 PinS

R

θJA

R

θJC(top)

R

θJB

Ψ

JT

Ψ

JB

R

θJC(bot)

Junction-to-ambient thermal resistance 35.6 °C/W
Junction-to-case (top) thermal resistance 22.7 °C/W
Junction-to-board thermal resistance 11.9 °C/W
Junction-to-top characterization parameter 0.2 °C/W
Junction-to-board characterization parameter 12 °C/W
Junction-to-case (bottom) thermal resistance 2.6 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

7.5 Electrical Characteristics

V

VAC_UVLOZ

otherwise noted)

QUIESCENT CURRENTS

I

BAT

I

BAT

I

BAT

I

VBUS_HIZ

I

VBUS_HIZ

I

VBUS

I

VBUS

I

BOOST

VBUS, VAC AND BAT PIN POWER-UP

V

BUS_OP

V

VAC_UVLOZ

V

VAC_UVLOZ_HYS

V

VAC_PRESENT

V

VAC_PRESENT_HYS

V

SLEEP

V

SLEEPZ

V

VAC_OV_RISE

< V

VAC

< V

VAC_OV

and V

VAC

> V

BAT

+ V

, TJ= –40°C to 125°C and TJ= 25°C for typical values (unless

SLEEP

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Battery discharge current (BAT,
SW, SYS) in buck mode

Battery discharge current (BAT)
in buck mode

= 4.5 V, V

BAT

leakage between BAT and VBUS,
TJ< 85°C

V

= 4.5 V, HIZ Mode and

BAT

OVPFET_DIS = 1 or No VBUS, I2C
disabled, BATFET Disabled. TJ<

BUS

< V

AC-UVLOZ

,

17 33 µA

V

85°C
V

= 4.5 V, HIZ Mode and
Battery discharge current (BAT,
SW, SYS)

BAT

OVPFET_DIS = 1 or No VBUS, I2C
Disabled, BATFET Enabled. TJ<

58 85 µA

85°C

Input supply current (VBUS) in
buck mode

Input supply current (VBUS) in
buck mode

Input supply current (VBUS) in
buck mode

Input supply current (VBUS) in
buck mode

Battery Discharge Current in
boost mode

VBUS operating range V
VBUS for active I2C, no battery

Sense VAC pin voltage
I2C active hysteresis VACfalling from above V
One of the conditions to turn on

REGN
One of the conditions to turn on

REGN
Sleep mode falling threshold

Sleep mode rising threshold
VAC 6.5-V Overvoltage rising

threshold

V

= 5 V, High-Z Mode and

VBUS

OVPFET_DIS = 1, No battery
V

= 12 V, High-Z Mode and

VBUS

OVPFET_DIS = 1, No battery
V

= 12 V, V

VBUS

converter not switching
V

> VUVLO, V

VBUS

converter switching, VBAT = 3.8V,

VBUS

> V

VBUS

VBAT

> V

,

VBAT

,

37 50 µA

68 90 µA

1.5 3 mA

3 mA

ISYS = 0A
V

= 4.2 V, boost mode, I

BAT

A, converter switching

rising 3.9 13.5 V

VBUS

V

rising 3.3 3.6

VAC

VAC_UVLOZ

V

rising 3.65 3.9

VAC

V

falling 500

VAC

(V

VAC–VVBAT

≤ V

REG

(V

VAC–VVBAT

≤ V

REG

), V

, VAC falling

, VAC rising

BUSMIN_FALL

), V

BUSMIN_FALL

VBUS

≤ V

≤ V

= 0

BAT

BAT

3 mA

300 mV

15 60 110 mV

115 220 340 mV

VAC rising; OVP (REG06[7:6]) = '01' 6.1 6.4 6.7 V

5 µA

V

V

mV

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SLUSCK5 –MARCH 2017

Electrical Characteristics (continued)

V

VAC_UVLOZ

otherwise noted)

V

VAC_OV_RISE

V

VAC_OV_RISE

V

VAC_OV_HYS

V

VAC_OV_HYS

V

VAC_OV_HYS

V

BAT_UVLOZ

V

BAT_DPL_FALL

V

BAT_DPL_RISE

V

BAT_DPL_HYST

V

BUSMIN_FALL

V

BUSMIN_HYST

I

BADSRC

POWER-PATH

V

SYS_MIN

V

SYS

V

SYS_MAX

R

ON(RBFET)

R

ON(HSFET)

R

ON(LSFET)

V

FWD

R

ON(BAT-SYS)

R

ON(BAT-SYS)

BATTERY CHARGER

V

BATREG_RANGE

V

BATREG_STEP

V

BATREG

V

BATREG_ACC

< V

VAC

< V

VAC_OV

and V

VAC

> V

BAT

+ V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VAC 10.5-V Overvoltage rising
threshold

VAC 14-V Overvoltage rising
threshold

VAC 6.5-V Overvoltage
hysteresis

VAC 10.5-V Overvoltage
hysteresis

VAC 14-V Overvoltage hysteresis
BAT for active I2C, no adapter V

Battery Depletion Threshold V
Battery Depletion Threshold V
Battery Depletion rising

hysteresis
Bad adapter detection falling

threshold
Bad adapter detection hysteresis 80 mV
Bad adapter detection current

source

System regulation voltage

System Regulation Voltage

Maximum DC system voltage
output

Top reverse blocking MOSFET
on-resistance between VBUS and
PMID - Q1

Top switching MOSFET on­resistance between PMID and
SW - Q2

Bottom switching MOSFET on­resistance between SW and GND

- Q3
BATFET forward voltage in

supplement mode
SYS-BAT MOSFET on-resistance

SYS-BAT MOSFET on-resistance

Charge voltage program range 3.856 4.624 V
Charge voltage step 32 mV

Charge voltage setting

Charge voltage setting accuracy

, TJ= –40°C to 125°C and TJ= 25°C for typical values (unless

SLEEP

VAC rising, OVP (REG06[7:6]) = '10' 10.35 10.9 11.5 V

VAC rising, OVP (REG06[7:6]) = '11' 13.5 14.2 14.85 V
VAC falling, OVP (REG06[7:6]) =

'01'
VAC falling, OVP (REG06[7:6]) =

'10'
VAC falling, OVP (REG06[7:6]) =

'11'

rising 2.5 V

BAT

falling 2.2 2.6 V

BAT

rising 2.35 2.8 V

BAT

V

rising 180 mV

BAT

V

falling 3.75 3.9 4.0 V

BUS

320 mV

250 mV

300 mV

Sink current from VBUS to GND 30 mA

V

< SYS_MIN[2:0] = 101,

VBAT

BATFET Disabled (REG07[5] = 1)
I

= 0 A, V

SYS

= 4.400 V, BATFET disabled

VBAT

> V

SYSMIN

, V

VBAT

(REG07[5] = 1)
I

= 0 A, , Q4 off, V

SYS

V

> V

VBAT

SYSMIN

= 3.5V

VBAT

≤ 4.400 V,

3.5 3.68 V

V

+

BAT

50 mV

4.4 4.45 4.48 V

-40°C≤ TA≤ 125°C 45 mΩ

V

= 5 V , -40°C≤ TA≤ 125°C 62 mΩ

REGN

V

= 5 V , -40°C≤ TA≤ 125°C 71 mΩ

REGN

30 mV

QFN package, Measured from BAT
to SYS, V

= 4.2V, TJ= 25°C

BAT

19.5 24 mΩ

QFN package, Measured from BAT
to SYS, V
125°C

VREG (REG04[7:3]) = 4.208 V
(01011), V, –40 ≤ TJ≤ 85°C

VREG (REG04[7:3]) = 4.352 V
(01111), V, –40 ≤ TJ≤ 85°C

V

= 4.208 V or V

BAT

–40 ≤ TJ≤ 85°C

= 4.2V, TJ= –40 -

BAT

BAT

= 4.352 V,

19.5 30 mΩ

4.187 4.208 4.229 V

4.330 4.352 4.374 V

–0.5% 0.5%

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Electrical Characteristics (continued)

V

VAC_UVLOZ

otherwise noted)

I

CHG_REG_RANGE

I

CHG_REG_STEP

I

CHG_REG

I

CHG_REG_ACC

I

CHG_REG

I

CHG_REG

I

CHG_REG

I

CHG_REG_ACC

V

BATLOWV_FALL

V

BATLOWV_RISE

I

PRECHG

I

PRECHG_ACC

I

TERM

I

TERM_ACC

I

TERM

I

TERM_ACC

I

TERM

I

TERM_ACC

V

SHORT

V

SHORTZ

I

SHORT

V

RECHG

V

RECHG

I

SYSLOAD

INPUT VOLTAGE AND CURRENT REGULATION

V

INDPM

V

INDPM_ACC

V

INDPM

V

INDPM_ACC

V

DPM_VBAT

V

DPM_VBAT_ACC

< V

VAC

< V

VAC_OV

and V

VAC

> V

BAT

+ V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Charge current regulation range 0 3000 mA
Charge current regulation step 60 mA

Charge current regulation setting
Charge current regulation

accuracy
Charge current regulation setting I

Charge current regulation
accuracy

Charge current regulation setting
Charge current regulation

accuracy
Battery LOWV falling threshold I
Battery LOWV rising threshold Pre-charge to fast charge 3.0 3.12 3.24 V
Precharge current regulation IPRECHG[3:0] = '0010' = 180 mA 153 171 189 mA
Precharge current regulation

accuracy
Termination current regulation I

Termination current regulation
accuracy

Termination current regulation
Termination current regulation

accuracy
Termination current regulation I

Termination current regulation
accuracy

Battery short voltage V
Battery short voltage V
Battery short current V
Recharge Threshold below

V

BAT_REG

Recharge Threshold below
V

BAT_REG

System discharge load current V

Input voltage regulation limit V
Input voltage regulation accuracy –3% 5%
Input voltage regulation limit V
Input voltage regulation accuracy –3% 3%
Input voltage regulation limit

tracking VBAT

Input voltage regulation accuracy
tracking VBAT

SLUSCK5 –MARCH 2017

, TJ= –40°C to 125°C and TJ= 25°C for typical values (unless

SLEEP

I

= 240 mA, V

CHG

V

= 3.8 V

VBAT

I

= 240 mA, V

CHG

V

= 3.8 V

VBAT

= 720 mA, V

CHG

V

= 3.8 V

VBAT

I

CHG_REG

V
I

CHG

V
I

CHG

V

CHG

= 720 mA, V

= 3.8 V

BAT

= 1.38 A, V

= 3.8 V

VBAT

= 720 mA or I

= 3.1 V or V

VBAT

= 240 mA 2.7 2.8 2.9 V

VBAT

VBAT

VBAT

VBAT

CHG
VBAT

= 3.1V or

= 3.1 V or

= 3.1 V or

= 3.1 V or

BAT

= 3.1 V or

= 1.38 A,

= 3.8 V

0.216 0.24 0.264 A

–10% 10%

0.685 0.720 0.755 A

-5% 5%

1.311 1.380 1.449 A

–5% 5%

IPRECHG[3:0] = '0010' = 180 mA –15 5 %

> 780 mA, ITERM[3:0] = '0010'

CHG

= 180 mA, V
I

> 780 mA, , ITERM[3:0] =

CHG

'0010' = 180 mA, V
I

≤ 780 mA, , ITERM[3:0] =

CHG

'0010' = 180 mA
I

≤ 780 mA, , ITERM[3:0] =

CHG

'0010' = 180 mA

= 600 mA, ITERM[3:0] = '0000'

CHG

= 60 mA, V
I

= 600 mA, ITERM[3:0] = '0000'

CHG

= 60 mA, V

falling 1.85 2 2.15 V

VBAT

rising 2.15 2.25 2.35 V

VBAT

< V

VBAT

V

falling, REG04[0] = 0 90 120 150 mV

BAT

V

falling, REG04[0] = 1 200 230 265 mV

BAT

= 4.2 V 30 mA

SYS

(REG06[3:0] = 0000) = 3.9 V 3.78 3.95 4.1 V

INDPM

(REG06[3:0] = 0110) = 4.4 V 4.268 4.4 4.532 V

INDPM

VBAT

VBAT

VBAT

SHORTZ

= 4.208 V

VBAT

= 4.208 V

= 4.208 V

= 4.208 V

VINDPM = 3.9V,

150 180 216 mA

-16.7% 20%

162 180 192 mA

-10% 10%
45 60 75 mA

–25% 25%

70 90 110 mA

4.171 4.3 4.43 V
VDPM_VBAT_TRACK = 300mV,
VBAT = 4.0V

–3% 3%

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9

bq25601

SLUSCK5 –MARCH 2017

Electrical Characteristics (continued)

V

VAC_UVLOZ

otherwise noted)

I

INDPM

I

IN_START

BAT PIN OVERVOLTAGE PROTECTION

V

BATOVP_RISE

V

BATOVP_FALL

THERMAL REGULATION AND THERMAL SHUTDOWN

T

JUNCTION_REG

T

JUNCTION_REG

T

SHUT

T

SHUT_HYST

JEITA Thermistor Comparator (BUCK MODE)

V

T1

V

T1

V

T2

V

T2

V

T3

V

T3

V

T5

V

T5

COLD OR HOT THERMISTER COMPARATOR (BOOST MODE)

V

BCOLD

V

BCOLD

V

BHOT

V

BHOT

< V

VAC

< V

VAC_OV

and V

VAC

> V

BAT

+ V

, TJ= –40°C to 125°C and TJ= 25°C for typical values (unless

SLEEP

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

VBUS

SW, I
500 mA, –40 ≤ TJ≤ 85°C

V

USB input current regulation limit

VBUS

SW, IINDPM (REG[4:0] = 01000) =
900 mA, –40 ≤ TJ≤ 85°C

V

VBUS

SW, IINDPM (REG[4:0] = 01110) =

1.5 A, –40 ≤ TJ≤ 85°C

Input current limit during system
start-up sequence

V

Battery overvoltage threshold

Battery overvoltage threshold

Junction Temperature Regulation
Threshold

Junction Temperature Regulation
Threshold

Thermal Shutdown Rising
Temperature

BAT

V

BAT_REG

V

BAT

V

BAT_REG

Temperature Increasing, TREG
(REG05[1] = 1) = 110℃

Temperature Increasing, TREG
(REG05[1] = 0) = 90℃

Temperature Increasing 160 °C

Thermal Shutdown Hysteresis 30 °C

T1 (0°C) threshold, Charge
suspended T1 below this
temperature.

Charger suspends charge. As
Percentage to V

Falling As Percentage to V
T2 (10°C) threshold, Charge back

to I

/2 and 4.2 V below this

CHG

temperature

As percentage of V

Falling As Percentage to V
T3 (45°C) threshold, charge back

to ICHG and 4.05V above this
temperature.

Charger suspends charge. As
Percentage to V

Falling As Percentage to V
T5 (60°C) threshold, charge

suspended above this

As Percentage to V

temperature.
Falling As Percentage to V

Cold Temperature Threshold, TS
pin Voltage Rising Threshold

As Percentage to V

-20°C w/ 103AT), TJ= –20°C ­125°C

Falling TJ= –20°C - 125°C 78.5% 79% 79.5%
Hot Temperature Threshold, TS

pin Voltage falling Threshold

As Percentage to V
60°C w/ 103AT), TJ= –20°C - 125°C

Rising TJ= –20°C - 125°C 33.8% 34.4% 34.9%

= 5 V, current pulled from

(REG[4:0] = 00100) =

INDPM

= 5 V, current pulled from

= 5 V, current pulled from

rising, as percentage of

falling, as percentage of

REGN

REGN

REGN

REGN

REGN

REGN

REGN

REGN

(Approx.

REGN

(Approx.

REGN

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450 500 mA

750 900 mA

1.3 1.5 A

200 mA

103 104 105 %

101 102 103 %

110 °C

90 °C

72.4% 73.3% 74.2%

69% 71.5% 74%

67.2% 68% 69%

66% 66.8% 67.7%

43.8% 44.7% 45.8%

45.1% 45.7% 46.2%

33.7% 34.2% 35.1%

34.5% 35.3% 36.2%

79.5% 80% 80.5%

30.2% 31.2% 32.2%

10

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Electrical Characteristics (continued)

V

VAC_UVLOZ

otherwise noted)

CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE)

I

HSFET_OCP

I

BATFET_OCP

CHARGE UNDER-CURRENT COMPARATOR (CYCLE-BY-CYCLE)

V

LSFET_UCP

PWM

f

SW

D

MAX

BOOST MODE OPERATION

V

OTG_REG

V

OTG_REG_ACC

V

BATLOWV_OTG

I

OTG

I

OTG_OCP_ACC

V

OTG_OVP

I

OTG_HSZCP

REGN LDO

V

REGN

V

REGN

LOGIC I/O PIN CHARACTERISTICS (CE, PSEL, SCL, SDA,, INT)

V

ILO

V

IH

I

BIAS

V

ILO

V

IH

I

BIAS

LOGIC I/O PIN CHARACTERISTICS (PG, STAT)

V

OL

(1) Specified by design. Not production tested.

< V

VAC

< V

VAC_OV

and V

VAC

> V

BAT

+ V

, TJ= –40°C to 125°C and TJ= 25°C for typical values (unless

SLEEP

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

HSFET cycle-by-cycle over­current threshold

System over load threshold 6.0 A

LSFET under-current falling
threshold

PWM switching frequency

Maximum PWM duty cycle

(1)

Boost mode regulation voltage
Boost mode regulation voltage

accuracy

Battery voltage exiting boost
mode

From sync mode to non-sync mode 160 mA

Oscillator frequency, buck mode 1320 1500 1680 kHz
Oscillator frequency, boost mode 1150 1412 1660 kHz

V

= 3.8 V, I

VBAT

BOOSTV[1:0] = '10' = 5.15 V
V

= 3.8 V, I

VBAT

BOOSTV[1:0] = '10' = 5.15 V
V

falling, MIN_V

VBAT

(REG01[0]) = 0
V

rising, MIN_V

VBAT

(REG01[0]) = 0
V

falling, MIN_V

VBAT

(REG01[0]) = 1
V

rising, MIN_V

VBAT

(REG01[0]) = 1

OTG mode output current BOOST_LIM (REG02[7]) = 1 1.2 1.4 1.6 A
Boost mode RBFET over-current

protection accuracy

BOOST_LIM = 0.5 A (REG02[7] = 0) 0.5 0.722 A

OTG overvoltage threshold Rising threshold 5.55 5.8 6.15 V
HSFET under current falling

threshold

REGN LDO output voltage V
REGN LDO output voltage V

VBUS
VBUS

= 9V, I
= 5V, I

Input low threshold CE 0.4 V
Input high threshold CE 1.3 V
High-level leakage current CE Pull up rail 1.8 V 1 µA
Input low threshold PSEL 0.4 V
Input high threshold PSEL 1.3 V
High-level leakage current PSEL Pull up rail 1.8V 1 µA

Low-level output voltage 0.4 V

SLUSCK5 –MARCH 2017

5.2 8.0 A

97%

= 0 A,

(PMID)

(PMID)

= 0 A,

BAT

BAT

BAT

BAT

_SEL

_SEL

_SEL

_SEL

4.972 5.126 5.280 V

-3 3 %

2.6 2.8 2.9 V

2.9 3.0 3.15 V

2.4 2.5 2.6 V

2.7 2.8 2.9 V

100 mA

= 40mA 5.6 6 6.55 V

REGN

= 20mA 4.6 4.7 4.8 V

REGN

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Junction Temperature (°C)

SYSMIN Voltage (V)

-40 -25 -10 5 20 35 50 65 80 95 110 125

3.5

3.55

3.6

3.65

3.7

3.75

3.8

3.85

D001

Junction Temperature (°C)

BATREG Charge Voltage (V)

-40 -25 -10 5 20 35 50 65 80 95 110 125

4

4.1

4.2

4.3

4.4

4.5

D001

V

BATREG

= 4.208 V

V

BATREG

= 4.352 V

Output Current (A)

OTG Output Voltage (V)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

0

1

2

3

4

5

6

D001

Charge Current (A)

Charge Current Accuracy (%)

0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3

-8

-6

-4

-2

0

2

4

6

D001

Charge Current (A)

Charge Efficiency (%)

0 0.5 1 1.5 2 2.5 3

60

65

70

75

80

85

90

95

100

D001

VBUS Voltage

5 V
9 V
12 V

OTG Current (A)

Efficiency (%)

0.2 0.4 0.6 0.8 1 1.2 1.4

65

70

75

80

85

90

95

100

D001

V

BAT

= 3.2 V

V

BAT

= 3.8 V

V

BAT

= 4.1 V

bq25601

SLUSCK5 –MARCH 2017

7.6 Typical Characteristics

fSW= 1.5 MHz inductor DCR = 18 mΩ
V

=3.8V

BAT

Figure 1. Charge Efficiency vs. Charge Current

V

= 5.15 V inductor DCR = 18 mΩ

OTG

Figure 2. Efficiency vs. OTG Current

www.ti.com

I

= 1.2 A V

OTG

V

= 3.8 V

VBAT

Figure 3. OTG Output Voltage vs. Output Current Figure 4. Charge Current Accuracy

12

Figure 5. SYSMIN Voltage vs. Junction Temperature Figure 6. BATREG Charge Voltage vs. Junction

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OTG

= 5.15 V

Temperature

Product Folder Links: bq25601

Junction Temperature (°C)

Charge Current (A)

55 65 75 85 95 105 115 125 135

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

2.25

D001

110 °C
90 °C

Junction Temperature (°C)

Input Current Limit (A)

-40 -25 -10 5 20 35 50 65 80 95

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

2.25

2.5

D001

IINDPM = 0.5 A
IINDPM = 0.9 A
IINDPM = 1.5 A

Junction Temperature (°C)

Charge Current (A)

-40 -25 -10 5 20 35 50 65 80 95 110 125

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

D001

I

CHG

= 0.24 A

I

CHG

= 0.72 A

I

CHG

= 1.38 A

bq25601

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Typical Characteristics (continued)

Figure 7. Input Current Limit vs. Junction Temperature Figure 8. Charge Current vs. Junction Temperature

SLUSCK5 –MARCH 2017

Figure 9. Charge Current vs. Junction Temperature

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bq25601

SLUSCK5 –MARCH 2017

www.ti.com

8 Detailed Description

8.1 Overview

The bq25601 device is a highly integrated 3.0-A switch-mode battery charger for single cell Li-Ion and Li-polymer
battery. It includes the input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2), low-side
switching FET (LSFET, Q3), and battery FET (BATFET, Q4), and bootstrap diode for the high-side gate drive.

14

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TS

Battery

Sensing

Thermistor

I2C

Interface

USB

Adapter

+

±

+

±

FBO

PGND

REGN

RBFET (Q1)

VBUS

LSFET (Q3)

HSFET (Q2)

SW

BATFET

(Q4)

SYS

BAT

I

CHG

VBUS_OVP_BOOST

/QON

Q1 Gate

Control

REGN

PMID

+

±

+

±

+

±

Q3_OCP_BOOST

Q2_UCP_BOOST

I

Q3

I

Q2

V

VBUS

V

OTG_OVP

V

OTG_HSZCP

V

OTG_BAT

I

LSFET_UCP

I

Q3

104% × V

BAT_REG

BAT

+

±

+

±

UCP

BATOVP

CONVERTER

Control

+

±

+

±

I

CHG_REG

V

BAT_REG

BAT

V

SYSMIN

+

±

+

±

+

±

+

±

I

INDPM

IC T

J

T

REG

V

INDPM

SYS

REGN

LDO

EN_HIZ

UVLO

SLEEP

ACOV

+

±

V

VBUS_UVLOZ

V

BAT

+ V

SLEEP

V

VAC_OV

BTST

REFRESH

Q2_OCP

V

BTST_REFRESH

V

BTST

- V

SW

I

HSFET_OCP

I

Q2

EN_CHARGE

EN_BOOST

EN_HIZ

Q4 Gate

Control

V

QON

+

±

+

±

+

±

+

±

+

±

+

±

+

±

/CESDASCL

Input

Source

Detection

REF
DAC

I

CHG_REG

V

BAT_REG

STAT /

IMON

/PG

INT

PSEL

CHARGE

CONTROL

STATE

MACHINE

Converter

Control State

Machine

BATLOWV

SUSPEND

RECHRG

TERMINATION

BATSHORT

TSHUT

BAD_SRC

BAT_GD

T

SHUT

IC T

J

BAT

V

BATLOWV

BAT

I

BADSRC

I

DC

V

BATGD

BAT

I

TERM

I

CHG

BAT

V

SHORT

V

REG

-V

RECHG

I

CHG

bq25601

V

VBUS

I

IN

I

IN

+

±

V

VBUS

+

±

V

VBUS

V

VBUS

EN_REGN

Copyright © 2017, Texas Instruments Incorporated

bq25601

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8.2 Functional Block Diagram

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15

bq25601

SLUSCK5 –MARCH 2017

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8.3 Feature Description

8.3.1 Power-On-Reset (POR)

The device powers internal bias circuits from the higher voltage of VBUS and BAT. When VBUS rises above
V

VBUS_UVLOZ

driver are active. I2C interface is ready for communication and all the registers are reset to default value. The
host can access all the registers after POR.

8.3.2 Device Power Up from Battery without Input Source

If only battery is present and the voltage is above depletion threshold (V
connects battery to system. The REGN stays off to minimize the quiescent current. The low RDSON of BATFET
and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time.

The device always monitors the discharge current through BATFET (Supplement Mode). When the system is
overloaded or shorted (I
indicate BATFET is disabled until the input source plugs in again or one of the methods described in BATFET
Enable (Exit Shipping Mode) is applied to re-enable BATFET.

8.3.3 Power Up from Input Source

When an input source is plugged in, the device checks the input source voltage to turn on REGN LDO and all the
bias circuits. It detects and sets the input current limit before the buck converter is started. The power up
sequence from input source is as listed:

1. Power Up REGN LDO

2. Poor Source Qualification

3. Input Source Type Detection is based on or PSEL to set default input current limit (IINDPM) register or input
source type.

4. Input Voltage Limit Threshold Setting (VINDPM threshold)

5. Converter Power-up

or BAT rises above V

> I

BAT

BATFET_OCP

BAT_UVLOZ

, the sleep comparator, battery depletion comparator and BATFET

BAT_DPL_RISE)

, the BATFET turns on and

), the device turns off BATFET immediately and set BATFET_DIS bit to

8.3.3.1 Power Up REGN Regulation

The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. The REGN also
provides bias rail to TS external resistors. The pull-up rail of STAT can be connected to REGN as well. The
REGN is enabled when all the below conditions are valid:

• V

• V

VAC
VAC

above V
above V

VAC_PRESENT

+ V

BAT

SLEEPZ

in buck mode or VBUS below V

BAT

+ V

in boost mode

SLEEP

• After 220-ms delay is completed
If any one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off.

The device draws less than IVBUS_HIZ from VBUS during HIZ state. The battery powers up the system when
the device is in HIZ.

8.3.3.2 Poor Source Qualification

After REGN LDO powers up, the device confirms the current capability of the input source. The input source
must meet both of the following requirements in order to start the buck converter.

• VBUS voltage below V

• VBUS voltage above V

VAC_OV

VBUSMIN

when pulling I

BADSRC

(typical 30 mA)

Once the input source passes all the conditions above, the status register bit VBUS_GD is set high and the INT
pin is pulsed to signal to the host. If the device fails the poor source detection, it repeats poor source qualification
every 2 seconds.

8.3.3.3 Input Source Type Detection

After the VBUS_GD bit is set and REGN LDO is powered, the device runs input source detection through or the
PSEL pin. The bq25601 sets input current limit through PSEL pins.

16

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SLUSCK5 –MARCH 2017

Feature Description (continued)

After input source type detection is completed, an INT pulse is asserted to the host. in addition, the following
registers and pin are changed:

1. Input Current Limit (IINDPM) register is changed to set current limit

2. PG_STAT bit is set

3. VBUS_STAT bit is updated to indicate USB or other input source

The host can over-write IINDPM register to change the input current limit if needed. The charger input current is
always limited by the IINDPM register.

8.3.3.3.1 PSEL Pins Sets Input Current Limit in bq25601

The bq25601 has PSEL pin for input current limit setting to interface with USB PHY. It directly takes the USB
PHY device output to decide whether the input is USB host or charging port. When the device operates in host­control mode, the host needs to IINDET_EN bit to read the PSEL value and update the IINDPM register. When
the device is in default mode, PSEL value updates IINDPM in real time.

Table 1. Input Current Limit Setting from PSEL

Input Detection PSEL Pin

USB SDP High 500 mA 001

Adapter Low 2.4A 011

INPUT CURRENT LIMIT

(ILIM)

VBUS_STAT

8.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)

The device supports wide range of input voltage limit (3.9 V – 5.4V) for USBThe device's VINDPM is set at 4.5V.
The device supports dynamic VINDPM trackingsettings which tracks the battery voltage. This function can be
enabled via the VDPM_BAT_TRACK[1:0] register bits. When enabled, the actual input voltage limit will be the
higher of the VINDPM register and VBAT + VDPM_BAT_TRACK offset.

8.3.3.5 Converter Power-Up

After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery
charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery.

The device provides soft-start when system rail is ramped up. When the system rail is below 2.2 V, the input
current is limited to is to the lower of 200 mA or IINDPM register setting. After the system rises above 2.2 V, the
device limits input current to the value set by IINDPM register.

As a battery charger, the device deploys a highly efficient 1.5 MHz step-down switching regulator. The fixed
frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery
voltage, charge current and temperature, simplifying output filter design.

The device switches to PFM control at light load or when battery is below minimum system voltage setting or
charging is disabled. The PFM_DIS bit can be used to prevent PFM operation in either buck or boost
configuration.

8.3.4 Boost Mode Operation From Battery

The device supports boost converter operation to deliver power from the battery to other portable devices
through USB port. The boost mode output current rating meets the USB On-The-Go 500 mA output requirement.
The maximum output current is up to 1.2 A. The boost operation can be enabled if the conditions are valid:

1. BAT above V

2. VBUS less than BAT+V

OTG_BAT

(in sleep mode)

SLEEP

3. Boost mode operation is enabled (OTG_CONFIG bit = 1)

4. Voltage at TS (thermistor) pin is within acceptable range (V

BHOT

< VTS< V

BCOLD

)

5. After 30-ms delay from boost mode enable

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17

POR

watchdog timer expired

Reset registers

I2C interface enabled

Y

N

Y

N

Y

NY

N

Default Mode

Reset watchdog timer

Reset selective registers

Host Mode

Start watchdog timer

Host programs registers

WD_RST bit = 1?

I2C Write?

I2C Write?

Watchdog Timer

Expired?

bq25601

SLUSCK5 –MARCH 2017

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During boost mode, the status register VBUS_STAT bits is set to 111, the VBUS output is 5.15 V and the output
current can reach up to 1.2 A, selected through I2C (BOOST_LIM bit). The boost output is maintained when BAT
is above V

OTG_BAT

threshold.

When OTG is enabled, the device starts up with PFM and later transits to PWM to minimize the overshoot. The
PFM_DIS bit can be used to prevent PFM operation in either buck or boost configuration.

8.3.5 Host Mode and Standalone Power Management

8.3.5.1 Host Mode and Default Mode in bq25601

The bq25601 is a host controlled charger, but it can operate in default mode without host management. in default
mode, the device can be used as an autonomous charger with no host or while host is in sleep mode. When the
charger is in default mode, WATCHDOG_FAULT bit is HIGH. When the charger is in host mode,
WATCHDOG_FAULT bit is LOW.

After power-on-reset, the device starts in default mode with watchdog timer expired, or default mode. All the
registers are in the default settings. During default mode, any change on PSEL pin will make real time IINDPM
register changes.

in default mode, the device keeps charging the battery with default 10-hour fast charging safety timer. At the end
of the 10-hour, the charging is stopped and the buck converter continues to operate to supply system load.

Writing a 1 to the WD_RST bit transitions the charger from default mode to host mode. All the device parameters
can be programmed by the host. To keep the device in host mode, the host has to reset the watchdog timer by
writing 1 to WD_RST bit before the watchdog timer expires (WATCHDOG_FAULT bit is set), or disable watchdog
timer by setting WATCHDOG bits = 00.

When the watchdog timer expires (WATCHDOG_FAULT bit = 1), the device returns to default mode and all
registers are reset to default values except IINDPM, VINDPM, BATFET_RST_EN, BATFET_DLY, and
BATFET_DIS bits.

8.3.6 Power Path Management

The device accommodates a wide range of input sources from USB, wall adapter, to car charger. The device
provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or
both.

8.3.7 Battery Charging Management

The device charges 1-cell Li-Ion battery with up to 3.0-A charge current for high capacity tablet battery. The 19.5­mΩ BATFET improves charging efficiency and minimize the voltage drop during discharging.

18

Figure 10. Watchdog Timer Flow Chart

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