Texas Instruments q25601 Service Manual

Download

Page 1

VBUS SW

BTST

SYS BAT

I2C Bus

USB

QON

REGN

CHG

Host

Host Control

Optional

Product Folder

Order Now

Technical Documents

Tools & Software

Support & Community

bq25601

SLUSCK5 –MARCH 2017

bq25601 I2C Controlled 3-A Single-Cell Battery Charger

for High Input Voltage and Narrow Voltage DC (NVDC) Power Path Management

1 Features

• High-Efficiency, 1.5-MHz, Synchronous SwitchMode Buck Charger

– 92% Charge Efficiency at 2 A from 5-V Input – Optimized for USB Voltage Input (5 V) – Selectable Low Power Pulse Frequency

Modulation (PFM) Mode for Light Load Operations

• Supports USB On-The-Go (OTG) – Boost Converter With Up to 1.2-A Output – 92% Boost Efficiency at 1-A Output – Accurate Constant Current (CC) Limit – Soft-Start Up To 500-µF Capacitive Load – Output Short Circuit Protection – Selectable Low Power PFM Mode for Light

Load Operations

• Single Input to Support USB Input and High Voltage Adapters

– Support 3.9-V to 13.5-V Input Voltage Range

With 22-V Absolute Maximum Input Voltage Rating

– Programmable Input Current Limit (100 mA to

3.2 A With 100-mA Resolution) to Support USB 2.0, USB 3.0 Standards and High Voltage Adaptors (IINDPM)

– Maximum Power Tracking by Input Voltage

Limit Up to 5.4 V (VINDPM)

– VINDPM Threshold Automatically Tracks

Battery Voltage

– Auto Detect USB SDP, DCP and Non-

Standard Adaptors

• High Battery Discharge Efficiency With 19.5-mΩ Battery Discharge MOSFET

• Narrow VDC (NVDC) Power Path Management – Instant-On Works with No Battery or Deeply

Discharged Battery

– Ideal Diode Operation in Battery Supplement

Mode

• BATFET Control to Support Ship Mode, Wake Up and Full System Reset

• Flexible Autonomous and I2C Mode for Optimal

System Performance

• High Integration Includes All MOSFETs, Current Sensing and Loop Compensation

• High Accuracy – ±0.5% Charge Voltage Regulation – ±5% at 1.5-A Charge Current Regulation

• Create a Custom Design Using the bq25601 With the WEBENCH®Power Designer

2 Applications

• Smart Phones

• Portable Internet Devices and Accessory

3 Description

The bq25601 device is a highly-integrated 3-A switchmode battery charge management and system power path management device for single cell Li-Ion and Lipolymer battery. The low impedance power path optimizes switch-mode operation efficiency, reduces battery charging time and extends battery life during discharging phase. The I2C serial interface with charging and system settings makes the device a truly flexible solution.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)

bq25601 WQFN (24) 4.00 mm × 4.00 mm (1) For all available packages, see the orderable addendum at

the end of the data sheet.

Simplified Application

(1)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

Page 2

bq25601

SLUSCK5 –MARCH 2017

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Description (continued)......................................... 3

6 Pin Configuration and Functions......................... 4

7 Specifications......................................................... 6

7.1 Absolute Maximum Ratings ...................................... 6

7.2 ESD Ratings.............................................................. 6

7.3 Recommended Operating Conditions....................... 6

7.4 Thermal information .................................................. 7

7.5 Electrical Characteristics........................................... 7

7.6 Typical Characteristics............................................ 12

8 Detailed Description............................................ 14

8.1 Overview ................................................................. 14

8.2 Functional Block Diagram ....................................... 15

4 Revision History

DATE REVISION NOTES

March 2017 * Initial release.

www.ti.com

8.3 Feature Description................................................. 16

8.4 Register Maps......................................................... 31

9 Application and Implementation ........................ 42

9.1 Application information............................................ 42

9.2 Typical Application Diagram .................................. 43

10 Power Supply Recommendations ..................... 45

11 Layout................................................................... 46

11.1 Layout Guidelines ................................................. 46

11.2 Layout Example .................................................... 46

12 Device and Documentation Support ................. 48

12.1 Documentation Support ....................................... 48

12.2 Community Resources.......................................... 48

12.3 Trademarks........................................................... 48

12.4 Electrostatic Discharge Caution............................ 48

12.5 Glossary................................................................ 48

13 Mechanical, Packaging, and Orderable

Information........................................................... 49

Product Folder Links: bq25601

Page 3

bq25601

www.ti.com

SLUSCK5 –MARCH 2017

5 Description (continued)

The bq25601 is a highly-integrated 3.0-A switch-mode battery charge management and system power path management device for single cell Li-Ion and Li-polymer battery. It features fast charging with high input voltage support for a wide range of smart phones, tablets and portable devices. Its low impedance power path optimizes switch-mode operation efficiency, reduces battery charging time and extends battery life during discharging phase. Its input voltage and current regulation deliver maximum charging power to battery. The solution is highly integrated with input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2), low-side switching FET (LSFET, Q3), and battery FET (BATFET, Q4) between system and battery. It also integrates the bootstrap diode for the high-side gate drive for simplified system design. The I2C serial interface with charging and system settings makes the device a truly flexible solution.

The device supports a wide range of input sources, including standard USB host port, USB charging port, and USB compliant high voltage adapter. The device sets default input current limit based on the built-in USB interface. To set the default input current limit, the device takes the result from detection circuit in the system, such as USB PHY device. The device is compliant with USB 2.0 and USB 3.0 power spec with input current and voltage regulation. The device also meets USB On-the-Go (OTG) operation power rating specification by supplying 5.15 V on VBUS with constant current limit up to 1.2A.

The power path management regulates the system slightly above battery voltage but does not drop below 3.5 V minimum system voltage (programmable). With this feature, the system maintains operation even when the battery is completely depleted or removed. When the input current limit or voltage limit is reached, the power path management automatically reduces the charge current to zero. As the system load continues to increase, the power path discharges the battery until the system power requirement is met. This Supplement Mode prevents overloading the input source.

The device initiates and completes a charging cycle without software control. It senses the battery voltage and charges the battery in three phases: pre-conditioning, constant current and constant voltage. At the end of the charging cycle, the charger automatically terminates when the charge current is below a preset limit and the battery voltage is higher than recharge threshold. If the fully charged battery falls below the recharge threshold, the charger automatically starts another charging cycle.

The charger provides various safety features for battery charging and system operations, including battery negative temperature coefficient thermistor monitoring, charging safety timer and overvoltage and overcurrent protections. The thermal regulation reduces charge current when the junction temperature exceeds 110°C (programmable). The STAT output reports the charging status and any fault conditions. Other safety features include battery temperature sensing for charge and boost mode, thermal regulation and thermal shutdown and input UVLO and overvoltage protection. The VBUS_GD bit indicates if a good power source is present. The INT output Immediately notifies host when fault occurs.

The device also provides QON pin for BATFET enable and reset control to exit low power ship mode or full system reset function.

The device is available in 24-pin, 4 mm × 4 mm x 0.75 mm thin WQFN package.

Product Folder Links: bq25601

Page 4

18 GND 17 GND 16 SYS 15 14 BAT 13

SYS

BAT

(Not to scale)

Thermal

Pad

1VAC 2PSEL 3PG 4STAT 5SCL 6SDA

PMID21REGN20BTST19SW

VBUS

INT

7 8 11 129 10

bq25601

SLUSCK5 –MARCH 2017

6 Pin Configuration and Functions

www.ti.com

RTW Package

24-Pin WQFN

Top View

Pin Functions

NAME NO.

BAT

BTST 21 P CE 9 DI Charge enable pin. When this pin is driven low, battery charging is enabled.

GND

INT 7 DO

PG 3 DO

PMID 23 DO

PSEL 2 DI

QON 12 DI

REGN 22 P

SCL 5 DI SDA 6 DIO

13 14

17 18

(1) AI = Analog input, AO = Analog Output, AIO = Analog input Output, DI = Digital input, DO = Digital Output, DIO = Digital input Output, P

= Power

(1)

TYPE

Battery connection point to the positive terminal of the battery pack. The internal BATFET and current sensing is

connected between SYS and BAT. Connect a 10 µF close to the BAT pin. PWM high side driver positive supply. Internally, the BTST pin is connected to the cathode of the boost-strap

diode. Connect the 0.047-μF bootstrap capacitor from SW to BTST.

— Ground pins.

Open-drain interrupt Output. Connect the INT to a logic rail through 10-kΩ resistor. The INT pin sends an active low, 256-µs pulse to host to report charger device status and fault.

— No Connect. Keep the pins float.

Open drain active low power good indicator. Connect to the pull up rail through 10-kΩ resistor. LOW indicates a good input source if the input voltage is between UVLO and ACOV, above SLEEP mode threshold, and current limit is above 30 mA.

Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET. Put 10 μF ceramic capacitor on PMID to GND.

Power source selection input. Set 500 mA input current limit by pulling this pin high and set 2.4A input current limit by pulling this pin low. Once the device gets into host mode, the host can program different input current limits to IINDPM register.

BATFET enable/reset control input. When BATFET is in ship mode, a logic low of t BATFET to exit shipping mode. When VBUS is not pluggeD–in, a logic low of t resets SYS (system power) by turning BATFET off for t to provide full system power reset. The pin contains an internal pull-up to maintain default high logic.

LSFET driver and internal supply output. Internally, REGN is connected to the anode of the boost-strap diode. Connect a 4.7-μF (10-V rating) ceramic capacitor from REGN to GND. The capacitor should be placed close to the IC.

I2C interface clock. Connect SCL to the logic rail through a 10-kΩ resistor. I2C interface data. Connect SDA to the logic rail through a 10-kΩ resistor.

Product Folder Links: bq25601

DESCRIPTION

BATFET_RST

(minimum 250 ms) and then re-enable BATFET

QON_RST

duration turns on

SHIPMODE

(minimum 8 s) duration

Page 5

bq25601

www.ti.com

Pin Functions (continued)

NAME NO.

STAT 4 DO

SYS

TS 11 AI

VAC 1 AI Charge input voltage sense. This pin must be connected to VBUS pin. VBUS 24 P

Thermal Pad — P

19 20 15 16

(1)

TYPE

Open-drain charge status output. Connect the STAT pin to a logic rail via 10-kΩ resistor. The STAT pin indicates charger status. Collect a current limit resister and a LED from a rail to this pin. Charge in progress: LOW Charge complete or charger in SLEEP mode: HIGH Charge suspend (fault response): 1-Hz, 50% duty cycle Pulses This pin can be disabled via EN_ICHG_MON[1:0] register bits.

P Switching node output. Connected to output inductor. Connect the 0.047-μF bootstrap capacitor from SW to BTST.

Converter output connection point. The internal current sensing network is connected between SYS and BAT.

Connect a 20 µF capacitor close to the SYS pin. Temperature qualification voltage input to support JEITA profile. Connect a negative temperature coefficient

thermistor. Program temperature window with a resistor divider from REGN to TS to GND. Charge suspends when TS pin is out of range. When TS pin is not used, connect a 10-kΩ resistor from REGN to TS and connect a 10-kΩ resistor from TS to GND. It is recommended to use a 103AT-2 thermistor.

Charger input. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID pins. Place a 1-uF ceramic capacitor from VBUS to GND close to device.

Thermal pad and ground reference. This pad is ground reference for the device and it is also the thermal pad used to conduct heat from the device. This pad should be tied externally to a ground plane through PCB vias under the pad.

DESCRIPTION

SLUSCK5 –MARCH 2017

Product Folder Links: bq25601

Page 6

bq25601

SLUSCK5 –MARCH 2017

www.ti.com

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

Voltage Range (with respect to GND)

Output Sink Current STAT 6 mA Voltage Range (with respect to

GND) Voltage Range (with respect to

GND) Output Sink Current INT 6 mA Operating junction temperature, T Storage temperature, T

stg

(1) Stresses beyond those listed under Absolute maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted.

(2) VBUS is specified up to 22 V for a maximum of one hour at room temperature

VAC, VBUS (converter not switching)

BTST, PMID (converter not switching)

SW –2 16 V BTST to SW –0.3 7 V

PSEL –0.3 7 V REGN, TS, CE, PG, BAT, SYS (converter not switching) –0.3 7 V

SDA, SCL, INT, /QON, STAT –0.3 7 V

PGND to GND (QFN package only) –0.3 0.3 V

(1)

MIN MAX UNIT

(2)

–2 22 V

–0.3 22 V

–40 150 °C –65 150 °C

7.2 ESD Ratings

VALUE UNIT

(ESD)

Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins

(1)

Charged device model (CDM), per JEDEC specification JESD22-C101, all

(2)

pins

±2000

±250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT

BUS

SWOP

BATOP

Input voltage 3.9 13.5 Input current (VBUS) 3.25 A Output current (SW) 3.25 A Battery voltage 4.624 V Fast charging current 3.0 A Discharging current (continuous) 6 A Operating ambient temperature –40 85 °C

(1) The inherent switching noise voltage spikes should not exceed the absolute maximum voltage rating on either the BTST or SW pins. A

tight layout minimizes switching noise.

(1)

Product Folder Links: bq25601

Page 7

bq25601

www.ti.com

SLUSCK5 –MARCH 2017

7.4 Thermal information

bq25601

THERMAL METRIC

(1)

UNITRTW (WQFN)

24 PinS

θJA

θJC(top)

θJB

θJC(bot)

Junction-to-ambient thermal resistance 35.6 °C/W Junction-to-case (top) thermal resistance 22.7 °C/W Junction-to-board thermal resistance 11.9 °C/W Junction-to-top characterization parameter 0.2 °C/W Junction-to-board characterization parameter 12 °C/W Junction-to-case (bottom) thermal resistance 2.6 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

7.5 Electrical Characteristics

VAC_UVLOZ

otherwise noted)

QUIESCENT CURRENTS

BAT

VBUS_HIZ

VBUS

BOOST

VBUS, VAC AND BAT PIN POWER-UP

BUS_OP

VAC_UVLOZ

VAC_UVLOZ_HYS

VAC_PRESENT

VAC_PRESENT_HYS

SLEEP

SLEEPZ

VAC_OV_RISE

< V

VAC

< V

VAC_OV

and V

VAC

> V

BAT

+ V

, TJ= –40°C to 125°C and TJ= 25°C for typical values (unless

SLEEP

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Battery discharge current (BAT, SW, SYS) in buck mode

Battery discharge current (BAT) in buck mode

= 4.5 V, V

BAT

leakage between BAT and VBUS, TJ< 85°C

= 4.5 V, HIZ Mode and

BAT

OVPFET_DIS = 1 or No VBUS, I2C disabled, BATFET Disabled. TJ<

BUS

< V

AC-UVLOZ

17 33 µA

85°C V

= 4.5 V, HIZ Mode and Battery discharge current (BAT, SW, SYS)

BAT

OVPFET_DIS = 1 or No VBUS, I2C Disabled, BATFET Enabled. TJ<

58 85 µA

85°C

Input supply current (VBUS) in buck mode

Battery Discharge Current in boost mode

VBUS operating range V VBUS for active I2C, no battery

Sense VAC pin voltage I2C active hysteresis VACfalling from above V One of the conditions to turn on

REGN One of the conditions to turn on

REGN Sleep mode falling threshold

Sleep mode rising threshold VAC 6.5-V Overvoltage rising

threshold

= 5 V, High-Z Mode and

VBUS

OVPFET_DIS = 1, No battery V

= 12 V, High-Z Mode and

VBUS

OVPFET_DIS = 1, No battery V

= 12 V, V

VBUS

converter not switching V

> VUVLO, V

VBUS

converter switching, VBAT = 3.8V,

VBUS

> V

VBUS

VBAT

> V

VBAT

37 50 µA

68 90 µA

1.5 3 mA

3 mA

ISYS = 0A V

= 4.2 V, boost mode, I

BAT

A, converter switching

rising 3.9 13.5 V

VBUS

rising 3.3 3.6

VAC

VAC_UVLOZ

rising 3.65 3.9

VAC

falling 500

VAC

VAC–VVBAT

≤ V

REG

VAC–VVBAT

≤ V

REG

), V

, VAC falling

, VAC rising

BUSMIN_FALL

), V

BUSMIN_FALL

VBUS

≤ V

= 0

BAT

3 mA

300 mV

15 60 110 mV

115 220 340 mV

VAC rising; OVP (REG06[7:6]) = '01' 6.1 6.4 6.7 V

5 µA

Product Folder Links: bq25601

Page 8

bq25601

SLUSCK5 –MARCH 2017

Electrical Characteristics (continued)

VAC_UVLOZ

otherwise noted)

VAC_OV_RISE

VAC_OV_HYS

BAT_UVLOZ

BAT_DPL_FALL

BAT_DPL_RISE

BAT_DPL_HYST

BUSMIN_FALL

BUSMIN_HYST

BADSRC

POWER-PATH

SYS_MIN

SYS

SYS_MAX

ON(RBFET)

ON(HSFET)

ON(LSFET)

FWD

ON(BAT-SYS)

BATTERY CHARGER

BATREG_RANGE

BATREG_STEP

BATREG

BATREG_ACC

< V

VAC

< V

VAC_OV

and V

VAC

> V

BAT

+ V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VAC 10.5-V Overvoltage rising threshold

VAC 14-V Overvoltage rising threshold

VAC 6.5-V Overvoltage hysteresis

VAC 10.5-V Overvoltage hysteresis

VAC 14-V Overvoltage hysteresis BAT for active I2C, no adapter V

Battery Depletion Threshold V Battery Depletion Threshold V Battery Depletion rising

hysteresis Bad adapter detection falling

threshold Bad adapter detection hysteresis 80 mV Bad adapter detection current

source

System regulation voltage

System Regulation Voltage

Maximum DC system voltage output

Top reverse blocking MOSFET on-resistance between VBUS and PMID - Q1

Top switching MOSFET onresistance between PMID and SW - Q2

Bottom switching MOSFET onresistance between SW and GND

- Q3 BATFET forward voltage in

supplement mode SYS-BAT MOSFET on-resistance

SYS-BAT MOSFET on-resistance

Charge voltage program range 3.856 4.624 V Charge voltage step 32 mV

Charge voltage setting

Charge voltage setting accuracy

, TJ= –40°C to 125°C and TJ= 25°C for typical values (unless

SLEEP

VAC rising, OVP (REG06[7:6]) = '10' 10.35 10.9 11.5 V

VAC rising, OVP (REG06[7:6]) = '11' 13.5 14.2 14.85 V VAC falling, OVP (REG06[7:6]) =

'01' VAC falling, OVP (REG06[7:6]) =

'10' VAC falling, OVP (REG06[7:6]) =

'11'

rising 2.5 V

BAT

falling 2.2 2.6 V

BAT

rising 2.35 2.8 V

BAT

rising 180 mV

BAT

falling 3.75 3.9 4.0 V

BUS

320 mV

250 mV

300 mV

Sink current from VBUS to GND 30 mA

< SYS_MIN[2:0] = 101,

VBAT

BATFET Disabled (REG07[5] = 1) I

= 0 A, V

SYS

= 4.400 V, BATFET disabled

VBAT

> V

SYSMIN

, V

VBAT

(REG07[5] = 1) I

= 0 A, , Q4 off, V

SYS

> V

VBAT

SYSMIN

= 3.5V

VBAT

≤ 4.400 V,

3.5 3.68 V

BAT

50 mV

4.4 4.45 4.48 V

-40°C≤ TA≤ 125°C 45 mΩ

= 5 V , -40°C≤ TA≤ 125°C 62 mΩ

REGN

= 5 V , -40°C≤ TA≤ 125°C 71 mΩ

REGN

30 mV

QFN package, Measured from BAT to SYS, V

= 4.2V, TJ= 25°C

BAT

19.5 24 mΩ

QFN package, Measured from BAT to SYS, V 125°C

VREG (REG04[7:3]) = 4.208 V (01011), V, –40 ≤ TJ≤ 85°C

VREG (REG04[7:3]) = 4.352 V (01111), V, –40 ≤ TJ≤ 85°C

= 4.208 V or V

BAT

–40 ≤ TJ≤ 85°C

= 4.2V, TJ= –40 -

BAT

= 4.352 V,

19.5 30 mΩ

4.187 4.208 4.229 V

4.330 4.352 4.374 V

–0.5% 0.5%

www.ti.com

Product Folder Links: bq25601

Page 9

bq25601

www.ti.com

Electrical Characteristics (continued)

VAC_UVLOZ

otherwise noted)

CHG_REG_RANGE

CHG_REG_STEP

CHG_REG

CHG_REG_ACC

CHG_REG

CHG_REG_ACC

BATLOWV_FALL

BATLOWV_RISE

PRECHG

PRECHG_ACC

TERM

TERM_ACC

TERM

TERM_ACC

TERM

TERM_ACC

SHORT

SHORTZ

SHORT

RECHG

SYSLOAD

INPUT VOLTAGE AND CURRENT REGULATION

INDPM

INDPM_ACC

INDPM

INDPM_ACC

DPM_VBAT

DPM_VBAT_ACC

< V

VAC

< V

VAC_OV

and V

VAC

> V

BAT

+ V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Charge current regulation range 0 3000 mA Charge current regulation step 60 mA

Charge current regulation setting Charge current regulation

accuracy Charge current regulation setting I

Charge current regulation accuracy

Charge current regulation setting Charge current regulation

accuracy Battery LOWV falling threshold I Battery LOWV rising threshold Pre-charge to fast charge 3.0 3.12 3.24 V Precharge current regulation IPRECHG[3:0] = '0010' = 180 mA 153 171 189 mA Precharge current regulation

accuracy Termination current regulation I

Termination current regulation accuracy

Termination current regulation Termination current regulation

accuracy Termination current regulation I

Termination current regulation accuracy

Battery short voltage V Battery short voltage V Battery short current V Recharge Threshold below

BAT_REG

Recharge Threshold below V

BAT_REG

System discharge load current V

Input voltage regulation limit V Input voltage regulation accuracy –3% 5% Input voltage regulation limit V Input voltage regulation accuracy –3% 3% Input voltage regulation limit

tracking VBAT

Input voltage regulation accuracy tracking VBAT

SLUSCK5 –MARCH 2017

, TJ= –40°C to 125°C and TJ= 25°C for typical values (unless

SLEEP

= 240 mA, V

CHG

= 3.8 V

VBAT

= 240 mA, V

CHG

= 3.8 V

VBAT

= 720 mA, V

CHG

= 3.8 V

VBAT

CHG_REG

V I

CHG

V I

CHG

= 720 mA, V

= 3.8 V

BAT

= 1.38 A, V

= 3.8 V

VBAT

= 720 mA or I

= 3.1 V or V

VBAT

= 240 mA 2.7 2.8 2.9 V

VBAT

CHG VBAT

= 3.1V or

= 3.1 V or

BAT

= 3.1 V or

= 1.38 A,

= 3.8 V

0.216 0.24 0.264 A

–10% 10%

0.685 0.720 0.755 A

-5% 5%

1.311 1.380 1.449 A

–5% 5%

IPRECHG[3:0] = '0010' = 180 mA –15 5 %

> 780 mA, ITERM[3:0] = '0010'

CHG

= 180 mA, V I

> 780 mA, , ITERM[3:0] =

CHG

'0010' = 180 mA, V I

≤ 780 mA, , ITERM[3:0] =

CHG

'0010' = 180 mA I

≤ 780 mA, , ITERM[3:0] =

CHG

'0010' = 180 mA

= 600 mA, ITERM[3:0] = '0000'

CHG

= 60 mA, V I

= 600 mA, ITERM[3:0] = '0000'

CHG

= 60 mA, V

falling 1.85 2 2.15 V

VBAT

rising 2.15 2.25 2.35 V

VBAT

< V

VBAT

falling, REG04[0] = 0 90 120 150 mV

BAT

falling, REG04[0] = 1 200 230 265 mV

BAT

= 4.2 V 30 mA

SYS

(REG06[3:0] = 0000) = 3.9 V 3.78 3.95 4.1 V

INDPM

(REG06[3:0] = 0110) = 4.4 V 4.268 4.4 4.532 V

INDPM

VBAT

SHORTZ

= 4.208 V

VBAT

= 4.208 V

VINDPM = 3.9V,

150 180 216 mA

-16.7% 20%

162 180 192 mA

-10% 10% 45 60 75 mA

–25% 25%

70 90 110 mA

4.171 4.3 4.43 V VDPM_VBAT_TRACK = 300mV, VBAT = 4.0V

–3% 3%

Product Folder Links: bq25601

Page 10

bq25601

SLUSCK5 –MARCH 2017

Electrical Characteristics (continued)

VAC_UVLOZ

otherwise noted)

INDPM

IN_START

BAT PIN OVERVOLTAGE PROTECTION

BATOVP_RISE

BATOVP_FALL

THERMAL REGULATION AND THERMAL SHUTDOWN

JUNCTION_REG

SHUT

SHUT_HYST

JEITA Thermistor Comparator (BUCK MODE)

COLD OR HOT THERMISTER COMPARATOR (BOOST MODE)

BCOLD

BHOT

< V

VAC

< V

VAC_OV

and V

VAC

> V

BAT

+ V

, TJ= –40°C to 125°C and TJ= 25°C for typical values (unless

SLEEP

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VBUS

SW, I 500 mA, –40 ≤ TJ≤ 85°C

USB input current regulation limit

VBUS

SW, IINDPM (REG[4:0] = 01000) = 900 mA, –40 ≤ TJ≤ 85°C

VBUS

SW, IINDPM (REG[4:0] = 01110) =

1.5 A, –40 ≤ TJ≤ 85°C

Input current limit during system start-up sequence

Battery overvoltage threshold

Junction Temperature Regulation Threshold

Thermal Shutdown Rising Temperature

BAT

BAT_REG

BAT

BAT_REG

Temperature Increasing, TREG (REG05[1] = 1) = 110℃

Temperature Increasing, TREG (REG05[1] = 0) = 90℃

Temperature Increasing 160 °C

Thermal Shutdown Hysteresis 30 °C

T1 (0°C) threshold, Charge suspended T1 below this temperature.

Charger suspends charge. As Percentage to V

Falling As Percentage to V T2 (10°C) threshold, Charge back

to I

/2 and 4.2 V below this

CHG

temperature

As percentage of V

Falling As Percentage to V T3 (45°C) threshold, charge back

to ICHG and 4.05V above this temperature.

Charger suspends charge. As Percentage to V

Falling As Percentage to V T5 (60°C) threshold, charge

suspended above this

As Percentage to V

temperature. Falling As Percentage to V

Cold Temperature Threshold, TS pin Voltage Rising Threshold

As Percentage to V

-20°C w/ 103AT), TJ= –20°C 125°C

Falling TJ= –20°C - 125°C 78.5% 79% 79.5% Hot Temperature Threshold, TS

pin Voltage falling Threshold

As Percentage to V 60°C w/ 103AT), TJ= –20°C - 125°C

Rising TJ= –20°C - 125°C 33.8% 34.4% 34.9%

= 5 V, current pulled from

(REG[4:0] = 00100) =

INDPM

= 5 V, current pulled from

rising, as percentage of

falling, as percentage of

REGN

(Approx.

REGN

(Approx.

REGN

www.ti.com

450 500 mA

750 900 mA

1.3 1.5 A

200 mA

103 104 105 %

101 102 103 %

110 °C

90 °C

72.4% 73.3% 74.2%

69% 71.5% 74%

67.2% 68% 69%

66% 66.8% 67.7%

43.8% 44.7% 45.8%

45.1% 45.7% 46.2%

33.7% 34.2% 35.1%

34.5% 35.3% 36.2%

79.5% 80% 80.5%

30.2% 31.2% 32.2%

Product Folder Links: bq25601

Page 11

bq25601

www.ti.com

Electrical Characteristics (continued)

VAC_UVLOZ

otherwise noted)

CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE)

HSFET_OCP

BATFET_OCP

CHARGE UNDER-CURRENT COMPARATOR (CYCLE-BY-CYCLE)

LSFET_UCP

PWM

MAX

BOOST MODE OPERATION

OTG_REG

OTG_REG_ACC

BATLOWV_OTG

OTG

OTG_OCP_ACC

OTG_OVP

OTG_HSZCP

REGN LDO

REGN

LOGIC I/O PIN CHARACTERISTICS (CE, PSEL, SCL, SDA,, INT)

ILO

BIAS

ILO

BIAS

LOGIC I/O PIN CHARACTERISTICS (PG, STAT)

(1) Specified by design. Not production tested.

< V

VAC

< V

VAC_OV

and V

VAC

> V

BAT

+ V

, TJ= –40°C to 125°C and TJ= 25°C for typical values (unless

SLEEP

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

HSFET cycle-by-cycle overcurrent threshold

System over load threshold 6.0 A

LSFET under-current falling threshold

PWM switching frequency

Maximum PWM duty cycle

(1)

Boost mode regulation voltage Boost mode regulation voltage

accuracy

Battery voltage exiting boost mode

From sync mode to non-sync mode 160 mA

Oscillator frequency, buck mode 1320 1500 1680 kHz Oscillator frequency, boost mode 1150 1412 1660 kHz

= 3.8 V, I

VBAT

BOOSTV[1:0] = '10' = 5.15 V V

= 3.8 V, I

VBAT

BOOSTV[1:0] = '10' = 5.15 V V

falling, MIN_V

VBAT

(REG01[0]) = 0 V

rising, MIN_V

VBAT

(REG01[0]) = 0 V

falling, MIN_V

VBAT

(REG01[0]) = 1 V

rising, MIN_V

VBAT

(REG01[0]) = 1

OTG mode output current BOOST_LIM (REG02[7]) = 1 1.2 1.4 1.6 A Boost mode RBFET over-current

protection accuracy

BOOST_LIM = 0.5 A (REG02[7] = 0) 0.5 0.722 A

OTG overvoltage threshold Rising threshold 5.55 5.8 6.15 V HSFET under current falling

threshold

REGN LDO output voltage V REGN LDO output voltage V

VBUS VBUS

= 9V, I = 5V, I

Input low threshold CE 0.4 V Input high threshold CE 1.3 V High-level leakage current CE Pull up rail 1.8 V 1 µA Input low threshold PSEL 0.4 V Input high threshold PSEL 1.3 V High-level leakage current PSEL Pull up rail 1.8V 1 µA

Low-level output voltage 0.4 V

SLUSCK5 –MARCH 2017

5.2 8.0 A

97%

= 0 A,

(PMID)

= 0 A,

BAT

_SEL

4.972 5.126 5.280 V

-3 3 %

2.6 2.8 2.9 V

2.9 3.0 3.15 V

2.4 2.5 2.6 V

2.7 2.8 2.9 V

100 mA

= 40mA 5.6 6 6.55 V

REGN

= 20mA 4.6 4.7 4.8 V

REGN

Product Folder Links: bq25601

Page 12

Junction Temperature (°C)

SYSMIN Voltage (V)

-40 -25 -10 5 20 35 50 65 80 95 110 125

3.5

3.55

3.6

3.65

3.7

3.75

3.8

3.85

D001

Junction Temperature (°C)

BATREG Charge Voltage (V)

-40 -25 -10 5 20 35 50 65 80 95 110 125

4.1

4.2

4.3

4.4

4.5

D001

BATREG

= 4.208 V

BATREG

= 4.352 V

Output Current (A)

OTG Output Voltage (V)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

D001

Charge Current (A)

Charge Current Accuracy (%)

0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3

-8

-6

-4

-2

D001

Charge Current (A)

Charge Efficiency (%)

0 0.5 1 1.5 2 2.5 3

100

D001

VBUS Voltage

5 V 9 V 12 V

OTG Current (A)

Efficiency (%)

0.2 0.4 0.6 0.8 1 1.2 1.4

100

D001

BAT

= 3.2 V

BAT

= 3.8 V

BAT

= 4.1 V

bq25601

SLUSCK5 –MARCH 2017

7.6 Typical Characteristics

fSW= 1.5 MHz inductor DCR = 18 mΩ V

=3.8V

BAT

Figure 1. Charge Efficiency vs. Charge Current

= 5.15 V inductor DCR = 18 mΩ

OTG

Figure 2. Efficiency vs. OTG Current

www.ti.com

= 1.2 A V

OTG

= 3.8 V

VBAT

Figure 3. OTG Output Voltage vs. Output Current Figure 4. Charge Current Accuracy

Figure 5. SYSMIN Voltage vs. Junction Temperature Figure 6. BATREG Charge Voltage vs. Junction

OTG

= 5.15 V

Temperature

Product Folder Links: bq25601

Page 13

Junction Temperature (°C)

Charge Current (A)

55 65 75 85 95 105 115 125 135

0.25

0.5

0.75

1.25

1.5

1.75

2.25

D001

110 °C 90 °C

Junction Temperature (°C)

Input Current Limit (A)

-40 -25 -10 5 20 35 50 65 80 95

0.25

0.5

0.75

1.25

1.5

1.75

2.25

2.5

D001

IINDPM = 0.5 A IINDPM = 0.9 A IINDPM = 1.5 A

Junction Temperature (°C)

Charge Current (A)

-40 -25 -10 5 20 35 50 65 80 95 110 125

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

D001

CHG

= 0.24 A

CHG

= 0.72 A

CHG

= 1.38 A

bq25601

www.ti.com

Typical Characteristics (continued)

Figure 7. Input Current Limit vs. Junction Temperature Figure 8. Charge Current vs. Junction Temperature

SLUSCK5 –MARCH 2017

Figure 9. Charge Current vs. Junction Temperature

Product Folder Links: bq25601

Page 14

bq25601

SLUSCK5 –MARCH 2017

www.ti.com

8 Detailed Description

8.1 Overview

The bq25601 device is a highly integrated 3.0-A switch-mode battery charger for single cell Li-Ion and Li-polymer battery. It includes the input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2), low-side switching FET (LSFET, Q3), and battery FET (BATFET, Q4), and bootstrap diode for the high-side gate drive.

Product Folder Links: bq25601

Page 15

Battery

Sensing

Thermistor

I2C

Interface

USB

Adapter

FBO

PGND

REGN

RBFET (Q1)

VBUS

LSFET (Q3)

HSFET (Q2)

BATFET

(Q4)

SYS

BAT

CHG

VBUS_OVP_BOOST

/QON

Q1 Gate

Control

REGN

PMID

Q3_OCP_BOOST

Q2_UCP_BOOST

VBUS

OTG_OVP

OTG_HSZCP

OTG_BAT

LSFET_UCP

104% × V

BAT_REG

BAT

UCP

BATOVP

CONVERTER

Control

CHG_REG

BAT_REG

BAT

SYSMIN

INDPM

IC T

REG

INDPM

SYS

REGN

LDO

EN_HIZ

UVLO

SLEEP

ACOV

VBUS_UVLOZ

BAT

+ V

SLEEP

VAC_OV

BTST

REFRESH

Q2_OCP

BTST_REFRESH

BTST

- V

HSFET_OCP

EN_CHARGE

EN_BOOST

EN_HIZ

Q4 Gate

Control

QON

/CESDASCL

Input

Source

Detection

REF DAC

CHG_REG

BAT_REG

STAT /

IMON

/PG

INT

PSEL

CHARGE

CONTROL

STATE

MACHINE

Converter

Control State

Machine

BATLOWV

SUSPEND

RECHRG

TERMINATION

BATSHORT

TSHUT

BAD_SRC

BAT_GD

SHUT

IC T

BAT

BATLOWV

BAT

BADSRC

BATGD

BAT

TERM

CHG

BAT

SHORT

REG

-V

RECHG

CHG

bq25601

VBUS

EN_REGN

bq25601

www.ti.com

8.2 Functional Block Diagram

Product Folder Links: bq25601

SLUSCK5 –MARCH 2017

Page 16

bq25601

SLUSCK5 –MARCH 2017

www.ti.com

8.3 Feature Description

8.3.1 Power-On-Reset (POR)

The device powers internal bias circuits from the higher voltage of VBUS and BAT. When VBUS rises above V

VBUS_UVLOZ

driver are active. I2C interface is ready for communication and all the registers are reset to default value. The host can access all the registers after POR.

8.3.2 Device Power Up from Battery without Input Source

If only battery is present and the voltage is above depletion threshold (V connects battery to system. The REGN stays off to minimize the quiescent current. The low RDSON of BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time.

The device always monitors the discharge current through BATFET (Supplement Mode). When the system is overloaded or shorted (I indicate BATFET is disabled until the input source plugs in again or one of the methods described in BATFET Enable (Exit Shipping Mode) is applied to re-enable BATFET.

8.3.3 Power Up from Input Source

When an input source is plugged in, the device checks the input source voltage to turn on REGN LDO and all the bias circuits. It detects and sets the input current limit before the buck converter is started. The power up sequence from input source is as listed:

1. Power Up REGN LDO

2. Poor Source Qualification

3. Input Source Type Detection is based on or PSEL to set default input current limit (IINDPM) register or input source type.

4. Input Voltage Limit Threshold Setting (VINDPM threshold)

5. Converter Power-up

or BAT rises above V

> I

BAT

BATFET_OCP

BAT_UVLOZ

, the sleep comparator, battery depletion comparator and BATFET

BAT_DPL_RISE)

, the BATFET turns on and

), the device turns off BATFET immediately and set BATFET_DIS bit to

8.3.3.1 Power Up REGN Regulation

The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. The REGN also provides bias rail to TS external resistors. The pull-up rail of STAT can be connected to REGN as well. The REGN is enabled when all the below conditions are valid:

• V

VAC VAC

above V above V

VAC_PRESENT

+ V

BAT

SLEEPZ

in buck mode or VBUS below V

BAT

+ V

in boost mode

SLEEP

• After 220-ms delay is completed If any one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off.

The device draws less than IVBUS_HIZ from VBUS during HIZ state. The battery powers up the system when the device is in HIZ.

8.3.3.2 Poor Source Qualification

After REGN LDO powers up, the device confirms the current capability of the input source. The input source must meet both of the following requirements in order to start the buck converter.

• VBUS voltage below V

• VBUS voltage above V

VAC_OV

VBUSMIN

when pulling I

BADSRC

(typical 30 mA)

Once the input source passes all the conditions above, the status register bit VBUS_GD is set high and the INT pin is pulsed to signal to the host. If the device fails the poor source detection, it repeats poor source qualification every 2 seconds.

8.3.3.3 Input Source Type Detection

After the VBUS_GD bit is set and REGN LDO is powered, the device runs input source detection through or the PSEL pin. The bq25601 sets input current limit through PSEL pins.

Product Folder Links: bq25601

Page 17

bq25601

www.ti.com

SLUSCK5 –MARCH 2017

Feature Description (continued)

After input source type detection is completed, an INT pulse is asserted to the host. in addition, the following registers and pin are changed:

1. Input Current Limit (IINDPM) register is changed to set current limit

2. PG_STAT bit is set

3. VBUS_STAT bit is updated to indicate USB or other input source

The host can over-write IINDPM register to change the input current limit if needed. The charger input current is always limited by the IINDPM register.

8.3.3.3.1 PSEL Pins Sets Input Current Limit in bq25601

The bq25601 has PSEL pin for input current limit setting to interface with USB PHY. It directly takes the USB PHY device output to decide whether the input is USB host or charging port. When the device operates in hostcontrol mode, the host needs to IINDET_EN bit to read the PSEL value and update the IINDPM register. When the device is in default mode, PSEL value updates IINDPM in real time.

Table 1. Input Current Limit Setting from PSEL

Input Detection PSEL Pin

USB SDP High 500 mA 001

Adapter Low 2.4A 011

INPUT CURRENT LIMIT

(ILIM)

VBUS_STAT

8.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)

The device supports wide range of input voltage limit (3.9 V – 5.4V) for USBThe device's VINDPM is set at 4.5V. The device supports dynamic VINDPM trackingsettings which tracks the battery voltage. This function can be enabled via the VDPM_BAT_TRACK[1:0] register bits. When enabled, the actual input voltage limit will be the higher of the VINDPM register and VBAT + VDPM_BAT_TRACK offset.

8.3.3.5 Converter Power-Up

After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery.

The device provides soft-start when system rail is ramped up. When the system rail is below 2.2 V, the input current is limited to is to the lower of 200 mA or IINDPM register setting. After the system rises above 2.2 V, the device limits input current to the value set by IINDPM register.

As a battery charger, the device deploys a highly efficient 1.5 MHz step-down switching regulator. The fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage, charge current and temperature, simplifying output filter design.

The device switches to PFM control at light load or when battery is below minimum system voltage setting or charging is disabled. The PFM_DIS bit can be used to prevent PFM operation in either buck or boost configuration.

8.3.4 Boost Mode Operation From Battery

The device supports boost converter operation to deliver power from the battery to other portable devices through USB port. The boost mode output current rating meets the USB On-The-Go 500 mA output requirement. The maximum output current is up to 1.2 A. The boost operation can be enabled if the conditions are valid:

1. BAT above V

2. VBUS less than BAT+V

OTG_BAT

(in sleep mode)

SLEEP

3. Boost mode operation is enabled (OTG_CONFIG bit = 1)

4. Voltage at TS (thermistor) pin is within acceptable range (V

BHOT

< VTS< V

BCOLD

)

5. After 30-ms delay from boost mode enable

Product Folder Links: bq25601

Page 18

POR

watchdog timer expired

Reset registers

I2C interface enabled

Default Mode

Reset watchdog timer

Reset selective registers

Host Mode

Start watchdog timer

Host programs registers

WD_RST bit = 1?

I2C Write?

Watchdog Timer

Expired?

bq25601

SLUSCK5 –MARCH 2017

www.ti.com

During boost mode, the status register VBUS_STAT bits is set to 111, the VBUS output is 5.15 V and the output current can reach up to 1.2 A, selected through I2C (BOOST_LIM bit). The boost output is maintained when BAT is above V

OTG_BAT

threshold.

When OTG is enabled, the device starts up with PFM and later transits to PWM to minimize the overshoot. The PFM_DIS bit can be used to prevent PFM operation in either buck or boost configuration.

8.3.5 Host Mode and Standalone Power Management

8.3.5.1 Host Mode and Default Mode in bq25601

The bq25601 is a host controlled charger, but it can operate in default mode without host management. in default mode, the device can be used as an autonomous charger with no host or while host is in sleep mode. When the charger is in default mode, WATCHDOG_FAULT bit is HIGH. When the charger is in host mode, WATCHDOG_FAULT bit is LOW.

After power-on-reset, the device starts in default mode with watchdog timer expired, or default mode. All the registers are in the default settings. During default mode, any change on PSEL pin will make real time IINDPM register changes.

in default mode, the device keeps charging the battery with default 10-hour fast charging safety timer. At the end of the 10-hour, the charging is stopped and the buck converter continues to operate to supply system load.

Writing a 1 to the WD_RST bit transitions the charger from default mode to host mode. All the device parameters can be programmed by the host. To keep the device in host mode, the host has to reset the watchdog timer by writing 1 to WD_RST bit before the watchdog timer expires (WATCHDOG_FAULT bit is set), or disable watchdog timer by setting WATCHDOG bits = 00.

When the watchdog timer expires (WATCHDOG_FAULT bit = 1), the device returns to default mode and all registers are reset to default values except IINDPM, VINDPM, BATFET_RST_EN, BATFET_DLY, and BATFET_DIS bits.

8.3.6 Power Path Management

The device accommodates a wide range of input sources from USB, wall adapter, to car charger. The device provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or both.

8.3.7 Battery Charging Management

The device charges 1-cell Li-Ion battery with up to 3.0-A charge current for high capacity tablet battery. The 19.5mΩ BATFET improves charging efficiency and minimize the voltage drop during discharging.

Figure 10. Watchdog Timer Flow Chart

Product Folder Links: bq25601

Page 19

bq25601

www.ti.com

SLUSCK5 –MARCH 2017

8.3.7.1 Autonomous Charging Cycle

With battery charging is enabled (CHG_CONFIG bit = 1 and CE pin is LOW), the device autonomously completes a charging cycle without host involvement. The device default charging parameters are listed in

Table 2. The host can always control the charging operations and optimize the charging parameters by writing to

the corresponding registers through I2C.

Table 2. Charging Parameter Default Setting

Default Mode bq25601

Charging voltage 4.208V Charging current 2.048 A

Pre-charge current 180 mA Termination current 180 mA Temperature profile JEITA

Safety timer 10 hours

A new charge cycle starts when the following conditions are valid:

• Converter starts

• Battery charging is enabled (CHG_CONFIG bit = 1 and I

CHG

• No thermistor fault on TS

• No safety timer fault

• BATFET is not forced to turn off (BATFET_DIS bit = 0) The charger device automatically terminates the charging cycle when the charging current is below termination

threshold, battery voltage is above recharge threshold, and device not is in DPM mode or thermal regulation. When a fully charged battery is discharged below recharge threshold (selectable through VRECHG bit), the device automatically starts a new charging cycle. After the charge is done, toggle CE pin or CHG_CONFIG bit can initiate a new charging cycle.

The STAT output indicates the charging status: charging (LOW), charging complete or charge disable (HIGH) or charging fault (Blinking). The STAT output can be disabled by setting EN_ICHG_MON bits = 11. in addition, the status register (CHRG_STAT) indicates the different charging phases: 00-charging disable, 01-precharge, 10-fast charge (constant current) and constant voltage mode, 11-charging done. Once a charging cycle is completed, an INT is asserted to notify the host.

8.3.7.2 Battery Charging Profile

The device charges the battery in five phases: battery short, preconditioning, constant current, constant voltage and top-off trickle charging (optional). At the beginning of a charging cycle, the device checks the battery voltage and regulates current and voltage accordingly.

Table 3. Charging Current Setting

BAT

< 2.2 V I

2.2 V to 3 V I > 3 V I

CHARGinG CURRENT

SHORT

PRECHG

CHG

Product Folder Links: bq25601

SETTinG

100 mA 01 180 mA 01

2.048 A 10

CHRG_STAT

Page 20

Regulation Voltage

VREG[7:3]

Charge Current

ICHG[5:0]

BATLOWV

(3 V)

SHORTZ

(2.2 V)

IPRECHG[7:4]

ITERM[3:0]

SHORT

Battery Voltage

Charge Current

Trickle Charge

Pre-charge

Fast Charge and Voltage Regulation

Safety Timer Expiration

Top-off Timer (optional)

bq25601

SLUSCK5 –MARCH 2017

www.ti.com

If the charger device is in DPM regulation or thermal regulation during charging, the actual charging current will be less than the programmed value. in this case, termination is temporarily disabled and the charging safety timer is counted at half the clock rate.

Figure 11. Battery Charging Profile

8.3.7.3 Charging Termination

The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is below termination current. After the charging cycle is completed, the BATFET turns off. The converter keeps running to power the system, and BATFET can turn on again to engage Supplement Mode.

When termination occurs, the status register CHRG_STAT is set to 11, and an INT pulse is asserted to the host. Termination is temporarily disabled when the charger device is in input current, voltage or thermal regulation. Termination can be disabled by writing 0 to EN_TERM bit prior to charge termination.

At low termination currents (25 mA-50 mA), due to the comparator offset, the actual termination current may be 10 mA-20 mA higher than the termination target. in order to compensate for comparator offset, a programmable top-off timer can be applied after termination is detected. The termination timer will follow safety timer constraints, such that if safety timer is suspended, so will the termination timer. Similarly, if safety timer is doubled, so will the termination timer. TOPOFF_ACTIVE bit reports whether the top off timer is active or not. The host can read CHRG_STAT and TOPOFF_ACTIVE to find out the termination status.

Top off timer gets reset at one of the following conditions:

1. Charge disable to enable

2. Termination status low to high

3. REG_RST register bit is set

The top-off timer settings are read in once termination is detected by the charger. Programming a top-off timer value after termination will have no effect unless a recharge cycle is initiated. An INT is asserted to the host when entering top-off timer segment as well as when top-off timer expires.

8.3.7.4 Thermistor Qualification

The charger device provides a single thermistor input for battery temperature monitor.

Product Folder Links: bq25601

Page 21

æ ö

ç ÷

ç ÷ è ø

è ø

æ ö

ç ÷

ç ÷ è ø

è ø

REGN

COLD

VT1

1 1

RT2 RTH

æ ö

´ ´ ´ -

ç ÷ è ø

æ ö æ ö

´ - - ´ -

ç ÷ ç ÷ è ø è ø

REGN COLD HOT

REGN REGN

HOT COLD

1 1

V RTH RTH

VT1 VT5

V V

RTH 1 RTH 1

VT5 VT1

Charging Current (%)

±5

25 40 55 70

100

T2 T3

Junction Temperature (°C)

5 15 20 30 35 45 50 60 65

ISET = 0

ISET = 1

Charging Voltage (V)

±5

25 40 55 70

4.1

REG

T2 T3

Junction Temperature (°C)

5 15 20 30 35 45 50 60 65

VSET = 1

VSET = 0

bq25601

www.ti.com

SLUSCK5 –MARCH 2017

8.3.7.5 JEITA Guideline Compliance During Charging Mode

To improve the safety of charging Li-ion batteries, JEITA guideline was released on April 20, 2007. The guideline emphasized the importance of avoiding a high charge current and high charge voltage at certain low and high temperature ranges.

To initiate a charge cycle, the voltage on TS pin must be within the VT1 to VT5 thresholds. If TS voltage exceeds the T1-T5 range, the controller suspends charging and waits until the battery temperature is within the T1 to T5 range.

At cool temperature (T1-T2), JEITA recommends the charge current to be reduced to half of the charge current or lower. At warm temperature (T3-T5), JEITA recommends charge voltage less than 4.1 V.

The charger provides flexible voltage/current settings beyond the JEITA requirement. The voltage setting at warm temperature (T3-T5) can be VREG or 4.1V (configured by JEITA_VSET). The current setting at cool temperature (T1-T2) can be further reduced to 20% of fast charge current (JEITA_ISET).

Figure 12. JEITA Profile: Charging Current Figure 13. JEITA Profile: Charging Voltage

Equation 1 through Equation 2 describe updates to the resistor bias network.

Select 0°C to 60°C range for Li-ion or Li-polymer battery:

• RTH

COLD

= 3.02 KΩ

HOT

= 27.28 KΩ

• RT1 = 5.23 KΩ

• RT2 = 30.9 KΩ

8.3.7.6 Boost Mode Thermistor Monitor during Battery Discharge Mode

For battery protection during boost mode, the device monitors the battery temperature to be within the to thresholds. When temperature is outside of the temperature thresholds, the boost mode is suspended. In additional, VBUS_STAT bits are set to 000 and NTC_FAULT is reported. Once temperature returns within thresholds, the boost mode is recovered and NTC_FAULT is cleared.

Product Folder Links: bq25601

(1)

(2)

Page 22

REGN

BCOLD

(±10°C)

BHOT

AGND

(65°C)

Temperature Range to Boost

Boost Disabled

Boost Enabled

Boost Disabled

bq25601

SLUSCK5 –MARCH 2017

www.ti.com

Figure 14. TS Pin Thermistor Sense Threshold in Boost Mode

8.3.7.7 Charging Safety Timer

The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions. The safety timer is 2 hours when the battery is below V than V

BATLOWV

threshold.

BATLOWV

threshold and 10 hours when the battery is higher

The user can program fast charge safety timer through I2C (CHG_TIMER bits). When safety timer expires, the fault register CHRG_FAULT bits are set to 11 and an INT is asserted to the host. The safety timer feature can be disabled through I2C by setting EN_TIMER bit

During input voltage, current, JEITA cool or thermal regulation, the safety timer counts at half clock rate as the actual charge current is likely to be below the register setting. For example, if the charger is in input current regulation (IDPM_STAT = 1) throughout the whole charging cycle, and the safety time is set to 5 hours, the safety timer will expire in 10 hours. This half clock rate feature can be disabled by writing 0 to TMR2X_EN bit.

During the fault, timer is suspended. Once the fault goes away, fault resumes. If user stops the current charging cycle, and start again, timer gets reset (toggle CE pin or CHRG_CONFIG bit).

8.3.7.8 Narrow VDC Architecture

The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The minimum system voltage is set by SYS_Min bits. Even with a fully depleted battery, the system is regulated above the minimum system voltage.

When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode), and the system is typically 180 mV above the minimum system voltage setting. As the battery voltage rises above the minimum system voltage, BATFET is fully on and the voltage difference between the system and battery is the VDS of BATFET.

When the battery charging is disabled and above minimum system voltage setting or charging is terminated, the system is always regulated at typically 50mV above battery voltage. The status register VSYS_STAT bit goes high when the system is in minimum system voltage regulation.

Product Folder Links: bq25601

Page 23

2.8A

-0.6A

3.2A

0.5A

3.6V

3.4V

3.2V

3.18V

1.2A

1.0A

DPM DPM

Supplement

Voltage

SYS

VBUS

BAT

ICHG

IIN

ISYS

Plot1

BAT (V)

SYS (V)

2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3

3.1

3.3

3.5

3.7

3.9

4.1

4.3

4.5

D002

Charge Disabled Charge Enabled Minimum System Voltage

bq25601

www.ti.com

SLUSCK5 –MARCH 2017

Figure 15. System Voltage vs Battery Voltage

8.3.7.9 Dynamic Power management

To meet maximum current limit in USB spec and avoid over loading the adapter, the device features Dynamic Power management (DPM), which continuously monitors the input current and input voltage. When input source is over-loaded, either the current exceeds the input current limit (IIDPM) or the voltage falls below the input voltage limit (VINDPM). The device then reduces the charge current until the input current falls below the input current limit and the input voltage rises above the input voltage limit.

When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to drop. Once the system voltage falls below the battery voltage, the device automatically enters the supplement mode where the BATFET turns on and battery starts discharging so that the system is supported from both the input source and battery.

During DPM mode, the status register bits VDPM_STAT (VINDPM) or IDPM_STAT (IINDPM) goes high.

Figure 16 shows the DPM response with 9-V/1.2-A adapter, 3.2-V battery, 2.8-A charge current and 3.5-V

minimum system voltage setting.

Figure 16. DPM Response

Product Folder Links: bq25601

Page 24

Plot1

V(BAT-SYS) (mV)

Current (A)

0 5 10 15 20 25 30 35 40 45 50 55

0.5

1.5

2.5

3.5

4.5

D001

bq25601

SLUSCK5 –MARCH 2017

www.ti.com

8.3.7.10 Supplement Mode

When the system voltage falls 180 mV (VBAT > VSYSMin) or 45 mV (VBAT < VSYSMin) below the battery voltage, the BATFET turns on and the BATFET gate is regulated the gate drive of BATFET so that the minimum BATFET VDS stays at 30 mV when the current is low. This prevents oscillation from entering and exiting the supplement mode.

As the discharge current increases, the BATFET gate is regulated with a higher voltage to reduce RDSON until the BATFET is in full conduction. At this point onwards, the BATFET VDS linearly increases with discharge current. Figure 17 shows the V-I curve of the BATFET gate regulation operation. BATFET turns off to exit supplement mode when the battery is below battery depletion threshold.

8.3.8 Shipping Mode and QON Pin

8.3.8.1 BATFET Disable Mode (Shipping Mode)

To extend battery life and minimize power when system is powered off during system idle, shipping, or storage, the device can turn off BATFET so that the system voltage is zero to minimize the battery leakage current. When the host set BATFET_DIS bit, the charger can turn off BATFET immediately or delay by t BATFET_DLY bit.

8.3.8.2 BATFET Enable (Exit Shipping Mode)

When the BATFET is disabled (in shipping mode) and indicated by setting BATFET_DIS, one of the following events can enable BATFET to restore system power:

1. Plug in adapter

2. Clear BATFET_DIS bit

3. Set REG_RST bit to reset all registers including BATFET_DIS bit to default (0)

4. A logic high to low transition on QON pin with t mode

8.3.8.3 BATFET Full System Reset

The BATFET functions as a load switch between battery and system when input source is not pluggeD–in. By changing the state of BATFET from on to off, systems connected to SYS can be effectively forced to have a power-on-reset. The QON pin supports push-button interface to reset system power without host by changing the state of BATFET.

When the QON pin is driven to logic low for t (BATFET_DIS = 0), the BATFET is turned off for t function can be disabled by setting BATFET_RST_EN bit to 0.

Figure 17. BAFET V-I Curve

SHIPMODE

QON_RST

Product Folder Links: bq25601

while input source is not plugged in and BATFET is enabled

BATFET_RST

SM_DLY

as configured by

deglitch time to enable BATFET to exit shipping

and then it is re-enabled to reset system power. This

Page 25

SYS

QON

Control

BAT

PULL-UP

QON

Turn on Q4 FET

when BATFET_DIS = 1 or SLEEPZ = 1

Reset Q4 FET

When BATFET_DIS = 0 and SLEEPZ = 0

SHIPMODE

Press

push button

Press

push button

QON_RST

BATFET_RST

off

Q4 on Q4 on

Q4 off due to I2C or

system overload

bq25601

www.ti.com

SLUSCK5 –MARCH 2017

8.3.8.4 QON Pin Operations

The QON pin incorporates two functions to control BATFET.

1. BATFET Enable: A QON logic transition from high to low with longer than t

SHIPMODE

deglitch turns on

BATFET and exit shipping mode

2. BATFET Reset: When QON is driven to logic low by at least t BATFET_DIS = 0), the BATFET is turned off for t

BATFET_RST

QON_RST

. The BATFET is re-enabled after t

while adapter is not plugged in (and

BATFET_RST

duration. This function allows systems connected to SYS to have power-on-reset. This function can be disabled by setting BATFET_RST_EN bit to 0.

Figure 18 shows the sample external configurations for each.

Figure 18. QON Timing

Figure 19. QON Circuit

8.3.9 Status Outputs (PG, STAT, INT)

8.3.9.1 Power Good indicator (PG Pin and PG_STAT Bit)

The PG_STAT bit goes HIGH and PG pin goes LOW to indicate a good input source when:

• VBUS above V

• VBUS above battery (not in sleep)

• VBUS below V

• VBUS above V

• Completed input Source Type Detection

8.3.9.2 Charging Status indicator (STAT)

The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED. The STAT pin

VBUS_UVLO

VAC_OV VBUSMin

threshold

(typical 3.8 V) when I

BADSRC

(typical 30 mA) current is applied (not a poor source)

function can be disabled by setting the EN_ICHG_MON bits = 11.

Product Folder Links: bq25601

Page 26

bq25601

SLUSCK5 –MARCH 2017

www.ti.com

Table 4. STAT Pin State

CHARGING STATE STAT INDICATOR

Charging in progress (including recharge) LOW Charging complete HIGH Sleep mode, charge disable HIGH Charge suspend (input overvoltage, TS fault, timer fault or system overvoltage)

Boost Mode suspend (due to TS fault)

Blinking at 1 Hz

8.3.9.3 Interrupt to Host (INT)

In some applications, the host does not always monitor the charger operation. The INT pulse notifies the system on the device operation. The following events will generate 256-μs INT pulse.

• USB/adapter source identified (through PSEL detection)

• Good input source detected – VBUS above battery (not in sleep) – VBUS below V – VBUS above V

VAC_OV

VBUSMin

threshold

(typical 3.8 V) when I

BADSRC

(typical 30 mA) current is applied (not a poor source)

• input removed

• Charge Complete

• Any FAULT event in REG09

• VINDPM / IINDPM event detected (maskable)

When a fault occurs, the charger device sends out INT and keeps the fault state in REG09 until the host reads the fault register. Before the host reads REG09 and all the faults are cleared, the charger device would not send any INT upon new faults. To read the current fault status, the host has to read REG09 two times consecutively. The first read reports the pre-existing fault register status and the second read reports the current fault register status.

8.3.10 Protections

8.3.10.1 Voltage and Current Monitoring in Converter Operation

The device closely monitors the input and system voltage, as well as internal FET currents for safe buck and boost mode operation.

8.3.10.1.1 Voltage and Current Monitoring in Buck Mode

8.3.10.1.1.1 Input Overvoltage (ACOV)

If VBUS voltage exceeds V

VAC_OV

(programmable via OVP[2:0] bits), the device stops switching immediately.

During input overvoltage event (ACOV), the fault register CHRG_FAULT bits are set to 01. An INT pulse is asserted to the host. The device will automatically resume normal operation once the input voltage drops back below the OVP threshold.

8.3.10.1.1.2 System Overvoltage Protection (SYSOVP)

The charger device clamps the system voltage during load transient so that the components connect to system would not be damaged due to high voltage. SYSOVP threshold is 350 mV above minimum system regulation voltage when the system is regulate at V

. Upon SYSOVP, converter stops switching immediately to clamp

SYSMIN

the overshoot. The charger provides 30 mA discharge current to bring down the system voltage.

8.3.10.2 Voltage and Current Monitoring in Boost Mode

The device closely monitors the VBUS voltage, as well as RBFET and LSFET current to ensure safe boost mode operation.

8.3.10.2.1 VBUS Soft Start

When the boost function is enabled, the device soft-starts boost mode to avoid inrush current.

Product Folder Links: bq25601

Page 27

bq25601

www.ti.com

8.3.10.2.2 VBUS Output Protection

SLUSCK5 –MARCH 2017

The device monitors boost output voltage and other conditions to provide output short circuit and overvoltage protection. The Boost build in accurate constant current regulation to allow OTG to adaptive to various types of load. If short circuit is detected on VBUS, the Boost turns off and retry 7 times. If retries are not successful, OTG is disabled with OTG_CONFIG bit cleared. In addition, the BOOST_FAULT bit is set and INT pulse is generated. The BOOST_FAULT bit can be cleared by host by re-enabling boost mode

8.3.10.2.3 Boost Mode Overvoltage Protection

When the VBUS voltage rises above regulation target and exceeds VOTG_OVP, the device enters overvoltage protection which stops switching, clears OTG_CONFIG bit and exits boost mode. At Boost overvoltage duration, the fault register bit (BOOST_FAULT) is set high to indicate fault in boost operation. An INT is also asserted to the host.

8.3.10.3 Thermal Regulation and Thermal Shutdown

8.3.10.3.1 Thermal Protection in Buck Mode

The bq25601 monitors the internal junction temperature TJto avoid overheat the chip and limits the IC surface temperature in buck mode. When the internal junction temperature exceeds thermal regulation limit (110°C), the device lowers down the charge current. During thermal regulation, the actual charging current is usually below the programmed battery charging current. Therefore, termination is disabled, the safety timer runs at half the clock rate, and the status register THERM_STAT bit goes high.

Additionally, the device has thermal shutdown to turn off the converter and BATFET when IC surface temperature exceeds T host. The BATFET and converter is enabled to recover when IC temperature is T T

(160ºC).

SHUT

(160ºC). The fault register CHRG_FAULT is set to 1 and an INT is asserted to the

SHUT

SHUT_HYS

(30ºC) below

8.3.10.3.2 Thermal Protection in Boost Mode

The device monitors the internal junction temperature to provide thermal shutdown during boost mode. When IC junction temperature exceeds T BATFET is turned off. When IC junction temperature is below T

(160ºC), the boost mode is disabled by setting OTG_CONFIG bit low and

SHUT

(160ºC) - T

SHUT

SHUT_HYS

(30ºC), the BATFET is

enabled automatically to allow system to restore and the host can re-enable OTG_CONFIG bit to recover.

8.3.10.4 Battery Protection

8.3.10.4.1 Battery overvoltage Protection (BATOVP)

The battery overvoltage limit is clamped at 4% above the battery regulation voltage. When battery over voltage occurs, the charger device immediately disables charging. The fault register BAT_FAULT bit goes high and an INT is asserted to the host.

8.3.10.4.2 Battery Over-Discharge Protection

When battery is discharged below V

BAT_DPL_FALL

, the BATFET is turned off to protect battery from over discharge. To recover from over-discharge latch-off, an input source plug-in is required at VBUS. The battery is charged with I register when the battery voltage is between V

8.3.10.4.3 System Over-Current Protection

(typically 100 mA) current when the VBAT < VSHORT, or precharge current as set in IPRECHG

SHORT

SHORTZ

and V

BAT_LOWV

When the system is shorted or significantly overloaded (IBAT > IBATOP) and the current exceeds BATFET overcurrent limit, the BATFET latches off. Section BATFET Enable (Exit Shipping Mode) can reset the latch-off condition and turn on BATFET.

Product Folder Links: bq25601

Page 28

SCL

SDA

SCL

START (S) STOP (P)

SCL

Data line stable;

Data valid

Change of data

allowed

bq25601

SLUSCK5 –MARCH 2017

www.ti.com

8.3.11 Serial interface

The device uses I2C compatible interface for flexible charging parameter programming and instantaneous device status reporting. I2CTM is a bi-directional 2-wire serial interface developed by Philips Semiconductor (now NXP Semiconductors). Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). Devices can be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave.

The device operates as a slave device with address 6BH, receiving control inputs from the master device like micro controller or a digital signal processor through REG00-REG0B. Register read beyond REG0B (0x0B) returns 0xFF. The I2C interface supports both standard mode (up to 100 kbits), and fast mode (up to 400 kbits). connecting to the positive supply voltage via a current source or pull-up resistor. When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain.

8.3.11.1 Data Validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each data bit transferred.

Figure 20. Bit Transfer on the I2C Bus

8.3.11.2 START and STOP Conditions

All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the SCL is HIGH defines a STOP condition. START and STOP conditions are always generated by the mAster. The bus is considered busy after the START condition, and free after the STOP condition.

Figure 21. TS START and STOP conditions

8.3.11.3 Byte Format

Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some other function, it can hold the clock line SCL low to force the mAster into a wait state (clock stretching). Data transfer then continues when the slave is ready for another byte of data and release the clock line SCL.

Product Folder Links: bq25601

Page 29

Slave AddressS 0 ACK Reg Addr ACK S Slave Addr ACK1

1 7 1 1 8 1 1 7 11

PNCKData

118

Slave AddressS 0 ACK Reg Addr ACK Data to Addr ACK P

1 7 1 1 8 1 8 1 1

SCL

START

ACK ACK STOP

ADDRESS DATA ACKDATA

81 - 7

R / W

9 1-7 8 9 81-7 9

SCL

MSB

ACK

1 2 7 8 9

Acknowledgement

signal from slave

Acknowledgement

signal from receiver

START or Repeated

START

S or Sr

STOP or

Repeated

START

P or Sr

1 2 8 9

bq25601

www.ti.com

SLUSCK5 –MARCH 2017

Figure 22. Data Transfer on the I2C Bus

8.3.11.4 Acknowledge (ACK) and Not Acknowledge (NACK)

The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter that the byte was successfully received and another byte may be sent. All clock pulses, including the acknowledge ninth clock pulse, are generated by the mAster. The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH period of this clock pulse.

When SDA remains HIGH during the ninth clock pulse, this is the Not Acknowledge signal. The mAster can then generate either a STOP to abort the transfer or a repeated START to start a new transfer.

8.3.11.5 Slave Address and Data Direction Bit

After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).

Figure 23. Complete Data Transfer

8.3.11.6 Single Read and Write

If the register address is not defined, the charger IC send back NACK and go back to the idle state.

Figure 24. Single Write

Figure 25. Single Read

8.3.11.7 Multi-Read and Multi-Write

Product Folder Links: bq25601

The charger device supports multi-read and multi-write on REG00 through REG0B.

Page 30

Slave AddressS 0 ACK Reg Addr ACK

1 7 1 1 8 1

ACK

PNCKData @ Addr + N

118

Data @ Addr + 1

ACK

Data @ Addr

Slave AddressS 1 ACK

1 7 1 1

Slave AddressS 0 ACK Reg Addr ACK

1 7 1 1 8 1

ACK

PACKData to Addr + N

118

Data to Addr + N

ACK

Data to Addr

bq25601

SLUSCK5 –MARCH 2017

www.ti.com

Figure 26. Multi-Write

Figure 27. Multi-Read

REG09 is a fault register. It keeps all the fault information from last read until the host issues a new read. For example, if Charge Safety Timer Expiration fault occurs but recovers later, the fault register REG09 reports the fault when it is read the first time, but returns to normal when it is read the second time. in order to get the fault information at present, the host has to read REG09 for the second time. The only exception is NTC_FAULT which always reports the actual condition on the TS pin. in addition, REG09 does not support multi-read and multi-write.

Product Folder Links: bq25601

Page 31

bq25601

www.ti.com

8.4 Register Maps

I2C Slave Address: 6BH

8.4.1 REG00

Table 5. REG00 Field Descriptions

Bit Field POR Type Reset Description Comment

EN_HIZ 0 R/W

6 EN_ICHG_MON[1] 0 R/W by REG_RST 00 - Enable STAT pin function

5 EN_ICHG_MON[0] 0 R/W by REG_RST

4 IINDPM[4] 1 R/W by REG_RST 1600 mA Input Current Limit 3 IINDPM[3] 0 R/W by REG_RST 800 mA 2 IINDPM[2] 1 R/W by REG_RST 400 mA 1 IINDPM[1] 1 R/W by REG_RST 200 mA

0 IINDPM[0] 1 R/W by REG_RST 100 mA

by REG_RST by Watchdog

0 – Disable, 1 – Enable

(default) 01 - Reserved 10 - Reserved 11 - Disable STAT pin function (float pin)

Enable HIZ Mode 0 – Disable (default) 1 – Enable

Offset: 100 mA Range: 100 mA (000000) – 3.2 A (11111)

Default:2400 mA (10111), maximum input current limit, not typical. IINDPM bits are changed automatically after input source detection is completed PSEL = Hi = 500 mA PSEL = Lo = 2.4 A Host can over-write IINDPM register bits after input source detection is completed.

SLUSCK5 –MARCH 2017

LEGEND: R/W = Read/Write; R = Read only

Product Folder Links: bq25601

Page 32

bq25601

SLUSCK5 –MARCH 2017

8.4.2 REG01

Table 6. REG01 Field Descriptions

Bit Field POR Type Reset Description Comment

7 PFM _DIS 0 R/W by REG_RST

6 WD_RST 0 R/W

5 OTG_CONFIG 0 R/W

4 CHG_CONFIG 1 R/W

3 SYS_Min[2] 1 R/W by REG_RST 2 SYS_Min[1] 0 R/W by REG_RST

1 SYS_Min[0] 1 R/W by REG_RST

0 Min_V

_SEL 0 R/W by REG_RST

BAT

by REG_RST by Watchdog

0 – Enable PFM 1 – Disable PFM

I2C Watchdog Timer Reset 0 – Normal ; 1 – Reset

0 – OTG Disable 1 – OTG Enable

0 - Charge Disable 1- Charge Enable

System Minimum Voltage

0 – 2.8 V BAT falling, 1 – 2.5 V BAT falling

Default: 0 - Enable Default: Normal (0) Back to 0 after

watchdog timer reset Default: OTG disable (0)

Note:

1. OTG_CONFIG would over-ride Charge Enable Function in CHG_CONFIG

Default: Charge Battery (1) Note:

1. Charge is enabled when both CE pin is pulled low AND CHG_CONFIG bit is 1.

000: 2.6 V 001: 2.8 V 010: 3 V 011: 3.2 V 100: 3.4 V 101: 3.5 V 110: 3.6 V 111: 3.7 V Default: 3.5 V (101)

Minimum battery voltage for OTG mode. Default falling 2.8 V (0); Rising threshold 3.0 V (0)

www.ti.com

LEGEND: R/W = Read/Write; R = Read only

Product Folder Links: bq25601

Page 33

bq25601

www.ti.com

8.4.3 REG02

Table 7. REG02 Field Descriptions

Bit Field POR Type Reset Description Comment

7 BOOST_LIM 1 R/W

6 Q1_FULLON 0 R/W

5 ICHG[5] 1 R/W

4 ICHG[4] 0 R/W

3 ICHG[3] 0 R/W

2 ICHG[2] 0 R/W

1 ICHG[1] 1 R/W

0 ICHG[0] 0 R/W

by REG_RST by Watchdog

by REG_RST 0 – Use higher Q1 RDSON when

by REG_RST by Watchdog

0 = 0.5 A 1 = 1.2 A

programmed IINDPM < 700mA (better accuracy)

1 – Use lower Q1 RDSON always (better efficiency)

1920 mA

960 mA

480 mA

240 mA

120 mA

60 mA

Default: 1.2 A (1) Note:

The current limit options listed are minimum current limit specs.

In boost mode, full FET is always used and this bit has no effect

Fast Charge Current Default: 2040mA (100010)

Range: 0 mA (0000000) – 3000 mA (110010)

Note: I

CHG

to register value 3000 mA (110010))

SLUSCK5 –MARCH 2017

= 0 mA disables charge. > 3000 mA (110010 clamped

LEGEND: R/W = Read/Write; R = Read only

Product Folder Links: bq25601

Page 34

bq25601

SLUSCK5 –MARCH 2017

8.4.4 REG03

Table 8. REG03 Field Descriptions

Bit Field POR Type Reset Description Comment

7 IPRECHG[3] 0 R/W by REG_RST

by Watchdog

6 IPRECHG[2] 0 R/W by REG_RST

by Watchdog

5 IPRECHG[1] 1 R/W by REG_RST

by Watchdog

4 IPRECHG[0] 0 R/W by REG_RST

by Watchdog

3 ITERM[3] 0 R/W by REG_RST

by Watchdog

2 ITERM[2] 0 R/W by REG_RST

by Watchdog

1 ITERM[1] 1 R/W by REG_RST

by Watchdog

0 ITERM[0] 0 R/W by REG_RST

by Watchdog

480 mA

240 mA

120 mA

60 mA

480 mA

240 mA

120 mA

60 mA

Precharge Current Default: 180 mA (0010) Offset: 60 mA

Note: IPRECHG > 780 mA clamped to 780 mA (1100)

Termination Current Default: 180 mA (0010) Offset: 60 mA

LEGEND: R/W = Read/Write; R = Read only

www.ti.com

Product Folder Links: bq25601

Page 35

bq25601

www.ti.com

8.4.5 REG04

Table 9. REG04 Field Descriptions

Bit Field POR Type Reset Description Comment

7 VREG[4] 0 R/W

6 VREG[3] 1 R/W

5 VREG[2] 0 R/W

4 VREG[1] 1 R/W

3 VREG[0] 1 R/W

2 TOPOFF_TIMER[1] 0 R/W

1 TOPOFF_TIMER[0] 0 R/W

0 VRECHG 0 R/W

by REG_RST by Watchdog

512 mV

256 mV

128 mV

64 mV

32 mV

00 – Disabled (Default) 01 – 15 minutes 10 – 30 minutes 11 – 45 minutes

0 – 100 mV 1 – 200 mV

Charge Voltage Offset: 3.856 V Range: 3.856 V to 4.624 V

(11000) Default: 4.208 V (01011) Special Value: (01111): 4.352 V

Note: Value above 11000 (4.624 V) is clamped to register value 11000 (4.624 V)

The extended time following the termination condition is met. When disabled, charge terminated when termination conditions are met

Recharge threshold Default: 100mV (0)

LEGEND: R/W = Read/Write; R = Read only

SLUSCK5 –MARCH 2017

Product Folder Links: bq25601

Page 36

bq25601

SLUSCK5 –MARCH 2017

8.4.6 REG05

Table 10. REG05 Field Descriptions

Bit Field POR Type Reset Description Comment

7 EN_TERM 1 R/W

6 Reserved 0 R/W

5 WATCHDOG[1] 0 R/W

4 WATCHDOG[0] 1 R/W

3 EN_TIMER 1 R/W

2 CHG_TIMER 1 R/W

1 TREG 1 R/W

JEITA_ISET

(0C-10C)

1 R/W

by REG_RST by Watchdog

0 – Disable 1 – Enable

Reserved Reserved

00 – Disable timer, 01 – 40 s, 10 – 80 s,11 – 160 s

0 – Disable 1 – Enable both fast charge and

precharge timer 0 – 5 hrs

1 – 10 hrs Thermal Regulation Threshold:

0 - 90°C 1 - 110°C

0 – 50% of ICHG 1 – 20% of ICHG

Default: Enable termination (1)

Default: 40 s (01)

Default: Enable (1)

Default: 10 hours (1)

Default: 110°C (1)

Default: 20% (1)

www.ti.com

LEGEND: R/W = Read/Write; R = Read only

Product Folder Links: bq25601

Page 37

bq25601

www.ti.com

SLUSCK5 –MARCH 2017

8.4.7 REG06

Table 11. REG06 Field Descriptions

Bit Field POR Type Reset Description Comment

7 OVP[1] 0 R/W by REG_RST

6 OVP[0] 1 R/W by REG_RST

5 BOOSTV[1] 1 R/W by REG_RST Boost Regulation Voltage:

4 BOOSTV[0] 0 R/W by REG_RST

3 VINDPM[3] 0 R/W by REG_RST 800 mV 2 VINDPM[2] 1 R/W by REG_RST 400 mV 1 VINDPM[1] 1 R/W by REG_RST 200 mV 0 VINDPM[0] 0 R/W by REG_RST 100 mV

Default: 6.5V (01)

VAC OVP threshold: 00 - 5.5 V 01 – 6.5 V (5-V input) 10 – 10.5 V (9-V input) 11 – 14 V (12-V input)

00 - 4.85V 01 - 5.00V 10 - 5.15V 11 - 5.30V

Absolute VINDPM Threshold Offset: 3.9 V

Range: 3.9 V (0000) – 5.4 V (1111)

Default: 4.5V (0110)

LEGEND: R/W = Read/Write; R = Read only

Product Folder Links: bq25601

Page 38

bq25601

SLUSCK5 –MARCH 2017

8.4.8 REG07

Table 12. REG07 Field Descriptions

Bit Field POR Type Reset Description Comment

7 IINDET_EN 0 R/W

6 TMR2X_EN 1 R/W

5 BATFET_DIS 0 R/W by REG_RST

JEITA_VSET

(45C-60C)

3 BATFET_DLY 1 R/W by REG_RST

2 BATFET_RST_EN 1 R/W 1 VDPM_BAT_TRACK[1] 0 R/W by REG_RST 00 - Disable function (VINDPM set

0 VDPM_BAT_TRACK[0] 0 R/W by REG_RST

0 R/W

by REG_RST by Watchdog

0 - Not in input current limit detection 1 - Force input current limit detection when VBUS is present

0 – Disable 1 – Safety timer slowed by 2X during input DPM (both V and I) or JEITA cool, or thermal regulation

0 – Allow Q4 turn on, 1 – Turn off Q4 with t (REG07[3])

0 – Set Charge Voltage to 4.1V ( max), 1 – Set Charge Voltage to VREG

0 – Turn off BATFET immediately when BATFET_DIS bit is set 1 –Turn off BATFET after t BATFET_DIS bit is set

0 – Disable BATFET reset function 1 – Enable BATFET reset function

by register) 01 - VBAT + 200mV 10 - VBAT + 250mV 11 - VBAT + 300mV

BATFET_DLY

delay time

(typ. 10 s) when

Returns to 0 after input detection is complete

Default: Allow Q4 turn on(0)

Default: 1 Turn off BATFET after t (typ. 10 s) when BATFET_DIS bit is set

Default: 1 Enable BATFET reset function

Sets VINDPM to track BAT voltage. Actual VINDPM is higher of register value and VBAT + VDPM_BAT_TRACK

www.ti.com

BATFET_DLY

LEGEND: R/W = Read/Write; R = Read only

Product Folder Links: bq25601

Page 39

bq25601

www.ti.com

8.4.9 REG08

Table 13. REG08 Field Descriptions

Bit Field POR Type Reset Description

7 VBUS_STAT[2] x R NA VBUS Status register 6 VBUS_STAT[1] x R NA

5 VBUS_STAT[0] x R NA

4 CHRG_STAT[1] x R NA Charging status:

3 CHRG_STAT[0] x R NA

2 PG_STAT x R NA

1 THERM_STAT x R NA

0 VSYS_STAT x R NA

000: No input 001: USB Host SDP (500 mA) → PSEL HIGH 010: Adapter 2.4A → PSEL LOW 111: OTG Software current limit is reported in IINDPM register

00 – Not Charging 01 – Pre-charge (< V 10 – Fast Charging 11 – Charge Termination

Power Good status: 0 – Power Not Good 1 – Power Good

0 – Not in ther mAl regulation 1 – in ther mAl regulation

0 – Not in VSYSMin regulation (BAT > VSYSMin) 1 – in VSYSMin regulation (BAT < VSYSMin)

LEGEND: R/W = Read/Write

BATLOWV

SLUSCK5 –MARCH 2017

)

Product Folder Links: bq25601

Page 40

bq25601

SLUSCK5 –MARCH 2017

8.4.10 REG09

Table 14. REG09 Field Descriptions

Bit Field POR Type Reset Description

7 WATCHDOG_FAULT x R NA 0 – Normal, 1- Watchdog timer expiration 6 BOOST_FAULT x R NA 5 CHRG_FAULT[1] x R NA

4 CHRG_FAULT[0] x R NA 3 BAT_FAULT x R NA 0 – Normal, 1 – BATOVP 2 NTC_FAULT[2] x R NA JEITA 1 NTC_FAULT[1] x R NA 0 NTC_FAULT[0] x R NA

0 – Normal, 1 – VBUS overloaded in OTG, or VBUS OVP, or battery is too low (any conditions that we cannot start boost function)

00 – Normal, 01 – input fault (VAC OVP or VBAT < VBUS < 3.8 V), 10 Thermal shutdown, 11 – Charge Safety Timer Expiration

000 – Normal, 010 – Warm, 011 – Cool, 101 – Cold, 110 – Hot (Buck mode)

000 – Normal, 101 – Cold, 110 – Hot (Boost mode)

LEGEND: R/W = Read/Write; R = Read only

www.ti.com

Product Folder Links: bq25601

Page 41

bq25601

www.ti.com

8.4.11 REG0A

Table 15. REG0A Field Descriptions

Bit Field POR Type Reset Description

7 VBUS_GD x R NA 6 VINDPM_STAT x R NA 0 – Not in VINDPM, 1 – in VINDPM

5 IINDPM_STAT x R NA 0 – Not in IINDPM, 1 – in IINDPM 4 Reserved x R NA

3 TOPOFF_ACTIVE x R NA

2 ACOV_STAT x R NA

1 VINDPM_INT_ MASK 0 R/W by REG_RST

0 IINDPM_INT_ MASK 0 R/W by REG_RST

0 – Not VBUS attached, 1 – VBUS Attached

0 – Top off timer not counting. 1 – Top off timer counting

0 – Device is NOT in ACOV 1 – Device is in ACOV

0 - Allow VINDPM INT pulse 1 - Mask VINDPM INT pulse

0 - Allow IINDPM INT pulse 1 - Mask IINDPM INT pulse

LEGEND: R/W = Read/Write; R = Read only

SLUSCK5 –MARCH 2017

Product Folder Links: bq25601

Page 42

bq25601

SLUSCK5 –MARCH 2017

8.4.12 REG0B

Table 16. REG0B Field Descriptions

Bit Field POR Type Reset Description

7 REG_RST 0 R/W NA

6 PN[3] x R NA 5 PN[2] x R NA 4 PN[1] x R NA 3 PN[0] x R NA 2 Reserved x R NA 1 DEV_REV[1] x R NA 0 DEV_REV[0] x R NA

0 – Keep current register setting 1 – Reset to default register value and reset safety timer Note: Bit resets to 0 after register reset is completed

bq25601 : 0010

LEGEND: R/W = Read/Write; R = Read only

9 Application and Implementation

NOTE

information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

www.ti.com

9.1 Application information

A typical application consists of the device configured as an I2C controlled power path management device and a single cell battery charger for Li-Ion and Li-polymer batteries used in a wide range of smart phones and other portable devices. It integrates an input reverse-block FET (RBFET, Q1), high-side switching FET (HSFET, Q2), low-side switching FET (LSFET, Q3), and battery FET (BATFET Q4) between the system and battery. The device also integrates a bootstrap diode for the high-side gate drive.

Product Folder Links: bq25601

Page 43

RIPPLE

V D (1 D)

fs L

´ ´ -

bq25601

PHY

Host

SYSTEM

3.5V ± 4.6V

SYSSYS

REGN

47 nF

4.7 µF

10 F10 F

10 F

1 H

1 F

10 F

5.23 k

30.1 k 10 k

2.2 k

VBUS

PMID

STAT

SDA

SCL

INT

PSEL

2.2 k

BTST

REGN

GND

SYS

BAT

QON

Opt.

Optional

VREF

3 x 10 k

VAC

3.9 V ± 13.5 V

bq25601

www.ti.com

9.2 Typical Application Diagram

SLUSCK5 –MARCH 2017

9.2.1 Design Requirements

9.2.2 Detailed Design Procedure

9.2.2.1 inductor Selection

The 1.5-MHz switching frequency allows the use of small inductor and capacitor values to maintain an inductor saturation current higher than the charging current (I

≥ I

CHG

+ (1/2) I

RIPPLE

SAT

The inductor ripple current depends on the input voltage (V frequency (fS) and the inductance (L).

The maximum inductor ripple current occurs when the duty cycle (D) is 0.5 or approximately 0.5. Usually inductor ripple is designed in the range between 20% and 40% maximum charging current as a trade-off between inductor size and efficiency for a practical design.

Figure 28. Power Path Management Application

CHG

Product Folder Links: bq25601

) plus half the ripple current (I

), the duty cycle (D = V

VBUS

RIPPLE

BAT/VVBUS

), the switching

(3)

(4)

Page 44

OUT OUT

V V

V 1

8LCfs

æ ö ç ÷ è ø

RIPPLE

COUT RIPPLE

2 3

= » ´

CIN CHG

bq25601

SLUSCK5 –MARCH 2017

www.ti.com

Typical Application Diagram (continued)

9.2.2.2 input Capacitor

Design input capacitance to provide enough ripple current rating to absorb input switching ripple current. The worst case RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate at 50% duty cycle, then the worst case capacitor RMS current I to 50% and can be estimated using Equation 5.

Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be placed to the drain of the high-side MOSFET and source of the low-side MOSFET as close as possible. Voltage rating of the capacitor must be higher than normal input voltage level. A rating of 25-V or higher capacitor is preferred for 15 V input voltage. Capacitance of 22-μF is suggested for typical of 3A charging current.

9.2.2.3 Output Capacitor

Ensure that the output capacitance has enough ripple current rating to absorb the output switching ripple current.

Equation 6 shows the output capacitor RMS current I

COUT

calculation.

The output capacitor voltage ripple can be calculated as follows:

At certain input and output voltage and switching frequency, the voltage ripple can be reduced by increasing the output filter LC.

The charger device has internal loop compensation optimized for >20μF ceramic output capacitance. The preferred ceramic capacitor is 10V rating, X7R or X5R.

occurs where the duty cycle is closest

Cin

(5)

(6)

(7)

Product Folder Links: bq25601

Page 45

bq25601

www.ti.com

SLUSCK5 –MARCH 2017

10 Power Supply Recommendations

in order to provide an output voltage on SYS, the bq25601 device requires a power supply between 3.9 V and

14.2 V input with at least 100-mA current rating connected to VBUS and a single-cell Li-Ion battery with voltage > V

BATUVLO

the charger to provide maximum output power to SYS.

connected to BAT. The source current rating needs to be at least 3 A in order for the buck converter of

Product Folder Links: bq25601

Page 46

bq25601

SLUSCK5 –MARCH 2017

www.ti.com

11 Layout

11.1 Layout Guidelines

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the components to minimize high frequency current path loop (see Figure 29) is important to prevent electrical and magnetic field radiation and high frequency resonant problems. Follow this specific order carefully to achieve the proper layout.

1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper trace connection or GND plane.

2. Place inductor input pin to SW pin as close as possible. Minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other trace or plane.

3. Put output capacitor near to the inductor and the device. Ground connections need to be tied to the IC ground with a short copper trace connection or GND plane.

4. Route analog ground separately from power ground. Connect analog ground and connect power ground separately. Connect analog ground and power ground together using thermal pad as the single ground connection point. Or using a 0-Ω resistor to tie analog ground to power ground.

5. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the device. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling.

6. Place decoupling capacitors next to the IC pins and make trace connection as short as possible.

7. It is critical that the exposed thermal pad on the backside of the device package be soldered to the PCB ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the other layers.

8. Ensure that the number and sizes of vias allow enough copper for a given current path.

See the EVM user's guide SLUUBL3 for the recommended component placement with trace and via locations. For the VQFN information, refer to SCBA017 and SLUA271.

11.2 Layout Example

Figure 29. High Frequency Current Path

Product Folder Links: bq25601

Page 47

bq25601

www.ti.com

Layout Example (continued)

SLUSCK5 –MARCH 2017

Figure 30. Layout Example

Product Folder Links: bq25601

Page 48

bq25601

SLUSCK5 –MARCH 2017

www.ti.com

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.3 Trademarks

E2E is a trademark of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments.

12.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

Product Folder Links: bq25601

Page 49

bq25601

www.ti.com

SLUSCK5 –MARCH 2017

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: bq25601

Page 50

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status

BQ25601RTWR ACTIVE WQFN RTW 24 3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 85 BQ25601 BQ25601RTWT ACTIVE WQFN RTW 24 250 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 85 BQ25601

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead finish/ Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Samples

Addendum-Page 1

Page 51

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

Page 52

PACKAGE MATERIALS INFORMATION

www.ti.com 17-Oct-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

BQ25601RTWR WQFN RTW 24 3000 330.0 12.4 4.35 4.35 1.1 8.0 12.0 Q2 BQ25601RTWR WQFN RTW 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 BQ25601RTWT WQFN RTW 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

Type

Package

Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

Page 53

PACKAGE MATERIALS INFORMATION

www.ti.com 17-Oct-2020

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

BQ25601RTWR WQFN RTW 24 3000 338.0 355.0 50.0 BQ25601RTWR WQFN RTW 24 3000 367.0 367.0 35.0 BQ25601RTWT WQFN RTW 24 250 210.0 185.0 35.0

Pack Materials-Page 2

Page 54

Page 55

Page 56

Page 57

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable

warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Texas Instruments q25601 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Features

2 Applications

3 Description

Table of Contents

4 Revision History

5 Description (continued)

6 Pin Configuration and Functions

7 Specifications

7.1 Absolute Maximum Ratings

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal information

7.5 Electrical Characteristics

7.6 Typical Characteristics

8 Detailed Description

8.1 Overview

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Power-On-Reset (POR)

8.3.2 Device Power Up from Battery without Input Source

8.3.3 Power Up from Input Source

8.3.3.1 Power Up REGN Regulation

8.3.3.2 Poor Source Qualification

8.3.3.3 Input Source Type Detection

8.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)

8.3.3.5 Converter Power-Up

8.3.4 Boost Mode Operation From Battery

8.3.5 Host Mode and Standalone Power Management

8.3.5.1 Host Mode and Default Mode in bq25601

8.3.6 Power Path Management

8.3.7 Battery Charging Management

8.3.7.1 Autonomous Charging Cycle

8.3.7.2 Battery Charging Profile

8.3.7.3 Charging Termination

8.3.7.4 Thermistor Qualification

8.3.7.5 JEITA Guideline Compliance During Charging Mode

8.3.7.6 Boost Mode Thermistor Monitor during Battery Discharge Mode

8.3.7.7 Charging Safety Timer

8.3.7.8 Narrow VDC Architecture

8.3.7.9 Dynamic Power management

8.3.7.10 Supplement Mode

8.3.8 Shipping Mode and QON Pin

8.3.8.1 BATFET Disable Mode (Shipping Mode)

8.3.8.2 BATFET Enable (Exit Shipping Mode)

8.3.8.3 BATFET Full System Reset

8.3.8.4 QON Pin Operations

8.3.9 Status Outputs (PG, STAT, INT)

8.3.9.1 Power Good indicator (PG Pin and PG_STAT Bit)

8.3.9.2 Charging Status indicator (STAT)

8.3.9.3 Interrupt to Host (INT)

8.3.10 Protections

8.3.10.1 Voltage and Current Monitoring in Converter Operation

8.3.10.2 Voltage and Current Monitoring in Boost Mode

8.3.10.3 Thermal Regulation and Thermal Shutdown

8.3.10.4 Battery Protection

8.3.11 Serial interface

8.3.11.1 Data Validity

8.3.11.2 START and STOP Conditions

8.3.11.3 Byte Format

8.3.11.4 Acknowledge (ACK) and Not Acknowledge (NACK)

8.3.11.5 Slave Address and Data Direction Bit

8.3.11.6 Single Read and Write

8.3.11.7 Multi-Read and Multi-Write

8.4 Register Maps

8.4.1 REG00

8.4.2 REG01

8.4.3 REG02

8.4.4 REG03

8.4.5 REG04

8.4.6 REG05

8.4.7 REG06

8.4.8 REG07

8.4.9 REG08

8.4.10 REG09

8.4.11 REG0A

8.4.12 REG0B