TEXAS INSTRUMENTS PTH12040W Technical data

NOMINAL SIZE = 2.05 in x 1.05 in

(52 mm x 26,7 mm)

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PTH12040W

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SLTS237A–DECEMBER 2004 – REVISED OCTOBER 2005

50-A, 8-V to 14-V INPUT, NON-ISOLATED WIDE-OUTPUT

ADJUST POWER MODULE

FEATURES APPLICATIONS

• 50-A Output Current

• 8-V to 14-V Input Voltage

• Wide-Output Voltage Adjust (0.8 V to 5.5 V)

• Efficiencies up to 96%

• On/Off Inhibit

• Differential Output Sense

• Output Overcurrent Protection

(Nonlatching, Auto-Reset)

• Overtemperature Protection

• Auto-Track™ Sequencing

• Start Up Into Output Prebias

• Margin Up/Down Controls

• Operating Temperature: –40°Cto85°C

• Multi-Phase, Switch-Mode Topology

• Programmable Undervoltage Lockout (UVLO)

• Safety Agency Approvals: UL/cUL 60950,

EN60950, VDE

• Advanced Computing and Server Applications

DESCRIPTION

The PTH12040W is a high-performance 50-A rated, non-isolated, power module, which uses the latest
multiphase switched-mode topology. This provides a small, ready-to-use module, that can power the most densly
populated multiprocessor systems.

Operating from an input voltage range of 8 V to 14 V, the PTH12040W requires a single resistor to set the output
voltage to any value over the range, 0.8 V to 5.5 V. The wide input voltage range makes the PTH12040W
particularly suitable for advanced computing and server applications that utilize a loosely regulated 12-V
intermediate distribution bus.

The modules incorporate a comprehensive list of features. They include on/off inhibit and margin up/down
controls. A differential remote output voltage sense ensures tight load regulation, and an output overcurrent and
overtemperature shutdown protect against most load faults. The programmable under-voltage lockout allows the
turn-on and turn-off voltage thresholds to be customized.

The PTH12040W incorporates Auto-Track™. The Auto-Track feature of the PTH family allows the outputs of
multiple modules to track a common voltage during power up and power down transitions. This simplifies power
up and power down supply-voltage sequencing in a power supply system.

The modules use double-sided surface mount construction to provide a low profile and compact footprint.
Package options include both through-hole and surface mount configurations.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Auto-Track, POLA, TMS320 are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2004–2005, Texas Instruments Incorporated

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PTH12040W

SLTS237A–DECEMBER 2004 – REVISED OCTOBER 2005

These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

STANDARD APPLICATION

Track

Margin Up

Margin Down

C

I

m

560 F
(Required)

2
4
6

8

V

Inhibit

I

19 20

MarginUpMargin

V

I

PTH12040W

UVLO Prog

Inhibit

GND

7

1

18

Track

Down

+Sense

-Sense

GND

3510 13 16

V Adj

O

V

O

17

R
1%

0.05 W

SET

11

9
12
15

14

C1

O

330 F

m

(Required)

+Sense

V

O

C2

O

m

330 F
(Required)

-Sense

L
O
A
D

GND

A. R

= Required to set the output voltage higher than the minimum value (see the elcetrical characheristics for

SET

values.)

B. CI= Required 560-µF electrolytic capacitor. 1000 µF recommended.

C. CO= Required 660-µF (or 680 µF) electrolytic capacitor.

ORDERING INFORMATION

PTH12040W PACKAGE OPTIONS (PTH12040Wxx)

VOLTAGE CODE DESCRIPTION Pb – free and RoHS PACKAGE REF

AH Horizontal T/H Yes EVF

0.8 V – 5.5 V (Adjust) AS Standard SMD

AZ Lead (Pb) – free SMD

(3)

(4)

(1) Add T to end of part number for tape and reel on SMD packages only.
(2) Reference the applicable package reference drawing for the dimensions and PC board layout.
(3) Standardoption specifies 63/37, Sn/Pb pin solder material.
(4) Pb – free option specifies Sn/Ag pin solder material.

Compatible

No EVG

Yes EVG

GND

(1)

(2)

2

PTH12040W

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SLTS237A–DECEMBER 2004 – REVISED OCTOBER 2005

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

UNIT

Signal input voltages Track control (pin 18) –0.3 V to VI+0.3V

T

T

T

T

(1) During soldering of package version, do not elevate peak temperature of the module, pins or internal components above the stated

Operating temperature range over VIrange –40°Cto85°C

A

Wave solder Surface temperature of module body or pins (5 PTH12040WAH 260°C

wave

temperature seconds)

Solder reflow

reflow

temperature

Storage temperature –40°C to 125°C

stg

Surface temperature of module body or pins

PTH12040WAS 235°C

PTH12040WAZ 260°C

Mechanical shock Per Mil-STD-883D, Method 2002.3, 1 msec, 1/2 Sine, mounted 500 G

Mechanical vibration Mil-STD-883D, Method 2007.2, 20–2000 Hz 15 G

Weight 17 grams

Flammability Meets UL94V-O

maximum.

(1)

(1)

(1)

ELECTRICAL CHARACTERISTICS

TA=25°C, VI=12V,VO= 3.3 V, CI= 1000 µF, CO= 660 µF, and IO=IOmax (unless otherwise stated)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

O

V

I

tol Set-point voltage tolerance ±2

V

O

∆Reg

∆Reg

∆Reg

∆Reg

∆Reg

η Efficiency I

V

R

trip Overcurrent threshold Reset, followed by auto-recovery 95 A

I

O

t

rr

∆V

tr

adj Margin up/down adjust With Margin up/down control ±5%

V

O

margin Margin input current Pin to GND –8

I

IL

I

track Track input current (pin 18) Pin to GND –0.10

IL

dV

track

Output current 60°C, 200 LFM airflow 0 50

Input voltage range Over IOrange 8

Temperature variation –40°C<TA<85°C ±0.5 %V

temp

Line regulation Over VIrange ±5mV

line

Load regulation Over IOrange ±5mV

load

Total output variation Includes set-point, line, load, –40°C ≤ TA≤ 85°C ±3

tot

Output adjust range 0.8 5.5

adj

= 205 Ω,VO= 5.0 V 96%

R

SET

=1.5kΩ,VO= 3.3 V 95%

R

SET

=3.01kΩ,VO= 2.5 V 93%

R

SET

=4.99kΩ,VO= 2.0 V 92%

R

SET

=35A R

O

=6.34kΩ,VO= 1.8 V 91%

SET

=9.76kΩ,VO= 1.5 V 90%

R

SET

= 18.2 kΩ,VO= 1.2 V 88%

R

SET

= 38.3 kΩ,VO= 1.0 V 86%

R

SET

= open circuit, VO= 0.8 V 82%

R

SET

(2)

VOripple (pk-pk) 20 MHz bandwidth All voltages 15 mVpp

Transient response 1 A/µs load step, 50 to 100% I

max, CO= 660 µF

O

Recovery time 70 µSec

VOover/undershoot 150 mV

(4)

/dt Track slew rate capability |V

TRACK–VO

| ≤ 50 mV and V

TRACK<VO

(nom) 1 V/ms

(1)

14 V

(2)

(2)

(3)

(5)

%V

%V

mA

A

O

O

O

V

µA

(1) See SOA curves or consult factory for appropriate derating.
(2) The set-point voltage tolerance is affected by the tolerance of R

with 100 ppm/°C or better temperature stability.

. The stated limit is unconditionally met if R

SET

has a tolerance of 1%

SET

(3) When the set-point voltage is adjusted higher than 3.6 V, a 10-V minimum input voltage is recommended.
(4) A small, low-leakage (<100 nA) MOSFET is recommended to control this pin. The open-circuit voltage is less than 1 Vdc.
(5) This control pin has an internal pull-up to 6.7 V. If left open-circuit, the module operates when input power is applied. A small, low

leakage (<100 nA) MOSFET or open-drain/collector voltage supervisor IC is recommended for control. See the Application Information
section for further guidance.

3

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PTH12040W

SLTS237A–DECEMBER 2004 – REVISED OCTOBER 2005

ELECTRICAL CHARACTERISTICS (continued)

TA=25°C, VI=12V,VO= 3.3 V, CI= 1000 µF, CO= 660 µF, and IO=IOmax (unless otherwise stated)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

UVLO Undervoltage lockout Pin 8 open On-threshold 7.5

Hysterisis 1

Inhibit control (pin 7) Referenced to GND

V

IH

V

IL

inhibit Input low current Pin to GND 0.5 mA

I

IL

inh Input standby current Inhibit (pin 7) to GND 35 mA

I

I

f

s

C

I

C

O

Input high voltage 2.5 Open

Input low voltage –0.2 0.5

Switching frequency Over VIand IOranges 0.9 1.05 1.2 MHz

External input capacitance 560

External output capacitance Ceramic 400

Capacitance value µF

Nonceramic 660

Equivalent series resistance (non-ceramic) 2

MTBF Reliability Per Bellcore TR-332 50% stress, T

=40°C, ground benigh

A

(6) Default voltages may be adjusted using the UVLO Prog control input. See the Application Information section for further guidance.
(7) This control pin has an internal pull-up to 5 V nominal. If it is left open-circuit, the module operates when input power is applied. A small,

low-leakage (<100 nA) MOSFET is recommended for control. For further information, see the related application note.

(8) A minimum capacitance of 560-µF is required at the input for proper operation. For best results, 1000 µF is recommended. The

capacitance must be rated for a minimum of 300 mArms of ripple current.

(9) A minimum value of output capacitance is required for proper operation. Adding additional capacitance at the load further improves

transient response.

(10) This is the calculated maximum. The minimum ESR requirement often results in a lower value. See the Application Information section

for further guidance.

(11) This is the typcial ESR for all the electrolytic (nonceramic) output capacitance. Use 4 mΩ as the minimum when using max-ESR values

to calculate.

(6)

(6)

(8)

1000 µF

(9)

(11)

14000

2.5

(10)

V

(7)

V

mΩ

6

10

Hrs

4

PTH12040W

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SLTS237A–DECEMBER 2004 – REVISED OCTOBER 2005

DEVICE INFORMATION

TERMINAL FUNCTIONS

TERMINAL

NAME NO.

GND

V

I

V

O

1, 3, 5, 10, 13, The common ground connection for the VIand VOpower connections. It is also the 0 Vdcreference for

16 the control inputs.

2, 4, 6 The positive input voltage power node to the module, which is referenced to common GND.

9, 12, 15 The regulated positive power output with respect to the GND node.

The Inhibit pin is an open-collector/drain negative logic input that is referenced to GND. Applying a

Inhibit

(1)

7

lowlevel ground signal to this input disables the module’s output and turns off the output voltage. When
the Inhibit control is active, the input current drawn by the regulator is significantly reduced. If the Inhibit
pin is left open-circuit, the module produces an output whenever a valid input source is applied.

A 1%, 0.05-W resistor must be connected between this pin and GND to set the output voltage higher
than the minimum value. The set-point range for the output voltage is from 0.8 V to 5.5 V. The resistor

VOAdjust 17 required for a given output voltage may be calculated from the following formula. If left open circuit, the

module output defaults to its lowest output voltage value. For further information on the adjustment
and/or trimming of the output voltage, see the related Application Information section.

R

set

+ 10 kW

0.8 V

VO* 0.8 V

* 1.696 kW

The specification table gives the preferred resistor values for a number of standard output voltages.

The sense inputs allow the regulation circuit to compensate for voltage drop between the module and

+Sense 11 the load. For optimal voltage accuracy, +Sense should be connected to VO. If it is left open, a low-value

internal resistor ensures that the output remains in regulation.

–Sense 14

For optimal voltage accuracy, –Sense should be connected to the ground return at the load. If it is left
open, a low-value internal resistor ensures that the output remains in regulation.

Connecting a resistor from this pin to signal ground allows the on threshold of the input undervoltage

UVLO Prog 8

lockout (UVLO) to be adjusted higher than the default value. The hysterisis can also be independenly
reduced by connecting a second resistor from this pin to VI. For further information, see the Application
Information section.

This is an analog control input that allows the output voltage to follow another voltage during power up
and power down sequences. The pin is active from 0 V, up to the nominal set-point voltage. Within this

Track 18

range, the module output follows the voltage at the Track pin on a volt-for-volt basis. When the control
voltage is raised above this range, the module regulates at its nominal output voltage. If unused, this
input should be connected to VIfor a faster power up. For further information, see the Application
Information section.

Margin

(1)

Down

Margin Up

20 requires an open-collector (open-drain) interface. It is not TTL compatible. A lower percent change can

(1)

19 collector (open-drain) interface. It is not TTL compatible. The percent change can be reduced with a

When this input is asserted to GND, the output voltage is decreased by 5% from the nominal. The input

be accommodated with a series resistor. For further information, see the Application Information section.

When this input is asserted to GND, the output voltage is increased by 5%. The input requires an open

series resistor. For further information, see the Application Information section.

(1) Denotes negative logic: Open = Normal operation / Ground = Function active

DESCRIPTION

17

18

19

20

16

15

13

14

PTHXX040W

1

2

3

12

(Top View)

4

5

891011

7

6

5

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2

4

6

8

10

12

14

I

O

- Output Current - A

VO=5V

VO= 3.3 V

V

O

= 1.8 V

VO= 1.2 V

VO= 0.8 V

01020304050

0

- Power Dissipation - W

P

D

PTH12040W

SLTS237A–DECEMBER 2004 – REVISED OCTOBER 2005

TYPICAL CHARACTERISTICS

Characteristic Data (VI=12V)

EFFICIENCY POWER DISSIPATION

vs vs

LOAD CURRENT LOAD CURRENT

100

VO= 3.3 V

90

VO=5V

(1)(2)

80

VO= 0.8 V

70

Efficiency - %

60

50

0 1020 3040 50

I - Output Current - A

O

VO= 1.8 V

VO= 1.2 V

Figure 1. Figure 2.

TEMPERATURE DERATING TEMPERATURE DERATING

vs vs

OUTPUT CURRENT OUTPUT CURRENT

90

80

o

70

60

50

40

- Ambient Temperature - C
A

T

30

20

01020304050

400 LFM

200 LFM

100 LFM

Nat Conv

VO= 3.3 V

IO- Output Current - A

90

80

o

70

60

50

40

- Ambient Temperature - C
A

T

30

20

01020304050

400 LFM

200 LFM

100 LFM

Nat Conv

I

- Output Current - A

O

VO= 1.2 V

Figure 3. Figure 4.

(1) The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the

converter. Applies to Figure 1 and Figure 2.

(2) The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum

operating temperatures. Derating limits apply to modules soldered directly to a 4-mm x 4-mm, double-sided PCB with 1-oz. copper. For
surface mount packages (AS and AZ suffix), multiple vias (plated through holes) are required to add thermal paths around the power
pins. Please refer to the mechanical specification for more information. Applies to Figure 3 and Figure 6.

6

0

2

4

6

8

10

12

VO= 3.3 V

VO= 1.8 V

VO= 1.2 V

VO= 0.8 V

01020304050

P Power Dissipation - W

D

-

I - Output Current - A

O

PTH12040W

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TYPICAL CHARACTERISTICS

Characteristic Data (VI=8V)

(4)(5)

(continued)

(3)

SLTS237A–DECEMBER 2004 – REVISED OCTOBER 2005

EFFICIENCY POWER DISSIPATION

vs vs

LOAD CURRENT LOAD CURRENT

100

90

80

70

Efficiency - %

60

50

40

VO= 0.8 V

01020304050

I - Output Current - A

O

VO= 3.3 V

VO= 1.8 V

VO= 1.2 V

Figure 5. Figure 6.

(3) The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the

converter. Applies to Figure 5 , and Figure 6.

7

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PTH12040W

SLTS237A–DECEMBER 2004 – REVISED OCTOBER 2005

APPLICATION INFORMATION

Capacitor Recommendations for the PTH12040W Power Module

The PTH12040W is a state-of-the-art multi-phase power converter topology that uses three parallel switching and
filter inductor paths between the common input and output filter capacitors. The three paths share the load
current, operate at the same frequency, and are evenly displaced in phase.

With multiple switching paths the transient output current capability is significantly increased. This reduces the
amount of external output capacitance required to support a load transient. As a further benefit, the ripple
current, as seen by the input and output capacitors, is reduced in magnitude and effectively tripled in frequency.

Input Capacitor

The improved transient response of a multi-phase converter places a bigger burden on the transient capability of
the input source. The size and value of the input capacitor is therefore determined by this converter’s transient
performance capability. The minimum amount of input capacitance required is 560 µF, with an RMS ripple
current rating of 300 mA. This minimum value assumes that the converter is supplied with a responsive, low
inductance input source. This source should have ample capacitive decoupling, and be distributed to the
converter via PCB power and ground planes. For high-performance applications, or wherever the transient
performance of the input source is limited, 1000 µF of input capacitance is recommended.

Ripple current, less than 100 mΩ of equivalent series resistance (ESR), and temperature are the main
considerations when selecting input capacitors. The ripple current reflected from the input of the PTH12040W
module is moderate to low. Therefore any good quality, computer-grade electrolytic capacitor, of either value
suggested, has an adequate ripple current rating.

Regular tantalum capacitors are not recommended for the input bus. These capacitors require a recommended
minimum voltage rating of 2 × (maximum dc voltage + ac ripple). This is standard practice to ensure reliability. No
tantalum capacitors were found with a sufficient voltage rating to meet this requirement. When the operating
temperature is below 0°C, the ESR of aluminum electrolytic capacitors increases. For these applications,
Os-Con, polyaluminum, and polymer-tantalum types should be considered. Adding one or two ceramic capacitors
to the input reduces high-frequency reflected ripple current.

Output Capacitors

The PTH12040W requires a minimum output capacitance of 660 µF (or 2 × 330 µF), with an ESR of 15 mΩ to
40 mΩ. This is necessary for the stable operation of the regulator. Additional capacitance can be added to
improve the module's performance to load transients. High quality computer-grade electrolytic capacitors are
recommended. Aluminum electrolytic capacitors provide adequate decoupling over the frequency range, 2 kHz to
150 kHz, and are suitable when ambient temperatures are above 0°C. For operation below 0°C, tantalum,
ceramic, or Os-Con type capacitors are necessary.

When using a combination of one or more nonceramic capacitors, the calculated equivalent ESR should be no
lower than 2 mΩ (4 mΩ when calculating using the manufacturer’s maximum ESR values). A list of preferred
low-ESR type capacitors are identified in Table 1.

Ceramic Capacitors

Above 150 kHz the performance of aluminum electrolytic capacitors is less effective. Multilayer ceramic
capacitors have very low ESR and a resonant frequency higher than the bandwidth of the regulator. They can be
used to reduce the reflected ripple current at the input as well as improve the transient response of the output.
When used on the output their combined ESR is not critical as long as the total value of ceramic capacitors, with
values between 10 µF and 100 µF, does not exceed 400 µF. Also, to prevent the formation of local resonances,
do not place more than five identical ceramic capacitors in parallel with values of 10 µF or greater.

8

PTH12040W

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SLTS237A–DECEMBER 2004 – REVISED OCTOBER 2005

APPLICATION INFORMATION (continued)

Tantalum Capacitors

Tantalum type capacitors are only used on the output bus, and are recommended for applications where the
ambient operating temperature is less than 0°C. The AVX TPS, Sprague 593D/594/595 and Kemet T495/T510
capacitor series are suggested over many other tantalum types due to their higher rated surge, power
dissipation, and ripple current capability. As a caution, many general purpose tantalum capacitors have higher
ESR, reduced power dissipation, and lower ripple current capability. These capacitors are also less reliable due
to their reduced power dissipation and surge current ratings. Tantalum capacitors that have no stated ESR or
surge current rating are not recommended for power applications.

When specifying Os-con and polymer-tantalum capacitors for the output, the minimum ESR limit is encountered
well before the maximum capacitance value is reached.

Capacitor Table

Table 1 identifies the characteristics of capacitors from a number of vendors with acceptable ESR and ripple

current (rms) ratings. The recommended number of capacitors required at both the input and output buses is
identified for each capacitor type.

Note: This is not an extensive capacitor list. Capacitors from other vendors are available with comparable
specifications. Those listed are for guidance. The RMS ripple current rating and ESR (at 100 kHz) are critical
parameters necessary to insure both optimum regulator performance and long capacitor life.

Designing for Very Fast Load Transients

The transient response of the dc/dc converter has been characterized using a load transient with a di/dt of
1 A/µs. The typical voltage deviation for this load transient is given in the data sheet specification table using the
mnimum required value of output capacitance. As the di/dt of a transient is increased, the response of a
converter’s regulation circuit ultimately depends on its output capacitor decoupling network. This is an inherent
limitation with any dc/dc converter once the speed of the transient exceeds its bandwidth capability. If the target
application specifies a higher di/dt or lower voltage deviation, the requirement can only be met with additional
output capacitor decoupling. In these cases special attention must be paid to the type, value and ESR of the
capacitors selected.

9