ELECTRICAL CHARACTERISTICS
PTH08T240F
SLTS277 – DECEMBER 2006
PTH08T240F
TA= 25 ° C, VI= 5 V, VO= 1.0 V, CI= 330 µF, CO= 1000 µF, and IO= IOmax (unless otherwise stated)
PARAMETER TEST CONDITIONS PTH08T240F UNIT
MIN TYP MAX
I
O
Output current Over VOrange 25 ° C, natural convection 0 10 A
11 ×
0.69 ≤ VO≤ 1.2 4.5
V
O
(1)
V
I
Input voltage range Over IOrange V
1.2 < VO≤ 2.0 4.5 14
V
OADJ
Output voltage adjust range Over IOrange 0.69 2.0 V
Set-point voltage tolerance ± 0.5 ± 1
(2)
%V
o
Temperature variation –40 ° C < TA< 85 ° C ± 0.3 %V
o
V
O
Line regulaltion Over VIrange ± 3 mV
Load regulation Over IOrange ± 2 mV
Total output variation Includes set-point, line, load, –40 ° C ≤ TA≤ 85 ° C ± 1.5
(2)
%V
o
R
SET
= 4.78 k Ω , VO= 1.8 V 90%
R
SET
= 7.09 k Ω , VO= 1.5 V 88%
η Efficiency IO= 10 A
R
SET
= 12.1 k Ω , VO= 1.2 V 87%
R
SET
= 20.8 k Ω , VO= 1.0 V 85%
VORipple (peak-to-peak) 20-MHz bandwidth 10
(3)
mV
PP
I
LIM
Overcurrent threshold Reset, followed by auto-recovery 20 A
t
tr
Recovery time tbd µs
w/o TurboTrans
CO= 1000 µ F, Type C
∆ V
tr
2.5 A/µs load step VOover/undershoot tbd mV
Transient response 50 to 100% IOmax
t
trTT
w/ TurboTrans Recovery time tbd µs
VO= 2.5 V
CO= tbd µ F, Type C,
mV
∆ V
trTT
VOover/undershoot tbd
RTT = tbd Ω
I
IL
Track input current (pin 10) Pin to GND –130
(4)
µA
dV
track
/dt Track slew rate capability CO≤ CO(max) 1 V/ms
VIincreasing, R
UVLO
= OPEN 4.3 4.45
Adjustable Under-voltage lockout
UVLO
ADJ
VIdecreasing, R
UVLO
= OPEN 4.0 4.2 V
(pin 11)
Hysteresis, R
UVLO
≤ 52.3 k Ω 0.5
Input high voltage (VIH) Open
(5)
V
Inhibit control (pin 11) Input low voltage (VIL) -0.2 0.8
Input low current (IIL), Pin 11 to GND -235 µA
I
in
Input standby current Inhibit (pin 11) to GND, Track (pin 10) open 5 mA
f
s
Switching frequency Over VIand IOranges, SmartSync (pin 1) to GND 260 300 340 kHz
Synchronization (SYNC)
f
SYNC
240 400 kHz
frequency
V
SYNCH
SYNC High-Level Input Voltage 2 5.5 V
V
SYNCL
SYNC Low-Level Input Voltage 0.8 V
t
SYNC
SYNC Minimum Pulse Width 200 nSec
Nonceramic 330
(6)
C
I
External input capacitance µF
Ceramic 22
(6)
(1) The maximum input voltage is duty cycle limited to (VO× 11) or 14 volts, whichever is less. The maximum allowable input voltage is a
function of switching frequency, and may increase or decrease when the SmartSync feature is utilized. Please review the SmartSync
section of the Application Information for further guidance.
(2) The set-point voltage tolerance is affected by the tolerance and stability of R
SET
. The stated limit is unconditionally met if R
SET
has a
tolerance of 1% with 100 ppm/°C or better temperature stability.
(3) For output voltages less than 1.7 V, the ripple may increase (up to 2 × ) when operating at input voltages greater than (VO× 11). See the
SmartSync section of the Application Information for input voltage and frequency limitations.
(4) A low-leakage (<100 nA), open-drain device, such as MOSFET or voltage supervisor IC, is recommended to control pin 10. The
open-circuit voltage is less than 8 Vdc.
(5) This control pin has an internal pull-up. Do not place an external pull-up on this pin. If it is left open-circuit, the module operates when
input power is applied. A small, low-leakage (<100 nA) MOSFET is recommended for control. For additional information, see the related
application information section.
(6) A 330 µF electrolytic input capacitor is required for proper operation. The electrolytic capacitor must be rated for a minimum of 500 mA
rms of ripple current.
4
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