TEXAS INSTRUMENTS PTH03010Y Technical data

(34,8 mm x 15,75 mm)

1.37 in x 0.62 in

Nominal Size

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PTH03010Y
PTH05010Y
PTH12010Y

SLTS223A–MARCH 2004 – REVISED OCTOBER 2005

15-A NON-ISOLATED DDR/QDR

MEMORY BUS TERMINATION MODULES

FEATURES

• VTTBus Termination Output
(Output Tracks the System V

• 15 A Output Current (12 A for 12-V Input)

• 3.3-V, 5-V or 12-V Input Voltage

• DDR and QDR Compatible

REF

)

• Efficiencies up to 91%

• Output Overcurrent Protection

(Nonlatching, Auto-Reset)

• 62 W/in3Power Density

• Safety Agency Approvals

UL/cUL60950, EN60950, VDE

• On/Off Inhibit (for VTTStandby) • Point-of-Load Alliance (POLA™) Compatible

• Undervoltage Lockout

• Operating Temperature: –40°Cto85°C

DESCRIPTION

The PTHxx010Y are a series of ready-to-use switching regulator modules from Texas Instruments designed
specifically for bus termination in DDR and QDR memory applications. Operating from either a 3.3-V, 5-V or 12-V
input, the modules generate a VTToutput that will source or sink up to 15 A of current (12 A for 12-V input) to
accurately track their V
voltage for the memory and chipset bus receiver comparators. V
voltage.

Both the PTHxx010Y series employs an actively switched synchronous rectifier output to provide state-of-the-art
stepdown switching conversion. The products are small in size (1.37 in × 0.62 in), and are an ideal choice where
space, performance, and high efficiency are desired, along with the convenience of a ready-to-use module.

Operating features include an on/off inhibit and output over-current protection (source mode only). The on/off
inhibit feature allows the VTTbus to be turned off to save power in a standby mode of operation. To ensure tight
load regulation, an output remote sense is also provided. Package options include both throughhole and surface
mount configurations.

input. VTTis the required bus termination supply voltage, and V

REF

is usually set to half the V

REF

is the reference

REF

power supply

DDQ

V

IN

V

DDQ

1 k
1 %

1 k
1 %

C

IN

(Required)

Q

1

GND

BSS138
(Optional)

Standby

CIN = Required Capacitor; 470 µF (3.3 ± 5 V Input), 560 µF (12 V Input).
Co1 = Required Low-ESR Electrolyitic Capacitor; 470 µF (3.3 ± 5 V Input), 940 µF (12 V Input).
Co2 = Ceramic Capacitance for Optimum Response to a 3 A (± 1.5 A) Load Transient; 200 µF (3.3 ± 5 V Input), 400 µF (12 V Input).
Con = Distributed hf-Ceramic Decoupling Capacitors for VTT bus; as Recommended for DDR Memory Applications.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

POLA is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

STANDARD APPLICATION

10 9 8

1

PTHxx010Y

(Top View)

2

54

3

7

6

Co

1

Low−ESR
(Required)

Co

2

Ceramic
(Optional)

V

REF

V

TT

Co

n

hf−Ceramic

V

TT

Termination Island

SSTL−2

Bus

Copyright © 2004–2005, Texas Instruments Incorporated

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PTH03010Y
PTH05010Y
PTH12010Y

SLTS223A–MARCH 2004 – REVISED OCTOBER 2005

ORDERING INFORMATION

PTHXX010Y (Base Part Number)

Input Voltage Part Number

PTH03010YAH Horizontal T/H Yes

3.3 V PTH03010YAS Standard SMD No

PTH03010YAZ Optional SMD Yes

PTH05010YAH Horizontal T/H Yes

5 V PTH05010YAS Standard SMD No

PTH05010YAZ Optional SMD Yes

PTH12010YAH Horizontal T/H Yes

12 V PTH12010YAS Standard SMD No

PTH12010YAZ Optional SMD Yes

(1) Add T to end of part number for tape and reel on SMD packages only.
(2) Reference the applicable package reference drawing for the dimensions and PC board layout.
(3) Lead (Pb) –free option specifies Sn/Ag pin solder material.
(4) Standard option specifies 63/37, Sn/Pb pin solder material.

(1)

DESCRIPTION Pb – free and Mechanical Package

RoHS

(2)

(3)

(4)

(3)

(3)

(4)

(3)

(3)

(4)

(3)

EUH

EUJ

EUJ

EUH

EUJ

EUJ

EUH

EUJ

EUJ

ENVIRONMENTAL AND ABSOLUTE MAXIMUM RATINGS

voltages are with respect to GND

UNIT

V

T

T

T

T

(1) For operation below 0°C the external capacitors must bave stable characteristics, use either a low ESR tantalum, Os-Con, or ceramic

(2) During soldering of package version, do not elevate peak temperature of the module, pins or internal components above the stated

Control input voltage –0.3 V to Vin+03 V

REF

Operating temperature Over VINrange –40°Cto85°C

A

range

Wave solder temperature Surface temperature of module body or pins PTHXX010YAH 260°C

wave

Solder reflow temperature Surface temperature of module body or pins

reflow

Storage temperature –40°C to 125°C

s

(5 seconds)

PTHXX010YAS 235°C

PTHXX010YAZ 260°C

Mechanical shock Per Mil-STD-883D, Method 2002.3 1 msec, 1/2 Sine, mounted 500 G

Mechanical vibration Mil-STD-883D, Method 2007.2 20-2000 Hz 20 G

Weight 3.7 grams

Flammability Meets UL 94V-O

capacitor.

maximum.

(1)

(2)

(2)

(2)

2

PTH03010Y
PTH05010Y

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SLTS223A–MARCH 2004 – REVISED OCTOBER 2005

ELECTRICAL SPECIFICATIONS

TA=25°C; nominal VIN;V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

O

V

IN

∆V

REF

|V

TT–VREF

η Efficiency I

V

r

trip Overcurrent threshold A

I

o

t

tr

V

tr

UVLO Under-voltage lockout

V

IH

V

IL

I

inhibit Pin to GND 130 µA

IL

inh Input standby current Inhibit (pin 3) to GND 10 mA

I

IN

f

s

C

IN

CO1, CO2 External output capacitance PTH03010Y/PTH05010Y 200

MTBF Reliability Per Bellcore TR-332 50 % stress, T

Output current Over ∆V

Input voltage range Over IOrange PTH05010Y 4.5 5.5 V

Tracking range for V

| Tracking tolerance to V

VoRipple (pk-pk) 20 MHz bandwidth 20 mVpp

Load transient response

Inhibit control (pin 4) V
Input high voltage

Inhibit control (pin 4) –0.2 0.6
Input low voltage

Inhibit control (pin 4)
Input low curent

Switching frequency Over VINand IOranges kHz

External input capacitance µF

=1.25V;CIN,CO1, and CO2 = typical values; and IO=IOmax (unless otherwise stated)

REF

REF

range

PTH03010Y/PTH05010Y 0 ±15

PTH12010Y ±12

PTH03010Y 2.95 3.65

PTH12010Y 10.8 13.2

REF

REF

Over line, load and temperature –10 10 mV

0.55 1.8 V

PTH03010Y 88%

= 10 A PTH05010Y 88%

o

PTH12010Y 85%

Reset, followed by auto recovery PTH03010Y/PTH05010Y 27.5

PTH12010Y 20

15 A/µs load step, from –1.5 A to

1.5 A

Recovery time 30 µsec

VOover/undershoot 30 40 mV

PTH03010Y 2.45 2.8

Increasing PTH05010Y 4.3 4.45 V

V

IN

PTH12010Y 9.5 10.4

PTH03010Y 2.0 2.40

Dncreasing PTH05010Y 3.4 3.7 V

V

IN

PTH12010Y 8.8 9

–0.5 Open

IN

Referenced to GND

PTH03010Y/PTH05010Y 250 300 350

PTH12010Y 200 250 300

PTH03010Y/PTH05010Y 470

PTH12010Y 560

Capacitance value: Nonceramic µF

Capacitance value: Ceramic µF

PTH03010Y/PTH05010Y 470

PTH12010Y 940

PTH12010Y 400

Equiv. series resistance (non-ceramic) 4

=40°C, ground benign 6

A

(3)

(3)

(4)

(4)

(6)

PTH12010Y

(1)

(1)

(2)

(5)

8200

(5)

6600

(4)

300

(4)

600

A

V

V

mΩ

6

10

Hrs

(1) Rating is conditional on the module being directly soldered to a 4-layer PCB with 1 oz. copper. See the SOA curves or contact the

factory for appropriate derating.

(2) This control pin has an internal pull-up to the input voltage V

applied. A small low-leakage (<100 nA) MOSFET is recommended for control. For further information, consult the related application

. If it is left open-circuit the module will operate when input power is

IN

note.

(3) An input capacitor is required for proper operation. The capacitor must be rated for a minimum a minimum of 500 mA rms( 750 mA rms

for 12-V input) of ripple current.

(4) The minimum value of external output capacitance value ensures that VTTmeets the specified transient performance requirements for

the memory bus terminations. Lower values of capacitance may be possible when the measured peak change in output current is
consistently less than 3 A.

(5) This is the calculated maximum. The minimum ESR limitation will often result in a lower value. Consult the application notes for further

guidance.

(6) This is the typcial ESR for all the electrolytic (non-ceramic) output capacitance. Use 7 mΩ as the minimum when using max-ESR values

to calculate.

3

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PTH03010Y
PTH05010Y
PTH12010Y

SLTS223A–MARCH 2004 – REVISED OCTOBER 2005

TERMINAL

NAME NO.

V

IN

GND 1, 7

V

REF

V

TT

VoSense 5

Inhibit 3

N/C 4, 9, 10 No connection

DESCRIPTION

2 The positive input voltage power node to the module, which is referenced to common GND.

This is the common ground connection for the VINand VTTpower connections. It is also the 0-VDC reference
for the control inputs.

The module senses the voltage at this input to regulate the output voltage, VTT. The voltage at V
the reference voltage for the system bus receiver comparators. It is normally set to precisely half the bus

8 driver supply voltage (V

V

pin should not exceed 500 Ω. See the Typical DDR Application Diagram in the Application Information

REF

section for reference.

This is the regulated power output from the module with respect to the GND node, and the tracking
termination supply for the application data and address buses. It is precisely regulated to the voltage applied

6

to the module's V
module. Once active it will track the voltage applied at V

The sense input allows the regulation circuit to compensate for voltage drop between the module and the
load. For optimal voltage accuracy VoSense should be connected to VTT.

The Inhibit pin is an open-collector/drain negative logic input that is referenced to GND. Applying a low-level
ground signal to this input turns off the output voltage, VTT. Although the module is inhibited, a voltage, V
will be present at the output terminals, fed through the DDR memory. When the Inhibit is active, the input
current drawn by the regulator is significantly reduced. If the Inhibit pin is left open circuit, the module will
produce an output whenever a valid input source is applied. See the Typical DDR Application Diagram in the
Application Information section for reference.

Terminal Functions

÷ 2), using a resistor divider. The Thevenin impedance of the network driving the

DDQ

input, and is active active about 20 ms after a valid input source is applied to the

REF

REF

.

REF

is also

DDQ

1

2

10 9 8

PTHXX010

(Top View)

7

6

543

4

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20

30

40

50

60

70

80

90

400 LFM

200 LFM

100 LFM

Nat Conv

234 80

I

L

− Load Current − A

106

VIN = 12 V

T

A

− Ambient Temperature −

5

C

10 0

90

80

70

Efficiency − %

60

SLTS223A–MARCH 2004 – REVISED OCTOBER 2005

TYPICAL CHARACTERISTICS (V

=1.25V)

REF

(1)(2)

EFFICIENCY OUTPUT RIPPLE POWER DISSIPATION

vs vs vs

LOAD CURRENT LOAD CURRENT LOAD CURRENT

VIN = 3.3 V

VIN = 5 V

VIN = 12 V

Output Ripple − mV

60

50

40

30

20

10

VIN = 3.3 V

VIN = 12 V

VIN = 5 V

5

4

3

2

− Power Dissipation − W
D

P

VIN = 5 V

1

PTH03010Y
PTH05010Y
PTH12010Y

VIN = 12 V

VIN = 3.3 V

50

36912150

IL − Load Current − A

0

36912150

I

− Load Current − A

L

0

3692150

IL − Load Current − A

Figure 1. Figure 2. Figure 3.

PTH03010Y/PTH05010Y AT PTH12010Y ONLY; VIN=12V

NOMINAL V

TEMPERATURE DERATING vs LOAD CURRENT

IN

TEMPERATURE DERATING

vs LOAD CURRENT

90

80

C

5

− Ambient Temperature −
T

Nat Cinv

70

60

50

40

A

30

20

100 LFM

200 LFM

3 6912150

I

− Load Current − A

L

400 LFM

Figure 4. Figure 5.

(1) The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the

converter. Applies to Figure 1, Figure 2, and Figure 3.

(2) The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum

operating temperatures. Derating limits apply to modules soldered directly to a 4 in x 4 in double-sided PCB with 1 oz. copper. For
surface mount packages (AS and AZ suffix), multiple vias (plated through holes) are required to add thermal paths around the power
pins. Please refer to the mechanical specification for more information. Applies to Figure 4, and Figure 5.

5

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PTH03010Y
PTH05010Y
PTH12010Y

SLTS223A–MARCH 2004 – REVISED OCTOBER 2005

TYPICAL CHARACTERISTICS

TRANSIENT PERFORMANCE FOR ∆3-A LOAD CHANGE

PTH03010Y/PTH05010Y: SOURCE-SINK-SOURCE PTH12010Y: SOURCE-SINK-SOURCE TRANSIENT

TRANSIENT

VTT − V

(50 mV/div)

(2A/div)

I

TT

REF

100 ms/div

VTT − V

(50 mV/div)

(2A/div)

I

TT

REF

100 ms/div

Figure 6. Figure 7.

6