Texas Instruments PGA309-HT Datasheet

PGA309-HT

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VOLTAGE OUTPUT PROGRAMMABLE SENSOR CONDITIONER

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FEATURES

• Complete Bridge Sensor Conditioner

• Voltage Output: Ratiometric or Absolute

• Digital Cal: No Potentiometers/Sensor Trims

• Sensor Error Compensation – Span, Offset, and Temperature Drifts

• Low Error, Time-Stable

• Sensor Linearization Circuitry

• Temperature Sense: Internal or External

• Calibration Lookup Table Logic – Uses External EEPROM (SOT23-5)

• Over/Under-Scale Limiting

• Sensor Fault Detection

• +2.7V TO +5.5V Operation

• Small TSSOP-16 Package

APPLICATIONS

• Bridge Sensors

• Remote 4-20mA Transmitters

• Strain, Load, and Weigh Scales

• Automotive Sensors

SBOS687A –OCTOBER 2013–REVISED DECEMBER 2013

SUPPORTS EXTREME TEMPERATURE APPLICATIONS

• Controlled Baseline

• One Assembly and Test Site

• One Fabrication Site

• Available in Extreme (–55°C to 150°C) Temperature Range

(1)

• Extended Product Life Cycle

• Extended Product-Change Notification

• Product Traceability

• Texas Instruments high temperature products utilize highly optimized silicon (die) solutions with design and process enhancements to maximize performance over extended temperatures. All devices are characterized and qualified for 1000 hours continuous operating life at maximum rated temperature.

EVALUATION TOOLS

• Hardware Designer’s Kit (PGA309EVM) – Temperature Eval of PGA309 + Sensor – Full Programming of PGA309 – Sensor Compensation Analysis Tool

(1) Custom temperature ranges available

DESCRIPTION

The PGA309 is a programmable analog signal conditioner designed for bridge sensors. The analog signal path amplifies the sensor signal and provides digital calibration for zero, span, zero drift, span drift, and sensor linearization errors with applied stress (pressure, strain, etc.). The calibration is done via a One-Wire digital serial interface or through a Two-Wire industry-standard connection. The calibration parameters are stored in external nonvolatile memory (typically SOT23-5) to eliminate manual trimming and achieve long-term stability.

The all-analog signal path contains a 2x2 input multiplexer (mux), auto-zero programmable-gain instrumentation amplifier, linearization circuit, voltage reference, internal oscillator, control logic, and an output amplifier. Programmable level shifting compensates for sensor dc offsets.

The core of the PGA309 is the precision, low-drift, no 1/f noise Front-End PGA (Programmable Gain Amplifier). The overall gain of the Front-End PGA + Output Amplifier can be adjusted from 2.7V/V to 1152V/V. The polarity of the inputs can be switched through the input mux to accommodate sensors with unknown polarity output. The Fault Monitor circuit detects and signals sensor burnout, overload, and system fault conditions.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Analog Sensor Linearization

Digital Temperature Compensation

Analog Signal Conditioning

PGA309

Digital Cal

VEXC

psi

Ext Temp

Nonlinear

Bridge

Transducer

Linearization

Circuit

Auto- Zero

PGA

Fault

Monitor

Int Temp

Control Register

Interface Circuitry

EEPROM

(SOT23-5)

Ref

+125 C°

- °40 C

Over/Under

Scale Limiter

Lin DAC

Temp ADC

Linear V

OUT

PGA309-HT

SBOS687A –OCTOBER 2013–REVISED DECEMBER 2013

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For reference application information, see the commercial device PGA309 User's Guide (SBOU024) available for download at www.ti.com.

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SBOS687A –OCTOBER 2013–REVISED DECEMBER 2013

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING

(1)

–55°C to 150°C TSSOP-16 (PW) PGA309ASPWT PGA309AS

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

(1)

Over operating free-air temperature range, unless otherwise noted.

PARAMETER PGA309 UNIT

Supply Voltage, VSD, V Input Voltage, V Input Current, VFB, V

IN1

, V

IN2

OUT

(2)

Input Current ±10 mA Output Current Limit 50 mA Storage Temperature Range –60 to +150 °C Operating Temperature Range –55 to +150 °C Junction Temperature +170 °C ESD Ratings Human Body Model (HBM) 4 kV

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.

(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails should

be current limited to 10mA or less.

+7.0 V

–0.3 to VSA+0.3 V

±150 mA

THERMAL INFORMATION

PGA309-HT

THERMAL METRIC

θ θ θ ψ ψ θ

JA JCtop JB

JT JB

JCbot

Junction-to-ambient thermal resistance Junction-to-case (top) thermal resistance Junction-to-board thermal resistance Junction-to-top characterization parameter Junction-to-board characterization parameter Junction-to-case (bottom) thermal resistance

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Spacer

(1)

PW UNITS

16 PINS

(2)

(3)

(4)

(5)

(6)

(7)

95.3

28.1

41.4

1.4

40.6 N/A

°C/W

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SBOS687A –OCTOBER 2013–REVISED DECEMBER 2013

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ELECTRICAL CHARACTERISTICS

Boldface limits apply over the specified temperature range, TJ= –55°C to +150°C.

At TJ= +25°C, VSA= VSD= +5V (VSA= V V

= REFIN/REF

REF

PARAMETER CONDITIONS MIN TYP MAX UNIT

Front-End PGA + Output Amplifier

Differential Signal Gain Range

OUT/VIN

Input Voltage Noise Density f = 1kHz 210 nV/√Hz V

Slew Rate 0.5 V/μs

OUT

Settling Time (0.01%) V

OUT

Settling Time (0.01%) V

OUT

Nonlinearity 0.002 %FSR

OUT

External Sensor Output Sensitivity VSA= VSD= V

Front-End PGA

Auto-Zero Internal Frequency 7 kHz

Offset Voltage (RTI)

vs Supply Voltage, V vs Common-Mode Voltage GF= Front-End PGA gain 1500/G

Linear Input Voltage Range

Input Bias Current 0.1 1.5 nA Input Impedance: Differential 30 || 6 GΩ || pF Input Impedance: Common-Mode 50 || 20 GΩ || pF Input Voltage Noise 0.1Hz to 10Hz, GF= 128 4 μV PGA Gain

Gain Range Steps 4, 8, 16, 23.27, 32, 42.67, 64, 128 4 to 128 V/V

Initial Gain Error GF= 4 to 42 0.2 ±1.3 %

vs Temperature 10 ppm/°C

Output Voltage Range 0.05 to VSA− 0.1 V

Bandwidth Gain = 4 400 kHz

Coarse Offset Adjust (RTI of Front-End PGA)

Range ±(14)(V

vs Temperature 0.004 %/°C

Drift ±14 steps, 4-bit + sign 4 mV

Fine Offset Adjust (Zero DAC) (RTO of the Front-End PGA)

Programming Range 0 V Output Voltage Range 0.1 VSA– 0.1 V Resolution 65,536 steps, 16-bit DAC 73 μV Integral Nonlinearity 20 LSB Differential Nonlinearity 0.5 LSB Gain Error 0.1 % Gain Error Drift 10 ppm/°C Offset 5 mV Offset Drift 10 μV/°C

(1) PGA309 total differential gain from input (V

gain) × (Gain DAC).

= +5V, unless otherwise noted.

OUT

(1)

(2)

(3)

(2)

SUPPLY ANALOG

Front-End PGA Gains: 4, 8, 16, 23.27, 32, 42.67, 64, 128

Output Amplifier gains: 2, 2.4, 3, 3.6, 4.5, 6, 9

OUT/VIN

IN1

(2) RTI = Referred-to-input. RTO = referred to output. (3) Linear input range is the allowed min/max voltage on the V

The allowed common-mode and differential voltage depends on gain and offset settings. Refer to the Gain Scaling section for more information.

, VSD= V

Fine gain adjust = 1 8 to 1152 V/V

Differential gain = 8, RL= 5kΩ || 200pF 6 μs

Differential gain = 191, RL= 5kΩ || 200pF 4.1 μs

Coarse offset adjust disabled ±3 ±70 μV

– V

) to output (V

IN2

SUPPLY DIGITAL

= +5V 1 to 245 mV/V

EXC

GF= 64 0.25 ±1.3 %

GF= 128 0.3 ±1.6 %

Gain = 128 60 kHz

)(0.00085) ±55 ±59.5 ±65 mV

REF

). V

OUT

and V

IN1

IN2

; VSAmust equal VSD), GNDD= GNDA= 0, and

PGA309

±2 μV/V

0.2 VSA− 1.5 V

/ (V

– V

OUT

IN1

) = (Front-end PGA gain) × (Output Amplifier

IN2

pins for the input PGA to continue to operate in a linear region.

6500/G

REF

μV/V

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SBOS687A –OCTOBER 2013–REVISED DECEMBER 2013

ELECTRICAL CHARACTERISTICS (continued)

Boldface limits apply over the specified temperature range, TJ= –55°C to +150°C.

At TJ= +25°C, VSA= VSD= +5V (VSA= V V

= REFIN/REF

REF

PARAMETER CONDITIONS MIN TYP MAX UNIT

Output Fine Gain Adjust (Gain DAC)

Range 0.33 to 1 V/V Resolution 65,536 steps, 16-bit DAC 10 μV/V Integral Nonlinearity 20 LSB Differential Nonlinearity 0.5 LSB

Output Amplifier

Offset Voltage (RTI of Output Amplifier)

vs Temperature 5 μV/°C

vs Supply Voltage, V

Common-Mode Input Range 0 VS– 1.5 V

Input Bias Current 100 pA Amplifier Internal Gain

Gain Range Steps 2, 2.4, 3, 3.6, 4.5, 6, 9 2to 9 V/V

Initial Gain Error 2, 2.4, 3.6 0.25 ±1.1 %

vs Temperature 2, 2.4, 3.6 5 ppm/°C

Output Voltage Range

Open-Loop Gain 115 dB Gain-Bandwidth Product 2 MHz Phase Margin Gain = 2, CL= 200pF 45 deg Output Resistance AC Small-signal, open-loop, f = 1MHz, IO= 0 675 Ω Over- and Under-Scale Limits V Over-Scale Thresholds Ratio of V

Over-Scale Comparator Offset -22 +60 +114 mV Over-Scale Comparator Offset Drift +0.37 mV/°C Under-Scale Thresholds Ratio of V

Under-Scale Comparator Offset –93 −50 +7 mV Under-Scale Comparator Offset Drift −0.15 mV/°C

= +5V, unless otherwise noted.

OUT

(4)

(5)

SUPPLY ANALOG

Ratio of V Ratio of V Ratio of V Ratio of V Ratio of V Ratio of V

Ratio of V Ratio of V Ratio of V Ratio of V

Ratio of V Ratio of V Ratio of V

(4) RTI = Referred-to-input. RTO = referred to output. (5) Unless limited by the over/under-scale setting.

, VSD= V

, Register 5—bits D5, D4, D3 = ‘000’ 0.9708

REF

, Register 5—bits D5, D4, D3 = ‘001’ 0.9610

REF

, Register 5—bits D5, D4, D3 = ‘010’ 0.9394

REF

, Register 5—bits D5, D4, D3 = ‘011’ 0.9160

REF

, Register 5—bits D5, D4, D3 = ‘100’ 0.9102

REF

, Register 5—bits D5, D4, D3 = ‘101’ 0.7324

REF

, Register 5—bits D5, D4, D3 = ‘110’ 0.5528

REF

, Register 5—bits D2, D1, D0 = ‘111’ 0.0605

REF

, Register 5—bits D2, D1, D0 = ‘110’ 0.0547

REF

, Register 5—bits D2, D1, D0 = ‘101’ 0.0507

REF

, Register 5—bits D2, D1, D0 = ‘100’ 0.0449

REF

, Register 5—bits D2, D1, D0 = ‘011’ 0.0391

REF

, Register 5—bits D2, D1, D0 = ‘010 0.0352

REF

, Register 5—bits D2, D1, D0 = ‘001’ 0.0293

REF

, Register 5—bits D2, D1, D0 = ‘000’ 0.0254

REF

SUPPLY DIGITAL

4.5 0.3 ±1.3 % 6 0.4 ±1.6 % 9 0.6 ±2.0 %

4.5 5 ppm/°C 6 15 ppm/°C 9 30 ppm/°C

RL= 10kΩ 0.1 4.9 V

= 4.096

REF

; VSAmust equal VSD), GNDD= GNDA= 0, and

PGA309

3 mV

30 μV/V

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SBOS687A –OCTOBER 2013–REVISED DECEMBER 2013

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ELECTRICAL CHARACTERISTICS (continued)

Boldface limits apply over the specified temperature range, TJ= –55°C to +150°C.

At TJ= +25°C, VSA= VSD= +5V (VSA= V V

= REFIN/REF

REF

PARAMETER CONDITIONS MIN TYP MAX UNIT

Fault Monitor Circuit

INP_HI, INN_HI Comparator Threshold See INP_LO, INN_LO Comparator Threshold 40 100 mV A1SAT_HI, A2SAT_HI Comparator Threshold VSA− 0.12 V A1SAT_LO, A2SAT_LO Comparator Threshold VSA− 0.12 V A3_VCM Comparator Threshold VSA− 1.2 V Comparator Hysteresis 20 mV

Internal Voltage Reference

REF1

Drift vs Temperature +10 ppm/°C

REF1

REF2

Drift vs Temperature +10 ppm/°C

REF2

Input Current REFIN/REF Output Current REFIN/REF

Temperature Sense Circuitry (ADC)

Internal Temperature Measurement Register 6, bit D9 = 1

xx Accuracy ±2 °C xx Resolution 12-Bit + sign, twos complement data format ±0.0625 °C xx Temperature Measurement Range −55 +150 °C xx Conversion Rate R1, R0= ‘11’, 12-bit + sign resolution 24 ms

Temperature ADC

External Temperature Mode Temp PGA + Temp ADC 1 to 8 V/V

xx Gain Range Steps G xx Analog Input Voltage Range

Temperature ADC Internal REF (2.048V) Register 6, bit D8 = 1

xx Full-Scale Input Voltage (+Input) − (−Input) ±2.048/G xx Differential Input Impedance 2.8/G xx Common-Mode Input Impedance G

xx Resolution R1, R0 = ‘00’, ADC2X = ‘0’, conversion time = 8ms 11 Bits + Sign

xx Integral Nonlinearity 0.004 % xx Offset Error G

xx Offset Drift G

(6) When V

EXC

reference selector circuit uses V configuration ensures accurate fault monitoring in conditions where V

= +5V, unless otherwise noted.

OUT

is enabled, a minimum reference selector circuit becomes the reference for the comparator threshold. This minimum

SUPPLY ANALOG

R1, R0 = ‘01’, ADC2X = ‘0’, conversion time = 32ms 13 Bits + Sign R1, R0 = ‘10’, ADC2X = ‘0’, conversion time = 64ms 14 Bits + Sign

R1, R0 = ‘11’, ADC2X = ‘0’, conversion time = 128ms 15 Bits + Sign

− 100mV and VSA− 1.2V and compares the V

EXC

amplifier relative to VSA.

, VSD= V

Internal V

VSA> 2.7V for V

VSA> 4.3V for V

SUPPLY DIGITAL

(6)

disabled 100 μA

REF

= 2.5V 1 mA

REF

= 4.096V 1 mA

REF

= 1, 2, 4, 8 GND −0.2 VSA+0.2 V

PGA

= 1 3.5 MΩ

PGA

= 2 3.5 MΩ

PGA

= 4 1.8 MΩ

PGA

= 8 0.9 MΩ

PGA

= 1 1.2 mV

PGA

= 2 0.7 mV

PGA

= 4 0.5 mV

PGA

= 8 0.4 mV

PGA

= 1 1.2 μV/°C

PGA

= 2 0.6 μV/°C

PGA

= 4 0.3 μV/°C

PGA

= 8 0.3 μV/°C

PGA

EXC

; VSAmust equal VSD), GNDD= GNDA= 0, and

PGA309

VSA− 1.2 or V

2.18 2.7 V

3.85 4.22 V

pin to the lower of the two references. This

might be higher or lower than the input CMR of the PGA input

INX

− 0.1 V

EXC

PGA

MΩ

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SBOS687A –OCTOBER 2013–REVISED DECEMBER 2013

ELECTRICAL CHARACTERISTICS (continued)

Boldface limits apply over the specified temperature range, TJ= –55°C to +150°C.

At TJ= +25°C, VSA= VSD= +5V (VSA= V V

= REFIN/REF

REF

= +5V, unless otherwise noted.

OUT

SUPPLY ANALOG

PARAMETER CONDITIONS MIN TYP MAX UNIT

Temperature ADC. continued

xx Offset vs V

xx Gain Error 0.05 0.6 % xx Gain Error Drift 5 ppm/°C xx Noise All gains < 1 LSB xx Gain vs V

xx Common-Mode Rejection At dc and G

Temp ADC Ext. REF (V

REFT

= V

, V

, or VSA) Register 6, bit D8 = 0

REF

EXC

xx Full-Scale Input Voltage (+Input) − (−Input) ±V xx Differential Input Impedance 2.4/G xx Common-Mode Input Impedance G

xx Resolution R1, R0 = ‘00’, ADC2X = ‘0’, conversion time = 6ms 11 Bits + Sign

R1, R0 = ‘01’, ADC2X = ‘0’, conversion time = 24ms 13 Bits + Sign R1, R0 = ‘10’, ADC2X = ‘0’, conversion time = 50ms 14 Bits + Sign

R1, R0 = ‘11’, ADC2X = ‘0’, conversion time = 100ms 15 Bits + Sign

xx Integral Nonlinearity 0.01 % xx Offset Error G

xx Offset Drift G

xx Gain Error −0.2 % xx Gain Error Drift 2 ppm/°C xx Gain vs V

xx Common-Mode Rejection At dc and G

External Temperature Current Excitation I

TEMP

xx Current Excitation 5.8 7 8 μA

xx Temperature Drift 5 nA/°C xx Voltage Compliance VSA−1.2 V

, VSD= V

At dc and G

SUPPLY DIGITAL

= 1 800 μV/V

PGA

= 2 400 μV/V

PGA

= 4 200 μV/V

PGA

= 8 150 μV/V

PGA

= 8 105 dB

PGA

= 1 100 dB

PGA

= 1 8 MΩ

PGA

= 2 8 MΩ

PGA

= 4 8 MΩ

PGA

= 8 8 MΩ

PGA

= 1 2.5 mV

PGA

= 2 1.25 mV

PGA

= 4 0.7 mV

PGA

= 8 0.3 mV

PGA

= 1 1.5 μV/°C

PGA

= 2 1.0 μV/°C

PGA

= 4 0.7 μV/°C

PGA

= 8 0.6 μV/°C

PGA

= 8 100 dB

PGA

= 1 85 dB

PGA

; VSAmust equal VSD), GNDD= GNDA= 0, and

PGA309

80 ppm/V

REFT/GPGA

PGA

80 ppm/V

5.2 8.3 µA

MΩ

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ELECTRICAL CHARACTERISTICS (continued)

Boldface limits apply over the specified temperature range, TJ= –55°C to +150°C.

At TJ= +25°C, VSA= VSD= +5V (VSA= V V

= REFIN/REF

REF

PARAMETER CONDITIONS MIN TYP MAX UNIT

Linearization Adjust and Excitation Voltage (V

Range 0 Register 3, bit D11 = 0

xx Linearization DAC Range With respect to V xx Linearization DAC Resolution ±127 steps, 7-bit + sign 1.307 mV/V xx V

Gain With respect to V

EXC

xx Gain Error Drift 25 ppm/°C

Range 1 Register 3, bit D11 = 1

xx Linearization DAC Range With respect to V xx Linearization DAC Resolution ±127 steps, 7-bit + sign 0.9764 mV/V xx V

Gain With respect to V

EXC

xx Gain Error Drift 25 ppm/°C

Range Upper Limit I

EXC

EXC SHORT

Digital Interface

Two-Wire Compatible Bus speed 1 400 kHz

(7)

One-Wire Maximum Lookup Table Size Two-Wire Data Rate PGA309 to EEPROM (SCL frequency) 65 kHz

Logic Levels

Input Levels (SDA, SCL, PRG, TEST) Low 0.2 • V

Input Levels (SDA, SCL, PRG, TEST) High 0.7 • V Input Levels (SDA, SCL) Hysteresis 0.1 • V

Pull-Up Current Source (SDA, SCL) 55 85 135 μA Pull-Down Current Source (TEST) 10.5 25 50 μA

Output LOW Level (SDA, SCL, PRG) Open drain, I

Power Supply

SA,VSD

ISA+ ISD, Quiescent Current VSA= VSD= +5V, without bridge load 1.2 1.6 mA

Power-On Reset (POR) Power-Up Threshold VSrising 2.2 2.8 V

Power-Down Threshold VSfalling 1.7 V

Temperature Range

Specified Performance Range –55 +150 °C

= +5V, unless otherwise noted.

OUT

(8)

EXC

)

SUPPLY ANALOG

, VSD= V

Short-circuit V

Serial speed baud rate 4.8K 38.4K Bits/s

SUPPLY DIGITAL

REF

= 5mA VSA−0.5 V

EXC

output current 50 mA

EXC

= 5mA 0.4 V

SINK

; VSAmust equal VSD), GNDD= GNDA= 0, and

PGA309

−0.166 to +0.166 V/V

0.83 V/V

−0.124 to +0.124 V/V

0.52 V/V

17 x 3 x 16 Bits

2.8 5.5 V

V V V

(7) Ensured by design, not production tested. (8) Lookup table allows multislope compensation over temperature. Lookup table has access to 17 calibration points consisting of three

adjustment values (Tx, Temperature, ZMx, Zero DAC, GMx, Gain DAC) that are stored in 16-bit data format (17x3x16 = Lookup table size).

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1000

10000

100000

1000000

10000000

80 90 100 110 120 130 140 150 160 170 180

Estimated Life (Hours)

Continuous T (°C)

EM Failure Mode

Wirebond Voiding Fail

Mode

PGA309-HT

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(1) See datasheet for absolute maximum and minimum recommended operating conditions. (2) Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect

life).

(3) The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the

dominant failure mechanism affecting device wearout for the specific device process and design characteristics.

(4) This device is qualified for 1000 hours of continuous operation at maximum rated temperature.

SBOS687A –OCTOBER 2013–REVISED DECEMBER 2013

Figure 1. PGA309-HT Operating Life Derating Chart

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