•Available in Extreme (–55°C to 150°C)
Temperature Range
(1)
•Extended Product Life Cycle
•Extended Product-Change Notification
•Product Traceability
•Texas Instruments high temperature products
utilize highly optimized silicon (die) solutions
with design and process enhancements to
maximize performance over extended
temperatures. All devices are characterized
and qualified for 1000 hours continuous
operating life at maximum rated temperature.
EVALUATION TOOLS
•Hardware Designer’s Kit (PGA309EVM)
– Temperature Eval of PGA309 + Sensor
– Full Programming of PGA309
– Sensor Compensation Analysis Tool
(1) Custom temperature ranges available
DESCRIPTION
The PGA309 is a programmable analog signal conditioner designed for bridge sensors. The analog signal path
amplifies the sensor signal and provides digital calibration for zero, span, zero drift, span drift, and sensor
linearization errors with applied stress (pressure, strain, etc.). The calibration is done via a One-Wire digital serial
interface or through a Two-Wire industry-standard connection. The calibration parameters are stored in external
nonvolatile memory (typically SOT23-5) to eliminate manual trimming and achieve long-term stability.
The all-analog signal path contains a 2x2 input multiplexer (mux), auto-zero programmable-gain instrumentation
amplifier, linearization circuit, voltage reference, internal oscillator, control logic, and an output amplifier.
Programmable level shifting compensates for sensor dc offsets.
The core of the PGA309 is the precision, low-drift, no 1/f noise Front-End PGA (Programmable Gain Amplifier).
The overall gain of the Front-End PGA + Output Amplifier can be adjusted from 2.7V/V to 1152V/V. The polarity
of the inputs can be switched through the input mux to accommodate sensors with unknown polarity output. The
Fault Monitor circuit detects and signals sensor burnout, overload, and system fault conditions.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
T
J
PACKAGEORDERABLE PART NUMBERTOP-SIDE MARKING
(1)
–55°C to 150°CTSSOP-16 (PW)PGA309ASPWTPGA309AS
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
(1)
Over operating free-air temperature range, unless otherwise noted.
PARAMETERPGA309UNIT
Supply Voltage, VSD, V
Input Voltage, V
Input Current, VFB, V
IN1
, V
IN2
OUT
SD
(2)
Input Current±10mA
Output Current Limit50mA
Storage Temperature Range–60 to +150°C
Operating Temperature Range–55 to +150°C
Junction Temperature+170°C
ESD RatingsHuman Body Model (HBM)4kV
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails should
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Internal Temperature MeasurementRegister 6, bit D9 = 1
xx Accuracy±2°C
xx Resolution12-Bit + sign, twos complement data format±0.0625°C
xx Temperature Measurement Range−55+150°C
xx Conversion RateR1, R0= ‘11’, 12-bit + sign resolution24ms
Temperature ADC
External Temperature ModeTemp PGA + Temp ADC1 to 8V/V
xx Gain Range StepsG
xx Analog Input Voltage Range
Temperature ADC Internal REF (2.048V)Register 6, bit D8 = 1
xx Full-Scale Input Voltage(+Input) − (−Input)±2.048/G
xx Differential Input Impedance2.8/G
xx Common-Mode Input ImpedanceG
xx ResolutionR1, R0 = ‘00’, ADC2X = ‘0’, conversion time = 8ms11Bits + Sign
xx Integral Nonlinearity0.004%
xx Offset ErrorG
xx Offset DriftG
(6) When V
EXC
reference selector circuit uses V
configuration ensures accurate fault monitoring in conditions where V
= +5V, unless otherwise noted.
OUT
OUT
OUT
is enabled, a minimum reference selector circuit becomes the reference for the comparator threshold. This minimum
(7) Ensured by design, not production tested.
(8) Lookup table allows multislope compensation over temperature. Lookup table has access to 17 calibration points consisting of three
adjustment values (Tx, Temperature, ZMx, Zero DAC, GMx, Gain DAC) that are stored in 16-bit data format (17x3x16 = Lookup table
size).
(1) See datasheet for absolute maximum and minimum recommended operating conditions.
(2) Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
(3) The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the
dominant failure mechanism affecting device wearout for the specific device process and design characteristics.
(4) This device is qualified for 1000 hours of continuous operation at maximum rated temperature.
Bridge sensor excitation. Connect to bridge if linearization and/or internal reference for bridge excitation
is to be used.
Analog ground. Connect to analog ground return path for VSA. Should be same as GNDD.
A
Analog voltage supply. Connect to analog voltage supply. To be within 200mV of VSD.
Signal input voltage 1. Connect to + or – output of sensor bridge. Internal multiplexer can change
connection internally to Front-End PGA.
Signal input voltage 2. Connect to + or – output of sensor bridge. Internal multiplexer can change
connection internally to Front-End PGA.
V
feedback pin. Voltage feedback sense point for over/under-scale limit circuitry. When internal gain
OUT
set resistors for the output amplifier are used, this is also the voltage feedback sense point for the
output amplifier. VFBin combination with VSJallows for ease of external filter and protection circuits
without degrading the PGA309 V
point of feedback for V
, if external protection is used.
OUT
accuracy. VFBmust always be connected to either V
OUT
Analog output voltage of conditioned sensor.
Output amplifier summing junction. Use for output amplifier compensation when driving large capacitive
loads (> 100pF) and/or for using external gain setting resistors for the output amplifier.
Digital voltage supply. Connect to digital voltage supply. To be within 200mV of VSA.
Digital ground. Connect to digital ground return path for VSD. Should be same as GNDA.
D
Single-wire interface program pin. UART-type interface for digital calibration of the PGA309 over a
assembly.
for a three-lead (VS, GND, V
OUT
) digitally-programmable sensor
OUT
Clock input/output for Two-Wire, industry-standard compatible interface for reading and writing digital
the PGA309 through the Two-Wire, industry-standard compatible interface.
Data input/output for Two-Wire, industry-standard compatible interface for reading and writing digital
the PGA309 through the Two-Wire, industry-standard compatible interface.
External temperature signal input. PGA309 can be configured to read a bridge current sense resistor
as an indicator of bridge temperature, or an external temperature sensing device such as diode
junction, RTD, or thermistor. This input can be internally gained by 1, 2, 4, or 8. In addition, this input
IN
can be read differentially with respect to V
internal, register-selectable, 7μA current source (I
thermistor, or diode excitation source.
GNDA
, V
, or the internal/external V
EXC
) that can be connected to TEMPINas an RTD,
TEMP
. There is also an
REF
Reference input/output pin. As an output, the internal reference (selectable as 2.5V or 4.096V) is
available for system use on this pin. As an input, the internal reference may be disabled and an
OUT
external reference can then be applied as the reference for the PGA309.
Product Folder Links: PGA309-HT
OUT
or the
90
80
70
60
50
40
30
20
10
0
-10
Frequency (Hz)
PSRR (dB)
101001k10k100k1M
Small-Signal
Vand VEnabled
V= 2.5V
PSRR at V
REFEXT
REF
OUT
80
60
40
20
0
Frequency (Hz)
Gain (dB)
101001k10k100k1M
G= Output Amplifier Gain
OUTAMP
G= 9V/V
G= 128V/V
OUTAMP
FRONT
G= 9V/V
G= 32V/V
OUTAMP
FRONT
G= 2V/V
G= 32V/V
OUTAMP
FRONT
G= 2V/V
G= 8V/V
OUTAMP
FRONT
Temperature ( C)°
-55 -35 -15525456585 105 125 145
9
8
7
6
5
4
3
2
1
0
Average
I( A)m
TEMP
70
60
50
40
30
20
10
0
-10
-20
-30
Frequency (Hz)
CMRR (dB)
101001k10k100k1M
RTO of Front- End PGA
Average
4.090
4.085
4.080
4.075
4.070
4.065
4.060
Temperature ( C)°
-55 -35 -15525456585 105 125 145
V
REF
(V)
Temperature ( C)°
-55 -35 -15525456585 105 125 145
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
Average, nA
I (nA)
B
PGA309-HT
www.ti.com
At TA= +25°C, VSA= VSD= +5V (VSA= V
V
V
vs TEMPERATUREIBCURRENT vs TEMPERATURE
REF
Figure 2.Figure 3.
I
CURRENT vs TEMPERATURECOMMON-MODE REJECTION RATIO vs FREQUENCY
TEMP
TYPICAL CHARACTERISTICS
SUPPLY ANALOG
= REFIN/REF
REF
, VSD= V
OUT
SUPPLY DIGITAL
= +5V, unless otherwise noted.
SBOS687A –OCTOBER 2013–REVISED DECEMBER 2013
, VSAmust equal VSD), GNDD= GNDA= 0, and
Figure 4.Figure 5.
POWER-SUPPLY REJECTION RATIO vs FREQUENCYCLOSED−LOOP GAIN vs FREQUENCY
The PGA309 is a programmable analog signal
conditioner designed for resistive bridge sensor
applications. It is a complete signal conditioner with
bridge excitation, initial span and offset adjustment,
temperatureadjustmentofspanandoffset,
internal/external temperature measurement capability,
output over-scale and under-scale limiting, fault
detection, and digital calibration. The PGA309, in a
calibrated sensor module, can reduce errors to the
level approaching the bridge sensor repeatability. See
Figure 25 for a block diagram of the PGA309.
Following is a brief overview of each major function.
SENSOR ERROR ADJUSTMENT RANGE
TheadjustmentcapabilityofthePGA309is
summarized in Table 1.
Table 1. PGA309 Adjustment Capability
FSS (full-scale sensitivity)1mV/V to 245mV/V
Span TCOver ±3300ppmFS/°C
Span TC nonlinearity≥ 10%
Zero offset±200%FS
Zero offset TCOver ±3000ppmFS/°C
Zero offset TC nonlinearity≥ 10%
Sensor impedanceDown to 200Ω
(2)
(1)
(2)
(3)
1. Depends on the temperature sensing scheme.
2. Combined coarse and fine offset adjust.
3. Lower impedance possible by using a dropping
resistor in series with the bridge.
GAIN SCALING
The core of the PGA309 is the precision low-drift and
no 1/f noise Front-End PGA. The overall gain of the
Front-End PGA + Output Amplifier can be adjusted
from 2.7V/V to 1152V/V. The polarity of the inputs
can be switched through the 2x2 input mux to
accommodate sensors with unknown polarity output.
The Front-End PGA provides initial coarse signal gain
using a no 1/f noise, auto-zero instrumentation
amplifier. The fine gain adjust is accomplished by the
16-bit attenuating Gain Digital-to-Analog Converter
(Gain DAC). This Gain DAC is controlled by the data
in the Temperature Compensation Lookup Table
drivenbytheTemperatureAnalog-to-Digital
SBOS687A –OCTOBER 2013–REVISED DECEMBER 2013
Converter (Temp ADC). In order to compensate for
second-order and higher drift nonlinearity, the span
drift can be fitted to piecewise linear curves during
calibration with the coefficients stored in an external
nonvolatile EEPROM lookup table.
Following the fine gain adjust stage is the Output
Amplifier that provides additional programmable gain.
Two key output amplifier connections, VFBand VSJ,
are brought out on the PGA309 for application
flexibility. These connections allow for an accurate
conditioned signal voltage while also providing a
means for PGA309 output overvoltage and large
capacitive loading for RFI/EMI filtering required in
many end applications.
OFFSET ADJUSTMENT
The sensor offset adjustment is performed in two
stages. The input-referred Coarse Offset Adjust DAC
has approximately a ±60mV offset adjustment range
for a selected V
of 5V. The fine offset and the
REF
offset drift are canceled by the 16-bit Zero DAC that
sums the signal with the output of the front-end
instrumentation amplifier. Similar to the Gain DAC,
the input digital values of the Zero DAC are controlled
by the data in the Temperature Compensation
Lookup Table, stored in external EEPROM, driven by
the Temp ADC. The programming range of the Zero
DAC is 0V to V
with an output range of 0.1V to
REF
VSA– 0.1V.
VOLTAGE REFERENCE
The PGA309 contains a precision low-drift voltage
reference (selectable for 2.5V or 4.096V) that can be
used for external circuitry through the REFIN/REF
OUT
pin. This same reference is used for the Coarse
Offset Adjust DAC, Zero DAC, Over/Under-Scale
Limits and sensor excitation/linearization through the
V
pin. When the internal reference is disabled, the
EXC
REFIN/REF
pin should be connected to an
OUT
external reference or to VSAfor ratiometric-scaled
systems.
SENSOR EXCITATION AND LINEARIZATION
A dedicated circuit with a 7-bit + sign DAC for sensor
voltage excitation and linearization is provided on the
PGA309. This block scales the reference voltage and
sums it with a portion of the PGA309 output to
compensate the positive or negative bow-shaped
nonlinearity exhibited by many sensors over their
appliedpressurerange.Sensorsnotrequiring
linearization can be connected directly to the supply
(VSA) or to the V
(Lin DAC) set to zero.
ADC FOR TEMPERATURE SENSINGalgorithm for accurate DAC adjustments between
Thetemperaturesensecircuitrydrivesthe
compensation for the sensor span and offset drift.
Either internal or external temperature sensing is
possible. The temperature can be sensed in one of
the following ways:If either Checksum1, Checksum2, or both are
•Bridgeimpedance change (excitation current
sense, in the positive or negative part of the
bridge),forsensors withlargetemperature
coefficient of resistance (TCR > 0.1%/°C).
•On-chip PGA309 temperature, when the chip is
located sufficiently close to the sensor.
•External diode, thermistor, or RTD placed on the
sensor membrane. An internal 7μA current source
may beenabled to excitethese typesof
temperature sensors.
The temperature signal is digitized by the onboard
Temp ADC. The output of the Temp ADC is used by
the control digital circuit to read the data from the
Lookup Table in an external EEPROM, and set the
output of the Gain DAC and the Zero DAC to the
calibrated values as temperature changes.
An additional function provided through the Temp
ADC is the ability to read the V
pin back through
OUT
the Temp ADC input mux. This provides flexibility for
a digital output through either One-Wire or Two-Wire
interface, as well as the possibility for an external
microcontrollertoperformreal-timecustom
calibration of the PGA309.
EXTERNAL EEPROM AND TEMPERATURE
COEFFICIENTS
The PGA309 uses an industry-standard Two-Wire
external EEPROM (typically, a SOT23-5 package). A
1k-bit (minimum) EEPROM is needed when using all
17 temperature coefficients. Larger EEPROMs may
be used to provide space for a serial number, lot
code, or other data.
The first part of the external EEPROM contains the
configuration data for the PGA309, with settings for:
•Register 3—Reference Control and Linearization
•Register 4—PGA Coarse Offset and Gain/Output
Amplifier Gain
•Register 5—PGA Configuration and Over/UnderScale Limit
•Register 6—Temp ADC Control
This section of the EEPROM contains its own
individual checksum (Checksum1).
The second part of the external EEPROM contains
up to 17 temperature index values and corresponding
temperature coefficients for the Zero DAC and Gain
DAC adjustments with measured temperature, and
also contains its own checksum (Checksum2). The
PGA309 lookup logic contains a linear interpolation
stored temperature indexes. This approach allows for
a piecewise linear temperature compensation of up to
17 temperature indexes and associated temperature
coefficients.
incorrect, the output of the PGA309 is set to highimpedance.
FAULT MONITOR
To detect sensor burnout or a short, a set of four
comparators are connected to the inputs of the FrontEnd PGA. If any of the inputs are taken to within
100mV of ground or V
, or violate the input CMR of
EXC
theFront-EndPGA,thenthecorresponding
comparator sets a sensor fault flag that causes the
PGA309 V
to be driven within 100mV of either V
OUT
SA
or ground, depending upon the alarm configuration
setting(Register5—PGAConfigurationand
Over/Under-Scale Limit). This will be well above the
set Over-Scale Limit level or well below the set
Under-Scale Limit level. The state of the fault
condition can be read in digital form in Register
8—Alarm Status Register. If the Over/Under-Scale
Limit is disabled, the PGA309 output voltage will still
be driven within 100mV of either VSAor ground,
depending upon the alarm configuration setting.
There are five other fault detect comparators that
help detect subtle PGA309 front-end violations that
could otherwise result in linear voltages at V
OUT
that
would be interpreted as valid states. These are
especially useful during factory calibration and setup,
andareconfiguredthroughRegister5—PGA
ConfigurationandOver/Under-ScaleLimit.The
respective status of each can also be read back
through Register 8—Alarm Status Register.
OVER-SCALE AND UNDER-SCALE LIMITSE
Theover-scaleandunder-scalelimitcircuitry
combined with the fault monitor circuitry provides a
means for system diagnostics. A typical sensorconditioned output may be scaled for 10% to 90% of
the system ADC range for the sensor normal
operating range. If the conditioned pressure sensor is
below 4%, it is considered under-pressure; if over
96%, it is considered over-pressure.
The PGA309 over/under-scale limit circuit can be
programmed individually for under-scale and overscale values that clip or limit the PGA309 output.
From a system diagnostic view, 10% to 90% of ADC
range is normal operation, less than 4% is underpressure, and greater than 96% is over-pressure. If
the fault detect circuitry is used, a detected fault will
cause the PGA309 output to be driven to positive or
negative saturation.
If this fault flag is programmed for high, then greaterDIGITAL INTERFACE
than 97% ADC range will be a fault; if programmed
for low. then less than 3% ADC range will be a fault.
In this configuration, the system software can be
used to distinguish between over- or under-pressure
condition, which indicates an out-of-control process,
or a sensor fault.
POWER-UP AND NORMAL OPERATION
The PGA309 has circuitry to detect when the power
supply is applied to the PGA309, and reset the
internal registers and circuitry to an initial state. This
reset also occurs when the supply is detected to be
invalid, so that the PGA309 is in a known state when
the supply becomes valid again. The rising threshold
for this circuit is typically 2.2V and the falling
threshold is typically 1.7V. After the power supply
becomes valid, the PGA309 waits for approximately
25ms and then attempts to read the configuration
data from the external EEPROM device.
If the EEPROM has the proper flag set in address
locations 0 and 1, then the PGA309 continues
reading the first part of the EEPROM; otherwise, the
PGA309 waits for one second before trying again. If
the PGA309 detects no response from the EEPROM,
the PGA309 waits for one second and tries again;
otherwise, the PGA309 tries to free the bus and waits
for 25ms before trying to read the EEPROM again. If
a successful read of the first part of the EEPROM is
accomplished, (including valid Checksum1 data), the
PGA309triggersthe TempADCtomeasure
temperature.For16-bitresolutionresults,the
converter takes approximately 125ms to complete a
conversion. Once the conversion is complete, the
PGA309 begins reading the Lookup Table information
from the EEPROM (second part) to calculate the
settings for the Gain DAC and Zero DAC.
The PGA309 reads the entire Lookup Table so that it
There are two digital interfaces on the PGA309. The
PRGpinusesaOne-Wire,UART-compatible
interface with bit rates from 4.8Kbits/s to 38.4Kbits/s.
The SDA and SCL pins together form an industry
standard Two-Wire interface at clock rates from 1kHz
to 400kHz. The external EEPROM uses the Two-Wire
interface. Communication to the PGA309 internal
registers, as well as to the external EEPROM, for
programming andreadbackcan beconducted
through either digital interface.
ItisalsopossibletoconnecttheOne-Wire
communication pin, PRG, to the V
three-wiresensormodulesandstillallowfor
programming. In this mode, the PGA309 output
amplifier may be enabled for a set time period and
then disabled again to allow sharing of the PRG pin
with the V
connection. This allows for both digital
OUT
calibration andanalog readback duringsensor
calibration in a three-wire sensor module.
The Two-Wire interface has timeout mechanisms to
prevent bus lockup from occurring. The Two-Wire
master controller in the PGA309 has a mode that
attempts to free up a stuck-at-zero SDA line by
issuing SCL pulses, even when the bus is not
indicated as idle after a timeout period has expired.
The timeout will only apply when the master portion
of the PGA309 is attempting to initiate a Two-Wire
communication.
PGA309 TRANSFER FUNCTION
Equation 1 shows the mathematical expression that is
used to compute the output voltage, V
equation can also be rearranged algebraically to
solve for differentterms. For example,during
calibration, this equation is rearranged to solve for
VIN.
can determine if the checksum for the Lookup Table
(Checksum2) is correct. Each entry in the Lookup
Table requires approximately 500μs to read from the
EEPROM. Once the checksum is determined to be
valid, the calculated values for the Gain and Zero
DACs are updated into their respective registers, and
the output amplifier is enabled. The PGA309 then
begins looping through this entire procedure, starting
with reading the EEPROM configuration registers
from the first part of the EEPROM, then starting a
new conversion on the Temp ADC, which then
triggers reading the Lookup Table data from the
second part of the EEPROM. This loop continues
indefinitely.
Where:
mux_sign: This term changes the polarity of the
input signal; value is ±1.
VIN: The input signal for the PGA309; VIN1 = V
VIN2 = V
V
Coarse_Offset
.
INN
: The coarse offset DAC output
voltage.
GI: Input stage gain.
V
Zero_DAC
: Zero DAC output voltage.
GD: Gain DAC.
GO: Output stage gain.
PGA309ASPWTACTIVETSSOPPW16250RoHS & GreenNIPDAULevel-2-260C-1 YEAR-55 to 150PGA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Package Type Package
(1)
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C)Device Marking
(4/5)
309AS
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
0.15
0.05
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EXAMPLE BOARD LAYOUT
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
16X (0.45)
14X (0.65)
1
8
16X (1.5)
SYMM
(R0.05) TYP
16
SYMM
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
METAL
15.000
SOLDER MASK DETAILS
METAL UNDER
SOLDER MASK
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SOLDER MASK
OPENING
EXPOSED METAL
4220204/A 02/2017
www.ti.com
EXAMPLE STENCIL DESIGN
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
16X (0.45)
14X (0.65)
1
8
16X (1.5)
SYMM
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
(R0.05) TYP
16
SYMM
9
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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