TEXAS INSTRUMENTS PCM5100 Technical data
Audio Interface
8x Interpolation Filter
32bit ∆Σ Modulator
Current
Segment
DAC
Current
Segment
DAC
I/V I/V
Analog
Mute
Analog
Mute
Zero
Data
Detector
UVP/Reset
PLL Clock
Power
Supply
Ch. PumpPOR
Clock Halt
Detection
Advanced Mute Control
MCK
BCK
LRCK
CAPP
CAPM
VNEG
LINE OUT
DIN (i2s)
PCM510x
CPVDD (3.3V)
AVDD (3.3V)
DVDD (3.3V)
GND
Draft Only
PCM5100, PCM5101, PCM5102
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2V
1
FEATURES
23
• Market-Leading Low Out-of-Band Noise
DirectPath™, 112/106/100dB Audio Stereo DAC with 32-bit, 384kHz PCM Interface
RMS
Check for Samples: PCM5100, PCM5101, PCM5102
• Selectable Digital-Filter Latency &
Performance
• No DC Blocking Capacitors Required
• Integrated Negative Charge Pump
• Internal Pop-Free Control For Sample-Rate
Changes Or Clock Halts
• Intelligent Muting System; Soft Up/Down Ramp
& Analog Mute For 120dB Mute SNR With
Popless Operation.
• Integrated High-Performance Audio PLL With
BCK Reference To Generate SCK Internally
• Small 20-pin TSSOP Package
SLAS764A –MAY 2011–REVISED MARCH 2012
Typical Performance (3.3V Power Supply)
Parameter PCM5102 / PCM5101 /
SNR 112 / 106 / 100dB
Dynamic Range 112 / 106 / 100dB
THD+N @ - 1dBFS –93 / –92 / –90dB
Full Scale Output 2.1V
Normal 8× Oversampling Digital Filter Latency: 20/f
Low Latency 8× Oversampling Digital Filter Latency: 3.5/f
Sampling Frequency 8kHz to 384kHz
System Clock Multiples (f
768, 1024, 1152, 1536, 2048, 3072; up to 50 MHz
): 64, 128, 192, 256, 384, 512,
SCK
PCM5100
(GND center)
RMS
S
S
Figure 1. PCM510x Functional Block Diagram
OTHER KEY FEATURES
• Accepts 16-, 24-, And 32-Bit Audio Data
• PCM Data Formats: I2S, Left-Justified
• Automatic Power-Save Mode When LRCK And
BCK Are Deactivated.
• 3.3V Failsafe LVCMOS Digital Inputs
• Hardware Configuration
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2System Two Cascade, Audio Precision are trademarks of Audio Precision.
3DirectPath is a trademark of Texas, Instruments, Inc..
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
• Single Supply Operation:
– 3.3V Analog, 3.3V Digital
• Integrated Power-On Reset
Copyright © 2011–2012, Texas Instruments Incorporated
PCM5100, PCM5101, PCM5102
Draft Only
SLAS764A –MAY 2011–REVISED MARCH 2012
APPLICATIONS
• A/V Receivers
• DVD, BD Players
• HDTV Receivers
• Applications Requiring 2V
Audio Output
RMS
DESCRIPTION
The PCM510x devices are a family of monolithic
CMOS integrated circuits that include a stereo digitalto-analog converter and additional support circuitry in
a small TSSOP package. The PCM510x uses the
latest generation of TI’s advanced segment-DAC
architecture to achieve excellent dynamic
performance and improved tolerance to clock jitter.
The PCM510x provides 2.1V
outputs, allowing designers to eliminate DC blocking
capacitors on the output, as well as external muting
circuits traditionally associated with single supply line
drivers.
ground centered
RMS
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The integrated line driver surpasses all other chargepump based line drivers by supporting loads down to
1kΩ. By supporting loads down to 1kΩ, the PCM510x
can essentially drive up to 10 products in parallel.
(LCD TV, DVDR, AV Receivers etc).
The integrated PLL on the device removes the
requirement for a system clock (commonly known as
master clock). This allows a 3-wire I2S connection,
along with reduced system EMI.
Intelligent clock error and PowerSense under voltage
protection utilizes a two level mute system for popfree performance. Upon clock error or system power
failure, the device digitally attenuates the data (or last
known good data), then mutes the analog circuit
Compared with existing DAC technology, the
PCM510x family offers up to 20dB lower out-of-band
noise, reducing EMI and aliasing in downstream
amplifiers/ADCs. (from traditional 100kHz OBN
measurements all the way to 3MHz)
The PCM510x accepts industry-standard audio data
formats with 16- to 32-bit data. Sample rates up to
384kHz are supported.
Table 1. Differences Between PCM510x Devices
Part Number Dynamic Range SNR THD
PCM5102 112dB 112dB –93dB
PCM5101 106dB 106dB –92dB
PCM5100 100dB 100dB –90dB
spacer
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
Supply Voltage AVDD, CPVDD, DVDD –0.3 to 3.9
Digital Input Voltage –0.3 to 3.9 V
Analog Input Voltage –0.3 to 3.9
Operating Temperature Range –25 to 85
Storage Temperature Range –65 to 150
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
θ
JA
ψ
JT
ψ
JB
θ
JC
θ
JB
Theta JA High K 91.2
Psi JT 1.0
Psi JB 41.5 ºC/W
Theta JC Top 25.3
Theta JB 42.0
°C
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SLAS764A –MAY 2011–REVISED MARCH 2012
ELECTRICAL CHARACTERISTICS
All specifications at TA= 25°C, AVDD= CPVDD= DVDD= 3.3V, fS= 48kHz, system clock = 512 fSand 24-bit data unless
otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 16 24 32 Bits
Data Format (PCM Mode)
Audio data interface format I2S, left justified
Audio data bit length 16, 24, 32-bit acceptable
Audio data format MSB First, 2’s Complement
f
S
Digital Input/Output
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
Sampling frequency 8 384 kHz
System clock frequency 64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, or
3072
f
, up to 50Mhz
SCK
Logic Family: 3.3V LVCMOS compatible
0.7×DV
Input logic level V
VIN= V
Input logic current µA
Output logic level V
DD
VIN= 0V –10
IOH= –4mA 0.8×DV
IOL= 4mA 0.22×DV
DD
DD
0.3×DV
DD
10
DD
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SLAS764A –MAY 2011–REVISED MARCH 2012
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ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA= 25°C, AVDD= CPVDD= DVDD= 3.3V, fS= 48kHz, system clock = 512 fSand 24-bit data unless
otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Dynamic Performance (PCM Mode)
THD+N at –1 dBFS
Dynamic range
(2)
Signal-to-noise ratio
Signal to noise ratio with EIAJ, A-weighted, fS= 48kHz 113 123
analog mute
(2)(3)
Channel Separation fS= 48 kHz 100/ 95/ 90 109/103/97
Analog Output
Output voltage 2.1 V
Gain error –6 ±2.0 6 % of FSR
Gain mismatch, channel-to- –6 ±2.0 6
channel
Bipolar zero error At bipolar zero –5 ±1.0 5 mV
Load impedance 1 kΩ
Filter Characteristics–1: Normal
Pass band 0.45f
Stop band 0.55f
Stop band attenuation –60
Pass-band ripple ±0.02
Delay time 20/f
Filter Characteristics–2: Low Latency
Pass band 0.47f
Stop band 0.55f
Stop band attenuation –52
Pass-band ripple ±0.0001
Delay time 3.5/f
(1) Filter condition: THD+N: 20Hz HPF, 20kHz AES17 LPF Dynamic range: 20Hz HPF, 20kHz AES17 LPF, A-weighted Signal-to-noise
ratio: 20Hz HPF, 20kHz AES17 LPF, A-weighted Channel separation: 20Hz HPF, 20kHz AES17 LPF Analog performance specifications
are measured using the System Two Cascade™ audio measurement system by Audio Precision™ in the RMS mode.
(2) Output load is 10kΩ, with 470Ω output resistor and a 2.2nF shunt capacitor (see recommended output filter).
(3) Assert XSMT or both L-ch and R-ch PCM data are BPZ
(1)(2)
(Values shown for three devices PCM5102/PCM5101/PCM5100)
fS= 48kHz –93/–92/–90 -83/ -82/ -80
(2)
fS= 96kHz –93/–92/–90
fS= 192kHz –93/–92/–90
EIAJ, A-weighted, fS= 48kHz 106/ 100/ 95 112/106/100
EIAJ, A-weighted, fS= 96kHz 112/106/100
EIAJ, A-weighted, fS= 192kHz 112/106/100
(2)
EIAJ, A-weighted, fS= 48kHz 112/106/100 dB
EIAJ, A-weighted, fS= 96kHz 112/106/100
EIAJ, A-weighted, fS= 192kHz 112/106/100
EIAJ, A-weighted, fS= 96kHz 123
EIAJ, A-weighted, fS= 192kHz 123
fS= 96kHz 109/103/97
fS= 192kHz 109/103/97
% of FSR
S
S
dB
S
S
S
dB
S
RMS
s
s
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SLAS764A –MAY 2011–REVISED MARCH 2012
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA= 25°C, AVDD= CPVDD= DVDD= 3.3V, fS= 48kHz, system clock = 512 fSand 24-bit data unless
otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power Supply Requirements
DV
AV
CPV
I
DD
I
DD
I
DD
I
CC
I
CC
I
CC
DD
DD
Digital supply voltage Target DVDD= 3.3V 3.0 3.3 3.6
Analog supply voltage 3.0 3.3 3.6 VDC
Charge-pump suply voltage 3.0 3.3 3.6
DD
fS= 48kHz 7 12
DVDDsupply current at 3.3V
(4)
fS= 96kHz 8 mA
fS= 192kHz 9
fS= 48kHz 8 13
DVDDsupply current at 3.3V
(5)
fS= 96kHz 9 mA
fS= 192kHz 10
DVDDsupply current at 3.3V
(6)
0.5 0.8 mA
fS= 48kHz 11 16
AVDD/ CPVDDSupply
(4)
Current
fS= 96kHz 11 mA
fS= 192kHz 11
fS= 48kHz 22 32
AVDD/ CPVDDSupply
(5)
Current
fS= 96kHz 22 mA
fS= 192kHz 22
AVDD/ CPVDDSupply fS= n/a 0.2 0.4
(6)
Current
fS= 48kHz 59.4 92.4
Power Dissipation, DVDD=
(4)
3.3V
fS= 96kHz 62.7 mW
fS= 192kHz 66.0
fS= 48kHz 99.0 148.5
Power Dissipation, DVDD=
(5)
3.3V
fS= 96kHz 102.3 mW
fS= 192kHz 105.6
Power Dissipation, DVDD= fS= n/a (Power Down Mode) 2.3 4.0
(6)
3.3V
mA
mW
(4) Input is Bipolar Zero data.
(5) Input is 1kHz -1dBFS data
(6) Power Down Mode
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Draft Only
SLAS764A –MAY 2011–REVISED MARCH 2012
TERMINAL FUNCTIONS, PCM510x
Table 2. TERMINAL FUNCTIONS, PCM510x
TERMINAL
NAME NO.
CPVDD 1 — Charge pump power supply, 3.3V
CAPP 2 O Charge pump flying capacitor terminal for positive rail
CPGND 3 — Charge pump ground
CAPM 4 O Charge pump flying capacitor terminal for negative rail
VNEG 5 O Negative charge pump rail terminal for decoupling, -3.3V
OUTL 6 O Analog output from DAC left channel
OUTR 7 O Analog output from DAC right channel
AVDD 8 -— Analog power supply, 3.3V
AGND 9 — Analog ground
DEMP 10 I De-emphasis control for 44.1kHz sampling rate
FLT 11 I Filter select : Normal latency (Low) / Low latency (High)
SCK 12 I System clock input
BCK 13 I Audio data bit clock input
DIN 14 I Audio data input
LRCK 15 I Audio data word clock input
FMT 16 I Audio format selection : I2S (Low) / Left justified (High)
XSMT 17 I Soft mute control
LDOO 18 — Internal logic supply rail terminal for decoupling
DGND 19 — Digital ground
DVDD 20 — Digital power supply, 3.3V
(1) Failsafe LVCMOS Schmitt trigger input
I/O DESCRIPTION
DEVICE INFORMATION
PCM510X (top view)
(1)
(1)
(1)
(1)
(1)
: Soft mute (Low) / soft un-mute (High)
(1)
: Off (Low) / On (High)
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-10
10
-110
-90
-70
-50
-30
-100 -80 -60 -40 -20 0
Input Level [dBFS]
THD+N [dB]
-110
-90
-70
-50
-30
-10
10
-100 -80 -60 -40 -20 0
Input Level [dBFS]
THD+N [dB]
-110
-90
-70
-50
-30
-10
10
-100 -80 -60 -40 -20 0
Input Level [dBFS]
THD+N [dB]
Draft Only
PCM5100, PCM5101, PCM5102
www.ti.com
SLAS764A –MAY 2011–REVISED MARCH 2012
TYPICAL CHARACTERISTICS
All specifications at TA= 25°C, AVDD= CPVDD= DVDD= 3.3V, fS= 48kHz, system clock = 512 fSand 24-bit data unless
otherwise noted.
PCM5100 THD+N PCM5101 THD+N
vs vs
Input Level Input Level
Figure 2. Figure 3.
PCM5102 THD+N
vs
Input Level
Figure 4.
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-180
-160
-140
-120
-100
-80
-60
-40
-20
0 5 10 15 20
Frequency [kHz]
Amplitude [dB]
-180
-160
-140
-120
-100
-80
-60
-40
-20
0 5 10 15 20
Frequency [kHz]
Amplitude [dB]
-180
-160
-140
-120
-100
-80
-60
-40
-20
0 5 10 15 20
Frequency [kHz]
Amplitude [dB]
PCM5100, PCM5101, PCM5102
Draft Only
SLAS764A –MAY 2011–REVISED MARCH 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
All specifications at TA= 25°C, AVDD= CPVDD= DVDD= 3.3V, fS= 48kHz, system clock = 512 fSand 24-bit data unless
otherwise noted.
PCM5100 FFT Plot at BPZ With AMUTE PCM5101 FFT Plot at BPZ With AMUTE
Figure 5. Figure 6.
PCM5102 FFT Plot at BPZ With AMUTE
Figure 7.
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-160
-140
-120
-100
-80
-60
-40
-20
0
0 50 100 150 200 250 300
Frequency [kHz]
Amplitude [dB]
-160
-140
-120
-100
-80
-60
-40
-20
0
0 50 100 150 200 250 300
Frequency [kHz]
Amplitude [dB]
-160
-140
-120
-100
-80
-60
-40
-20
0
0 50 100 150 200 250 300
Frequency [kHz]
Amplitude [dB]
Draft Only
PCM5100, PCM5101, PCM5102
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SLAS764A –MAY 2011–REVISED MARCH 2012
TYPICAL CHARACTERISTICS (continued)
All specifications at TA= 25°C, AVDD= CPVDD= DVDD= 3.3V, fS= 48kHz, system clock = 512 fSand 24-bit data unless
otherwise noted.
PCM5100 FFT Plot at –60dB To 300kHz PCM5101 FFT Plot at –60dB To 300kHz
Figure 8. Figure 9.
PCM5102 FFT Plot at –60dB To 300kHz
Figure 10.
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Internal Reset
I2S Clocks
SCK, BCK, LRCK
Internal Reset
4 ms
Reset Removal
2.8V
3.3V
AVDD, DVDD,
CPVDD
PCM5100, PCM5101, PCM5102
Draft Only
SLAS764A –MAY 2011–REVISED MARCH 2012
www.ti.com
APPLICATION INFORMATION
Reset and System Clock Functions
Power-On Reset Function
The PCM510x includes a power-on reset function shown in Figure 11. With VDD> 2.8V, the power-on reset
function is enabled. After the initialization period, the PCM510x is set to its default reset state.
Figure 11. Power-On Reset Timing, DVDD = 3.3V
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