TEXAS INSTRUMENTS PCM3793, PCM3794 Technical data

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  

SLES193C – AUGUST 2006 – REVISED FEBRUARY 2007

16-Bit, Low-Power Stereo Audio CODEC With Microphone Bias, Headphone, and Digital

Speaker Amplifier

PCM3793
PCM3794

FEATURES

• 2 (I2C) or 3 (SPI) Wire Serial Control

• Analog Front End: • Programmable Function by Register Control:

– Stereo Single-Ended Input With Multiplexer – Digital Attenuation of DAC: 0 dB to –62 dB
– Mono Differential Input – Power Up/Down Control for Each Module
– Stereo Programmable Gain Amplifier – 6-dB to –70-dB Gain for Analog Outputs
– Microphone Boost Amplifier (20 dB) and – 30-dB to –12-dB Gain for Analog Inputs

Bias

– 0/20 dB Boost Selectable for Microphone

• Analog BackEnd: Input

– Stereo/Mono Line Output With Volume – 0-dB to –21-dB Gain for Analog Mixing
– Stereo/Mono Headphone Amplifier With – Parameter Settings for ALC

Volume and Capless Mode

– Stereo/Mono Digital Speaker Amplifier

(BTL) With Volume (PCM3793)

• Analog Performance:

– Dynamic Range: 93 dB (DAC)
– Dynamic Range: 90 dB (ADC)
– 40-mW + 40-mW Headphone Output at

R

= 16 Ω

L

– Three-Band Tone Control and 3D Sound
– High-Pass Filter and Two-Stage Notch

Filter

– Analog Mixing

• Pop-Noise Reduction Circuit

• Short and Thermal Protection Circuit

• Package: 5-mm × 5-mm QFN Pacakge

• Operation Temperature Range: –40 ° C to 85 ° C

– 700-mW + 700-mW Speaker Output at

R

= 8 Ω

L

• Power Supply Voltage

– 1.71 V to 3.6 V for Digital I/O Section
– 1.71 V to 3.6 V for Digital Core Section

APPLICATIONS

• Portable Audio Player, Cellular Phone

• Video Camcorder, Digital Still Camera

• PMP/DMB

– 2.4 V to 3.6 V for Analog Section
– 2.4 V to 3.6 V for Power Amplifier Section

• Low Power Dissipation:

– 7 mW in Playback, 1.8 V/2.4 V, 48 kHz
– 13 mW in Record, 1.8 V/2.4 V, 48 kHz
– 30 µ W in Power Down

• Sampling Frequency: 5 kHz to 50 kHz

• Automatic Level Control for Recording

• Operation From a Single Clock Input Without

PLL

• System Clock:

– Common-Audio Clock (256 fS/384 fS), 12/24,

13/26, 13.5/27, 19.2/38.4, 19.68/39.36 MHz

DESCRIPTION

The PCM3793/94 is a low-power stereo CODEC
designed for portable digital audio applications. The
device integrates stereo digital speaker amplifier,
headphone amplifier, line amplifier, line input, boost
amplifier, microphone bias, programmable gain
control, analog mixing, sound effects, and automatic
level control (ALC). It is available in a small-footprint,
5-mm × 5-mm QFN package. The PCM3793/94
accepts right-justified, left-justified, I2S, and DSP
formats, providing easy interfacing to audio DSP,
decoder, and encoder chips. Sampling rates up to 50
kHz are supported. The user-programmable
functions are accessible through a two- or three-wire
serial control port.

• Headphone Plug Insert Detection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2006–2007, Texas Instruments Incorporated

www.ti.com

PCM3793
PCM3794

SLES193C – AUGUST 2006 – REVISED FEBRUARY 2007

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

ORDERING INFORMATION

PRODUCT PACKAGE TEMPERATURE TRANSPORT MEDIA

PCM3793RHB 32 QFN RHB –40 ° C to 85 ° C PCM3793

PCM3794RHB 32 QFN RHB –40 ° C to 85 ° C PCM3794

(1) For the most current specification and package information, see the TI Web site at www.ti.com .

PACKAGE PACKAGE ORDERING

CODE MARKING NUMBER

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Supply voltage VDD, VIO, VCC, V
Ground voltage differences: DGND, AGND, PGND ± 0.1 V
Input voltage –0.3 to 4 V
Input current (any pins except supplies and SPK out) ±10 mA
Ambient temperature under bias –40 to 110 ° C
Storage temperature –55 to 150 ° C
Junction temperature 150 ° C
Lead temperature (soldering) 260 ° C, 5 s
Package temperature (reflow, peak) 260 ° C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

PA

OPERATION

RANGE

PCM3793RHBT Small tape and reel
PCM3793RHBR Large tape and reel
PCM3794RHBT Small tape and reel
PCM3794RHBR Large tape and reel

(1)

(1)

PCM3793/94 UNIT

–0.3 to 4 V

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

VCC, V
V

DD

T

A

2

Analog supply voltage 2.4 3.3 3.6 V

PA

, V

Digital supply voltage 1.71 3.3 3.6 V

IO

Digital input logic family CMOS

Digital input clock frequency

Analog output load resistance HPOL and HPOR 16 Ω

Analog output load capacitance 30 pF
Digital output load capacitance 10 pF
Operating free-air temperature –40 85 ° C

SCKI system clock 3.072 18.432 MHz
LRCK sampling clock 8 48 kHz
LOL and LOR 10 k Ω

SPOLP, SPOLN, SPORP and SPORN 8 Ω

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MIN NOM MAX UNIT

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SLES193C – AUGUST 2006 – REVISED FEBRUARY 2007

ELECTRICAL CHARACTERISTICS

All specifications at TA= 25 ° C, V
otherwise noted).

PARAMETER TEST CONDITIONS UNIT

Audio Data Characteristics
DATA FORMAT

Resolution 16 Bits
Audio data interface format I2S, left-, right-justified, DSP
Audio data bit length 16 Bits
Audio data format MSB first, 2s complement
Sampling frequency (fS) 5 50 kHz

System clock MHz

Digital Input/Output

Logic family CMOS compatible

V

IH

V
I

IH

I

IL

V
V

Digital Input to Line Output Through DAC (LOL, LOR, and MONO)

RL= 10 k Ω , ALC = OFF, volume = 0 dB, speaker = powered down, analog mixing = disabled

DYNAMIC PERFORMANCE

SNR Signal-to-noise ratio EIAJ, A-weighted 86 93 dB

THD+N Total harmonic distortion + noise 0 dB 0.008%

Line Input to Line Output Through Mixing Path (LOL, LOR, and MONO)

RL= 10 k Ω , ALC = OFF, volume = 0 dB, speaker = powered down, analog mixing = enabled

DYNAMIC PERFORMANCE

SNR Signal-to-noise ratio EIAJ, A-weighted 84 93 dB

Input logic level

IL

Input logic current µ A

OH

Output logic level

OL

Full-scale output voltage

Dynamic range EIAJ, A-weighted 93 dB

Channel separation 91 dB

Load resistance 10 k Ω

Full-scale input and output
voltage

= V

= V

= V

DD

IO

CC

= 3.3 V, fS= 48 kHz, system clock = 256 fS, and 16-bit data (unless

PA

PCM3793RHB, PCM3794RHB

MIN TYP MAX

V

< 2 V 27

DD

V

> 2 V 40

DD

0.7 V

IO

0.3 V

IO

VIN= 3.3 V 10
VIN= 0 V –10
IOH= –2 mA 0.75 V
IOL= 2 mA 0.25 V

IO

IO

0 dB 2.828 Vp-p

1 Vrms

0 dB

2.828 Vp-p
1 Vrms

PCM3793
PCM3794

VDC
VDC

VDC
VDC

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PCM3793
PCM3794

SLES193C – AUGUST 2006 – REVISED FEBRUARY 2007

ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA= 25 ° C, V
otherwise noted).

PARAMETER TEST CONDITIONS UNIT

Digital Input to Headphone Output Through DAC (HPOL and HPOR)

RL= 16 Ω or 32 Ω , ALC = OFF, volume = 0 dB, speaker = powered down, analog mixing = disabled, not capless mode

DYNAMIC PERFORMANCE

Full-scale output voltage 0 dB

SNR Signal-to-noise ratio EIAJ, A-weighted 84 93 dB

THD+N Total harmonic distortion + noise

Load resistance 16 Ω

PSRR Power-supply rejection ratio 1 kHz, 140 mVp-p –45 dB

Line Input to Headphone Output Through Mixing Path (HPOL and HPOR)

RL= 16 Ω or 32 Ω , ALC = OFF, volume = 0 dB, speaker = powered down, analog mixing = enabled, not capless mode

DYNAMIC PERFORMANCE

Full-scale output voltage 0 dB

SNR Signal-to-noise ratio EIAJ, A-weighted 84 93 dB

Load resistance 16 Ω

Digital Input to Speaker Output Through DAC (SPOLP, SPOLN, SPORP, and SPORN): PCM3793

RL= 8 Ω , ALC = OFF, volume = 0 dB, headphone = powered down, analog mixing = disabled

DYNAMIC PERFORMANCE

Full-scale output voltage 0 dB

SNR Signal-to-noise ratio EIAJ, A-weighted 84 93 dB
THD+N Total harmonic distortion + noise 400 mW, RL= 8 Ω , volume = 0 dB 0.3%

Load resistance 8 Ω

PSRR Power-supply rejection ratio 1 kHz, 140 mVp-p –45 dB

Line Input to Speaker Output Through Mixing Path (SPOLP, SPOLN, SPORP, and SPORN): PCM3793

RL= 8 Ω , ALC = OFF, volume = 0 dB, headphone = powered down, analog mixing = enabled

DYNAMIC PERFORMANCE

Full-scale output voltage 0 dB

SNR Signal-to-noise ratio EIAJ, A-Weighted 84 93 dB

= V

= V

= V

DD

IO

CC

30 mW, RL= 32 Ω , volume = 0 dB 0.1%
40 mW, RL= 16 Ω , volume = –1 dB 0.03%

200 Hz, 140 mVp-p –40

20 kHz, 140 mVp-p –32

200 Hz, 140 mVp-p –50

20 kHz, 140 mVp-p –25

= 3.3 V, fS= 48 kHz, system clock = 256 fS, and 16-bit data (unless

PA

PCM3793RHB, PCM3794RHB

MIN TYP MAX

2.828 Vp-p

2.828 Vp-p

2.52 Vp-p

0.9 Vrms

2.52 Vp-p

0.9 Vrms

1 Vrms

1 Vrms

4

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SLES193C – AUGUST 2006 – REVISED FEBRUARY 2007

ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA= 25 ° C, V
otherwise noted).

PARAMETER TEST CONDITIONS UNIT

Line Input to Digital Output Through ADC (AIN1L/R, AIN2L/R, AIN3L, and AIN3L/R)

ALC = OFF, microphone boost = 0 dB, PGA = 0 dB, speaker and headphone = powered down, analog mixing = disabled

DYNAMIC PERFORMANCE

Full-scale input voltage 0 dB

Dynamic range EIAJ, A-weighted 90 dB

SNR Signal-to-noise ratio EIAJ, A-weighted 83 90 dB

Channel separation 87 dB

THD+N Total harmonic distortion + noise –1 dB 0.009%

ANALOG INPUT

Center voltage 0.5 V
Input impedance 10 20 k Ω

Microphone Bias

ALC = OFF, microphone boost = 0 dB, PGA = 0 dB, speaker and headphone = powered down, analog mixing = disabled

Bias voltage 0.75 V
Bias source current 2 mA
Output noise 14 µ V

Filter Characteristics
INTERPOLATION FILTER FOR DAC

Pass band 0.454 f
Stop band 0.546 f
Pass-band ripple ± 0.04 dB
Stop-band attenuation –50 dB
Group delay 19/f
De-emphasis error ± 0.1 dB

ANALOG FILTER FOR DAC

Frequency response f = 20 kHz ± 0.2 dB

DECIMATION FILTER FOR ADC

Pass band 0.408 f
Stop band 0.591 f
Pass-band ripple ± 0.02 dB
Stop-band attenuation f < 3.268 f
Group delay 17/f

HIGH-PASS FILTER FOR ADC

Frequency response Hz

= V

= V

= V

DD

IO

CC

= 3.3 V, fS= 48 kHz, system clock = 256 fS, and 16-bit data (unless

PA

PCM3793RHB, PCM3794RHB

MIN TYP MAX

2.828 Vp-p
1 Vrms

CC

CC

S

S

s

S

S

S

–60 dB

S

–3 dB, fc= 4 Hz 3.74
–0.5 dB, fc= 4 Hz 10.66
–0.1 dB, fc= 4 Hz 24.2
–3 dB, fc= 240 Hz 235.68
–0.5 dB, fc= 240 Hz 609.95
–0.1 dB, fc= 240 Hz 2601.2

PCM3793
PCM3794

V

V

s

s

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PCM3793
PCM3794

SLES193C – AUGUST 2006 – REVISED FEBRUARY 2007

ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA= 25 ° C, V
otherwise noted).

PARAMETER TEST CONDITIONS UNIT

Power Supply and Supply Current

V

IO

V

DD

V
V

Temperature Condition

θ

JA

Voltage range VDC

CC
PA

Supply current

Power dissipation

Operation temperature –40 85 ° C
Thermal resistance 30 ° C/W

DD

= V

= V

= V

IO

CC

= 3.3 V, fS= 48 kHz, system clock = 256 fS, and 16-bit data (unless

PA

PCM3793RHB, PCM3794RHB

MIN TYP MAX

V

IO

V

DD

V

CC

V

PA

1.71 3.3 3.6

1.71 3.3 3.6

2.4 3.3 3.6

2.4 3.3 3.6
BPZ input, all active, no load 24.3 35 mA
All inputs are held static 9 50 µ A
BPZ input 80.2 115.5 mW
All inputs are held static 30 165 µ W

6

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P0048-03

HPOR/LORAIN2L

BCK

AIN2R

24123222321420519618717

8

16

25

15

26

14

27

13

28

12

29

1130

1031

932

SPOLP

AIN3L

SPOLN

AIN3R

PGND

MICB

V

PA

V

CC

SPORP

AGND

SPORN

V

COM

HPCOM/MONO

HPOL/LOL

PCM3793RHB

(TOP VIEW)

AIN1R

DIN

AIN1L

DOUT

MODE

V

IO

MS/ADR

V

DD

MD/SDA

DGND

MC/SCL

SCKI

LRCK

HDTI

P0048-04

HPOR/LORAIN2L

BCK

AIN2R

24123222321420519618717

8

16

25

15

26

14

27

13

28

12

29

1130

1031

932

NC

AIN3LNCAIN3R

PGND

MICB

V

PA

V

CC

NC

AGNDNCV

COM

HPCOM/MONO

HPOL/LOL

PCM3794RHB

(TOP VIEW)

AIN1R

DIN

AIN1L

DOUT

MODE

V

IO

MS/ADR

V

DD

MD/SDA

DGND

MC/SCL

SCKI

LRCK

HDTI

PCM3793
PCM3794

SLES193C – AUGUST 2006 – REVISED FEBRUARY 2007

PIN ASSIGNMENTS

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PCM3793
PCM3794

SLES193C – AUGUST 2006 – REVISED FEBRUARY 2007

Table 1. TERMINAL FUNCTIONS

TERMINAL

NAME PCM3793RHB PCM3794RHB

AGND 19 19 – Ground for analog
AIN1L 27 27 I Analog input 1 for L-channel
AIN1R 26 26 I Analog input 1 for R-channel
AIN2L 25 25 I Analog input 2 for L-channel
AIN2R 24 24 I Analog input 2 for R-channel
AIN3L 23 23 I Analog input 3 for L-channel
AIN3R 22 22 I Analog input 3 for R-channel
BCK 1 1 I/O Serial bit clock
DGND 6 6 – Digital ground
DIN 2 2 I Serial audio data input
DOUT 3 3 O Serial audio data output
HDTI 8 8 I Headphone plug insertion detection
HPCOM/MONO 9 9 O Headphone common/mono line output
HPOL/LOL 17 17 O Headphone/lineout for R-channel
HPOR/LOR 16 16 O Headphone/lineout for L-channel
LRCK 32 32 I/O Left and right channel clock
MC/SCL 31 31 I Mode control clock for three-wire/two-wire interface
MD/SDA 30 30 I/O Mode control data for three-wire/two-wire interface
MICB 21 21 O Microphone bias source output
MODE 28 28 I Two- or three-wire interface selection (LOW: SPI, HIGH: I2C)
MS/ADR 29 29 I Mode control select for three-wire/two-wire interface
PGND 13 13 – Ground for speaker power amplifier
SCKI 7 7 I System clock
SPOLN 14 – O Speaker output L-channel for negative (PCM3793)
SPOLP 15 – O Speaker output L-channel for positive (PCM3793)
SPORN 10 – O Speaker output R-channel for negative (PCM3793)
SPORP 11 – O Speaker output R-channel for positive (PCM3793)
V

CC

V

COM

V

DD

V

IO

V

PA

20 20 – Analog power supply
18 18 – Analog common voltage

5 5 – Power supply for digital core
4 4 – Power supply for digital I/O

12 12 – Power supply for power amplifier

I/O DESCRIPTION

8

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FUNCTIONAL BLOCK DIAGRAM

AIN3L

AIN2L

AIN1L

AIN1R

AIN2R

AIN3R

BCK

DIN

D

OUT

LRCK

MS

/ADR

MC/SCL

MD

/SDA

MO

DE

Seri

al Interface (SPI/I C)

2

S

CKI

Audio Interface

PGND

AGND

DGND

V

COM

MICB

SPOLP

SPOLN

SPORP

SPORN

HDTI

B0

181-01

+6t

o –70dB

+6to –70dB

+6to –70dB

+6to –70dB

HPL

SPL

S

PR

MUX1

D

AL

A

DL

DAR

COM

HPR

HPC

LOUT

R

OUT

PG5

V

IO

V

DD

V

PA

V

CC

MONO

MC

B

Mic Bias

CO

M

PG1

PG3

P

G4

0or+20dB

0or+20dB

0to –21dB

0to –21dB

+30to –12dB

+30to –12dB

MONO

Cl

ock

Ma

nager

Power On

Reset

Power Up/Down

Manager

ADR

D2S

MUX3

MUX2

MUX4

PG6

PG2

Analog Input L-ch

Analog Input R-ch

M

XL

MXR

HPOR

HPOL

CO

M

V

CO

M

Pos

sible for Power Up/Down

PC

M3794 has no Speaker Output

SW

1

SW2

SW

3

SW6

SW5

SW4

HPOL/

LOL

HPOR/

LOR

HPCOM

/MONO

DS

ADC

DS

ADC

DS

DAC

DS

DAC

Digital

Filter

Digital

Filter

(1)

Digital

Filter

Digital

Filter

(1)

A

TT

Mute

(1)

DecimationFilter

InterpolationFilter

3-DEnhancement

3-Band ToneControl

NotchFilter

PCM3793
PCM3794

SLES193C – AUGUST 2006 – REVISED FEBRUARY 2007

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–120

–100

–80

–60

–40

–20

0

0 1 2 3 4

Frequency [ f ]´

S

Amplitude – dB

G001

Frequency [ f ]´

S

Amplitude – dB

–0.2

–0.1

0

0.1

0.2

0 0.1 0.2 0.3 0.4 0.5

G002

Frequency [ f ]´

S

Amplitude – dB

G003

–120

–100

–80

–60

–40

–20

0

0 1 2 3 4

Frequency [ f ]´

S

Amplitude – dB

–0.2

–0.1

0

0.1

0.2

0 0.1 0.2 0.3 0.4 0.5

G004

PCM3793
PCM3794

SLES193C – AUGUST 2006 – REVISED FEBRUARY 2007

All specifications at TA= 25 ° C, V

INTERPOLATION FILTER, STOP BAND INTERPOLATION FILTER, PASS BAND

TYPICAL PERFORMANCE CURVES

= V

= V

DD

IO

= V

CC

PA

unless otherwise noted.

= 3.3 V, fS= 8 to 48 kHz, system clock = 256 fS, and 16-bit data,

Figure 1. Figure 2.

DECIMATION FILTER, STOP BAND DECIMATION FILTER, PASS BAND

Figure 3. Figure 4.

10

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Frequency [ f ]´

S

Amplitude – dB

G005

–20

–15

–10

–5

0

5

0 0.0005 0.001 0.0015 0.002

Frequency [ f ]´

S

Amplitude – dB

G006

–20

–15

–10

–5

0

5

0 0.01 0.02 0.03 0.04

Frequency – Hz

Amplitude – dB

G007

–15

–10

–5

0

5

10

15

0.01 0.1 1 10 1k100 10k

100k

Frequency – Hz

Amplitude – dB

G008

–15

–10

–5

0

5

10

15

0

200

600400 800

1k

All specifications at TA= 25 ° C, V
unless otherwise noted.

TYPICAL PERFORMANCE CURVES (continued)

= V

= V

= V

DD

IO

CC

= 3.3 V, fS= 8 to 48 kHz, system clock = 256 fS, and 16-bit data,

PA

PCM3793
PCM3794

SLES193C – AUGUST 2006 – REVISED FEBRUARY 2007

HIGH-PASS FILTER PASS-BAND CHARACTERISTICS HIGH-PASS FILTER PASS-BAND CHARACTERISTICS

(fC= 4 Hz at fS= 48 kHz) (fC= 240 Hz at fS= 48 kHz)

Figure 5. Figure 6.

All specifications at TA= 25 ° C, V

= V

= V

= V

DD

IO

CC

= 3.3 V, fS= 44.1 kHz, system clock = 256 fS, and 16-bit data, unless

PA

otherwise noted.

THREE-BAND TONE CONTROL (BASS, MIDRANGE,

TREBLE) THREE-BAND TONE CONTROL (BASS)

Figure 7. Figure 8.

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Frequency – Hz

A

mplitude – dB

G009

–15

–10

–5

0

5

10

15

0

1k

3k2k 4k

5k

Frequency – Hz

Amplitude – dB

G010

–15

–10

–5

0

5

10

15

2k

4k

8k6k 10k

12k 14k

PG3/PG4 Gain – dB

SNR – dB

G011

40

50

60

70

85

90

100

0

5

1510 20

25 30

Single Input

Differential Input

f = 1 kHz

IN

PG3/PG4 Gain – dB

SNR – dB

G012

40

45

65

60

55

50

70

75

80

85

90

0

5

1510 20

25 30

Single Input

Differential Input

f = 1 kHz

IN

PCM3793
PCM3794

SLES193C – AUGUST 2006 – REVISED FEBRUARY 2007

TYPICAL PERFORMANCE CURVES (continued)

All specifications at TA= 25 ° C, V
otherwise noted.

THREE-BAND TONE CONTROL (MIDRANGE) THREE-BAND TONE CONTROL (TREBLE)

DD

= V

= V

= V

IO

CC

= 3.3 V, fS= 44.1 kHz, system clock = 256 fS, and 16-bit data, unless

PA

All specifications at TA= 25 ° C, V

ADC SNR AT HIGH GAIN (PG1/PG2 = 0 dB) ADC SNR AT HIGH GAIN (PG1/PG2 = 20 dB)

12

Figure 9. Figure 10.

Figure 11. Figure 12.

= V

DD

= V

IO

= V

CC

= 3.3 V, fS= 48 kHz, system clock = 256 fS, and 16-bit data, unless

PA

otherwise noted.

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Power Supply – V

THD+N – %

SNR – dB

G013

0

0.2

0.4

0.6

0.8

1

90

91

92

93

94

95

2 2.5 3.53 4

f = 1 kHz

IN

THD+N

SNR

Power Supply – V

THD+N – %

SNR – dB

G014

0

0.01

0.02

0.03

0.04

0.05

90

91

92

93

94

95

2 2.5 3.53 4

f = 1 kHz

IN

THD+N

SNR

Power Supply – V

THD+N – %

SNR – dB

G015

0.007

0.008

0.009

0.010

0.011

0.012

90

91

92

93

94

95

2 2.5 3.53 4

f = 1 kHz

IN

THD+N

SNR

Power Supply – V

THD+N – %

SNR – dB

G016

0.007

0.008

0.009

0.010

0.011

0.012

87

88

89

90

91

92

2 2.5 3.53 4

f = 1 kHz

IN

THD+N

SNR

All specifications at TA= 25 ° C, V
otherwise noted.

THD+N/SNR vs POWER SUPPLY THD+N/SNR vs POWER SUPPLY

DAC TO SPEAKER OUTPUT, 8- Ω DAC TO HEADPHONE OUTPUT, 16- Ω

TYPICAL PERFORMANCE CURVES (continued)

= V

= V

= V

DD

IO

CC

= 3.3 V, fS= 48 kHz, system clock = 256 fS, and 16-bit data, unless

PA

PCM3793
PCM3794

SLES193C – AUGUST 2006 – REVISED FEBRUARY 2007

Figure 13. Figure 14.

THD+N/SNR vs POWER SUPPLY THD+N/SNR vs POWER SUPPLY

DAC TO LINE OUTPUT, 10-k Ω ADC TO DIGITAL OUTPUT

Figure 15. Figure 16.

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0

20

2 2.5 3.5 43

40

60

80

100

120

Power Supply – V

O

utput Power – mW

G017

Vol = 6 dB

Vol = 0 dB

f = 1 kHz

IN

Power Supply – V

Ou

tput Power – mW

G018

0

400

300

200

100

500

600

700

800

900

2

2.5 3

3.5 4

Vol = +6 dB

Vol = 0 dB

f = 1 kHz

IN

Output Power – mW

T

HD+N – %

G019

0.01

0.1

1

10

100

0

20

6040 80

100 120

f = 1 kHz

IN

2.4 V

2.7 V

3.3 V

3.6 V

Output Power – mW

T

HD+N – %

G020

0.01

0.1

1

0

20

6040

80

f = 1 kHz

IN

2.4 V

2.7 V

3.3 V

3.6 V

PCM3793
PCM3794

SLES193C – AUGUST 2006 – REVISED FEBRUARY 2007

TYPICAL PERFORMANCE CURVES (continued)

All specifications at TA= 25 ° C, V
otherwise noted.

DD

= V

= V

= V

IO

CC

= 3.3 V, fS= 48 kHz, system clock = 256 fS, and 16-bit data, unless

PA

OUTPUT POWER vs POWER SUPPLY OUTPUT POWER vs POWER SUPPLY

(HEADPHONE, 16- Ω ) (SPEAKER, 8- Ω )

Figure 17. Figure 18.

THD+N vs OUTPUT POWER THD+N vs OUTPUT POWER

(HEADPHONE, 16- Ω , VOLUME = 6 dB) (HEADPHONE, 16- Ω , VOLUME = 0 dB)

14

Figure 19. Figure 20.

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Output Power – mW

THD+N – %

G021

0.01

0.1

1

10

100

0

200

600400 800

1000

f = 1 kHz

IN

2.4 V

2.7 V

3.3 V

3.6 V

Output Power – mW

THD+N – %

G022

0.01

0.1

1

0

100 200 300

500400

600

2.4 V

2.7 V

3.3 V

3.6 V

f = 1 kHz

IN

Frequency – kHz

Amplitude – dB

G023

–140

0 20

155 10

–120

–100

–80

–60

–40

–20

0

f = 1 kHz/–60 dB

IN

Frequency – kHz

A

mplitude – dB

G024

–140

0 20

155 10

–120

–100

–80

–60

–40

–20

0

f = 1 kHz/–60 dB

IN

All specifications at TA= 25 ° C, V
otherwise noted.

THD+N vs OUTPUT POWER THD+N vs OUTPUT POWER

(SPEAKER, 8- Ω , VOLUME = 6 dB) (SPEAKER, 8- Ω , VOLUME = 0 dB)

TYPICAL PERFORMANCE CURVES (continued)

= V

= V

= V

DD

IO

CC

= 3.3 V, fS= 48 kHz, system clock = 256 fS, and 16-bit data, unless

PA

PCM3793
PCM3794

SLES193C – AUGUST 2006 – REVISED FEBRUARY 2007

OUTPUT SPECTRUM (DAC TO HEADPHONE OUTPUT,

Figure 21. Figure 22.

16- Ω ) OUTPUT SPECTRUM (DAC TO SPEAKER OUTPUT, 8- Ω )

Figure 23. Figure 24.

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PCM3793
PCM3794

SLES193C – AUGUST 2006 – REVISED FEBRUARY 2007

PCM3793/94 DESCRIPTION

Analog Input

The AIN1L, AIN1R, AIN2L, AIN2R, AIN3L, and AIN3R pins can be used as microphone or line inputs with
selectable 0- or 20-dB boost and 1-Vrms input. All analog inputs have high input impedance (20 k Ω ), which is
not changed by gain settings. One pair of inputs is selected by register 87 (AIL[1:0], AIR[1:0]). AIN1L and AIN1R
can be used as monaural differential inputs.

Gain Settings for Analog Input

Analog signals can be adjusted from 30 dB to –12 dB in 1-dB steps following the 0- or 20-dB boost amplifier.
The gain level can be set for each channel by registers 79 and 80 (ALV[5:0], ARV[5:0]).

A/D Converter

The ADC includes a multilevel delta-sigma modulator, aliasing filter, decimation filter, high-pass filter, and notch
filter and can accept a 1-Vrms full-scale voltage input. The decimation filter has a digital soft mute controlled by
register 81 (RMUL, RMUR). The high-pass filter can be disabled by register 81 (HPF[1:0]) and the notch filter
can be disabled by registers 96 to 104 if it is not necessary to cancel a dc offset or compensate for wind noise.

D/A Converter

The DAC includes a multilevel delta-sigma modulator and interpolation filter. These can be used to obtain high
PSRR, low jitter sensitivity, and low out-of-band noise quickly and easily. The interpolation filter includes digital
attenuator, digital soft mute, three-band tone control (bass, midrange and treble), and 3-D sound controlled by
registers 92 to 95. The de-emphasis filter (32, 44.1 and 48 kHz) is controlled by registers 68 to 70 (ATL[5:0],
ATR[5:0], PMUL, PMUR, DEM[1:0]). Oversampling rate control can reduce out-of-band noise when operating at
low sampling rate by using register 70 (OVER).

Common Voltage

The V

pin is normally biased to 0.5 V

COM

, and it provides the common voltage to internal circuitry. It is

CC

recommended that a 10- µ F capacitor be connected between this pin and ground to provide clean voltage and
avoid pop noise. The PCM3793/94 may have a little pop noise on each analog output if a capacitor smaller than
10 µ F is used.

Line Output

The HPOL/LOL and HPOR/LOR and HPCOM/MONO pins can be used as a monaural single-ended, monaural
differential, or stereo single-line output with 1-V

output by register 74 (HPS[1:0]). The line outputs can drive a

rms

10-k Ω load. These outputs include an analog volume amplifier, except for the HPCOM/MONO pin that can be
set from 6 dB to –70 dB and mute with 0.5-, 1-, 2- or 4-dB steps for each output, as controlled by registers 64
and 65 (HLV[5:0], HRV[5:0], HMUL, HMUR). A dc blocking capacitor is not required when connecting to an
external speaker amplifier with monaural differential input. The center voltage is 0.5 V

with zero data input.

CC

Headphone Output

The HPOL/LOL, HPOR/LOR, and HPCOM/MONO pins are stereo, monaural, or monaural differential
headphone outputs with more than 30 or 40 mWrms output power into a 32- or 16- Ω load, either through a dc
blocking capacitor or without a capacitor, as selected by register 74 (HPS[2:0]). These outputs include analog
volume amplifiers, except for the HPCOM/MONO pin, which can be set from 6 dB to –70 dB with 0.5-, 1-, 2- or
4-dB steps for each output using registers 64 and 65 (HLV[5:0], HRV[5:0], HMUL, HMUR). The center voltage is

0.5 V

with zero data input.

CC

Headphone Plug Insertion Detection

The HDTI pin detects the insertion status of headphone plug and writes the status to register 77 (HPDS), which
can be read by the I2C interface. The polarity of the status indication can be inverted by register 75 (HPDP). The
headphone and speaker amplifiers are disabled or enabled automatically by headphone plug
insertion/extractrion if register 75, HPDE = 1. They are controlled by register settings if register 75, HPDE = 0.
HPCOM/MONO is not affected by the status when register 74, CMS[0] = 1.

16

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PCM3793
PCM3794

SLES193C – AUGUST 2006 – REVISED FEBRUARY 2007

Speaker Output (Class-D, PCM3793)

The SPOLP, SPOLN and SPORP, SPORN pins are stereo or mono speaker differential outputs (BTL) with a
maximum of 700 mWrms (V
maximum battery life and minimum heat, eliminates the LC low-pass filter, and includes analog volume
amplification for each output from 6 dB to –70 dB with 0.5-, 1-, 2- or 4-dB steps, which can be set by register 66,
67 (SLV[5:0], SLR[5:0]). Spectrum spreading technology and selectable switching frequency to reduce EMI
noise is controlled by register 71 (DFQ[2:0], SPS[1:0] and SPSE). The speaker amplifiers have a thermal
shutdown circuit which detects when the device temperature reaches approximately 150 ° C; then the speaker
amplifier is powered down.

Analog Mixing and Bypass

Mixing amplifiers (MXL, MXR) mix gain-controlled analog inputs from the AIN pins which have bypassed ADC
and DAC and direct the mixed signal to the headphone or speaker outputs. Analog mixing is controlled by
register 87 (AD2S, AIR[1:0], AIL[1:0]), register 88 (MXR[2:0], MXL[2:0]), and register 89 (GMR[2:0], GML[2:0]).
The analog mixing functions are suitable for FM radio, headset, and another analog sources without an ADC.

Microphone Bias

The MICB pin is the microphone bias source for an external microphone and can provide 2 mA (typical) bias
current.

Automatic Level Control (ALC) for Recording

The sound for microphone recording should be expanded to a suitable level without saturation. The digitally
controlled automatic level control (ALC) provides automatic expansion for small input signals and compression
for large input signals while recording. The expansion level, compression level, attack time, and recovery time
can be selected by register 83. The register 83 description explains the details of these settings.

= 3.6 V, volume = 6 dB) into an 8- Ω load. The digital speaker amplifier offers

PA

3-D Sound

A 3-D sound effect is provided by mixing L-channel and R-channel data with band pass filter that can be
controlled two parameters, mixing ratio and band pass filter characteristic by register 95 (3DP[3:0], 3FLO). The
3-D sound effect can be applied to the DAC digital input or ADC digital output, as selected by register 95
(SDAS).

Three-Band Tone Control

Tone control has bass, midrange, and treble controls that can be adjusted from 12 dB to –12 dB in 1-dB steps
by registers 92 to 94 (LGA[4:0], MGA[4:0] and HGA[4:0]). Register 92 (LPAE) attenuates the digital input signal
automatically to prevent clipping of the output signal at settings above 0 dB for bass control. LPAE has no effect
on midrange and treble controls.

High-Pass Filter and Notch Filter

The high-pass filter eliminates the dc offset of the ADC analog signal and can be set for a cutoff frequency of 4
Hz or 240 Hz at of 48-kHz sampling frequency by register 81 (HPF[1:0]). A register 95 (SDAS) selection applies
the filter to either the DAC digital input or the ADC digital output.

Notch filters are provided to remove noise of a particular frequency, such as CCD noise, motor noise, or other
mechanical noise in a particualr application. The PCM3793/94 has two notch filters for which the center
frequency and frequency bandwidth can be programmed by registers 96 to 104. A register 95 (SDAS) selection
applies the filter to either the DAC digital input or the ADC digital output.

Digital Monaural Mixing

Register 96 (MXEN) enables or disables the internal mixing of stereo digital data to monaural digital data.

Zero-Cross Detection

Zero-cross detection minimizes audible zipper noise while changing analog volume and digital attenuation. This
function can be applied to digital input or digital output by register 86 (ZCRS).

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PCM3793
PCM3794

SLES193C – AUGUST 2006 – REVISED FEBRUARY 2007

Short Protection

The short-circuit protection on each headphone output prevents damage to the device while an output is shorted
to V

, an output is shorted to PGND, or any two outputs are shorted together. When the short circuit is detected

PA

on the outputs, the PCM3793/94 powers down the shorted amplifier at once. The short-protection status can be
monitored by reading register 77 (STHC, STHL, SCHR) through the I2C interface. Short-circuit protection
operates in any enabled headphone amplifier.

Thermal Protection

The thermal protection on the speaker amplifier prevents damage to the device when the internal die
temperature exceeds approximately 150 ° C. Once the die temperature exceeds the thermal set point, all analog
outputs are powered down. This status can be reset by setting register 76 (RLSR, RLSL) and can be watched
by reading register 77 (STSR, STSL) on the two-wire (I2C) interface. Thermal protection operates in any enabled
speaker amplifier.

Pop-Noise Reduction Circuit

The pop-noise reduction circuit prevents audible noise when turning the power supply on/off and powering the
device up/down in portable applications. It is recommended to establish the register settings in the sequence
that is shown in Table 3 and Table 4 . No particular external parts are required, and power-supply sequencing is
not necessary.

Power Up/Down for Each Module

Using register 72 (PMXL, PMXR), register 73 (PBIS, PDAR, PDAL, PHPC, PHPR, PHPL, PSPR, PSPL), register
82 (PAIR, PAIL, PADS, PMCB, PADR, PADL), and register 90 (PCOM), unused modules can be powered down
to minimize power consumption (7 mW during playback only and 13 mW when recording only).

Digital Interface

All digital I/O pins can interface at various power supply voltages. The V

pin can be connected to a 1.71-V to

IO

3.6-V power supply.

Power Supply

The V
The V
these pins (for example, V

pin and the V

CC

pin and the V

DD

pin can be connected to 2.4 V to 3.6 V. The same voltage must be applied to both pins.

PA

pin can be connected to 1.71 V to 3.6 V. A different voltage can be applied to each of

IO

DD

= 1.8 V, V

= 3.3 V).

IO

DESCRIPTION OF OPERATION

System Clock Input

The PCM3793/94 can accept clocks of various frequencies without a PLL. They are used for clocking the digital
filters and automatic level control and delta-sigma modulators and are classified as common-audio and
application-specific clocks. Table 2 shows frequencies of the common-audio clock and application-specific clock.

Figure 25 shows the timing requirements for system clock inputs. The sampling rate and frequency of the

system clocks are determined by the settings of register 86 (MSR[2:0]) and register 85 (NPR[5:0]). Note that the
sampling rate of the application-specific clock has a little sampling error.

Table 2. System Clock Frequencies

CLOCK FREQUENCIES

Common-audio clock 11.2896, 12.288, 16.9344, 18.432 MHz

Application-specific clock 12, 13, 13.5, 24, 26, 27, 19.2, 19.68, 38.4, 39.36 MHz

18

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t

w(SCKH)

SCKI

t

w(SCKL)

0.7V

IO

0.3V

IO

T0005-12

PCM3793
PCM3794

SLES193C – AUGUST 2006 – REVISED FEBRUARY 2007

PARAMETERS SYMBOL MIN UNITS

System-clock pulse duration, high t

System-clock pulse duration, low t

w(SCKH)
w(SCKL)

Figure 25. System Clock Timing

Power-On Reset and System Reset

The power-on-reset circuit outputs a reset signal, typically at V
the voltage of other power supplies (V

, V

CC

and V

PA

). Internal circuits are cleared to default status, then signals

IO

= 1.2 V, and this circuit does not depend on

DD

are removed from all analog and digital outputs. The PCM3793/94 does not require any power supply
sequencing. Register data must be written after turning all power supplies on.

System reset is enabled by setting register 85 (SRST), and all register are cleared automatically. All circuits are
reset to their default status at once. Note that the PCM3793/94 has audible pop noise on the analog outputs
when enabling SRST.

7 ns
7 ns

Power On/Off Sequence

To reduce audible pop noise, a sequence of register settings is required after turning all power supplies on when
powering up, or before turning the power supplies off when powering down. If some modules are not required for
a particular application or operation, they should be placed in the power-down state after performing the
power-on sequence. The recommended power-on and power-off sequences are shown in Table 3 and Table 4 ,
respectively.

Table 3. Recommended Power-On Sequence

STEP REGISTER NOTE

1 – Turn on all power supplies
2 4027h Headphone amplifier L-ch volume (–6 dB)
3 4127h Headphone amplifier R-ch volume (–6 dB)
4 4227h Speaker amplifier L-ch volume (–6 dB)
5 4327h Speaker amplifier R-ch volume (–6 dB)
6 4427h Digital attenuator L-ch (–24 dB)
7 4527h Digital attenuator R-ch (–24 dB)
8 4620h DAC audio interface format (left-justified)

9 4BC0h Headphone detection enable and inverting polarity. Short and thermal detection enable
10 5102h ADC audio interface format (left-justified)
11 5A10h V
12 49E0h DAC (DAL, DAR) and analog bias power up
13 5601h Zero-cross detection enable
14 4803h Analog mixer (MXL, MXR) power up
15 5811h Analog mixer input (SW2, SW5) select
16 49FCh Headphone amplifier (HPL, HPR, HPC) power up

SETTINGS

(1)

(2)

(2)

(2)

(2)

(2)

(2)

(3)

(3)

ramp up/down time control. PG1, PG2 gain control (0 dB)

COM

(1) Power supply sequencing is not required. It is recommended to set register data with system clock input after turning all power supplies

on.
(2) Any level is acceptable for volume or attenuation. Level should be resumed by register data recorded when system power off.
(3) Audio interface format should be set to match the DSP or decoder being used.

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PCM3793
PCM3794

SLES193C – AUGUST 2006 – REVISED FEBRUARY 2007

Table 3. Recommended Power-On Sequence (continued)

STEP REGISTER NOTE

17 4C03h Speaker amplifier shut down release
18 4A01h V
19 523Fh Analog front end (ADL, ADR, D2S, MCB, PG1, 2, 5, 6) power up
20 5711h Analog input (MUX3, MUX4) select. Analog input (MUX1, MUX2) select
21 4F0Ch Analog input L-ch (PG3) volume (0 dB)
22 500Ch Analog input R-ch (PG4) volume (0 dB)
23 – Any settings for other devices or wait time
24 49FFh Speaker amplifier (SPL, SPR) power up

(4) The PCM3793 requires time for V

and the setting of register 90 CMT[1:0]. Wait time [s] = 4 × C
(5) The PCM3794 does not require this setting because it has no speaker output.

STEP REGISTER NOTE

1 447Fh DAC L-ch digital soft-mute enable
2 457Fh DAC R-ch digital soft-mute enable
3 5132h ADC L-ch/R-ch digital soft-mute enable, ADC audio interface format (left-justified)
4 5811h Analog mixer input (SW2, SW5) Select
5 49FFh Headphone amplifier (HPL, HPR, HPC) power up
6 5200h Analog front end (ADL, ADR, D2S, MCB, PG1, 2, 5, 6) power down
7 5A10h V
8 4A00h V

9 – Wait time (100 ms)
10 5A00h V
11 – Wait time (100 ms)
12 5A20h V
13 – Wait time (4000 ms)
14 5A30h V
15 49E0h Headphone amplifier (HPL, HPR, HPC) power down, speaker amplifier (SPL, SPR) power down
16 4800h Analog mixer (MXL, MXR) power down
17 4900h DAC (DAL, DAR) and analog bias power down
18 – Turn off all power supplies

(1) Any level is acceptable for volume or attenuation.
(2) Audio interface format should be set according to DSP or decoder.
(3) PCM3794 has no speaker amplifier.
(4) These modules must be powered up during the power-down sequence.
(5) Power supply sequencing is not required. It is recommended to turn off all power supply after register settings with system clock input.

SETTINGS

power up

COM

(2)

(2)

(4) (5)

(5)

to reach the common level from GND level. The delay depends on the capacitor value for V

COM

× R

VCOM

CMT

Table 4. Recommended Power-Off Sequence

SETTINGS

(1)

(1)

(2)

(4)

, speaker amplifier (SPL, SPR) power up

ramp up/down time control, PG1, PG2 gain control (0 dB)

COM

power down

COM

ramp up/down time control

COM

ramp up/down time control

COM

ramp up/down time control

COM

(5)

COM

(3) (4)

Power-Supply Current

The current consumption of the PCM3793/94 depends on power up/down status of each circuit module. In order
to reduce the power consumption, disabling each module is recommended when it is not used in an application
or operation. Table 5 shows the current consumption in some states.

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PCM3793
PCM3794

SLES193C – AUGUST 2006 – REVISED FEBRUARY 2007

Table 5. Power Consumption Table

OPERATION MODE POWER SUPPLY CURRENT [mA] PD [mW] PD [mW]

V

DD

(1.8 V) (3.3 V) (3.3 V) (3.3 V) (3.3 V) (V

All Power Down 0 0 0.007 0.002 0 0.03 0.03
All Active 2.5 5.1 7.5 11.6 0.1 67.7 80.2

PLAYBACK WITH DIGITAL INPUT

Line output and headphone output 1.18 2.51 1.79 0.54 0.09 10.1 16.3
Headphone output with sound effect 1.81 3.84 1.79 0.54 0.09 11.2 20.7
Capless headphone output 1.18 2.51 1.8 0.75 0.09 10.8 17.0
Headphone output with line input (AIN2L/AIN2R) 1.18 2.52 2.09 0.54 0.09 11.1 17.3
Headphone output with mono microphone input (AIN1L, 20 dB) 1.18 2.52 2.5 0.54 0.09 12.5 18.6
Headphone output with mono differential microphone input 1.18 2.52 2.8 0.54 0.09 13.4 19.6

(AIN1L/AIN1R, 20 dB)
Stereo speaker output 1.21 2.58 2.18 10.94 0.09 45.8 52.1
Mono speaker output 1.20 2.57 2.01 5.61 0.09 27.6 33.9
Speaker output with line input (AIN2L/AIN2R) 1.21 2.57 2.48 10.95 0.09 46.8 53.1
Speaker output with mono microphone input (AIN1L, 20 dB) 1.21 2.58 2.89 10.96 0.09 48.2 54.5
Speaker output with mono differential microphone input 1.2 2.58 3.2 10.98 0.09 49.3 55.6

(AIN1L/AIN1R, 20 dB)

PLAYBACK WITHOUT DIGITAL INPUT

Line input (AIN2L/AIN2R) to headphone output 0 0 0.76 0.53 0 4.3 4.3
Mono line input (AIN2L) to headphone output 0 0 0.61 0.53 0 3.8 3.8
Mono microphone Input (AIN1L, 20 dB) to headphone output 0 0 1.18 0.53 0 5.6 5.6
Mono differential microphone input (AIN1L/AIN1R, 20 dB) to 0 0 1.48 0.53 0 6.6 6.6

headphone output
Mono microphone input (AIN1L, 20 dB) to speaker output 0 0 1.57 10.92 0 41.2 41.2

RECORDING

Line input (AIN3L/AIN3R) 1.86 3.89 4.58 0.13 0.1 19.2 28.7
Microphone input (AIN1L/AIN1R, 20 dB) 1.86 3.91 5.14 0.13 0.1 21.1 30.6
Microphone input (AIN1L/AIN1R, 20 dB) with ALC 2.78 5.77 5.14 0.13 0.1 22.7 36.8
Mono microphone input (AIN1L, 20 dB) 1.4 2.93 3.6 0.13 0.1 15.2 22.3
Mono microphone input (AIN1L, 20 dB) with ALC 2.2 4.74 3.6 0.13 0.1 16.6 28.3
Mono differential microphone input (AIN1L/AIN1R, 20 dB) 1.4 2.94 3.96 0.13 0.1 16.3 23.5
Mono differential microphone input (AIN1L/AIN1R, 20 dB) with 2.2 4.74 3.96 0.13 0.1 17.8 29.5

ALC

Conditions: 48 kHz/256 fS, 16 bits, slave mode, zero data input, no load

V

DD

V

CC

V

PA

V

TOTAL TOTAL

IO

DD

= 1.8 (V

V)

= 3.3 V)

DD

Audio Serial Interface

The audio serial interface for the PCM3793/94 comprises LRCK, BCK, DIN, and DOUT. Sampling rate (fS), left
and right channel are present on LRCK. DIN receives the serial data for the DAC interpolation filter, and DOUT
transmits the serial data from the ADC decimation filter. BCK clocks the transfer of serial audio data on DIN and
DOUT in its high-to-low transition. BCK and LRCK should be synchronized with audio system clock. Ideally, it is
recommended that they be derived from it.

The PCM3793/94 requires LRCK to be synchronized with the system clock. The PCM3793/94 does not require
a specific phase relationship between LRCK and the system clock.

The PCM3793/94 has both master mode and slave mode interface formats, which can be selected by register
84, MSTR. In master mode, the PCM3793/94 generates LRCK and BCK from the system clock.

Audio Data Formats and Timing

The PCM3793/94 supports I2S, right-justified, left-justified and DSP formats. The data formats are shown in

Figure 28 and are selected using register 70 (RFM[1:0], PFM[1:0]). All formats require binary 2s-complement,

MSB-first audio data. The default format is I2S. Figure 26 shows a detailed timing diagram.

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