SLES055 – NOVEMBER 2002
24-BIT STEREO AUDIO CODEC WITH 96-kHz ADC, 192-kHz DAC, AND
SINGLE-ENDED ANALOG INPUT/OUTPUT
PCM3010
FEATURES
24-Bit Delta-Sigma ADC and DAC
D
D Stereo ADC:
– Single-Ended Voltage Input: 3 Vp-p
– Antialiasing Filter Included
– 1/128, 1/64 Decimation Filter:
– Pass-Band Ripple: ±0.05 dB
– Stop-Band Attenuation: –65 dB
– On-Chip High-Pass Filter: 0.84 Hz at
f
= 44.1 kHz
S
– High Performance:
– THD+N: –95 dB (Typical)
– SNR: 100 dB (Typical)
– Dynamic Range: 102 dB (Typical)
D Stereo DAC:
– Single-Ended Voltage Output: 3 Vp-p
– Analog Low-Pass Filter Included
– ×8 Oversampling Digital Filter:
– Pass-Band Ripple: ±0.03 dB
– Stop-Band Attenuation: –50 dB
– High Performance:
– THD+N: –96 dB (Typical)
– SNR: 104 dB (Typical)
– Dynamic Range: 104 dB (Typical)
D Multiple Functions:
– Digital De-Emphasis: 32 kHz, 44.1 kHz,
48 kHz
– Power Down: ADC/DAC Simultaneous
– 16-, 24-Bit Audio Data Formats
D Sampling Rate: 16–96 kHz (ADC), 16–192 kHz
(DAC)
D System Clock: 128 f
512 f
, 768 f
S
S
, 192 fS, 256 fS, 384 fS,
S
D Dual Power Supplies: 5 V for Analog and 3.3 V
for Digital
D Package: 24-Pin SSOP, Lead-Free Product
APPLICATIONS
DVD Recorders
D
D CD Recorders
D PC Audio
D Sound Control System
DESCRIPTION
The PCM3010 is a low-cost single-chip 24-, 16-bit
stereo audio codec (ADC and DAC) with single-ended
analog voltage input and output. Both the
analog-to-digital converters (ADCs) and digital-toanalog converters (DACs) employ delta-sigma
modulation with 64-times oversampling. The ADCs
include a digital decimation filter with a high-pass filter,
and the DACs include an 8-times-oversampling digital
interpolation filter. The DACs also include a digital
de-emphasis function. The PCM3010 accepts four
different audio data formats for the ADC and DAC. The
PCM3010 provides a power-down mode, which works
on the ADC and DAC simultaneously . The PCM3010 is
suitable for a wide variety of cost-sensitive consumer
applications where good performance is required. The
PCM3010 is fabricated using a highly advanced CMOS
process and is available in a small 24-pin SSOP
package.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible
to damage because very small parametric changes could cause the device not to meet its published specifications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
Copyright 2002, Texas Instruments Incorporated
1
PCM3010
SLES055 – NOVEMBER 2002
DB PACKAGE
(TOP VIEW)
VINL
V
R
IN
V
1
REF
V
2
REF
V
1
CC
AGND1
FMT0
FMT1
TEST
LRCK
BCK
DIN
PACKAGE/ORDERING INFORMATION
PRODUCT
PCM3010DB 24-lead SSOP 24DB –25°C to 85°C PCM3010
PACKAGE
PACKAGE
CODE
1
2
3
4
5
6
7
8
9
10
11
12
OPERATION
TEMPERATURE RANGE
24
23
22
21
20
19
18
17
16
15
14
13
PACKAGE
MARKING
V
COM
V
L
OUT
V
R
OUT
V
2
CC
AGND2
DEMP0
DEMP1
PDWN
SCKI
V
DD
DGND
DOUT
ORDERING
NUMBER
PCM3010DB Tube
PCM3010DBR Tape and reel
TRANSPORT MEDIA
2
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block diagram
VINL
V
1
REF
V
2
REF
VINR
V
L
OUT
Single-End
Differential
Converter
Reference
and Buffer
Single-End
Differential
Converter
Analog LPF
and
Buffer Amp
Fifth-Order
Delta-Sigma
Modulator
Fifth-Order
Delta-Sigma
Modulator
Multilevel
Delta-Sigma
Modulator
× 1/128, 1/64
Decimation
Filter
with HPF
Clock and
Timing Generator,
Timing and
Power Control
SLES055 – NOVEMBER 2002
PCM3010
Audio
Data
Interface
DOUT
BCK
LRCK
DIN
SCKI
PDWN
TEST
V
V
COM
OUT
× 8
Oversampling
Interpolation
Filter
R
Analog LPF
and
Buffer Amp
Multilevel
Delta-Sigma
Modulator
Power Supply
VCC2AGND2 VCC1AGND1
DGND
Mode
Control
Interface
V
DD
FMT0
FMT1
DEMP0
DEMP1
Figure 1. PCM3010 Block Diagram
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3
PCM3010
SLES055 – NOVEMBER 2002
analog front-end (right-channel)
10 µF
10 µF
1 µF
+
+
+
VINL
V
REF
0.1 µF
V
REF
0.1 µF
1
1
3
2
4
0.5 VCC1
20 kΩ
–
+
–
+
Reference
(+)
(–)
Delta-Sigma
Modulator
4
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Terminal Functions
TERMINAL
NAME NO.
AGND1 6 – ADC analog ground
AGND2 20 – DAC analog ground
BCK 11 I Audio data bit clock input
DEMP1 18 I De-emphasis select input, 1
DEMP0 19 I De-emphasis select input, 0
DGND 14 – Digital ground
DIN 12 I Audio data digital input
DOUT 13 O Audio data digital output
FMT0 7 I Audio data format select input, 0
FMT1 8 I Audio data format select input, 1
LRCK 10 I Audio data latch enable input
PDWN 17 I ADC and DAC power-down control input, active LOW
SCKI 16 I System clock input
TEST 9 I Test control, must be open or connected to DGND
VCC1 5 – ADC analog power supply, 5 V
VCC2 21 – DAC analog power supply, 5 V
V
COM
V
DD
VINL 1 I ADC analog input, L-channel
VINR 2 I ADC analog input, R-channel
V
L 23 O DAC analog output, L-channel
OUT
V
R 22 O DAC analog output, R-channel
OUT
V
1 3 – ADC reference voltage decoupling, 1 (= 0.5 VCC1)
REF
V
2 4 – ADC reference voltage decoupling, 2
REF
†
Schimtt-trigger input with 50-kΩ typical internal pulldown resistor, 5-V tolerant.
‡
Schimtt-trigger input, 5-V tolerant.
I/O
‡
†
†
‡
†
†
‡
‡
24 – DAC common voltage decoupling (= 0.5 VCC2)
15 – Digital power supply, 3.3 V
DESCRIPTIONS
SLES055 – NOVEMBER 2002
PCM3010
†
†
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5
PCM3010
SLES055 – NOVEMBER 2002
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage: V
Supply voltage differences: V
1, VCC2 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
V
DD
1, VCC2 ±0.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
†
4.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ground voltage differences: AGND1, AGND2, DGND ±0.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage: PDWN
Digital input voltage: DOUT –0.3 V to (V
Analog input voltage, V
Analog input voltage, V
, TEST, FMT0, FMT1, DEMP0, DEMP1, LRCK, BCK, DIN, SCKI –0.3 V to +6.5 V. . . .
L, VINR, V
IN
, V
COM
OUT
REF
L, V
1, V
OUT
2 –0.3 V to (VCC1 + 0.3 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REF
R –0.3 V to (VCC2 + 0.3 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current (any pins except supplies) ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient temperature under bias –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature –55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Junction temperature 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature (soldering) 260°C, 5 s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package temperature (IR reflow, peak) 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
electrical characteristics, all specifications at TA = 25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V,
= 44.1 kHz, SCKI = 384 fS, 24-bit data (unless otherwise noted)
f
S
PARAMETER TEST CONDITIONS
DIGITAL INPUT/OUTPUT
DATA FORMAT
Audio data interface format Left-justified, I2S, right-justified
Audio data bit length 16, 24 Bits
Audio data format MSB-first, 2s complement
f
S
INPUT LOGIC
V
IH
V
IL
I
IH
I
IL
I
IH
I
IL
OUTPUT LOGIC
V
OH
V
OL
ADC CHARACTERISTICS
NOTES: 1. Pins 7, 8, 9, 17, 18, 19: PDWN , TEST , FMT0, FMT1, DEMP0, DEMP1 (Schmitt-trigger input with 50-kΩ typical internal pulldown
Sampling frequency, ADC 16 44.1 96 kHz
Sampling frequency, DAC 16 44.1 192 kHz
System clock frequency
Input logic level (see Notes 1 and 2)
Input logic current (see Note 2)
Input logic current (see Note 1)
Output logic level (see Note 3)
Resolution 24 Bits
resistor, 5-V tolerant).
2. Pins 10–12, 16: LRCK, BCK, DIN, SCKI (Schmitt-trigger input, 5-V tolerant).
3. Pin 13: DOUT.
128 fS, 192 fS, 256 fS, 384 fS, 512 fS, 768
f
S
VIN = V
DD
VIN = 0 V ±10 µA
VIN = V
DD
VIN = 0 V ±10 µA
I
= –4 mA 2.4
OUT
I
= 4 mA 0.4
OUT
PCM3010DB
MIN TYP MAX
4 50 MHz
2.0 5.5 VDC
0.8 VDC
±10 µA
65 100 µA
UNIT
VDC
6
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THD+N,
V
OUT
dB
dB
SLES055 – NOVEMBER 2002
PCM3010
electrical characteristics, all specifications at TA = 25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V,
= 44.1 kHz, SCKI = 384 fS, 24-bit data (unless otherwise noted) (continued)
f
S
PARAMETER TEST CONDITIONS
ACCURACY
Gain mismatch, channel-to-channel 1 kHz, full-scale input ±1 ±6 % of FSR
Gain error 1 kHz, full-scale input ±2 ±6 % of FSR
DYNAMIC PERFORMANCE (see Note 4)
THD+N VIN = –0.5 dB
THD+N VIN = –60 dB
Dynamic range
S/N ratio
Channel separation
ANALOG INPUT
Input voltage 60% of VCC1 Vp–p
Center voltage 50% of VCC1 V
Input impedance 20 kΩ
Anti-aliasing filter frequency response –3 dB 300 kHz
DIGITAL FILTER PERFORMANCE
Pass band 0.454 f
Stop band 0.583 f
Pass-band ripple ±0.05 dB
Stop-band attenuation –65 dB
Delay time 17.4/f
HPF frequency response –3 dB 0.019 f
DAC CHARACTERISTICS
Resolution 24 Bits
DC ACCURACY
Gain mismatch, channel-to-channel ±1.0 ±4.0 % of FSR
Gain error ±2.0 ±6.0 % of FSR
Bipolar zero error ±1.0 % of FSR
DYNAMIC PERFORMANCE (see Note 5)
THD+N, V
NOTES: 4. fIN = 1 kHz, using System Two audio measurement system, RMS mode with 20-kHz LPF, 400-Hz HPF in calculation.
5. f
OUT
= 0 dB
0
OUT
= 1 kHz, using System Two audio measurement system, RMS mode with 20-kHz LPF, 400-Hz HPF.
fS = 44.1 kHz –95 –86
fS = 96 kHz
fS = 44.1 kHz –39
fS = 96 kHz
fS = 44.1 kHz, A-weighted 97 102
fS = 96 kHz, A-weighted
fS = 44.1 kHz, A-weighted 95 100
fS = 96 kHz, A-weighted
fS = 44.1 kHz 93 98
fS = 96 kHz
fS = 44.1 kHz –96 –88
fS = 96 kHz
fS = 192 kHz –97
PCM3010DB
MIN TYP MAX
–92
–40
102
102
100
S
S
S
S
–97
UNIT
dB
dB
dB
dB
dB
Hz
Hz
sec
mHz
dB
System Two is a trademark of Audio Precision, Inc.
All other trademarks are the property of their respective owners.
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7
PCM3010
THD+N
V
OUT
dB
dB
Dynamic range
dB
S/N ratio
dB
Channel se aration
dB
Voltage range
VDC
I
CC
(ICC1 +
mA
I
DD
mA
Power dissi ation, o eration
mW
SLES055 – NOVEMBER 2002
electrical characteristics, all specifications at TA = 25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V,
= 44.1 kHz, SCKI = 384 fS, 24-bit data (unless otherwise noted) (continued)
f
S
PARAMETER TEST CONDITIONS
DYNAMIC PERFORMANCE (see Note 5) (Continued)
THD+N V
Dynamic range
S/N ratio
Channel separation
ANALOG OUTPUT
Output voltage 60% of VCC2 Vp-p
Center voltage 50% of VCC2 V
Load impedance AC coupling 5 kΩ
LPF frequency response
DIGITAL FILTER PERFORMANCE
Pass band ±0.03 dB 0.454 f
Stop band 0.546 f
Pass-band ripple ±0.03 dB
Stop-band attenuation 0.546 f
Delay time 20/f
De-emphasis error ±0.1 dB
POWER SUPPLY REQUIREMENTS
VCC1
VCC2
V
DD
I
(ICC1 +
ICC2)
I
DD
TEMPERATURE RANGE
θ
JA
NOTES: 5. f
Voltage range
pp
Supply current
Power dissipation, operation
Power dissipation, power down (see Note 6) 1 mW
Operating temperature –25 85 °C
Thermal resistance 24-pin SSOP 100 °C/W
OUT
6. Halt SCKI, BCK, LRCK.
= –60 dB
60
OUT
p
= 1 kHz, using System Two audio measurement system, RMS mode with 20-kHz LPF, 400-Hz HPF.
fS = 44.1 kHz –42
fS = 96 kHz
fS = 192 kHz –43
fS = 44.1 kHz, EIAJ, A-weighted 98 104
fS = 96 kHz, EIAJ, A-weighted
fS = 192 kHz, EIAJ, A-weighted 105
fS = 44.1 kHz, EIAJ, A-weighted 98 104
fS = 96 kHz, EIAJ, A-weighted
fS = 192 kHz, EIAJ, A-weighted 105
fS = 44.1 kHz 95 102
fS = 96 kHz
fS = 192 kHz 103
f = 20 kHz –0.03
f = 44 kHz
S
fS = 44.1 kHz 31 40
fS = 96 kHz 32
fS = 192 kHz 9
fS = 44.1 kHz 10 15
fS = 96 kHz 20
fS = 192 kHz 14
fS = 44.1 kHz 190 250
fS = 96 kHz
fS = 192 kHz 90
PCM3010DB
MIN TYP MAX
–43
105
105
102
–0.20
S
–50 dB
S
4.5 5.0 5.5
3.0 3.3 3.6
230
UNIT
dB
dB
dB
dB
dB
Hz
S
Hz
sec
VDC
mA
mA
mW
8
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digital filter
0
–50
–100
Amplitude – dB
–150
SLES055 – NOVEMBER 2002
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (ADC PORTION)
AMPLITUDE
vs
FREQUENCY
0
–10
–20
–30
–40
–50
–60
Amplitude – dB
–70
–80
–90
AMPLITUDE
vs
FREQUENCY
PCM3010
–200
0 8 16 24 32
Frequency [× fS]
Figure 2. Overall Characteristics
AMPLITUDE
vs
FREQUENCY
0.2
–0.0
0.0
–0.2
–0.4
Amplitude – dB
–0.6
–0.8
–1.0
0.0 0.1 0.2 0.3 0.4 0.5
Frequency [× fS]
–100
0.0 0.2 0.4 0.6 0.8 1.0
Frequency [× fS]
Figure 3. Stop-Band Attenuation Characteristics
AMPLITUDE
vs
FREQUENCY
0
–1
–2
–3
–4
–5
–6
Amplitude – dB
–7
–8
–9
–10
0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55
–4.13 dB @ 0.5 f
Frequency [× fS]
Figure 4. Pass-Band Ripple Characteristics Figure 5. Transient Band Characteristics
S
All specifications at TA = 25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 44.1 kHz, SCKI = 384 fS, 24-bit data, unless otherwise noted.
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9
PCM3010
SLES055 – NOVEMBER 2002
digital filter (continued)
AMPLITUDE
vs
FREQUENCY
0
–10
–20
–30
–40
–50
–60
Amplitude – dB
–70
–80
–90
–100
0.0 0.1 0.2 0.3 0.4 0.5
Frequency [× fS/1000]
Figure 6. Low-Cut HPF Stop-Band Characteristics
analog filter
AMPLITUDE
vs
FREQUENCY
0
AMPLITUDE
vs
FREQUENCY
0.2
–0.0
0.0
–0.2
–0.4
Amplitude – dB
–0.6
–0.8
–1.0
01234
Frequency [× fS/1000]
Figure 7. Low-Cut HPF Pass-Band Characteristics
AMPLITUDE
vs
FREQUENCY
0.0
–0.0
–10
–20
–30
Amplitude – dB
–40
–50
10 100 1k 10M10k 100k 1M
f – Frequency – Hz
Figure 8. Antialiasing Filter Stop-Band
Characteristics
All specifications at TA = 25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 44.1 kHz, SCKI = 384 fS, 24-bit data, unless otherwise noted.
10
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–0.2
–0.4
–0.6
Amplitude – dB
–0.8
–1.0
10 100 1k 10M10k 100k 1M
f – Frequency – Hz
Figure 9. Antialiasing Filter Pass-Band
Characteristics
digital filter
0
–20
–40
–60
–80
Amplitude – dB
–100
–120
SLES055 – NOVEMBER 2002
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (DAC PORTION)
AMPLITUDE
vs
FREQUENCY
Amplitude – dB
0.05
0.04
0.03
0.02
0.01
0.00
0.00
–0.01
–0.02
–0.03
–0.04
AMPLITUDE
vs
FREQUENCY
PCM3010
–140
01234
Frequency [× fS]
Figure 10. Frequency Response (Sharp Rolloff)
LEVEL
vs
FREQUENCY
0
–1
–2
–3
–4
–5
Level – dB
–6
–7
–8
–9
–0.05
0.0 0.1 0.2 0.3 0.4 0.5
Frequency [× fS]
Figure 11. Frequency Response, Pass-Band
(Sharp Rolloff)
ERROR
vs
FREQUENCY
0.5
0.4
0.3
0.2
0.1
–0.0
0.0
Error – dB
–0.1
–0.2
–0.3
–0.4
–10
0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0
f – Frequency – kHz
Figure 12. De-Emphasis (fS = 32 kHz)
All specifications at TA = 25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 44.1 kHz, SCKI = 384 fS, 24-bit data, unless otherwise noted.
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–0.5
0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0
f – Frequency – kHz
Figure 13. De-Emphasis Error (fS = 32 kHz)
11
PCM3010
SLES055 – NOVEMBER 2002
digital filter (continued)
LEVEL
vs
FREQUENCY
0
–1
–2
–3
–4
–5
Level – dB
–6
–7
–8
–9
–10
02468101214161820
f – Frequency – kHz
Figure 14. De-Emphasis (fS = 44.1 kHz)
LEVEL
vs
FREQUENCY
0
ERROR
vs
FREQUENCY
0.5
0.4
0.3
0.2
0.1
–0.0
0.0
Error – dB
–0.1
–0.2
–0.3
–0.4
–0.5
02468101214161820
f – Frequency – kHz
Figure 15. De-Emphasis Error (fS = 44.1 kHz)
ERROR
vs
FREQUENCY
0.5
–1
–2
–3
–4
–5
Level – dB
–6
–7
–8
–9
–10
0 2 4 6 8 10121416182022
f – Frequency – kHz
Figure 16. De-Emphasis (fS = 48 kHz)
All specifications at TA = 25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 44.1 kHz, SCKI = 384 fS, 24-bit data, unless otherwise noted.
0.4
0.3
0.2
0.1
–0.0
0.0
Error – dB
–0.1
–0.2
–0.3
–0.4
–0.5
0 2 4 6 8 10121416182022
f – Frequency – kHz
Figure 17. De-Emphasis Error (fS = 48 kHz)
12
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analog filter
AMPLITUDE
vs
FREQUENCY
0
–10
–20
–30
Amplitude – dB
–40
–50
10 100 1k 10M10k 100k 1M
f – Frequency – Hz
Figure 18. Analog Filter Stop-Band Performance
(10 Hz–10 MHz)
SLES055 – NOVEMBER 2002
PCM3010
AMPLITUDE
vs
FREQUENCY
–0.0
0.0
–0.2
–0.4
–0.6
Amplitude – dB
–0.8
–1.0
10 100 1k 10M10k 100k 1M
f – Frequency – Hz
Figure 19. Analog Filter Pass-Band Performance
(10 Hz–10 MHz)
TYPICAL PERFORMANCE CURVES (ADC PORTION)
TOTAL HARMONIC DISTORTION + NOISE
vs
FREE-AIR TEMPERATURE
–90
–95
–60 dB
–100
–105
–50 –25 0 25 50 75 100
THD+N – Total Harmonic Distortion + Noise at –0.5 dB – dB
TA – Free-Air Temperature – °C
Figure 20
–0.5 dB
–30
–35
–40
–45
THD+N – Total Harmonic Distortion + Noise at –60 dB – dB
DYNAMIC RANGE and SNR
vs
FREE-AIR TEMPERATURE
110
105
Dynamic Range
100
SNR
Dynamic Range and SNR – dB
95
–50 –25 0 25 50 75 100
TA – Free-Air Temperature – °C
Figure 21
All specifications at TA = 25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 44.1 kHz, SCKI = 384 fS, 24-bit data, unless otherwise noted.
www.ti.com
13
PCM3010
SLES055 – NOVEMBER 2002
TOTAL HARMONIC DISTORTION + NOISE
vs
SUPPLY VOLTAGE
–90
–95
–100
–105
4.25 4.50 4.75 5.00 5.25 5.50 5.75
THD+N – Total Harmonic Distortion + Noise at –0.5 dB – dB
VCC – Supply Voltage – V
–0.5 dB
–60 dB
Figure 22
–30
–35
–40
–45
THD+N – Total Harmonic Distortion + Noise at –60 dB – dB
DYNAMIC RANGE and SNR
vs
SUPPLY VOLTAGE
110
105
Dynamic Range
100
SNR
Dynamic Range and SNR – dB
95
4.25 4.50 4.75 5.00 5.25 5.50 5.75
VCC – Supply Voltage – V
Figure 23
TOTAL HARMONIC DISTORTION + NOISE
vs
SAMPLING FREQUENCY
–90
–0.5 dB
–95
–60 dB
–100
–105
16 32 48 64 80 96 112
THD+N – Total Harmonic Distortion + Noise at –0.5 dB – dB
fS – Sampling Frequency – kHz
Figure 24
–30
–35
–40
–45
THD+N – Total Harmonic Distortion + Noise at –60 dB – dB
DYNAMIC RANGE and SNR
vs
SAMPLING FREQUENCY
110
105
Dynamic Range
100
SNR
Dynamic Range and SNR – dB
95
16 32 48 64 80 96 112
fS – Sampling Frequency – kHz
Figure 25
All specifications at TA = 25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 44.1 kHz, SCKI = 384 fS, 24-bit data, unless otherwise noted.
14
www.ti.com
TYPICAL PERFORMANCE CURVES (DAC PORTION)
TOTAL HARMONIC DISTORTION + NOISE
vs
FREE-AIR TEMPERATURE
–90
–95
–100
–60 dB
–105
–50 –25 0 25 50 75 100
THD+N – Total Harmonic Distortion + Noise at 0 dB – dB
TA – Free-Air Temperature – °C
Figure 26 Figure 27
0 dB
–30
–35
–40
–45
THD+N – Total Harmonic Distortion + Noise at –60 dB – dB
SLES055 – NOVEMBER 2002
PCM3010
DYNAMIC RANGE and SNR
vs
FREE-AIR TEMPERATURE
110
105
100
Dynamic Range and SNR – dB
95
–50 –25 0 25 50 75 100
TA – Free-Air Temperature – °C
SNR
Dynamic Range
TOTAL HARMONIC DISTORTION + NOISE
vs
SUPPLY VOLTAGE
–90
–95
0 dB
–100
–60 dB
–105
4.25 4.50 4.75 5.00 5.25 5.50 5.75
THD+N – Total Harmonic Distortion + Noise at 0 dB – dB
VCC – Supply Voltage – V
Figure 28 Figure 29
–30
–35
–40
–45
THD+N – Total Harmonic Distortion + Noise at –60 dB – dB
DYNAMIC RANGE and SNR
vs
SUPPLY VOLTAGE
110
SNR
105
Dynamic Range
100
Dynamic Range and SNR – dB
95
4.25 4.50 4.75 5.00 5.25 5.50 5.75
VCC – Supply Voltage – V
All specifications at TA = 25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 44.1 kHz, SCKI = 384 fS, 24-bit data, unless otherwise noted.
www.ti.com
15
PCM3010
SLES055 – NOVEMBER 2002
TOTAL HARMONIC DISTORTION + NOISE
vs
SAMPLING FREQUENCY
–90
–30
–95
0 dB
–100
–60 dB
–105
16 32 48 64 80 96 112
THD+N – Total Harmonic Distortion + Noise at 0 dB – dB
fS – Sampling Frequency – kHz
Figure 30
DYNAMIC RANGE and SNR
vs
SAMPLING FREQUENCY
110
105
SNR
–35
–40
–45
THD+N – Total Harmonic Distortion + Noise at –60 dB – dB
Dynamic Range
100
Dynamic Range and SNR – dB
95
16 32 48 64 80 96 112
fS – Sampling Frequency – kHz
Figure 31
All specifications at TA = 25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 44.1 kHz, SCKI = 384 fS, 24-bit data, unless otherwise noted.
16
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ADC output spectrum
0
–20
–40
–60
–80
Amplitude – dB
–100
–120
AMPLITUDE
vs
FREQUENCY
SLES055 – NOVEMBER 2002
PCM3010
TYPICAL PERFORMANCE CURVES
AMPLITUDE
vs
FREQUENCY
0
–20
–40
–60
–80
Amplitude – dB
–100
–120
–140
0 5 10 15 20
f – Frequency – kHz
Figure 32. Output Spectrum (–0.5 dB, N = 8192)
DAC output spectrum
AMPLITUDE
vs
FREQUENCY
0
–20
–40
–60
–80
Amplitude – dB
–100
–120
–140
0 5 10 15 20
f – Frequency – kHz
Figure 33. Output Spectrum (–60 dB, N = 8192)
AMPLITUDE
vs
FREQUENCY
0
–20
–40
–60
–80
Amplitude – dB
–100
–120
–140
0 5 10 15 20
f – Frequency – kHz
Figure 34. Output Spectrum (0 dB, N = 8192)
All specifications at TA = 25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 44.1 kHz, SCKI = 384 fS, 24-bit data, unless otherwise noted.
www.ti.com
–140
0 5 10 15 20
f – Frequency – kHz
Figure 35. Output Spectrum (–60 dB, N = 8192)
17
PCM3010
SLES055 – NOVEMBER 2002
supply current
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
35
ICC1 + ICC2
30
25
20
15
– Supply Current – mA
10
CC
I
5
0
–50 –25 0 25 50 75 100
TA – Free-Air Temperature – °C
I
DD
Figure 36
SUPPLY CURRENT
vs
SAMPLING FREQUENCY
35
ICC1 + ICC2
30
25
20
15
– Supply Current – mA
10
CC
I
5
0
16 32 48 64 80 96 112
fS – Sampling Frequency – kHz
I
DD
Figure 37. Supply Current vs Sampling Frequency,
ADC and DAC Operating
SUPPLY CURRENT
vs
V
1, VCC2 SUPPLY VOLTAGE
CC
35
ICC1 + ICC2
30
25
20
15
– Supply Current – mA
10
CC
I
5
0
4.25 4.50 4.75 5.00 5.25 5.50 5.75
VCC1, VCC2 – Supply Voltage – V
35
30
25
20
15
– Supply Current – mA
10
CC
I
5
0
2.7 3.0 3.3 3.6 3.9
Figure 38
All specifications at TA = 25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 44.1 kHz, SCKI = 384 fS, 24-bit data, unless otherwise noted.
SUPPLY CURRENT
vs
V
SUPPLY VOLTAGE
DD
I
DD
VDD – Supply Voltage – V
Figure 39
18
www.ti.com
SLES055 – NOVEMBER 2002
THEORY OF OPERATION
ADC portion
The ADC block consists of a reference circuit, two single-ended to differential converter channels, a fifth-order
delta-sigma modulator with full-differential architecture, a decimation filter with low-cut filter, and a serial
interface circuit which is also used as a serial interface for the DAC input signal as shown in the block diagram,
Figure 1.
The analog front-end diagram illustrates the architecture of the single-ended to differential converter and
antialiasing filter. Figure 40 illustrates the block diagram of the fifth-order delta-sigma modulator and transfer
function.
An on-chip reference circuit with two external capacitors provides all the reference voltages which are needed
in the ADC portion, and defines the full-scale voltage range of both channels.
An on-chip single-ended to differential signal converter saves the design, space, and extra parts cost of an
external signal converter.
Full-differential architecture provides a wide dynamic range and excellent power supply rejection performance.
The input signal is sampled at a ×64 oversampling rate, and an on-chip antialiasing filter eliminates the external
sample-hold amplifier. A fifth-order delta-sigma noise shaper , which consists of five integrators using a switched
capacitor technique followed by a comparator, shapes the quantization noise generated by the comparator and
1-bit DAC outside the audio signal band.
PCM3010
The high order delta-sigma modulation randomizes the modulator outputs and reduces the idle tone level.
The 64-fS, 1-bit stream from the delta-sigma modulator is converted to a 1-fS, 24-bit or 16-bit digital signal by
removing the high-frequency noise components with a decimation filter.
The dc component of the signal is removed by the HPF , and the HPF output is converted to a time-multiplexed
serial signal through the serial interface, which provides flexible serial formats.
Analog
In
X(z)
st
+
–
1
SW-CAP
Integrator
1-Bit
DAC
–
+
nd
2
SW-CAP
Integrator
+
Y(z) = STF(z) * X(z) + NTF(z) * Qn(z)
Signal Transfer Function
Noise Transfer Function
+
rd
3
SW-CAP
Integrator
H(z)
+
–
+
+
STF(z) = H(z) / [1 + H(z)]
NTF(z) = 1 / [1 + H(z)]
th
4
SW-CAP
Integrator
th
5
SW-CAP
Integrator
+
+
+
Qn(z)
+
Comparator
Digital
Out
Y(z)
Figure 40. Block Diagram of Fifth-Order Delta-Sigma Modulator
www.ti.com
19
PCM3010
SLES055 – NOVEMBER 2002
DAC portion
The DAC portion is based on the delta-sigma modulator, which consists of an 8-level amplitude quantizer and
a 4th-order noise shaper. This section converts the oversampled input data to the 8-level delta-sigma format.
A block diagram of the 8-level delta-sigma modulator is shown in Figure 41. This 8-level delta-sigma modulator
has the advantage of improved stability and clock jitter over the typical one-bit (2-level) delta-sigma modulator.
The combined oversampling rate of the delta-sigma modulator and the internal 8× interpolation filter is 64 f
all system clocks. The theoretical quantization noise performance of the 8-level delta-sigma modulator is shown
in Figure 42.
for
S
8 f
OUT
64 f
IN
S
S
+
+
–1
Z
–
+
+
8-Level Quantizer
–1
Z
+
+
+
++
–1
Z
–
+
+
+
–1
Z
Figure 41. 8-Level Delta-Sigma Modulator Block Diagram
20
www.ti.com
AMPLITUDE
vs
FREQUENCY
0
–20
–40
–60
–80
–100
Amplitude – dB
–120
–140
–160
–180
012345678
Frequency [ fS]
Dynamic Range – dB
SLES055 – NOVEMBER 2002
PCM3010
DYNAMIC RANGE
vs
JITTER
125
120
115
110
105
100
95
90
0 100 200 300 400 500 600
Jitter – ps
Figure 42. Quantization Noise Spectrum
( 64 Oversampling)
Figure 43. Jitter Dependence
( 64 Oversampling)
system clock
The system clock for the PCM3010 must be 128 fS, 192 fS, 256 fS, 384 fS, 512 fS or 768 fS, where fS is the audio
sampling rate, 16 kHz to 192 kHz. The PCM3010 detects 128 f
automatically with the built-in circuit. Operation at the 192-kHz sampling rate is available on the DAC only , and
when a system clock of 128 f
or 192 fS is detected, the ADC is disabled (DOUT = LOW). T able 1 lists the typical
S
system clock frequency, and Figure 44 illustrates the system clock timing.
Table 1. Typical System Clock
SAMPLING RATE
FREQUENCY (fS) – LRCK
32 kHz – – 8.192 12.288 16.384 24.576
44.1 kHz – – 11.2896 16.9344 22.5792 33.8688
48 kHz – – 12.288 18.432 24.576 36.864
96 kHz – – 24.576 36.864 49.152 –
192 kHz 24.576
†
DAC only.
128 f
S
†
192 f
36.864
SYSTEM CLOCK FREQUENCY – MHz
S
†
256 f
, 192 fS, 256 fS, 384 fS, 512 fS or 768 f
S
S
– – – –
384 f
S
512 f
S
768 f
S
S
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21
PCM3010
SLES055 – NOVEMBER 2002
system clock (continued)
System Clock
t
SCKL
t
SCKH
1/128 fS or 1/192 f
1/256 fS or 1/384 f
1/512 fS or 1/768 f
2.0 V
0.8 V
S
S
S
t
SCKH
t
SCKL
PARAMETER
System clock pulse duration HIGH 8 ns
System clock pulse duration LOW 8 ns
MIN MAX UNIT
Figure 44. System Clock Timing
power supply on, external reset, and power down
The PCM3010 has both an internal power-on reset circuit and an external reset circuit. The sequences for both
resets are explained as follows.
Figure 45 is the timing diagram for the internal power-on reset. Two power-on reset circuits are implemented
for V
2.2 V, typically.
Internal reset is released 1024 SCKI clock cycles following the release from power-on reset, and the PCM3010
begins normal operation. V
rises. When synchronization between SCKI, BCK and LRCK is obtained while V
fade sequence and provide outputs corresponding to DIN after t
power-on reset. On the other hand, DOUT from the ADC provides an output corresponding to V
after t
reset is not released and device operation remains in the power-down mode. After resynchronization, the DAC
performs the fade-in sequence and the ADC resumes normal operation following internal initialization.
Figure 46 is the external-reset timing diagram. External forced reset, driving the PDWN
PCM3010 in the power-down mode, which is its lowest power-dissipation state.
When PDWN
LRCK, then V
At the same time as the internal reset becomes LOW, DOUT becomes ZERO, the PCM3010 enters into
power-down mode. To enter into normal operation mode again, change PDWN
sequence shown in Figure 45 occurs.
Notes:
1. A large popping noise may be generated on V
2. To switch PDWN
3. To switch the control pins on the fly during normal operation can degrade analog performance. It is
1 and VDD, respectively . Initialization (reset) occurs automatically when VCC1 and VDD exceed 4.0 V and
CC
ADCDLY1
L and V
OUT
= 4500/fS following release from power-on reset. If the synchronization is not held, the internal
R from the DAC are forced to the V
OUT
DACDLY1
(= 0.5 VCC2) level as VCC2
COM
= 2100/fS following release from
OUT
L and V
OUT
IN
pin LOW, puts the
transitions from HIGH to LOW while synchronization is maintained between SCKI, BCK, and
OUT
L and V
R are faded out and forced to the V
OUT
(= 0.5 VCC2) level after t
COM
DACDLY1
to HIGH again. The reset
OUT
L and V
R when the power supply is turned off during
OUT
normal operation.
during fade in or fade out causes an immediate change between fade in and fade out.
recommended that changing control pins, changing clocks, stopping clocks, turning power supplies off, etc.,
be done in the power-down mode.
R go into the
L and VINR
= 2100/fS.
22
www.ti.com
)
power supply on, external reset and power down (continued)
VCC1, V
LRCK, BCK, SCKI
Internal Reset
V
OUT
L, V
DD
PDWN
OUT
0 V
R
(VCC1 = 4 V, VDD = 2.2 V, Typ)
Synchronous Clocks
1024 SCKI
Power Down
t
DACDLY1
V
COM
2100/f
(0.5 VCC2)
t
ADCDLY1
S
4500/f
Normal Operation
S
SLES055 – NOVEMBER 2002
PCM3010
(VCC1 = 5 V,
VDD = 3.3 V, Typ)
DOUT
VCC1, V
LRCK, BCK, SCKI
Internal Reset
V
OUT
L, V
DD
PDWN
OUT
Zero
Figure 45. DAC Output and ADC Output for Power-On Reset
(VCC1 = 5 V,
0 V
Synchronous Clocks
Normal Operation
t
DACDLY1
2100/f
S
R
Power Down
V
(0.5 VCC2)
COM
Synchronous Clocks
1024 SCKI
Normal Operation
t
ADCDLY1
4500/f
S
t
DACDLY1
2100/f
VDD = 3.3 V, Typ
S
DOUT
Zero
Figure 46. DAC Output and ADC Output for External Reset (PDWN Pin)
www.ti.com
23
PCM3010
SLES055 – NOVEMBER 2002
PCM audio interface
Digital audio data is interfaced to the PCM3010 on LRCK (pin 10), BCK (pin 11), DIN (pin 12), and DOUT
(pin 13). The PCM3010 can accept the following 16-bit and 24-bit formats. These formats are selected through
FMT0 (pin 7) and FMT1 (pin 8), as shown in Table 2.
Table 2. Audio Data Format Select
FMT1 FMT0 DAC DATA FORMAT ADC DATA FORMAT
LOW LOW 24-bit, MSB-first, right-justified 24-bit, MSB-first, left-justified
LOW HIGH 16-bit, MSB-first, right-justified 24-bit, MSB-first, left-justified
HIGH LOW 24-bit, MSB-first, left-justified 24-bit, MSB-first, left-justified
HIGH HIGH 24-bit, MSB-first, I2S 24-bit, MSB-first, I2S
The PCM3010 accepts two combinations of BCK and LRCK, 64 or 48 clocks of BCK in one clock of LRCK. The
following figures illustrate audio data input/output format and timing.
FORMAT 0: FMT[1:0] = 00
DAC: 24-Bit, MSB-First, Right-Justified
LRCK
Right ChannelLeft Channel
BCK
DIN
24
ADC: 24-Bit, MSB-First, Left-Justified
LRCK
BCK
DOUT
MSB
FORMAT 1: FMT[1:0] = 01
DAC: 16-Bit, MSB-First, Right-Justified
LRCK
BCK
DIN
16 14 15 16321
ADC: 24-Bit, MSB-First, Left-Justified
LRCK
BCK
MSB
MSB
LSB
22 23 24321
LSB
MSB
LSB
MSB
Right ChannelLeft Channel
22 23 24321
Right ChannelLeft Channel
MSB
Right ChannelLeft Channel
22 23 24321
LSB
122 23 24321
LSB
14 15 16321
LSB
24
DOUT
MSB
LSB
MSB
Figure 47. Audio Data Input/Output Format
www.ti.com
22 23 24321
LSB
122 23 24321
PCM audio interface (continued)
FORMAT 2: FMT[1:0] = 10
DAC: 24-Bit, MSB-First, Left-Justified
LRCK
BCK
DIN
MSB LSB
ADC: 24-Bit, MSB-First, Left-Justified
LRCK
BCK
DOUT
MSB
FORMAT 3: FMT[1:0] = 11
DAC: 24-Bit, MSB-First, I2S
LRCK
LSB
SLES055 – NOVEMBER 2002
Right ChannelLeft Channel
22 23 24321
MSB LSB
Right ChannelLeft Channel
22 23 24321
MSB
Right ChannelLeft Channel
LSB
PCM3010
122 23 24321
122 23 24321
BCK
DIN
MSB LSB
ADC: 24-Bit, MSB-First, I2S
LRCK
BCK
DOUT
MSB LSB
22 23 24321
MSB LSB
Right ChannelLeft Channel
22 23 24321
MSB LSB
Figure 48. Audio Data Input/Output Format (Continued)
22 23 24321
22 23 24321
www.ti.com
25
PCM3010
SLES055 – NOVEMBER 2002
PCM audio interface (continued)
t
LRP
t
BCY
t
BCH
t
BCL
t
BL
t
LB
t
LRP
t
DIS
t
DIH
t
CKDO
t
LRDO
t
R
t
F
LRCK
t
BCL
t
BCH
BCK
t
BCY
DIN
DOUT
PARAMETER
BCK pulse cycle time 80 ns
BCK pulse duration, HIGH 35 ns
BCK pulse duration, LOW 35 ns
BCK rising edge to LRCK edge 10 ns
LRCK edge to BCK rising edge 10 ns
LRCK pulse duration 2.1 µs
DIN setup time 10 ns
DIN hold time 10 ns
DOUT delay time from BCK falling edge 20 ns
DOUT delay time from LRCK edge 20 ns
Rising time of all signals 10 ns
Falling time of all signals 10 ns
t
BL
t
LB
t
DIS
t
CKDO
t
DIH
t
LRDO
MIN MAX UNIT
1.4 V
1.4 V
1.4 V
0.5 V
DD
Figure 49. Audio Data Input/Output Timing
synchronization with digital audio system
The PCM3010 operates with LRCK and BCK synchronized to the system clock. The PCM3010 does not need
a specific phase relationship between LRCK, BCK and the system clock, but does require the synchronization
of LRCK, BCK, and the system clock.
If the relationship between system clock and LRCK changes more than ±6 BCKs during one sample period due
to LRCK jitter, etc., internal operation of DAC halts within 6/f
resynchronization between the system clock, LRCK, and BCK is completed and then t
Internal operation of the ADC also halts within 6/f
, and the digital output is forced to a ZERO code until
S
resynchronization between the system clock, LRCK, and BCK is completed, and then t
In the case of changes less than ±5 BCKs, resynchronization does not occur and the previously described
discontinuity in analog/digital output control does not occur.
26
www.ti.com
, and the analog output is forced to 0.5 VCC2 until
S
DACDLY2
ADCDLY2
elapses.
elapses.
SLES055 – NOVEMBER 2002
synchronization with digital audio system (continued)
Figure 50 illustrates the DAC analog output and ADC digital output for loss of synchronization.
During undefined data, some noise may be generated in the audio signal. Also, the transition from normal to
undefined data and from undefined or zero data to normal creates a data discontinuity on the analog and digital
outputs, which may generate some noise in the audio signal.
State of Synchronization
DAC V
OUT
ADC DOUT
Figure 50. DAC Output and ADC Output for Lost of Synchronization
Within 6/f
NORMAL DATA
NORMAL DATA
S
V
(0.5 VCC2)
UNDEFINED
DATA
UNDEFINED
DATA
COM
ZERO DATA
t
DACDLY2
32/f
t
ADCDLY2
32/f
SYNCHRONOUSASYNCHRONOUSSYNCHRONOUS
S
NORMAL DATA
S
NORMAL DATA
PCM3010
de-emphasis control
DEMP1, DEMP0: De-emphasis control pins select the de-emphasis mode of the DACs as shown below.
DEMP1 DEMP0 DESCRIPTION
LOW LOW De-emphasis 44.1 kHz ON
LOW HIGH De-emphasis OFF
HIGH LOW De-emphasis 48 kHz ON
HIGH HIGH De-emphasis 32 kHz ON
test control
TEST: The TEST pin is used for device testing; it must be connected to DGND for normal operation.
www.ti.com
27
PCM3010
SLES055 – NOVEMBER 2002
typical circuit connection
The following figure illustrates typical circuit connection.
5 V
3.3 V
0 V
L-Ch IN
R-Ch IN
Control
Clock
Data
NOTES: A. 0.1 µF ceramic and 10 µF electrolytic capacitors typical, depending on power supply quality and pattern layout.
(See Note C)
(See Note C)
(See Note B)
(See Note B)
(See Note A)
Format 0
Format 1
L/R Clock
Bit Clock
Data IN
B. 0.1 µF ceramic and 10 µF electrolytic capacitors are recommended.
C. 1 µF electrolytic capacitor typical, gives 8-Hz cutoff frequency of input HPF in normal operation and gives settling time with
20 ms (1 µF × 20 kΩ) time constant in power ON and power down OFF period.
D. 10 µF electrolytic capacitor typical, gives 2-Hz cutoff frequency for 10-kΩ post-LPF input resistance in normal operation and
gives settling time with 100 ms (10 µF × 10 kΩ) time constant in power ON and power down OFF period.
+
+
+
+
+
10
11
12
1
2
3
4
5
6
7
8
9
VINL
VINR
V
REF
V
REF
VCC1
AGND1
FMT0
FMT1
TEST
LRCK
BCK
DIN
V
V
OUT
1
2
V
OUT
VCC2
AGND2
DEMP0
DEMP1
PDWN
DGND
DOUT
COM
SCKI
V
DD
24
L
23
R
22
21
20
19
18
17
16
15
14
13
(See Note B)
+
(See Note D)
+
(See Note D)
+
(See Note A)
+
+
(See Note A)
Post LPF
Post LPF
De-emphasis 0
De-emphasis 1
Power Down
System Clock
Data OUT
Control
Clock
Data
design and layout considerations in application
power supply pins (VCC1, VCC2, VDD)
The digital and analog power supply lines to the PCM3010 should be bypassed to the corresponding ground
pins, with 0.1-µF ceramic and 10-µF electrolytic capacitors as close to the pins as possible to maximize the
dynamic performance of the ADC and the DAC.
Although the PCM3010 has three power lines to maximize the potential of dynamic performance, using one
common 5-V power supply for V
and V
2 power supply , for VDD. This power supply arrangement is recommended to avoid unexpected power
CC
supply trouble, like latch-up or power supply sequencing problems.
grounding (AGND1, AGND2, DGND)
To maximize the dynamic performance of the PCM3010, the analog and digital grounds are not connected
internally. These points should have very low impedance to avoid digital noise feeding back into the analog
ground. They should be connected directly to each other under the connected parts to reduce the potential for
noise problems.
28
1 and VCC2 and a 3.3-V power supply , which is generated from the 5-V VCC1
CC
www.ti.com
SLES055 – NOVEMBER 2002
VIN pins
A 1-µF electrolytic capacitor is recommended as an ac-coupling capacitor, which gives an 8-Hz cutof f frequency.
If a higher full-scale input voltage is required, it can be adjusted by adding only one series resistor to each V
pin.
1, V
V
REF
A 0.1-µF ceramic capacitor and a 10-µF electrolytic capacitor are recommended between V
REF
2 pins
REF
1, V
AGND1 to ensure low source impedance of the ADC references. These capacitors should be located as close
as possible to the V
pin
V
COM
A 0.1-µF ceramic capacitor and a 10-µF electrolytic capacitor are recommended between V
REF
1 and V
2 pins and the AGND1 pin to reduce dynamic errors on the ADC references.
REF
and AGND2
COM
to ensure low source impedance of the DAC common voltage. These capacitors should be located as close as
possible to the V
pin to reduce dynamic errors on the DAC common voltage.
COM
system clock
The quality of SCKI may influence dynamic performance, as the PCM3010 (both DAC and ADC) operates
based on SCKI. Therefore, it may be necessary to consider the jitter, duty cycle, rise and fall time, etc., of the
system clock.
reset control
If large capacitors (more than 22 µF) are used on V
PDWN
= LOW is required after the V
REF
1, V
REF
2, and V
REF
1, V
COM
REF
2, and V
, external reset control by
COM
transient response settles.
external mute control
PCM3010
IN
2, and
REF
T o eliminate the clicking noise which is generated by DAC output dc level change during power-down ON/OFF
control, external mute control is generally required. The recommended control sequence is: external mute ON,
codec power down ON, SCKI stop and restart if necessary, codec power down OFF, and external mute OFF.
www.ti.com
29
PCM3010
SLES055 – NOVEMBER 2002
MECHANICAL DATA
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,65
28
1
2,00 MAX
0,38
0,22
15
14
A
0,05 MIN
0,15
5,60
5,00
M
8,20
7,40
Seating Plane
0,10
0,25
0,09
0°–ā8°
Gage Plane
0,25
0,95
0,55
PINS **
DIM
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
14
6,50
6,50
5,905,90
2016
7,50
6,90
24
8,50
28
10,50
9,907,90
30
10,50
9,90
38
12,90
12,30
4040065 /E 12/01
30
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
PCM3010DB ACTIVE SSOP DB 24 58 Green (RoHS &
no Sb/Br)
PCM3010DBG4 ACTIVE SSOP DB 24 58 Green (RoHS &
no Sb/Br)
PCM3010DBR ACTIVE SSOP DB 24 2000 Green (RoHS &
no Sb/Br)
PCM3010DBRG4 ACTIVE SSOP DB 24 2000 Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and alifetime-buyperiod is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples mayormay not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specifiedlead-freeprocesses.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneousmaterial)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
(3)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,65
28
1
2,00 MAX
0,38
0,22
15
14
A
0,05 MIN
0,15
5,60
5,00
M
8,20
7,40
Seating Plane
0,10
0,25
0,09
0°–ā8°
Gage Plane
0,25
0,95
0,55
PINS **
DIM
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
14
6,50
6,50
5,905,90
2016
7,50
6,90
24
8,50
28
10,50
9,907,90
30
10,50
9,90
38
12,90
12,30
4040065 /E 12/01
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