Texas Instruments PCI4450GFN, PCI4450GJG Datasheet

PCI4450 GFN/GJG

PC Card and OHCI Controller

SCPS046 – JANUAR Y 1999

D 1997 PC Standard Compliant D PCI Bus Power Management Interface

Specification 1.1 Compliant

D ACPI 1.0 Compliant D PCI Local Bus Specification Revision

2.1/2.2 Compliant

D PC 98/99 Compliant D Compliant with the PCI Bus Interface

Specification for PCI-to-CardBus Bridges

D Fully Compliant with the PCI Bus Power

Management Specification for PCI to CardBus Bridges Specification

D Ultra Zoomed Video D Zoomed Video Auto-Detect D Advanced filtering on Card Detect Lines

Provide 90 Microseconds of Noise Immunity.

D Programmable D3 Status Pin D Internal Ring Oscillator D 3.3-V Core Logic with Universal PCI

Interfaces Compatible with 3.3-V and 5-V PCI Signaling Environments

D Mix-and-Match 5-V/3.3-V PC Card16 Cards

and 3.3-V CardBus Cards

D Supports Two PC Card or CardBus Slots

With Hot Insertion and Removal

D Uses Serial Interface to TI TPS2206 Dual

Power Switch

D Supports 132 Mbyte/sec. Burst Transfers

to Maximize Data Throughput on Both the PCI Bus and the CardBus Bus

D Supports Serialized IRQ with PCI

Interrupts

D 8 Programmable Multifunction Pins D Interrupt Modes Supported: Serial

ISA/Serial PCI, Serial ISA/Parallel PCI, Parallel PCI Only.

D Serial EEPROM Interface for Loading

Subsystem ID and Subsystem Vendor ID

D Supports Zoomed Video with Internal

Buffering

D Dedicated Pin for PCI CLKRUN D Four General-Purpose Event Registers D Multifunction PCI Device with Separate

Configuration Space for each Socket

D Five PCI Memory Windows and Two I/O

Windows Available to each PC Card16 Socket

D Two I/O Windows and Two Memory

Windows Available to each CardBus Socket

D ExCA-Compatible Registers are Mapped

in Memory or I/O Space

D Supports Distributed DMA and PC/PCI

DMA

D Intel 82365SL-DF Register Compatible D Supports 16-bit DMA on Both PC Card

Sockets

D Supports Ring Indicate, SUSPEND, and

PCI CLKRUN

D Advanced Submicron, Low-Power CMOS

Technology

D Provides VGA / Palette Memory and I/O,

and Subtractive Decoding Options

D LED Activity Pins D Supports PCI Bus Lock (LOCK) D Packaged in a 256-pin BGA or 257-pin

Micro-Star BGA

D OHCI Link Function Designed to IEEE 1394

Open Host Controller Interface (OHCI) Specification

D Implements PCI Burst Transfers and Deep

FIFOs to Tolerate Large Host Latency

D Supports Physical Write Posting of up to 3

Outstanding Transactions

D OHCI Link Function is IEEE 1394-1995

Compliant and Compatible with Proposal 1394a

D Supports Serial Bus Data Rates of 100,

200, and 400 Mbits/second

D Provides Bus-Hold Buffers on the

PHY-Link I/F for Low-cost Single Capacitor Isolation

Please be aware that an important notic e concerning availability, standard warranty, and use in critical applications of T exasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Intel is a trademark of Intel Corporation. PC Card is a trademark of Personal Computer Memory Card International Association (PCMCIA). TI is a trademark of T exas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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PCI4450 GFN/GJG PC Card and OHCI Controller

SCPS046 – JANUAR Y 1999

Description 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

T erminal Assignments 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signal Names and T erminal Assignments 5. . . . . . . . . . . . . . . . . . .

PCI4450 System Block Diagram 9. . . . . . . . . . . . . . . . . . . . . . . . . . .

T erminal Functions 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O Characteristics 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clamping Voltages 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCI Interface 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PC Card Applications Overview 28. . . . . . . . . . . . . . . . . . . . . . . . .

Programmable Interrupt Subsystem 35. . . . . . . . . . . . . . . . . . . . . .

Power Management Overview 38. . . . . . . . . . . . . . . . . . . . . . . . . .

PC Card Controller Programming Model 43. . . . . . . . . . . . . . . . . .

PCI Configuration Registers (Functions 0 and 1) 44. . . . . . . . . . .

ExCA Compatibility Registers (Functions 0 and 1) 82. . . . . . . . . .

CardBus Socket Registers (Functions 0 and 1) 106. . . . . . . . . . .

Distributed DMA (DDMA) Registers 114. . . . . . . . . . . . . . . . . . . . . .

Table of Contents

GPIO Interface 182. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial EEPROM 183. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Absolute Maximum Ratings 185. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Recommended Operating Conditions 186. . . . . . . . . . . . . . . . . . . . . . .

Electrical Characteristics 187. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCI Clock/Reset Timing Requirements 188. . . . . . . . . . . . . . . . . . . . .

PCI Timing Requirements 188. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Switrching Characteristics for PHY -Link Interface 188. . . . . . . . . . . . .

Parameter Measurement Information 189. . . . . . . . . . . . . . . . . . . . . . .

PCI Bus Parameter Measurement Information 190. . . . . . . . . . . . . . .

PC Card Cycle Timing 191. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timing Requirements, (Memory Cycles) 192. . . . . . . . . . . . . . . . . . . .

Timing Requirements, (I/O Cycles) 197. . . . . . . . . . . . . . . . . . . . . . . . .

Switching Characteristics (Miscellaneous) 193. . . . . . . . . . . . . . . . . .

PC Card Parameter Mesasurement Information 193. . . . . . . . . . . . . .

Mechanical Data 195. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI4450 GFN/GJG

PC Card and OHCI Controller

SCPS046 – JANUAR Y 1999

description

The T exas Instruments PCI4450 is an integrated dual-socket PC Card controller and IEEE 1394 Open HCI host controller. This high-performance integrated solution provides the latest in both PC Card and IEEE 1394 technology.

The PCI4450 is a three-function PCI device compliant with 1 provide the independent PC Card socket controllers compliant with the 1997 PC Card Standard. The PCI4450 provides features that make it the best choice for bridging between the PCI bus and PC Cards, and supports any combination of 16-bit and CardBus PC Cards in the two sockets, powered at 5 V or 3.3 V, as required.

All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI4450 is register compatible with the Intel 82365SL–DF ExCA controller. The PCI4450 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI4450 can be programmed to accept posted writes to improve bus utilization.

Function 2 of the PCI4450 is compatible with IEEE1394A and the latest 1394 open host controller interface (OHCI) specifications. The chip provides the IEEE1394 link function and is compatible with data rates of 100, 200, and 400 Mbits per second. Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies. The PCI4450 provides physical write posting and a highly tuned physical data path for SBP-2 performance. Multiple cache line burst transfers, advanced internal arbitration, and bus holding buffers on the PHY/Link interface are other features that make the PCI4450 the best-in-class 1394 Open HCI solution.

The PCI4450 provides an internally buffered zoomed video (ZV) path. This reduces the design effort of PC board manufacturers to add a ZV-compatible solution and guarantees compliance with the CardBus loading specifications.

V arious implementation specific functions and general-purpose inputs and outputs are provided through eight multifunction terminals. These terminals present a system with options in PC/PCI DMA, PCI LOCK and parallel interrupts, PC Card activity indicator LEDs, and other platform specific signals. ACPI-complaint general-purpose events may be programmed and controlled through the multifunction terminals, and an ACPI-compliant programming interface is included for the general-purpose inputs and outputs.

PCI Local Bus Specification 2.2

. Functions 0 and

The PCI4450 is compliant with the latest low-power modes which enable the host power system to further reduce power consumption. The

(CardBus) Controller

OnNowt Power Management are supported. Furthermore, an advanced complementary metal-oxide semiconductor (CMOS) process achieves low system power consumption.

Unused PCI4450 inputs must be pulled to a valid logic level using a 43 kΩ resistor.

use of symbols in this document

Throughout this data sheet the overbar symbol denotes an active-low signal. For example: FRAME denotes that this is an active-low signal.

and

IEEE 1394 Host Controller Device Class Specifications

PCI Bus Power Management Specification

, and provides several

required for Microsoft

PC Card

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI4450 GFN/GJG PC Card and OHCI Controller

SCPS046 – JANUAR Y 1999

terminal assignments

2019181716151413121110987654321

B B B B B B B B B B B A A A A A A A

B B B B B B B B B B B A A A A A A A A

A B C

B B

B B B A A A

B B A A A

B B B A A

B B

B B B A A A

P P P A A A

P P A A A A

P P P A A A

P P

P P P Z Z A

P P Z Z A

P P P Z Z Z Z

P P

P P P P P P P T S S S S Z Z Z Z

P P P P P P T S S S S S Z Z Z Z

P P P P P P S S S S Z Z Z

B B

P P

B B B

Bottom View

T S

A A

A A A

Z Z Z

E F G H

L M N P R T U V W Y

P A B Z S 1394 PHY/Link

PCI Interface PC Card A PC Card B Zoom Video

VCC 3.3 Volt

Ground (GND)

TPS Power Switch

Miscellaneous

Figure 1. PCI4450 Pin Diagram

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI4450 GFN/GJG

PC Card and OHCI Controller

SCPS046 – JANUAR Y 1999

signal names and terminal assignments

Signal names and their terminal assignments are shown in Tables 1 and 2 and are sorted alphanumerically by the assigned terminal.

Table 1. GFN Terminals Sorted Alphanumerically for CardBus // 16-bit Signals and OHCI

GFN SIGNAL NAME GFN SIGNAL NAME GFN SIGNAL NAME

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C1 C2 C3 C4 C5 C6 C7 C8

GND A_CAD16//A_A17 A_CAD1 1//A_OE A_CC/BE0//A_CE1 A_RSVD//A_D14 A_CAD3//A_D5 A_CAD1//A_D4 A_CCD1//A_CD1 B_CAD29//B_D1 B_CCLKRUN//B_WP(IOIS16) B_CSTSCHG//B_BVD1(STSCHG/RI) B_CINT//B_READY(IREQ) B_CAD24//B_A2 B_CAD23//B_A3 B_CAD21//B_A5 B_CAD19//B_A25 B_CC/BE2//B_A12 B_CFRAME//B_A23 B_CGNT//B_WE B_CSTOP//B_A20 A_RSVD//A_A18 A_CAD14//A_A9 A_CAD15//A_IOWR A_CAD10//A_CE2 V

CCA

A_CAD5//A_D6 A_CAD4//A_D12 A_CAD0//A_D3 B_CAD30//B_D9 B_CCD2//B_CD2 B_CSERR//B_WAIT B_CVS1//B_VS1 V

CCB

B_CREQ//B_INPACK B_CRST//B_RESET B_CAD18//B_A7 B_CCLK//B_A16 B_CDEVSEL//B_A21 B_CPERR//B_A14 B_CPAR//B_A13 A_CGNT//A_WE A_CPAR//A_A13 A_CC/BE1//A_A8 A_CAD12//A_A11 A_CAD9//A_A10 A_CAD8//A_D15 A_CAD6//A_D13 A_CAD2//A_D11

C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E1 E2 E3 E4 E17 E18 E19 E20 F1 F2 F3 F4 F17 F18 F19 F20

B_RSVD//B_D2 B_CAD27//B_D0 B_CAUDIO//B_BVD2(SPKR) B_CAD26//B_A0 B_CC/BE3//B_REG B_CAD22//B_A4 B_CVS2//B_VS2 B_CAD17//B_A24 B_CTRDY//B_A22 B_CBLOCK//B_A19 B_RSVD//B_A18 B_CAD14//B_A9 A_CDEVSEL//A_A21 A_CBLOCK//A_A19 A_CPERR//A_A14 GND A_CAD13//A_IORD V

A_CAD7//A_D7 GND B_CAD31//B_D10 B_CAD28//B_D8 V

B_CAD25//B_A1 GND B_CAD20//B_A6 V

B_CIRDY//B_A15 GND B_CC/BE1//B_A8 B_CAD15//B_IOWR B_CAD13//B_IORD A_CIRDY//A_A15 A_CTRDY//A_A22 A_CCLK//A_A16 A_CSTOP//A_A20 B_CAD16//B_A17 B_CAD12//B_A11 V

CCB

B_CAD9//B_A10 A_CAD17//A_A24 A_CC/BE2//A_A12 V

CCA

B_CAD11//B_OE B_CC/BE0//B_CE1 B_CAD7//B_D7

A_CVS2//A_VS2

A_CAD19//A_A25

A_CAD18//A_A7

A_CFRAME//A_A23

G17

B_CAD10//B_CE2

G18

B_CAD8//B_D15

G19

B_RSVD//B_D14

G20

B_CAD5//B_D6

A_CAD21//A_A5

A_CRST//A_RESET

A_CAD20//A_A6

GND

H17

GND

H18

B_CAD6//B_D13

H19

B_CAD3//B_D5

H20

B_CAD4//B_D12

A_CC/BE3//A_REG

A_CAD23//A_A3

A_CREQ//A_INPACK

A_CAD22//A_A4

J17

B_CAD1//B_D4

J18

B_CAD2//B_D11

J19

B_CAD0//B_D3

J20

B_CCD1//B_CD1

A_CAD26//A_A0

A_CAD24//A_A2

A_CAD25//A_A1

V K17 K18 K19 K20 L1 L2 L3 L4 L17 L18 L19 L20 M1 M2 M3 M4 M17 M18 M19 M20

PCLK

CLKRUN

PRST

GNT

A_CVS1//A_VS1

A_CINT//A_READY(IREQ)

A_CSERR//A_WAIT

CCA

AD31

AD30

REQ

A_CAUDIO//A_BVD2(SPKR)

A_CSTSCHG//A_BVD1(STSCHG/RI)

A_CCLKRUN//A_WP(IOIS16)

A_CCD2//A_CD2

AD26

AD27

AD28

AD29

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI4450 GFN/GJG PC Card and OHCI Controller

SCPS046 – JANUAR Y 1999

signal names and terminal assignments (continued)

Table 1. GFN Terminals Sorted Alphanumerically for CardBus // 16-bit Signals and OHCI (Continued)

GFN SIGNAL NAME GFN SIGNAL NAME GFN SIGNAL NAME

N1 N2 N3 N4 N17 N18 N19 N20 P1 P2 P3 P4 P17 P18 P19 P20 R1 R2 R3 R4 R17 R18 R19 R20 T1 T2 T3 T4 T17 T18 T19 T20 U1 U2 U3 U4 U5 U6

A_CAD27//A_D0 A_CAD28//A_D8 A_CAD29//A_D1 GND GND C/BE3 AD24 AD25 A_CAD30//A_D9 A_RSVD//A_D2 ZV_HREF ZV_Y1 AD20 AD23 V

CCP

IDSEL/MFUNC7 A_CAD31//A_D10 ZV_VSYNC ZV_Y2 V

AD19 AD21 AD22 ZV_Y0 ZV_Y3 ZV_Y5 ZV_UV0 IRDY AD16 AD17 AD18 ZV_Y4 ZV_Y6 ZV_UV2 GND ZV_SDATA V

U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 W1 W2 W3

PHY_CTL0 GND PHY_DATA6 V

SUSPEND CLOCK GND AD6 V

AD12 GND TRDY DEVSEL C/BE2 ZV_Y7 ZV_UV1 ZV_UV3 ZV_LRCLK MFUNC5 PHY_CLK PHY_DATA0 PHY_DATA3 PHY_DATA7 MFUNC3 SPKROUT DATA AD0 V

CCP

AD7 AD9 AD13 C/BE1 STOP FRAME ZV_UV4 ZV_UV6 ZV_SCLK

W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20

ZV_MCLK LPS PHY_CTL1 PHY_DATA1 PHY_DATA4 MFUNC4 SCL MFUNC0 LATCH IRQSER AD2 AD4 C/BE0 AD10 AD14 PAR PERR ZV_UV5 ZV_UV7 ZV_PCLK MFUNC6 PHY_LREQ LINKON PHY_DATA2 PHY_DATA5 SDA MFUNC2 MFUNC1 G_RST RI_OUT AD1 AD3 AD5 AD8 AD11 AD15 SERR

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PCI4450 GFN/GJG

PC Card and OHCI Controller

SCPS046 – JANUAR Y 1999

signal names and terminal assignments (continued)

Table 2. GJG Terminals Sorted Alphanumerically for CardBus // 16-bit Signals and OHCI

NO. SIGNAL NAME NO. SIGNAL NAME NO. SIGNAL NAME

A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 C1 C2 C18 C19 D1 D2 D4 D5 D6 D7 D8 D9 D10 D11

A_CC/BE1//A_A8 GND A_CAD12//A_A11 A_CAD10//A_CE2 A_CAD8//A_D15 A_CAD3//A_D5 A_CAD0//A_D3 B_CAD29//B_D1 B_CSTSCHG//B_BVD1(STSCHG /RI ) V

B_CC/BE3//B_REG B_CREQ//B_INPACK B_CVS2//B_VS2 B_CAD17//B_A24 GND B_CCLK//B_A16 B_CDEVSEL//B_A21 A_CPAR//A_A13 A_RSVD//A_A18 A_CAD16//A_A17 A_CAD15//A_IOWR A_CAD11//A_OE V

CCA

A_CAD6//A_D13 A_CAD2//A_D11 B_CAD30//B_D9 B_CCLKRUN//B_WP(IOIS16) B_CVS1//B_VS1 V

CCB

B_CAD22//B_A4 B_CAD20//B_A6 B_CAD18//B_A7 B_CIRDY//B_A15 B_CTRDY//B_A22 B_CGNT//B_WE B_CSTOP//B_A20 GND A_CBLOCK//A_A19 B_CPERR//B_A14 B_CPAR//B_A13 A_CPERR//A_A14 A_CSTOP//A_A20 A_CAD14//A_A9 A_CAD13//A_IORD A_CC/BE0//A_CE1 A_CAD5//A_D6 GND B_RSVD//B_D2 B_CCD2//B_CD2 B_CAD26//B_A0

D12 D13 D14 D15 D16 D18 D19 E1 E2 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E18 E19 F1 F2 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F18 F19 G1 G2 G4 G5 G6 G7 G13 G14 G15

B_CAD24//B_A2 B_CAD23//B_A3 V

B_CFRAME//B_A23 B_CBLOCK//B_A19 B_RSVD//B_A18 B_CC/BE1//B_A8 V

A_CCLK//A_A16 A_CGNT//A_WE A_CDEVSEL//A_A21 V

A_RSVD//A_D14 A_CAD1//A_D4 B_CAD31//B_D10 B_CAD27//B_D0 B_CINT//B_READY(IREQ) B_CAD25//B_A1 B_CAD21//B_A5 B_CAD19//B_A25 B_CC/BE2//B_A12 B_CAD16//B_A17 B_CAD14//B_A9 V

CCA

A_CFRAME//A_A23 A_CIRDY//A_A15 A_CTRDY//A_A22 A_CAD9//A_A10 A_CAD7//A_D7 A_CCD1//A_CD1 B_CAD28//B_D8 B_CAUDIO//B_BVD2(SPKR) B_CSERR//B_WAIT GND B_CRST//B_RESET B_CAD15//B_IOWR B_CAD12//B_A11 B_CAD13//B_IORD V

CCB

B_CAD11//B_OE GND A_CAD18//A_A7 A_CAD19//A_A25 A_CAD17//A_A24 A_CC/BE2//A_A12 A_CAD4//A_D12 B_CAD7//B_D7 B_CAD10//B_CE2 B_CAD9//B_A10

G16

B_CC/BE0//B_CE1 G18

B_CAD8//B_D15 G19

GND H1

A_CAD20//A_A6 H2

A_CRST//A_RESET H4

A_CAD21//A_A5 H5

A_CAD22//A_A4 H6

A_CVS2//A_VS2 H14

B_CAD4//B_D12 H15

B_RSVD//B_D14 H16

B_CAD5//B_D6 H18

B_CAD6//B_D13 H19

B_CAD3//B_D5 J1

A_CAD23//A_A3 J2

A_CC/BE3//A_REG J4

A_CREQ//A_INPACK J5

A_CAD24//A_A2 J6

A_CAD25//A_A1 J14

V J15 J16 J18 J19 K1 K2 K4 K5 K6 K14 K15 K18 K19 L1 L2 L4 L5 L6 L14 L15 L16 L18 L19 M1 M2 M4 M5 M6 M14 M15 M16

B_CAD1//B_D4

B_CAD2//B_D11

B_CAD0//B_D3

B_CCD1//B_CD1

A_CVS1//A_VS1

A_CINT//A_READY(IREQ)

A_CSERR//A_WAIT

CCA

A_CAD26//A_A0

GNT

PCLK

CLKRUN

PRST

A_CSTSCHG//A_BVD1(STSCHG/RI)

A_CCLKRUN//A_WP(IOIS16)

A_CCD2//A_CD2

A_CAD27//A_D0

A_CAUDIO//A_BVD2(SPKR)

REQ

AD31

AD28

AD30

AD29

A_CAD29//A_D1

GND

A_CAD30//A_D9

A_RSVD//A_D2

A_CAD28//A_D8

C/BE3

AD27

AD26

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PCI4450 GFN/GJG PC Card and OHCI Controller

SCPS046 – JANUAR Y 1999

signal names and terminal assignments (continued)

Table 2. GJG Terminals Sorted Alphanumerically for CardBus // 16-bit Signals and OHCI (Continued)

NO. SIGNAL NAME NO. SIGNAL NAME NO. SIGNAL NAME

M18 M19 N1 N2 N4 N5 N6 N7 N13 N14 N15 N16 N18 N19 P1 P2 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P18 P19 R1 R2 R4 R5

AD25 AD24 ZV_HREF ZV_VSYNC ZV_Y0 ZV_Y1 ZV_Y2 A_CAD31//A_D10 AD3 AD22 AD23 GND V

CCP

IDSEL/MFUNC7 V

ZV_Y3 ZV_Y4 ZV_Y5 ZV_Y6 LINKON PHY_DATA3 MFUNC2 MFUNC1 G_RST IRQSER AD6 AD9 V

AD19 AD21 AD20 ZV_Y7 ZV_UV0 ZV_UV2 MFUNC6

R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R18 R19 T1 T2 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T18 T19 U1 U2 U18 U19 V1

PHY_LREQ PHY_DATA0 PHY_DATA7 MFUNC3 SUSPEND RI_OUT AD2 AD5 AD8 AD16 C/BE2 AD18 AD17 ZV_UV1 ZV_UV4 GND V

PHY_CLK GND PHY_DATA6 MFUNC4 SPKROUT CLOCK AD1 AD4 C/BE0 AD12 C/BE1 FRAME IRDY ZV_UV3 ZV_UV6 TRDY DEVSEL ZV_UV5

V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18

ZV_SCLK ZV_LRCLK ZV_PCLK LPS PHY_CTL1 PHY_DATA1 PHY_DATA5 SCL V

DATA AD0 V

GND AD11 AD14 PAR PERR STOP ZV_UV7 ZV_MCLK ZV_SDATA MFUNC5 PHY_CTL0 PHY_DATA2 PHY_DATA4 SDA MFUNC0 LATCH GND V

CCP

AD7 AD10 AD13 AD15 SERR

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI4450 GFN/GJG

PC Card and OHCI Controller

SCPS046 – JANUAR Y 1999

PCI4450 System Block Diagram

Figure 2 shows a simplified system implementation example using the PCI4450. The PCI interface includes all address/data and control signals for PCI protocol. Highlighted in this diagram is the functionality supported by the PCI4450. The PCI4450 supports PC/PCI DMA, PCI Way DMA (distributed DMA), PME wake-up from D3

through D0, 4 interrupt modes, an integrated zoomed video port, and 12 multifunction pins (8 MFUNC,

cold

and 4 GPIO pins) that can be programmed for a wide variety of functions.

PCI Bus

Activity LED’ s

Real Time

Clock

CLKRUN

South Bridge

OHCI-PHY Interface

IRQSER

DMA PME

Zoomed Video

19 Video

4 Audio

Interrupt Routing Options:

Embedded

Controller

VGA

Controller

Audio

Codec

1) Serial ISA/Serial PCI

2) Serial ISA/Parallel PCI

TPS2206

Power

Switch

PC Card

Socket A

PC Card

Socket B

†

The PC Card interface is 68 pins for CardBus and 16-bit PC Cards. In zoomed-video mode 23 pins are used for routing the zoomed video signals to the VGA controller .

Clock

23 for ZV†

23 for ZV

PCI4450

Enable

PHY

1394 Ports

Figure 2. PCI4450 System Block Diagram

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PCI4450 GFN/GJG

I/O

PC Card and OHCI Controller

SCPS046 – JANUAR Y 1999

terminal functions

This section describes the PCI4450 terminal functions. The terminals are grouped in tables by functionality such as PCI system function, power supply function, etc., for quick reference. The terminal numbers are also listed for convenient reference.

Table 3. Power Supply

TERMINAL

NAME GFN NO. GJG NO.

GND

CCA

CCB

CCP

A1, D4, D8, D13, D17, H4, H17,

N4, N17, U4, U8, U13, U17

D6, D11, D15, F4, F17, K4, L17,

R4, R17, U6, U10, U15

B5, F3, L4 B6, F1, K5

B13, E19 B12, F18 P19, V14 N18, W13 Clamp voltage for PCI signaling (3.3 Vdc or 5 Vdc)

A3, A16, C1, D8, F12, G1, G19,

M2, N16, T4, T7, V14, W12

A11, D14, E1, E6, E19, J14, P1,

P15, T5, V10, V13

Table 4. PC Card Power Switch

TERMINAL

NAME GFN NO. GJG NO.

CLOCK U12 T11 I/O

DAT A V12 V1 1 O

LATCH W12 W1 1 O

I/O

TYPE

3-line power switch clock. Information on the DA T A line is sampled at the rising edge of CLOCK. This terminal defaults as an input which means an external clock source must be used. If the internal ring oscillator is used, then an external CLOCK source is not required. The internal oscillator may be enabled by setting bit 27 of the system control register (PCI offset 80h) to a 1b. A 43 kW pulldown resistor should be tied to this terminal.

3-line power switch data. DAT A is used to serially communicate socket power-control information to the power switch.

3-line power switch latch. LA TCH is asserted by the PCI4450 to indicate to the PC Card power switch that the data on the DA TA line is valid.

FUNCTION

Device ground terminals

Power supply terminal for core logic (3.3 Vdc) Clamp voltage for PC Card A interface. Indicates Card A

signaling environment. Clamp voltage for PC Card B interface. Indicates Card B

signaling environment.

FUNCTION

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terminal functions (continued)

I/O

PCI4450 GFN/GJG

PC Card and OHCI Controller

SCPS046 – JANUAR Y 1999

Table 5. PCI System

TERMINAL

NAME GFN NO. GJG NO.

CLKRUN

PCLK K17 K15 I

PRST K19 K19 I

G_RST Y12 P11 I

K18 K18 I/O

I/O

TYPE

FUNCTION

PCI clock run. CLKRUN is used by the central resource to request permission to stop the PCI clock or to slow it down, and the PCI4450 responds accordingly. If CLKRUN is not implemented, then this pin should be tied low. CLKRUN is enabled by default by bit 1 (KEEPCLK) in the system control register .

PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCLK.

PCI reset. When the PCI bus reset is asserted, PRST causes the PCI4450 to place all output buffers in a high-impedance state and reset all internal registers. When PRST is asserted, the device is completely nonfunctional. After PRST is deasserted, the PCI4450 is in its default state. When the SUSPEND mode is enabled, the device is protected from the PRST and the internal registers are preserved. All outputs are placed in a high-impedance state, but the contents of the registers are preserved.

Global reset. When the global reset is asserted, the G_RST signal causes the PCI4450 to place all output buffers in a high-impedance state and reset all internal registers. When G_RST is asserted, the device is completely in its default state. For systems that require wake-up from D3, G_RST will normally be asserted only during initial boot. PRST should be asserted following initial boot so that PME context is retained when transitioning from D3 to D0. For systems that do not require wake-up from D3, G_RST should be tied to PRST.

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I/O

PC Card and OHCI Controller

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terminal functions (continued)

Table 6. PCI Address and Data

TERMINAL

NAME GFN NO. GJG NO.

AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD1 1 AD10

AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

C/BE3 C/BE2 C/BE1 C/BE0

PAR W19 V17 I/O

L18 L19 M20 M19 M18 M17 N20 N19 P18 R20 R19 P17 R18 T20 T19 T18 Y19

W18

V17 U16 Y18

W17

V16 Y17 V15 U14 Y16

W15

Y15

W14

Y14 V13

N18 U20 V18

W16

L15 L18 L19

L16 M15 M16 M18 M19 N15 N14 P18 P19 P16 R18 R19 R15 W17 V16 W16

T15 V15 W15 P14 R14 W14 P13 R13

T13 N13 R12

T12 V12

M14 R16

T16

T14

TYPE

I/O

PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the

I/O

primary interface. During the address phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit address or other destination information. During the data phase, AD31–AD0 contain data.

PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address phase of a primary bus PCI cycle, C/BE3–C/BE0 define the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which

I/O

byte paths of the full 32-bit data bus carry meaningful data. C/BE0 applies to byte 0 (AD7–AD0), C/BE1 applies to byte 1 (AD15–AD8), C/BE2 applies to byte 2 (AD23–AD16), and C/BE3 applies to byte 3 (AD31–AD24).

PCI bus parity. In all PCI bus read and write cycles, the PCI4450 calculates even parity across the AD31–AD0 and C/BE3–C/BE0 buses. As an initiator during PCI cycles, the PCI4450 outputs this parity indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator’s parity indicator . A compare error results in the assertion of a parity error (PERR).

FUNCTION

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terminal functions (continued)

I/O

PCI4450 GFN/GJG

PC Card and OHCI Controller

SCPS046 – JANUAR Y 1999

Table 7. PCI Interface Control

TERMINAL

NAME GFN NO. GJG NO.

DEVSEL U19 U19 I/O

FRAME V20 T18 I/O

GNT K20 K14 I

LOCK

(MFUNC7)

IDSEL/MFUNC7 P20 N19 I

IRDY T17 T19 I/O

PERR

REQ L20 L14 O

SERR Y20 W18 O

STOP V19 V19 I/O

TRDY U18 U18 I/O

P20 N19 I/O

W20 V18 I/O

TYPE

I/O

PCI device select. The PCI4450 asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator on the bus, the PCI4450 monitors DEVSEL until a target responds. If no target responds before timeout occurs, then the PCI4450 terminates the cycle with an initiator abort.

PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME is deasserted, the PCI bus transaction is in the final data phase.

PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI4450 access to the PCI bus after the current data transaction has completed. GNT may or may not follow a PCI bus request, depending on the PCI bus parking algorithm.

PCI bus lock. MFUNC7/LOCK can be configured as PCI LOCK and used to gain exclusive access downstream. Since this functionality is not typically used, other functions may be accessed through this terminal. MFUNC7/LOCK defaults to and can be configured through the multifunction routing status register.

Initialization device select. IDSEL selects the PCI4450 during configuration space accesses. IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus. If the LATCH terminal (W12/W11) has an external pulldown resistor, then this terminal is configurable as MFUNC7 and IDSEL defaults to the AD23 terminal.

PCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK where both IRDY and TRDY are asserted. Until IRDY and TRDY are both sampled asserted, wait states are inserted.

PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not match P AR when PERR is enabled through bit 6 of the command register .

PCI bus request. REQ is asserted by the PCI4450 to request access to the PCI bus as an initiator .

PCI system error. SERR is an output that is pulsed from the PCI4450 when enabled through the command register , indicating a system error has occurred. The PCI4450 need not be the target of the PCI cycle to assert this signal. When SERR is enabled in the bridge control register, this signal also pulses, indicating that an address parity error has occurred on a CardBus interface.

PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus transaction. STOP is used for target disconnects and is commonly asserted by target devices that do not support burst data transfers.

PCI target ready. TRDY indicates the primary bus target’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY and TRDY are asserted. Until both IRDY and TRDY are asserted, wait states are inserted.

FUNCTION

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I/O

PC Card and OHCI Controller

SCPS046 – JANUAR Y 1999

terminal functions (continued)

Table 8. System Interrupt

TERMINAL

NAME GFN NO. GJG NO.

INTA

(MFUNC0)

INTB

(MFUNC1)

INTC

(MFUNC2)

IRQSER W13 P12 I/O

MFUNC6 MFUNC5 MFUNC4 MFUNC3 MFUNC2 MFUNC1 MFUNC0

RI_OUT/PME Y13 R11 O

W1 1 W10 I/O

Y11 P10 I/O

Y10 P9 I/O

Y4 V5

W9 V10 Y10 Y11

W1 1

T9 R9 P9

P10

W10

I/O

TYPE

FUNCTION

Parallel PCI interrupt. INTA can be mapped to MFUNC0 when parallel PCI interrupts are used. See

programmable interrupt subsystem

defaults to a general-purpose input. Parallel PCI interrupt. INTB can be mapped to MFUNC1 when parallel PCI interrupts are

used. See

programmable interrupt subsystem

defaults to a general-purpose input. Parallel PCI interrupt. INTC can be mapped to MFUNC2 when parallel PCI interrupts are

used. See

programmable interrupt subsystem

defaults to a general-purpose input. Serial interrupt signal. IRQSER provides the IRQSER-style serial interrupting scheme.

Serialized PCI interrupts can also be sent in the IRQSER stream. See

interrupt subsystem

Interrupt request/secondary functions multiplexed. The primary function of these terminals is to provide programmable options supported by the PCI4450. These interrupt multiplexer outputs can be mapped to various functions. See options.

All of these terminals have secondary functions, such as PCI interrupts, PC/PCI DMA, OHCI

LEDs, GPE request/grant, ring indicate output, and zoomed video status, that can be selected with the appropriate programming of this register . When the secondary functions are enabled, the respective terminals are not available for multifunction routing.

See the

multifunction routing status register

Ring indicate out and power management event output. T erminal provides an output to the system for ring-indicate or PME signals. Alternately, RI_OUT can be routed on MFUNC7.

for details on interrupt signaling.

for details on interrupt signaling. MFUNC0/INTA

for details on interrupt signaling. MFUNC1/INTB

for details on interrupt signaling. MFUNC2/INTC

multifunction routing status register

for programming options.

programmable

for

TERMINAL

NAME GFN NO. GJG NO.

PCGNT

(MFUNC2)

PCGNT

(MFUNC3)

PCREQ

(MFUNC7)

PCREQ

(MFUNC4)

PCREQ

(MFUNC0)

Y10

V10

P20

W1 1

N19

W10

I/O

TYPE

I/O

Table 9. PC/PCI DMA

FUNCTION

PC/PCI DMA grant. PCGNT is used to grant the DMA channel to a requester in a system supporting the PC/PCI DMA scheme. PCGNT, is available on MFUNC2 or MFUNC3.

This terminal is also used for the serial EEPROM interface.

PC/PCI DMA request. PCREQ is used to request DMA transfers as DREQ in a system supporting the PC/PCI DMA scheme. PCREQ is available on MFUNC7, MFUNC4, or MFUNC0.

This terminal is also used for the serial EEPROM interface.

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terminal functions (continued)

I/O AND MEMORY

PCI4450 GFN/GJG

PC Card and OHCI Controller

SCPS046 – JANUAR Y 1999

Table 10. Zoomed Video

TERMINAL

NAME

ZV_HREF P3 N1 A10 O Horizontal sync to the zoomed video port

ZV_VSYNC R2 N2 A1 1 O Vertical sync to the zoomed video port

ZV_Y7 ZV_Y6 ZV_Y5 ZV_Y4 ZV_Y3 ZV_Y2 ZV_Y1 ZV_Y0

ZV_UV7 ZV_UV6 ZV_UV5 ZV_UV4 ZV_UV3 ZV_UV2 ZV_UV1

ZV_UV0 ZV_SCLK W3 V2 A7 O Audio SCLK PCM ZV_MCLK W4 W3 A6 O Audio MCLK PCM ZV_PCLK Y3 V4 IOIS16 O Pixel clock to the zoomed video port

ZV_LRCLK V4 V3 INP ACK O Audio LRCLK PCM ZV_SDA T A U5 W4 SPKR O Audio SDATA PCM

GFN

NO.

P4 T1

V2 T4

GJG NO.

R1 P6 P5 P4 P2 N6 N5 N4

U2 V1 T2 U1 R4 T1 R2

I/O AND MEMORY

INTERFACE

SIGNAL

A20 A14 A19 A13 A18

A17

A25 A12 A24 A15 A23 A16 A22 A21

I/O

TYPE

O Video data to the zoomed video port in YV:4:2:2 format

FUNCTION

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terminal functions (continued)

Table 11. Miscellaneous

TERMINAL

NAME

MFUNC0 W11 W10 I/O

MFUNC1 Y11 P10 I/O

MFUNC2

MFUNC3

MFUNC4

MFUNC5

MFUNC6 Y4 R5 I/O

IDSEL/MFUNC7 P20 N19 I/O

SCL W10 V9 I/O

SDA Y9 W9 I/O

SPKROUT

SUSPEND

GFN

NO.

Y10 P9 I/O

V10 R9 I/O

W9 T9 I/O

V5 W5 I/O

V11 T10 O

U11 R10 I

GJG

NO.

I/O

TYPE

FUNCTION

Multifunction terminal 0. Defaults as a general-purpose input (GPI0), and can be programmed to perform various functions. Refer to

Multifunction terminal 1. Defaults as a general-purpose input (GPI1), and can be programmed to perform various functions. Refer to

Multifunction terminal 2. Defaults as a general-purpose input (GPI2), and can be programmed to perform various functions. Refer to

Multifunction terminal 3. Defaults as a general-purpose input (GPI3), and can be programmed to perform various functions. Refer to

Multifunction terminal 4. Defaults as a high–impedance reserved input, and can be programmed to perform various functions. Refer to

Multifunction terminal 5. Defaults as a high–impedance reserved input, and can be programmed to perform various functions. Refer to

Multifunction terminal 6. Defaults as a high–impedance reserved input, and can be programmed to perform various functions. Refer to

IDSEL and multifunction terminal 7. Defaults as IDSEL, but may be used as a multifunction terminal. Refer to

Serial ROM clock. This terminal provides the SCL serial clock signaling in a two–wire serial ROM implementation, and is sensed at reset for serial ROM detection.

Serial ROM data. This terminal provides the SDA serial data signaling in a two–wire serial ROM implementation.

Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO through the PCI4450 from the PC Card interface. SPKROUT is driven as the XOR combination of card SPKR//CAUDIO inputs.

Suspend. SUSPEND is used to protect the internal registers from clearing when PRST is asserted. See

multifunction routing register

suspend mode

multifunction routing register

description and Section 3.4 for details.

for details.

description.

multifunction routing register

description.

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terminal functions (continued)

I/O

FUNCTION

Table 12. 16-bit PC Card Address and Data (slots A and B)

TERMINAL

GFN NO. GJG NO.

NAME

†

T erminal name for slot A is preceded with A_. For example, the full name for terminal G2 is A_A25.

‡

T erminal name for slot B is preceded with B_. For example, the full name for terminal A16 is B_A25.

A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D15 D14 D13 D12

D11

D10

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

SLOT

†

G2 F1 G4 E2 D1 E4 D2 B1 A2 E3 E1 D3 C2 F2 C4 C5 B2 C3 G3 H3 H1

J2 K2 K3 K1

C6 A5 C7 B7 C8 R1 P1 N2 D7 B6 A6 A7 B8 P2 N3 N1

SLOT

‡

A16 C16 A18 C17 B18 A20 C18 C19 E17 B17 D16 B19 B20 A17 E18 E20 C20 D18 B16 D14 A15 C14 A14 A13 D12 C12

G18 G19 H18 H20

J18

D9 B9

D10

F20 G20 H19

J17

J19

C9 A9

C10

SLOT

†

G4 G5 F2 F5 E5 D2 C2 B2 B3 E2 F4 D1 B1 G6 A4 F6 D4 A2 G2 H1 H4 H5

J1 J5 J6

K6 A6

E7 B7 G7 B8 N7 M4 M6 F7 D7 A7 E8 A8 M5 M1

SLOT

E14 A15 D15 B17 A18 B19 D16 D18 E16 A17 B16 C18 C19 E15 F15 G15 E18 D19 B15 B14 E13 B13 D13 D12 E12 D11

G18 H15 H18 H14

J16

E9 B9

F9 G13 H16 H19

J15 J18

A9 E10

I/O

TYPE

‡

O PC Card address. 16-bit PC Card address lines. A25 is the most significant bit.

I/O PC Card data. 16-bit PC Card data lines. D15 is the most significant bit.

PCI4450 GFN/GJG

PC Card and OHCI Controller

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PCI4450 GFN/GJG

I/O

FUNCTION

PC Card and OHCI Controller

SCPS046 – JANUAR Y 1999

terminal functions (continued)

Table 13. 16-bit PC Card Interface Control (slots A and B)

TERMINAL

GFN NO. GJG NO.

NAME

BVD1

(STSCHG/RI)

BVD2

(SPKR)

CD1 CD2

CE1 CE2

INPACK J3 B14 J4 A13 I

IORD D5 D20 D5 F16 O

IOWR B3 D19 B4 F14 O

SLOT

†

M2 A11 L1 A10 I

M1 C11 L6 F10 I

A8M4J20

A4B4F19

‡

B10F8L4

G17D6A5

SLOT

†

J19

D10

G16 G14

I/O

TYPE

‡

Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries. BVD1 and BVD2 indicate the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are kept high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See ExCA card status-change interrupt configuration register for the enable bits. See ExCA card status-change register and the ExCA interface status register for the status bits for this signal.

Status change. STSCHG is used to alert the system to a change in the READY , write protect, or battery voltage dead condition of a 16-bit I/O PC Card.

Ring indicate. RI is used by 16-bit modem cards to indicate a ring detection. Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that

include batteries. BVD2 and BVD1 indicate the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See ExCA card status-change interrupt configuration register for enable bits. See ExCA card status-change register and the ExCA interface status register for the status bits for this signal.

Speaker . SPKR is an optional binary audio signal available only when the card and socket have been configured for the 16-bit I/O interface. The audio signals from cards A and B are combined by the PCI4450 and are output on SPKROUT.

DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. The PC Card asserts BVD2 to indicate a request for a DMA operation.

PC Card detect 1 and PC Card detect 2. CD1 and CD2 are internally connected

to ground on the PC Card. When a PC Card is inserted into a socket, CD1 and CD2 are pulled low. For signal status, see ExCA interface status register.

Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered

address bytes. CE1 enables even-numbered address bytes, and CE2 enables odd-numbered address bytes.

Input acknowledge. INP ACK is asserted by the PC Card when it can respond to an I/O read cycle at the current address.

DMA request. INPACK can be used as the DMA request signal during DMA operations from a 16-bit PC Card that supports DMA. If used as a strobe, the PC Card asserts this signal to indicate a request for a DMA operation.

I/O read. IORD is asserted by the PCI4450 to enable 16-bit I/O PC Card data output during host I/O read cycles.

DMA write. IORD is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI4450 asserts IORD during DMA transfers from the PC Card to host memory .

I/O write. IOWR is driven low by the PCI4450 to strobe write data into 16-bit I/O PC Cards during host I/O write cycles.

DMA read. IOWR is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI4450 asserts IOWR during transfers from host memory to the PC Card.

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PC Card and OHCI Controller

I/O

FUNCTION

terminal functions (continued)

Table 13. 16-bit PC Card Interface Control (slots A and B) (continued)

TERMINAL

GFN NO. GJG NO.

NAME

OE A3 F18 B5 F19 O

READY

(IREQ)

REG J1 C13 J2 A12 O

RESET H2 B15 H2 F13 O PC Card reset. RESET forces a hard reset to a 16-bit PC Card.

WAIT

WE C1 A19 E4 B18 O

(IOIS16)

VS1 VS2

†

T erminal name for slot A is preceded with A_. For example, the full name for terminal C1 is A_WE.

‡

T erminal name for slot B is preceded with B_. For example, the full name for terminal A19 is B_WE.

SLOT

†

L2 A12 K2 E11 I

L3 B1 1 K4 F11 I

M3 A10 L2 B10 I

L1G1B12

SLOT

‡

C15K1H6

SLOT

†

B11 A14

I/O

TYPE

‡

Output enable. OE is driven low by the PCI4450 to enable 16-bit memory PC Card data output during host memory read cycles.

DMA terminal count. OE is used as terminal count (TC) during DMA operations to a 16-bit PC Card that supports DMA. The PCI4450 asserts OE to indicate TC for a DMA write operation.

Ready . The ready function is provided by READY when the 16-bit PC Card and the host socket are configured for the memory-only interface. READY is driven low by the 16-bit memory PC Cards to indicate that the memory card circuits are busy processing a previous write command. READY is driven high when the 16-bit memory PC Card is ready to accept a new data transfer command.

Interrupt request. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host that a device on the 16-bit I /O PC Card requires service by the host software. IREQ is high (deasserted) when no interrupt is requested.

Attribute memory select. REG remains high for all common memory accesses. When REG is asserted, access is limited to attribute memory (OE or WE active) and to the I/O space (IORD or IOWR active). Attribute memory is a separately accessed section of card memory and is generally used to record card capacity and other configuration and attribute information.

DMA acknowledge. REG is used as a DMA acknowledge (DACK) during DMA operations to a 16-bit PC Card that supports DMA. The PCI4450 asserts REG to indicate a DMA operation. REG is used in conjunction with the DMA read (IOWR) or DMA write (IORD) strobes to transfer data.

Bus cycle wait. WAIT is driven by a 16-bit PC Card to delay the completion of (i.e., extend) the memory or I/O cycle in progress.

Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also used for memory PC Cards that employ programmable memory technologies.

DMA terminal count. WE is used as TC during DMA operations to a 16-bit PC Card that supports DMA. The PCI4450 asserts WE to indicate TC for a DMA read operation.

Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16) function.

I/O is 16 bits. IOIS16 applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card when the address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that is addressed is capable of 16-bit accesses.

DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, the PC Card asserts WP to indicate a request for a DMA operation.

Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction

I/O

with each other, determine the operating voltage of the 16-bit PC Card.

PCI4450 GFN/GJG

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PCI4450 GFN/GJG

I/O

FUNCTION

PC Card and OHCI Controller

SCPS046 – JANUAR Y 1999

terminal functions (continued)

Table 14. CardBus PC Card Interface System (slots A and B)

TERMINAL GFN NO. GJG NO.

NAME

CCLK E3 B17 E2 A17 O

CCLKRUN

CRST H2 B15 H2 F13 I/O

†

T erminal name for slot A is preceded with A_. For example, the full name for terminal E3 is A_CCLK.

‡

T erminal name for slot B is preceded with B_. For example, the full name for terminal B17 is B_CCLK.

SLOT

†

M3 A10 L2 B10 O

‡

SLOT

†

I/O

TYPE

‡

CardBus PC Card clock. CCLK provides synchronous timing for all transactions on the CardBus interface. All signals except CRST, CCLKRUN, CINT, CSTSCHG, CAUDIO, CCD2, CCD1, and CVS2–CVS1 are sampled on the rising edge of CCLK, and all timing parameters are defined with the rising edge of this signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the low state or slowed down for power savings.

CardBus PC Card clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the CCLK frequency , and by the PCI4450 to indicate that the CCLK frequency is decreased. CardBus clock run (CCLKRUN) follows the PCI clock run (CLKRUN).

CardBus PC Card reset. CRST is used to bring CardBus PC Card-specific registers, sequencers, and signals to a known state. When CRST is asserted, all CardBus PC Card signals must be placed in a high-impedance state, and the PCI4450 drives these signals to a valid logic level. Assertion can be asynchronous to CCLK, but deassertion must be synchronous to CCLK.

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terminal functions (continued)

I/O

FUNCTION

Table 15. CardBus PC Card Address and Data (slots A and B)

TERMINAL

GFN NO. GJG NO.

NAME

CAD31 CAD30 CAD29 CAD28 CAD27 CAD26 CAD25 CAD24 CAD23 CAD22 CAD21 CAD20 CAD19 CAD18 CAD17 CAD16 CAD15 CAD14 CAD13 CAD12 CAD11 CAD10

CAD9 CAD8 CAD7 CAD6 CAD5 CAD4 CAD3 CAD2 CAD1 CAD0

CC/BE3 CC/BE2 CC/BE1 CC/BE0

CPAR C2 B20 B1 C19 I/O

†

T erminal name for slot A is preceded with A_. For example, the full name for terminal C2 is A_CP AR.

‡

T erminal name for slot B is preceded with B_. For example, the full name for terminal B20 is B_CP AR.

SLOT

†

R1 P1 N3 N2 N1 K1 K3 K2

J4 H1 H3 G2 G3

F1 A2 B3 B2 D5 C4 A3 B4 C5 C6 D7 C7 B6 B7 A6 C8 A7 B8

F2 C3 A4

SLOT

‡

D9 B9

A9 D10 C10 C12 D12 A13 A14 C14 A15 D14 A16 B16 C16 E17 D19 C20 D20 E18 F18 G17 E20 G18 F20 H18 G20 H20 H19

J18 J17 J19

C13 A17 D18 F19

SLOT

†

N7 M4 M1 M6

J6 J5

J1 H5 H4 H1

G4 G2 G5

B3 B4 D4 D5 A4 B5 A5 F6 A6 F7 B7 D7

A7 B8 E8 A8

A2 D6

SLOT

E10 D11 E12 D12 D13 B13 E13 B14 E14 B15 A15 E16 F14 E18 F16 F15 F19 G14 G15 G18 G13 H18 H16 H14 H19

J16 J15 J18

A12 E15 D19 G16

E9 B9 A9 F9

I/O

TYPE

‡

PC Card address and data. These signals make up the multiplexed CardBus address and data bus on the CardBus interface. During the address phase of a CardBus cycle,

I/O

CAD31–CAD0 contain a 32-bit address. During the data phase of a CardBus cycle, CAD31–CAD0 contain data. CAD31 is the most significant bit.

CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the same CardBus terminals. During the address phase of a CardBus cycle, CC/BE3–CC/BE0 defines the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit

I/O

data bus carry meaningful data. CC/BE0 applies to byte 0 (CAD7–CAD0), CC/BE1 applies to byte 1 (CAD15–CAD8), CC/BE2 applies to byte 2 (CAD23–CAD16), and CC/BE3 applies to byte 3 (CAD31–CAD24).

CardBus parity . In all CardBus read and write cycles, the PCI4450 calculates even parity across the CAD and CC/BE buses. As an initiator during CardBus cycles, the PCI4450 outputs CP AR with a one-CCLK delay . As a target during CardBus cycles, the calculated parity is compared to the initiator’s parity indicator; a compare error results in a parity error assertion.

PCI4450 GFN/GJG

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PCI4450 GFN/GJG

I/O

FUNCTION

CCD1

A8M4J20

J19

PC Card and OHCI Controller

SCPS046 – JANUAR Y 1999

terminal functions (continued)

Table 16. CardBus PC Card Interface Control (slots A and B)

TERMINAL GFN NO. GJG NO.

NAME

CAUDIO M1 C11 L6 F10 I

CBLOCK D2 C18 C2 D16 I/O CardBus lock. CBLOCK is used to gain exclusive access to a target.

CCD1 CCD2

CDEVSEL D1 B18 E5 A18 I/O

CFRAME G4 A18 F2 D15 I/O

CGNT

CINT

CIRDY E1 D16 F4 B16 I/O

CPERR D3 B19 D1 C18 I/O

CREQ

CSERR L3 B11 K4 F1 1 I

CSTOP E4 A20 D2 B19 I/O

CSTSCHG

CTRDY E2 C17 F5 B17 I/O

CVS1 CVS2

†

T erminal name for slot A is preceded with A_. For example, the full name for terminal M1 is A_CAUDIO.

‡

T erminal name for slot B is preceded with B_. For example, the full name for terminal C1 1 is B_CAUDIO.

SLOT

†

A8 J20 F8 J19

C1 A19 E4 B18 I

L2 A12 K2 E1 1 I

J3 B14 J4 A13 I

M2 A11 L1 A10 I

L1G1B12

‡

B10F8L4

C15K1H6

SLOT

†

D10

B11 A14

I/O

TYPE

‡

CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker . The PCI4450 supports the binary audio mode and outputs a binary signal from the card to SPKROUT .

CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction

I with CVS1 and CVS2 to identify card insertion and interrogate cards to determine the

operating voltage and card type. CardBus device select. The PCI4450 asserts CDEVSEL to claim a CardBus cycle

as the target device. As a CardBus initiator on the bus, the PCI4450 monitors CDEVSEL until a target responds. If no target responds before timeout occurs, then the PCI4450 terminates the cycle with an initiator abort.

CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When CFRAME is deasserted, the CardBus bus transaction is in the final data phase.

CardBus bus grant. CGNT is driven by the PCI4450 to grant a CardBus PC Card access to the CardBus bus after the current data transaction has been completed.

CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the host.

CardBus initiator ready. CIRDY indicates the CardBus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY and CTRDY are asserted. Until CIRDY and CTRDY are both sampled asserted, wait states are inserted.

CardBus parity error. CPERR is used to report parity errors during CardBus transactions, except during special cycles. It is driven low by a target two clocks following that data when a parity error is detected.

CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus bus as an initiator.

CardBus system error . CSERR reports address parity errors and other system errors that could lead to catastrophic results. CSERR is driven by the card synchronous to CCLK, but deasserted by a weak pullup, and may take several CCLK periods. The PCI4450 can report CSERR to the system by assertion of SERR on the PCI interface.

CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus transaction. CSTOP is used for target disconnects, and is commonly asserted by target devices that do not support burst data transfers.

CardBus status change. CSTSCHG is used to alert the system to a change in the card’s status and is used as a wake-up mechanism.

CardBus target ready . CTRDY indicates the CardBus target’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY and CTRDY are asserted; until this time, wait states are inserted.

CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used

I/O

in conjunction with CCD1 and CCD2 to identify card insertion and interrogate cards to determine the operating voltage and card type.

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terminal functions (continued)

I/O

System cloc

des a 49.15

System clock. This in ut rovides a 49.152 MHz clock signal for data

Table 17. IEEE1394 PHY/Link Interface Terminals

PCI4450 GFN/GJG

PC Card and OHCI Controller

SCPS046 – JANUAR Y 1999

TERMINAL

NAME GFN NO. GJG NO.

PHY_CTL1 PHY_CTL0

PHY_DA T A7 PHY_DA T A6 PHY_DA T A5 PHY_DA T A4 PHY_DA T A3 PHY_DA T A2 PHY_DA T A1 PHY_DA T A0

PHY_CLK V6 T6 I

PHY_LREQ Y5 R6 O

LINKON Y6 P7 I 1394 link on. This input from the PHY indicates that the link should turn on.

LPS W5 V5 O Link power status. LPS indicates that link is powered and fully functional.

U7 V9

U9 Y8

V8 Y7

R8 T8 V8

V7 R7

I/O

TYPE

I/O

FUNCTION

Phy–link interface control. These bi-direction signals control passage of information between the PHY and link. The link can only drive these terminals after the PHY has granted permission following a link request (LREQ).

Phy–link interface data. These bi-directional signals pass data between the PHY and link. These terminals are driven by the link on transmissions and are driven by the PHY on receptions. Only DATA1–DATA0 are valid for 100 Mbit speed. DATA4–DATA0 are valid for 200 Mbit speed and DATA7–DATA0 are valid for 400 Mbit speed.

k. This input provi

synchronization. Link request. This signal is driven by the link to initiate a request for the PHY to

perform some service.

2 MHz clock signal for dat

I/O characteristics

Figure 3 shows a 3-state bidirectional buffer illustration for reference. The table,

conditions

provides the electrical characteristics of the inputs and outputs. The PCI4450 meets the ac

specifications of the PC Card 95 Standard and the PCI Bus 2.1 specifications.

Tied for Open Drain

CCP

recommended operating

Pad

Figure 3. 3-State Bidirectional Buffer

clamping voltages

The I/O sites can be pulled through a clamping diode to a voltage rail for protection. The 3.3-V core power supply is independent of the clamping voltages. The clamping (protection) diodes are required if the signaling environment on an I/O is system dependent. For example, PCI signaling can be either 3.3 Vdc or 5.0 Vdc, and the PCI4450 must reliably accommodate both voltage levels. This is accomplished by using a 3.3-V buffer with a clamping diode to V the 5.0-V power supply.

A standard die has only one clamping voltage for the sites as shown in Figure 3. After the terminal assignments are fixed, the fabrication facility will support a design by splitting the clamping voltage for customization. The PCI4450 requires five separate clamping voltages since it supports a wide range of features. The five voltages are listed and defined in the table,

. If a system design requires a 5.0-V PCI bus, then the V

CCP

recommended operating conditions

would be connected to

CCP

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PCI interface

This section describes the PCI interface of the PCI4450, and how the device responds to and participates in PCI bus cycles. The PCI4450 provides all required signals for PCI master/slave devices and may operate in either 5-V or 3.3-V PCI signaling environments by connecting the V

PCI bus lock (LOCK)

The bus locking protocol defined in the PCI Specification is not highly recommended, but is provided on the PCI4450 as an additional compatibility feature. The PCI LOCK terminal is multiplexed with GPIO2, and the terminal function defaults to a general-purpose input (GPI). The use of LOCK is only supported by PCI-to-CardBus bridges in the downstream direction (away from the processor).

PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is asserted, nonexclusive transactions may proceed to an address that is not currently locked. A grant to start a transaction on the PCI bus does not guarantee control of LOCK; control of LOCK is obtained under its own protocol. It is possible for different initiators to use the PCI bus while a single master retains ownership of LOCK. To avoid confusion with the PCI bus clock, the CardBus signal for this protocol is CBLOCK.

An agent may need to do an exclusive operation because a critical memory access to memory might be broken into several transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock is defined by PCI to be 16 bytes aligned. The lock protocol defined by PCI allows a resource lock without interfering with nonexclusive, real-time data transfer, such as video.

terminals to the desired signaling level.

CCP

The PCI bus arbiter may be designed to support only complete bus locks using the LOCK protocol. In this scenario the arbiter will not grant the bus to any other agent (other than the LOCK master) while LOCK is asserted. A complete bus lock may have a significant impact on the performance of the video. The arbiter that supports complete bus lock must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked operation is in progress.

The PCI4450 supports all LOCK protocol associated with PCI-to-PCI bridges, as also defined for PCI-to-CardBus bridges. This includes disabling write posting while a locked operation is in progress, which can solve a potential deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can occur if a CardBus target supports delayed transactions and blocks access as the target until it completes a delayed read. This target characteristic is prohibited by the 2.1 PCI Specification, and the issue is resolved by the PCI master using LOCK.

loading the subsystem identification (EEPROM interface)

The subsystem vendor ID register and subsystem ID register make up a double word of PCI configuration space located at offset 40h for functions 0 and 1. This doubleword register, used for system and option card (mobile dock) identification purposes, is required by some operating systems. Implementation of this unique identifier register is a PC ‘97 requirement.

The PCI4450 offers two mechanisms to load a read-only value into the subsystem registers. The first mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the subsystem registers is read-only, but the access mode may be made read/write by clearing the SUBSYSRW bit in the system control register (bit 5 of the system control register, offset 80h). Once this bit is cleared (0), the BIOS may write a subsystem identification value into the registers at offset 40h. The BIOS must set the SUBSYSRW bit such that the subsystem vendor ID register and subsystem ID register are limited to read-only access. This approach saves the added cost of implementing the serial EEPROM.

In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID register must be loaded with a unique identifier through a serial EEPROM interface. The PCI4450 loads the double-word of data from the serial EEPROM after a reset of the primary bus. The SUSPEND input gates the

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PRST and G_RST from the entire PCI4450 core, including the serial EEPROM state machine. Refer to

mode

for details on using SUSPEND. The PCI4450 provides a two-line serial bus interface to the serial

suspend

EEPROM. The system designer must implement a pulldown resistor on the PCI4450 LATCH terminal to indicate the serial

EEPROM mode. Only when this pulldown resistor is present will the PCI4450 attempt to load data through the serial EEPROM interface. The serial EEPROM interface is a two-pin interface with one data signal (SDA) and one clock signal (SCL). Figure 4 illustrates a typical PCI4450 application using the serial EEPROM interface.

Serial EEPROM

A0 A1A2SCL

SDA

SCL SDA

PCI4450

Latch

Figure 4. Serial EEPROM Application

As stated above, when the PCI4450 is reset by G_RST, the subsystem data is read automatically from the EEPROM. The PCI4450 masters the serial EEPROM bus and reads four bytes as described in Figure 5.

Slave Address

b6 b5 b4 b3 b2 b1 b0 0 A b7 b6 b5 b4 b3 b2 b1 b0 A S b6 b5 b4 b3 b2 b1 b0 1 A

R/W# Restart R/W#

Data Byte 0 M PData Byte 1 M Data Byte 2 M Data Byte 3 M

S/P – Start/Stop Condition A – Slave Acknowledgment M – Master Acknowledgment

Word Address Slave Address

Figure 5. EEPROM Interface Subsystem Data Collection

The EEPROM is addressed at slave address A0h (1010 0000b), as indicated in Figure 5, and the EEPROM word address auto-increments after each byte transfers according to the protocol. All hardware address bits for the EEPROM should be tied to the appropriate level to achieve this slave address. Thus, to provide the subsystem register with data AABBCCDDh the EEPROM should be programmed with address 0 = AAh, 1 = BBh, 2 = CCh, and 3 = DDh.

The serial EEPROM chip in the sample application circuit, Figure 4, assumes the 1010b high address nibble. The lower three address bits are terminal inputs to the chip, and the sample application shows these terminal inputs tied to GND.

The serial EEPROM interface signals require pullup resistors. The serial EEPROM protocol allows bidirectional transfers. Both the SCL and SDA signals are placed in a high-impedance state and pulled high when the bus is not active. A high-to-low transition of the SDA line defines a start condition (S). A low-to-high transition of SDA while SCL is high is defined as the stop condition (P). One bit is transferred during each clock pulse. The data

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on the SDA line must remain stable during the high period of the clock pulse, as changes in the data line at this time will be interpreted as a control signal. Data is valid and stable during the clock high period. Figure 6 illustrates this protocol.

SDA

SCL

Start

Condition

Stop

Condition

Change of

Data Allowed

Data Line Stable,

Data Valid

Figure 6. Serial EEPROM Start/Stop Conditions and BIt Transfers

Each address byte and data transfer is followed by an acknowledge bit, as indicated in Figure 5. When the PCI4450 transmits the addresses, it returns the SDA signal to the high state and places the line in a high-impedance state. The PCI4450 then generates an SCL clock cycle and expects the EEPROM to pull down the SDA line during the acknowledge pulse. This procedure is referred to as a slave acknowledge with the PCI4450 transmitter and the EEPROM receiver. Figure 7 illustrates general acknowledges.

During the data byte transfers from the serial EEPROM to the PCI4450, the EEPROM clocks the SCL signal. After the EEPROM transmits the data to the PCI4450, it returns the SDA signal to the high state and places the line in a high-impedance state. The EEPROM then generates an SCL clock cycle and expects the PCI4450 to pull down the SDA line during the acknowledge pulse. This procedure is referred to as a master acknowledge with the EEPROM transmitter and the PCI4450 receiver. Figure 7 illustrates general acknowledges.

SCL From

Master

SDA Output

By Transmitter

123 789

SDA Output By Receiver

Figure 7. Serial EEPROM Protocol – Acknowledge

EEPROM interface status information is communicated through the general status register located at PCI offset 85h. The EEDETECT bit in this register indicates whether or not the PCI4450 serial EEPROM circuitry detects the pulldown resistor on LATCH. An error condition, such as a missing acknowledge, results in the DAT AERR bit being set. The EEBUSY bit is set while the subsystem ID register is loading (serial EEPROM interface is busy).

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serial ROM implementation

A serial ROM interface exists in both the Open HCI function and the PC Card controller functions. The PCI4450 implementation adds a busy indication between the interfaces to allow the function 2 loading to follow the functions 0 and 1 load. All serial ROM addressing uses slave address 8’hA0. The functions 0 and 1 serial EEPROM state machine is modified to provide a busy indication to function 2 and to start loading registers at word address 8’h20 to allow for some serial ROM format flexibility in function 2.

Primarily , the serial ROM is used to preload the PCI4450 registers with data, and only write accessible bits in these registers may be preloaded. Figure 8 illustrates the PCI4450 serial ROM data format, which is an expanded version of both the OHCI-Lynx and PCI1450 serial ROM formats.

Slave Address 8’b10100000 Flag byte Word address 32 (20h)

SubSys byte 3 Word address 33

MaxLat / MinGnt

SubSys byte 0 SubSys byte 1 Word address 2 SubSys byte 0 Word address 36

SubSys byte 2 Word address 3 SysCtrl byte 0 Word address 37 SubSys byte 3

Link_Enh byte 0 W ord address 5 SysCtrl byte 2 Word address 39

MiniROM_Addr W ord address 6 SysCtrl byte 3 Word address 40

GUIDHi byte 0 GUIDHi byte 1 GUIDHi byte 2

GUIDHi byte 3 Word address 10 MF route byte 0 Word address 44 GUIDLo byte 0 W ord address 1 1 MF route byte 1 Word address 45 GUIDLo byte 1

GUIDLo byte 2 Word address 13 MF route byte 3 Word address 47 GUIDLo byte 3 Word address 14 Card Control Word address 48

CheckSum

Link_Enh byte 1 Word address 16 Diagnostic Word address 50

PCI misc byte 0 Word address 17 PMC byte 1 Word address 51 PCI misc byte 1

RSVD

Word address 0 Word address 1

Word address 4

Word address 7 Word address 8 Word address 9

Word address 12

Word address 15

Word address 18

SubSys byte 2 Word address 34 SubSys byte 1 Word address 35

SysCtrl byte 1 Word address 38

General control Word address 41

GP event enable Word address 42

GP output Word address 43

MF route byte 2 Word address 46

Device control Word address 49

ExCA ID and rev Word address 52

...

AVAIL

Figure 8. Serial ROM Data Format

The flag byte at word address 32 indicates to the PCI4450 whether or not the PC Card controller functions loads the data from word address range 33–52. A flag byte set to 8’hFF indicates to stop loading the serial ROM data for functions 0 and 1, but is independent of the function 2 1394 Open HCI controller load from word address range 0–18.

An additional change in the serial ROM behavior with respect to Open HCI GUIDROM register access is the MiniROM_Addr. The MiniROM_Addr field in the ROM data is loaded from byte location 6 (EEPROM word address 6) and indicates to function 2 where to begin accessing the serial ROM via the GUID ROM register. The GUIDROM.addrReset bit function changes slightly to reset serial ROM access to the byte location indicated by MiniROM_Addr. A MiniROM_Addr value of zero provides identical operation as the OHCI-Lynx.

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PC Card applications overview

This section describes the PC Card interfaces of the PCI4450. A discussion on PC Card recognition details the card interrogation procedure. This section discusses the card powering procedure, including the protocol of the P2C power switch interface. The internal ZV buffering provided by the PCI4450 and programming model is detailed in this section. Also, standard PC Card register models are described, as well as a brief discussion of the PC Card software protocol layers.

PC Card insertion/removal and recognition

The 1995 PC Card Standard addresses the card detection and recognition process through an interrogation procedure that the socket must initiate upon card insertion into a cold, unpowered socket. Through this interrogation, card voltage requirements and interface (16-bit vs. CardBus) are determined.

The scheme uses the CD1, CD2, VS1, and VS2 signals (CCD1, CCD2, CVS1, CVS2 for CardBus). A PC Card designer connects these four pins in a certain configuration depending on the type of card and the supply voltage. The encoding scheme for this, defined in the 1997 PC Card Standard, is shown in Table 18.

Table 18. PC Card – Card Detect and Voltage Sense Connections

CD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1 Key Interface Voltage

Ground Ground Open Open 5 V 16-bit PC Card 5 V Ground Ground Open Ground 5 V 16-bit PC Card 5 V and 3.3 V

Ground Ground Ground Ground 5 V 16-bit PC Card Ground Ground Open Ground LV 16-bit PC Card 3.3 V

Ground Connect to CVS1 Open Connect to CCD1 LV CardBus PC Card 3.3 V Ground Ground Ground Ground LV 16-bit PC Card 3.3 V and X.X V

Connect to CVS2 Ground Connect to CCD2 Ground LV CardBus PC Card 3.3 V and X.X V Connect to CVS1 Ground Ground Connect to CCD2 LV CardBus PC Card

Ground Ground Ground Open LV 16-bit PC Card Y.Y V

Connect to CVS2 Ground Connect to CCD2 Open LV CardBus PC Card Y .Y V

Ground Connect to CVS2 Connect to CCD1 Open LV CardBus PC Card X.X V and Y.Y V

Connect to CVS1 Ground Open Connect to CCD2 LV CardBus PC Card Y.Y V

Ground Connect to CVS1 Ground Connect to CCD1 Reserved Ground Connect to CVS2 Connect to CCD1 Ground Reserved

5 V , 3.3 V, and

X.X V

3.3 V, X.X V , and Y.Y V

P2C power switch interface (TPS2202A/2206)

A power switch with a PCMCIA-to-peripheral control (P2C) interface is required for the PC Card powering interface. The TI TPS2206 (or TPS2202A) Dual-Slot PC Card Power-Interface Switch provides the P2C interface to the CLOCK, DA TA, and LA TCH terminals of the PCI4450. Figure 9 shows the terminal assignments of the TPS2206. Figure 10 illustrates a typical application where the PCI4450 represents the PCMCIA controller.

There are two ways to provide a clock source to the power switch interface. The first method is to provide an external clock source such as a 32 kHz real time clock to the CLOCK terminal. The second method is to use the internal ring oscillator. If the internal ring oscillator is used, then the PCI4450 provides its own clock source for the PC Card interrogation logic and the power switch interface. The mode of operation is determined by the setting of bit 27 of the system control register (PCI offset 80h). This bit is encoded as follows:

0 = CLOCK terminal (terminal U12) is an input (default). 1 = CLOCK terminal is an output that utilizes the internal oscillator.

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A 43 kW pulldown resistor should be tied to the CLOCK pin.

PCI4450 GFN/GJG

PC Card and OHCI Controller

SCPS046 – JANUAR Y 1999

Power Supply

12 V

5 V

3.3 V

5V 5V

DATA

CLOCK

LATCH

RESET

12V

AVPP AVCC AVCC AVCC

GND

RESET

3.3V

NC – No internal connection

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

5V NC NC NC NC NC 12V BVPP BVCC BVCC BVCC NC OC

3.3V

Figure 9. TPS2206 Terminal Assignments

TPS2206

12 V 5 V

3.3 V

AVPP

AVCC AVCC AVCC

PC Card A

PP1

PP2

Supervisor

PCI4450

RESET

BVPP

BVCC

Serial I/F

PC Card Interface (68 pins/socket)

BVCC BVCC

PC Card B

PP1

PP2

Figure 10. TPS2206 Typical Application

zoomed video support

The zoomed video (ZV) port on the PCI4450 provides an internally buffered 16-bit ZV PC Card data path. This internal routing is programmed through the multimedia control register. Figure 10 summarizes the zoomed video subsystem implemented in the PCI4450, and details the bit functions found in the multimedia control register.

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An output port (PORTSEL) is always selected. The PCI4450 defaults to socket 0 (see the multimedia control register). When ZVOUTEN is enabled, the zoomed video output terminals are enabled and allow the PCI4450 to route the zoomed video data. However, no data is transmitted unless either ZVEN0 or ZVEN1 is enabled in the multimedia control register. If the PORTSEL maps to a card port that is disabled (ZVEN =0 or ZVEN1 = 0), then the zoomed video port is driven low (i.e., no data is transmitted).

Zoomed Video Subsystem

Card Output

Enable Logic

ZVEN0

ZVOUTEN

PC Card

Socket 0

PC Card

Socket 1

Card Output

Enable Logic

†

ZVST A T must be enabled through the GPIO Control Register .

PC Card

I/F

PC Card

I/F

ZVEN1

PORTSEL

ZVST AT†

19 Video Signals

4 Audio Signals

VGA

Audio

Codec

Figure 11. Zoomed Video Subsystem

zoomed video auto detect

Zoomed video auto detect, when enabled, allows the PCI4450 to automatically detect zoomed video data by sensing the pixel clock from each socket and/or from a third zoomed video source that may exist on the motherboard. The PCI4450 automatically switches the internal zoomed video MUX to route the zoomed video stream to the PCI4450’s zoomed video output port. This eliminates the need for software to switch the internal MUX using the multimedia control register (PCI offset 84h, bits 6 and 7).

The PCI4450 can be programmed to switch a third zoomed video source by programming MFUNC2 or MFUNC3 as a zoomed video pixel clock sense pin and connecting this pin to the pixel clock of the third zoomed video source. ZVSTAT may then be programmed onto MFUNC4, MFUNC1, or MFUNC0 and this signal may switch the zoomed video buffers from the third zoomed video source. To account for the possibility of several zoomed video sources being enabled at the same time, a programmable priority scheme may be enabled.

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