TEXAS INSTRUMENTS PCI1620 Technical data
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查询PCI1620供应商
Data Manua
August 2003 PCIBus Solutions
SCPS064C
IMPORTANT NOTICE
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Contents
1 Introduction 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Description 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Features 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Related Documents 1−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Trademarks 1−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Terms and Definitions 1−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 Ordering Information 1−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Terminal Descriptions 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Terminal Assignments for PCI1620 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Feature/Protocol Descriptions 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Summary of UltraMedia Cards 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1 SmartMedia 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 MultiMediaCard (MMC) 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.3 Secure Digital (SD) 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.4 Memory Stick 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.5 Smart Card 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 I/O Characteristics 3−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Clamping Voltages 3−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Peripheral Component Interconnect (PCI) Interface 3−3. . . . . . . . . . . . . .
3.4.1 PCI Bus Lock (LOCK
3.4.2 Serial EEPROM I2C Bus 3−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.3 PCI1620 EEPROM Map 3−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.4 Loading the Subsystem Identification (EEPROM Interface) 3−6
3.5 PC Card Applications Overview 3−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1 Card Detection in an UltraMedia System 3−6. . . . . . . . . . . . . . .
3.5.2 Query Terminals 3−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
3.5.3 P
3.5.4 Zoomed-Video Support 3−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.5 Standardized Zoomed-Video Register Model 3−11. . . . . . . . . . .
3.5.6 Integrated Pullup Resistors 3−11. . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.7 SPKROUT Usage 3−12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.8 LED Socket Activity Indicators 3−13. . . . . . . . . . . . . . . . . . . . . . . .
3.5.9 CardBus Socket Registers 3−13. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.10 PCI Firmware Loading Function Programming Model 3−14. . . .
3.6 Programmable Interrupt Subsystem 3−16. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1 PC Card Functional and Card Status-Change Interrupts 3−17.
3.6.2 Interrupt Masks and Flags 3−18. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.3 Using Parallel IRQ Interrupts 3−19. . . . . . . . . . . . . . . . . . . . . . . . .
3.6.4 Using Parallel PCI Interrupts 3−19. . . . . . . . . . . . . . . . . . . . . . . . .
C Power Switch Interface 3−8. . . . . . . . . . . . . . . . . . . . . . . . . .
) 3−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iii
3.6.5 Using Serialized IRQSER Interrupts 3−20. . . . . . . . . . . . . . . . . . .
3.6.6 SMI Support in the PCI1620 3−20. . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 Power Management Overview 3−19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.1 Integrated Low-Dropout Voltage Regulator (LDO-VR) 3−20. . . .
3.7.2 Clock Run Protocol 3−21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.3 CardBus PC Card Power Management 3−21. . . . . . . . . . . . . . . .
3.7.4 16-Bit PC Card Power Management 3−21. . . . . . . . . . . . . . . . . . .
3.7.5 Suspend Mode 3−21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.6 Requirements for Suspend Mode 3−22. . . . . . . . . . . . . . . . . . . . .
3.7.7 Ring Indicate 3−22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.8 PCI Power Management 3−23. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.9 CardBus Bridge Power Management 3−24. . . . . . . . . . . . . . . . . .
3.7.10 ACPI Support 3−25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.11 Master List of PME
Context Bits and
Global Reset-Only Bits 3−26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 PC Card Controller Programming Model 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 PCI Configuration Registers (Functions 0 and 1) 4−1. . . . . . . . . . . . . . . . .
4.2 Vendor ID Register 4−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Device ID Register 4−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Command Register 4−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Status Register 4−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 Revision ID Register 4−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 Class Code Register 4−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8 Cache Line Size Register 4−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9 Latency Timer Register 4−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10 Header Type Register 4−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.11 BIST Register 4−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12 CardBus Socket Registers/ExCA Base Address Register 4−7. . . . . . . . .
4.13 Capability Pointer Register 4−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14 Secondary Status Register 4−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.15 PCI Bus Number Register 4−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.16 CardBus Bus Number Register 4−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.17 Subordinate Bus Number Register 4−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.18 CardBus Latency Timer Register 4−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.19 CardBus Memory Base Registers 0, 1 4−10. . . . . . . . . . . . . . . . . . . . . . . . . .
4.20 CardBus Memory Limit Registers 0, 1 4−11. . . . . . . . . . . . . . . . . . . . . . . . . .
4.21 CardBus I/O Base Registers 0, 1 4−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.22 CardBus I/O Limit Registers 0, 1 4−12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.23 Interrupt Line Register 4−12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.24 Interrupt Pin Register 4−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.25 Bridge Control Register 4−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.26 Subsystem Vendor ID Register 4−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.27 Subsystem ID Register 4−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.28 PC Card 16-Bit I/F Legacy-Mode Base-Address Register 4−16. . . . . . . . .
iv
4.29 Subsystem Vendor ID Register (Firmware Loader Function) 4−16. . . . . . .
4.30 Subsystem ID Register (Firmware Loader Function) 4−17. . . . . . . . . . . . .
4.31 System Control Register 4−18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.32 MC_CD_Debounce Register 4−20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.33 General Control Register 4−21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.34 General-Purpose Event Status Register 4−22. . . . . . . . . . . . . . . . . . . . . . . .
4.35 General-Purpose Event Enable Register 4−23. . . . . . . . . . . . . . . . . . . . . . .
4.36 General-Purpose Input Register 4−23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.37 General-Purpose Output Register 4−24. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.38 Multifunction Routing Status Register 4−25. . . . . . . . . . . . . . . . . . . . . . . . . .
4.39 Retry Status Register 4−27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.40 Card Control Register 4−28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.41 Device Control Register 4−29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.42 Diagnostic Register 4−30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.43 Capability ID Register 4−31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.44 Next Item Pointer Register 4−31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.45 Power Management Capabilities Register 4−32. . . . . . . . . . . . . . . . . . . . . .
4.46 Power Management Control/Status Register 4−33. . . . . . . . . . . . . . . . . . . .
4.47 Power Management Control/Status Bridge Support
Extensions Register 4−34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.48 Power-Management Data Register 4−34. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.49 Serial Bus Data Register 4−35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.50 Serial Bus Index Register 4−35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.51 Serial Bus Slave Address Register 4−36. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.52 Serial Bus Control/Status Register 4−37. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 ExCA Compatibility Registers (Functions 0 and 1) 5−1. . . . . . . . . . . . . . . . . .
5.1 ExCA Identification and Revision Register 5−5. . . . . . . . . . . . . . . . . . . . . .
5.2 ExCA Interface Status Register 5−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 ExCA Power Control Register 5−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 ExCA Interrupt and General Control Register 5−9. . . . . . . . . . . . . . . . . . .
5.5 ExCA Card Status-Change Register 5−10. . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6 ExCA Card Status-Change Interrupt Configuration Register 5−11. . . . . . .
5.7 ExCA Address Window Enable Register 5−12. . . . . . . . . . . . . . . . . . . . . . . .
5.8 ExCA I/O Window Control Register 5−13. . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers 5−14. . . .
5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers 5−14. . . .
5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers 5−15. . . . .
5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers 5−15. . . .
5.13 ExCA Memory Windows 0−4 Start-Address Low-Byte Registers 5−16. . .
5.14 ExCA Memory Windows 0−4 Start-Address High-Byte Registers 5−17. . .
5.15 ExCA Memory Windows 0−4 End-Address Low-Byte Registers 5−18. . . .
5.16 ExCA Memory Windows 0−4 End-Address High-Byte Registers 5−19. . .
5.17 ExCA Memory Windows 0−4 Offset-Address Low-Byte Registers 5−20. .
5.18 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers 5−21.
v
5.19 ExCA Card Detect and General Control Register 5−22. . . . . . . . . . . . . . . .
5.20 ExCA Global Control Register 5−23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers 5−24. . .
5.22 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers 5−24. . .
5.23 ExCA Memory Windows 0−4 Page Registers 5−25. . . . . . . . . . . . . . . . . . .
6 CardBus Socket Registers (Functions 0 and 1) 6−1. . . . . . . . . . . . . . . . . . . . . .
6.1 Socket Event Register 6−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Socket Mask Register 6−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Socket Present State Register 6−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4 Socket Force Event Register 6−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5 Socket Control Register 6−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6 Socket Power Management Register 6−8. . . . . . . . . . . . . . . . . . . . . . . . . . .
7 PCI Firmware Loading Function Programming Model (Function 2) 7−1. . .
7.1 Vendor ID Register 7−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Device ID Register 7−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 Command Register 7−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4 Status Register 7−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5 Class Code and Revision ID Register 7−4. . . . . . . . . . . . . . . . . . . . . . . . . .
7.6 Cache Line Size Register 7−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7 Latency Timer Register 7−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8 Header Type Register 7−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.9 BIST Register 7−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.10 Base Address Register 7−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.11 Subsystem Vendor ID Register 7−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.12 Subsystem ID Register 7−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.13 Capabilities Pointer Register 7−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.14 Interrupt Line Register 7−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.15 Interrupt Pin Register 7−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.16 Min Grant Register 7−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.17 Max Latency Register 7−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.18 Capability ID Register 7−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.19 Next-Item Pointer Register 7−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.20 Power-Management Capabilities Register 7−9. . . . . . . . . . . . . . . . . . . . . .
7.21 Power-Management Control/Status Register 7−10. . . . . . . . . . . . . . . . . . . .
7.22 Power-Management Bridge Support Extension Register 7−10. . . . . . . . . .
7.23 Power-Management Data Register 7−11. . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 Electrical Characteristics 8−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1 Absolute Maximum Ratings Over Operating Temperature Ranges 8−1.
8.2 Recommended Operating Conditions 8−2. . . . . . . . . . . . . . . . . . . . . . . . . .
8.3 Electrical Characteristics Over Recommended
Operating Conditions 8−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4 PCI Clock/Reset Timing Requirements Over Recommended Ranges
of Supply Voltage and Operating Free-Air Temperature 8−3. . . . . . . . . . .
8.5 PCI Timing Requirements Over Recommended Ranges of Supply
Voltage and Operating Free-Air Temperature 8−4. . . . . . . . . . . . . . . . . . . .
vi
8.6 Switching Characteristics for PHY-Link Interface 8−4. . . . . . . . . . . . . . . . .
8.7 Parameter Measurement Information 8−5. . . . . . . . . . . . . . . . . . . . . . . . . .
8.8 PCI Bus Parameter Measurement Information 8−6. . . . . . . . . . . . . . . . . . .
8.9 PC Card Cycle Timing 8−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.10 Timing Requirements Over Recommended Ranges of Supply
Voltage and Operating Free-Air Temperature, Memory Cycles 8−8. . . .
8.11 Timing Requirements Over Recommended Ranges of Supply
Voltage and Operating Free-Air Temperature, I/O Cycles 8−8. . . . . . . . .
8.12 Switching Characteristics Over Recommended Ranges of Supply
Voltage and Operating Free-Air Temperature, Miscellaneous 8−9. . . . . .
8.13 PC Card Parameter Measurement Information 8−9. . . . . . . . . . . . . . . . . .
9 Mechanical Data 9−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vii
List of Illustrations
Figure Title Page
2−1 PCI1620 GHK Terminal Diagram 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 PCI1620 PDV Terminal Diagram 2−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1 PCI1620 System Block Diagram 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2 3-State Bidirectional Buffer 3−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3 Serial EEPROM Application 3−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4 Example SmartMedia Query Terminal Configuration 3−8. . . . . . . . . . . . . . . . . . .
3−5 TPS222X Typical Application 3−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6 Zoomed-Video Implementation Using PCI1620 3−10. . . . . . . . . . . . . . . . . . . . . . .
3−7 Zoomed-Video Switching Application 3−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−8 SPKROUT Connection to Speaker Driver 3−13. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−9 Two Sample LED Circuits 3−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−10 IRQ Implementation 3−19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−11 Signal Diagram of Suspend Function 3−22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−12 RI_OUT
3−13 Block Diagram of a Status/Enable Cell 3−25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−1 ExCA Register Access Through I/O 5−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−2 ExCA Register Access Through Memory 5−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−1 Accessing CardBus Socket Registers Through PCI Memory 6−1. . . . . . . . . . . .
8−1 Load Circuit and Voltage Waveforms 8−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−2 PCLK Timing Waveform 8−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−3 RSTIN
8−4 Shared Signals Timing Waveforms 8−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−5 PC Card Memory Cycle 8−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−6 PC Card I/O Cycle 8−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−7 Miscellaneous PC Card Delay Times 8−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Diagram 3−23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Waveforms 8−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
viii
List of Tables
Table Title Page
1−1 Terms and Definitions 1−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−1 Signal Names by PDV Terminal Number 2−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 Signal Names by GHK Terminal Number 2−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−3 CardBus PC Card Signal Names Sorted Alphabetically 2−8. . . . . . . . . . . . . . . .
2−4 16-Bit PC Card Signal Names Sorted Alphabetically 2−10. . . . . . . . . . . . . . . . . . .
2−5 Power Supply Terminals 2−12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6 PC Card Power Switch Terminals 2−12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−7 PCI System Terminals 2−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−8 PCI Address and Data Terminals 2−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−9 PCI Interface Control Terminals 2−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−10 Multifunction and Miscellaneous Terminals 2−16. . . . . . . . . . . . . . . . . . . . . . . . . .
2−11 CardBus PC Card Interface System Terminals (Slots A and B) 2−17. . . . . . . . .
2−12 CardBus PC Card Address and Data Terminals (Slots A and B) 2−18. . . . . . . .
2−13 CardBus PC Card Terminals (Slots A and B) 2−19. . . . . . . . . . . . . . . . . . . . . . . .
2−14 16-Bit PC Card Address and Data Terminals (Slots A and B) 2−20. . . . . . . . . .
2−15 16-Bit PC Card Interface Control Terminals (Slots A and B) 2−21. . . . . . . . . . . .
2−16 UltraMedia Mapping to the PCMCIA 68-Terminal Connector 2−23. . . . . . . . . . .
2−17 UltraMedia Terminals (Slots A & B) 2−25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1 Serial EEPROM Map 3−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2 PC Card—Card Detect and Voltage Sense Connections 3−7. . . . . . . . . . . . . . .
3−3 Query Terminal Definition 3−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4 Query Terminals − Voltage 3−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5 Query Terminals − Media Interface Implementation 3−8. . . . . . . . . . . . . . . . . . . .
3−6 Functionality of the ZV Output Signals 3−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−7 Terminals With Integrated Pullup Resistors 3−12. . . . . . . . . . . . . . . . . . . . . . . . . . .
3−8 CardBus Socket Registers 3−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−9 Firmware Loader I/O Register Map 3−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−10 Firmware Loader Control Register Description 3−16. . . . . . . . . . . . . . . . . . . . . . .
3−11 Interrupt Mask and Flag Registers 3−17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−12 PC Card Interrupt Events and Description 3−18. . . . . . . . . . . . . . . . . . . . . . . . . . .
3−13 Interrupt Pin Register Cross Reference 3−20. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−14 SMI Control 3−20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−15 Requirements for Internal/External 2.5-V Core Power Supply 3−20. . . . . . . . . .
3−16 Power Management Registers 3−24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1 Functions 0 and 1 PCI Configuration Register Map 4−1. . . . . . . . . . . . . . . . . . . .
4−2 Command Register Description 4−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−3 Status Register Description 4−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ix
4−4 Secondary Status Register Description 4−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−5 Interrupt Pin Register Cross Reference 4−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−6 Bridge Control Register Description 4−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−7 System Control Register Description 4−18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−8 General Control Register Description 4−21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−9 General-Purpose Event Status Register Description 4−22. . . . . . . . . . . . . . . . . . .
4−10 General-Purpose Event Enable Register Description 4−23. . . . . . . . . . . . . . . . .
4−11 General-Purpose Input Register Description 4−23. . . . . . . . . . . . . . . . . . . . . . . . .
4−12 General-Purpose Output Register Description 4−24. . . . . . . . . . . . . . . . . . . . . . .
4−13 Multifunction Routing Status Register Description 4−25. . . . . . . . . . . . . . . . . . . .
4−14 Retry Status Register Description 4−27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−15 Card Control Register Description 4−28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−16 Device Control Register Description 4−29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−17 Diagnostic Register Description 4−30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−18 Power Management Capabilities Register Description 4−32. . . . . . . . . . . . . . . .
4−19 Power Management Control/Status Register Description 4−33. . . . . . . . . . . . . .
4−20 Power Management Control/Status Bridge Support Extensions
Register Description 4−34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−21 Serial Bus Data Register Description 4−35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−22 Serial Bus Index Register Description 4−35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−23 Serial Bus Slave Address Register Description 4−36. . . . . . . . . . . . . . . . . . . . . .
4−24 Serial Bus Control/Status Register Description 4−37. . . . . . . . . . . . . . . . . . . . . . .
5−1 ExCA Registers and Offsets 5−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−2 ExCA Identification and Revision Register Description 5−5. . . . . . . . . . . . . . . . .
5−3 ExCA Interface Status Register Description 5−6. . . . . . . . . . . . . . . . . . . . . . . . . .
5−4 ExCA Power Control Register Description—82365SL Support 5−7. . . . . . . . . .
5−5 ExCA Power Control Register Description—82365SL-DF Support 5−8. . . . . . .
5−6 ExCA Interrupt and General Control Register Description 5−9. . . . . . . . . . . . . .
5−7 ExCA Card Status-Change Register Description 5−10. . . . . . . . . . . . . . . . . . . . . .
5−8 ExCA Card Status-Change Interrupt Configuration
Register Description 5−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−9 ExCA Address Window Enable Register Description 5−12. . . . . . . . . . . . . . . . . . .
5−10 ExCA I/O Window Control Register Description 5−13. . . . . . . . . . . . . . . . . . . . . .
5−11 ExCA Memory Windows 0−4 Start-Address High-Byte
Registers Description 5−17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−12 ExCA Memory Windows 0−4 End-Address High-Byte
Registers Description 5−19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−13 ExCA Memory Windows 0−4 Offset-Address High-Byte
Registers Description 5−21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−14 ExCA Card Detect and General Control Register Description 5−22. . . . . . . . . .
5−15 ExCA Global Control Register Description 5−23. . . . . . . . . . . . . . . . . . . . . . . . . .
6−1 CardBus Socket Registers 6−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−2 Socket Event Register Description 6−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−3 Socket Mask Register Description 6−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−4 Socket Present State Register Description 6−4. . . . . . . . . . . . . . . . . . . . . . . . . . .
x
6−5 Socket Force Event Register Description 6−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−6 Socket Control Register Description 6−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−7 Socket Power Management Register Description 6−8. . . . . . . . . . . . . . . . . . . . .
7−1 Function 2 Configuration Register Map 7−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−2 Command Register Description 7−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−3 Status Register Description 7−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−4 Class Code and Revision ID Register Description 7−4. . . . . . . . . . . . . . . . . . . . .
7−5 Base Address Register Description 7−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−6 Power-Management Capabilities Register Description 7−9. . . . . . . . . . . . . . . . .
7−7 Power-Management Control/Status Register Description 7−10. . . . . . . . . . . . . . .
8−1 PC Card Address Setup Time, t
8−2 PC Card Command Active Time, t
8−3 PC Card Command Active Time, t
8−4 PC Card Address Hold Time, t
, 8-Bit and 16-Bit PCI Cycles 8−7. . . . . . .
su(A)
, 8-Bit PCI Cycles 8−7. . . . . . . . . . . . . . . .
c(A)
, 16-Bit PCI Cycles 8−7. . . . . . . . . . . . . .
c(A)
, 8-Bit and 16-Bit PCI Cycles 8−7. . . . . . . . .
h(A)
xi
xii
1 Introduction
1.1 Description
The Texas Instruments PCI1620 is an integrated dual-socket PC Card controller, FlashMedia controller
(SmartMedia Card, MultiMediaCard, SD Card, Memory Stick card) and Smart Card controller.
The PCI1620 UltraMedia controller is a three-function PCI device compliant with PCI Local Bus Specification 2.2.
Functions 0 and 1 provide two independent PC Card socket controllers compliant with PC Card Standard 8.0.
Function 2 is the interface to load the PCI1620 program RAM with firmware. The PCI1620 provides features that make
it ideal for bridging between the PCI bus and PC Cards, and supports any combination of 16-bit, CardBus, and
UltraMedia PC Cards in the two sockets, powered at 5 V, 3.3 V, or 1.8 V as required.
UltraMedia cards that comply with the latest PCMCIA standard provide for very low-cost flash media and Smart Card
adapters, because the control logic is integrated into the PCI1620. The PCI1620 supports a passive 4-in-1 adapter,
as well as active PC Card-style Flash media and Smart Card adapters.
No PCMCIA card or socket service software changes are required to move systems from an existing CardBus socket
controller to the PCI1620. The FlashMedia UltraMedia applications use existing host ATA drivers, and Texas
Instruments provides a qualified Smart Card driver for UltraMedia-based Smart Card adapters. The PCI1620 is
register compatible with the Intel 82365SL–DF ExCA controller and implements the host interface defined in the PC
Card Standard. The PCI1620 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit
PCI cycles for maximum performance. Independent buffering and the pipeline architecture provide a high
performance level with sustained bursting. The PCI1620 can be programmed to accept posted writes to improve bus
utilization.
Various implementation-specific functions and general-purpose inputs and outputs are provided through seven
multifunction terminals. These terminals present a system with options for PCI LOCK, serial and parallel interrupts,
PC Card activity indicator LEDs, and other platform-specific signals. ACPI-compliant general-purpose events may
be programmed and controlled through the multifunction terminals, and an ACPI-compliant programming interface
is included for the general-purpose inputs and outputs.
The PCI1620 is compliant with PCI Bus Power Management Interface Specification 1.1, and provides several
low-power modes, which enable the host power system to further reduce power consumption. The PCI1620 also has
a three-terminal serial interface compatible with both the TI TPS2226 and TPS2228 power switches.
1.2 Features
The PCI1620 supports the following features:
• PC Card Standard 8.0 compliant
• PCI Bus Power Management Interface Specification 1.1 compliant
• Advanced Configuration and Power Interface Specification 1.0 compliant
• PCI Local Bus Specification Revision 2.2 compliant
• PC 98/99 compliant
• Has integrated voltage regulator to use 1.8-V core voltage
• Compliant with the PCI Bus Interface Specification for PCI-to-CardBus Bridges
• Advanced filtering on card detect lines provides 90 microseconds of noise immunity.
• Programmable D3 status terminal
• 1.8-V core logic and 3.3-V I/O cells with internal voltage regulator to generate 1.8-V core V
• Universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
• Mix-and-match 5-V/3.3-V 16-bit PC Cards and 3.3-V CardBus cards
• Supports two PC Card or CardBus slots with hot insertion and removal
CC
1−1
• Uses serial interface to TI TPS2226 and TI TPS2228 dual power switch
• Supports 132-MBps burst transfers to maximize data throughput on both the PCI bus and the CardBus bus
• Supports serialized IRQ with PCI interrupts
• 13 programmable multifunction terminals
• Interrupt modes supported: serial ISA/serial PCI, serial ISA/parallel PCI, parallel PCI only
• Serial EEPROM interface for loading subsystem ID and subsystem vendor ID
• Supports external zoomed video
• Dedicated terminal for PCI CLKRUN
• Four general-purpose event registers
• Multifunction PCI device with separate configuration space for each socket
• Five PCI memory windows and two I/O windows available to each 16-bit PC Card socket
• Two I/O windows and two memory windows available to each CardBus socket
• ExCA-compatible registers are mapped in memory or I/O space
• Intel 82365SL–DF register compatible
• Supports ring indicate, suspend, and PCI clock run
• Advanced submicron, low-power CMOS technology
• Provides VGA/palette memory and I/O, and subtractive decoding options
• LED activity terminals
• Supports PCI bus lock (LOCK)
1.3 Related Documents
• PC Card Controller Device Class Power Management Reference Specification
• PC Card Standard release 7
• PCI Local Bus Specification revision 2.2
• PCI to PCMCIA CardBus Bridge Register Description (Yenta), revision 2.1
• Texas Instruments TPS2226 and TPS2228 product data sheets
• SmartMedia Specifications, Issued 5/19/99
• MultiMediaCard Specification Version 2.2
• Multimedia Host Specification Version 3.7, Sandisk
• SD Memory Card Specifications, SD Group, 2000.
• Memory Stick Format Specification, Sony
• Memory Stick I/F Specification − Helen/Helious, TI Wireless Japan, Feb. 2000.
• ISO Standards for Identification Cards ISO/IEC 7816
• 3Soft M8052 MegaMacro Design Specification
• ANSI AT Attachment (ATA) Specification for Disk Drives x3.221−1994
1.4 Trademarks
Intel is a trademark of Intel Corporation.
MegaMacro is a trademark of MEJ Electronics Ltd., UK.
Memory Stick is a trademark of Sony Kabushiki Kaisha TA Sony Corporation, Japan.
MicroStar BGA and UltraMedia are trademarks of Texas Instruments.
SmartMedia is a trademark of Kabushiki Kaisha Toshiba DBA Toshiba Corporation, Japan.
SmartSocket is a trademark of ControlNet, Incorporated.
Other trademarks are the property of their respective owners.
1−2
1.5 Terms and Definitions
Terms and definitions used in this document are given in Table 1−1.
Table 1−1. Terms and Definitions
TERM DEFINITIONS
ATA AT (advanced technology, as in PC A T) attachment interface
ATA driver An existing host software component that loads when a SmartMedia adapter and card is inserted into a PC Card
CIS Card information structure. Tuple list defined by the PC Card standard to communicate card information to the host
CSR Control and status register
Flash Media SmartMedia, Memory Stick, or SD Flash operating in an ATA compatible mode
Function 2 firmware loader A hardware element of the PCI1620 that provides a software interface to the TI firmware loader driver to load the
ISO/IEC 7816 The Smart Card standard
Magic Gate A security technology for Memory Stick promoted and licensed by Sony
Memory Stick A small-form-factor flash interface that is defined, promoted, and licensed by Sony
MMC MultiMediaCard. Specified by the MMC Association, and scope is encompassed by the SD Flash specification.
OHCI Open host controller interface
PCMCIA Personal Computer Memory Card International Association. Standards body that governs the PC Card standards
RSVD Reserved for future use
SD Flash Secure Digital Flash. Standard governed by the SD Association
Smart Card The name applied to ID cards containing integrated circuits, as defined by ISO/IEC 7816-1
SmartMedia Also known as SSFDC, defined by Toshiba and governed by SSFDC Forum
SPI Serial peripheral interface, a general-purpose synchronous serial interface. For more information, see the
SSFDC Solid State Floppy Disk Card. The SSFDC Forum specifies SmartMedia
TI firmware loader driver A qualified software component provided by Texas Instruments that loads the firmware into the PCI1620 on power
TI Smart Card driver A qualified software component provided by Texas Instruments that loads when an UltraMedia-based Smart Card
TI SmartSocket driver A qualified software component provided by T exas Instruments that loads when an unsupported UltraMedia-based
UART Universal asynchronous receiver and transmitter
UltraMedia De facto industry standard promoted by Texas Instruments that integrates CardBus, Smart Card, Memory Stick,
socket. This driver is logically attached to a predefined CIS provided by the PCI1620 when the adapter and media
are both inserted.
computer
program RAM with firmware
Multimedia Card System Specification, version 2.2.
up and initialization.
adapter is inserted into a PC Card slot. This driver is logically attached to a CIS provided by the PCI1620 when the
adapter is inserted.
card is inserted into a PC Card slot. This driver serves to give the user a message that the inserted card is not
supported.
MultiMediaCard/Secure Digital and SmartMedia functionality into one controller.
1.6 Ordering Information
ORDERING NUMBER NAME VOLTAGE PACKAGE
PCI1620 PC Card, Cardbus card, Flash Media and
Smart Card controller
3.3-V, 5-V tolerant I/Os 209-terminal GHK, 208-terminal PDV
packages
1−3
1−4
2 Terminal Descriptions
BOTTOM VIEW
The PCI1620 is available in a 209-terminal MicroStar BGA package (GHK), and in a 208-terminal plastic quad
flatpack package (PDV).
2.1 Terminal Assignments for PCI1620
Figure 2−1 shows the terminal layout for the 209-terminal MicroStar BGA package (GHK). Figure 2−2 shows the
terminal assignments for the 208-terminal quad flatpack (PDV) package.
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
2
75
9
6
4
810
12
13141511
16
18
1917
Figure 2−1. PCI1620 GHK Terminal Diagram
2−1
I)
M
PDV LOW-PROFILE QUAD FLAT PACKAGE (LQFP)
TOP VIEW
/RI)
)
//A_CD2
156 MFUNC0
155 DATA
154 CLOCK
153 LATCH
152 SPKROUT
151 A_CAD31//A_D10
150 A_RSVD//A_D2
149 A_CAD30//A_D9
148 A_CAD29//A_D1
147 GND
146 A_CAD28//A_D8
145 A_CAD27//A_D0
MFUNC1 157
SUSPEND
MFUNC2 159
MFUNC3 160
MFUNC4 161
MFUNC5 162
FUNC6/CLKRUN 163
RI_OUT
FRAME
DEVSEL
158
C/BE3
164
/PME 165
GND 166
AD25 167
168
PRST
169
GNT
170
REQ
AD31 171
AD30 172
AD11 173
174
V
CC
AD29 175
AD28 176
177
GRST
AD27 178
AD26 179
180
V
CCP
AD24 181
PCLK 182
IDSEL 183
AD23 184
GND 185
AD22 186
AD21 187
AD20 188
AD19 189
AD18 190
AD17 191
AD16 192
193
C/BE2
194
195
V
CC
196
IRDY
197
TRDY
198
GND 199
200
STOP
201
PERR
202
SERR
PAR 203
C/BE1 204
AD15 205
AD14 206
AD13 207
AD12 208
4
144 A_CCD2
//A_WAIT
139 A_CSERR
143 VCC142 A_CCLKRUN//A_WP(IOIS16)
141 A_CSTSCHG//A_BVD1(STSCHG
138 A_CINT//A_READY(IREQ)
136 A_CAD26//A_A0
140 A_CAUDIO//A_BVD2(SPKR
137 A_CVS1//A_VS1
14
135 A_CAD25//A_A1
//A_INPACK
134 A_CAD24//A_A2
133 VCC132 A_CC/BE3//A_REG
131 A_CAD23//A_A3
130 A_CREQ
PCI1620
//A_RESET
A_CAD22//A_A4
125 A_CAD20//A_A6
129
128 VR_OUT
127 A_CAD21//A_A5
126 A_CRST
30
31
//A_A12
124 A_CVS2//A_VS2
123 A_CAD19//A_A25
122 A_CAD18//A_A7
121 A_CAD17//A_A24
120 A_CC/BE2
33
34
A_CFRAME//A_A23
119
118 VCC117 A_CIRDY//A_A15
39
//A_A22
CCA
116 A_CTRDY
113 A_CDEVSEL//A_A21
115 A_CCLK//A_A16
114 V
//A_WE
111 A_CSTOP//A_A20
112 A_CGNT
//A_A14
A_CPERR
110 GND
109
47
//A_A19
//A_A8
108 A_CBLOCK
107 A_CPAR//A_A13
106 A_RSVD//A_A18
105 A_CC/BE1
104 A_CAD16//A_A17
103 A_CAD14//A_A9
102 A_CAD15//A_IOWR
101 A_CAD13//A_IORD
100 A_CAD12//A_A11
99 A_CAD11//A_OE
98 A_CAD10//A_CE2
97 A_CAD9//A_A10
96 A_CC/BE0
95 GND
94 A_CAD8//A_D15
93 A_CAD7//A_D7
92 A_RSVD//A_D14
91 V
90 A_CAD5//A_D6
89 A_CAD6//A_D13
88 A_CAD3//A_D5
87 A_CAD4//A_D12
86 A_CAD1//A_D4
85 A_CAD2//A_D11
84 A_CAD0//A_D3
83 A_CCD1
82 B_CAD31//B_D10
81 CLK48
80 B_RSVD//B_D2
79 B_CAD30//B_D9
78 B_CAD29//B_D1
B_CAD28//B_D8
77
76 B_CAD27//B_D0
75 B_CCD2
74 B_CCLKRUN//B_WP(IOIS16)
B_CSTSCHG//B_BVD1(STSCHG/R
73
72 B_CAUDIO//B_BVD2(SPKR)
71 B_CSERR
70 V
69 B_CINT//B_READY(IREQ)
68 B_CVS1//B_VS1
67
B_CAD26//B_A0
66 B_CAD25//B_A1
65 B_CAD24//B_A2
64 B_CC/BE3
63 B_CAD23//B_A3
62 GND
61 B_CREQ
60 B_CAD22//B_A4
59 B_CAD21//B_A5
58 B_CRST
57
B_CAD20//B_A6
56 B_CVS2//B_VS2
55 B_CAD19//B_A25
54 B_CAD18//B_A7
53 B_CAD17//B_A24
CC
CC
//A_CE1
//A_CD1
//B_CD2
//B_WAIT
//B_REG
//B_INPACK
//B_RESET
CC
AD9 2
AD8 3
AD7 5
AD6 7
AD5 8
AD4 9
C/BE0
GND 6
AD10 1
V
AD3 10
AD1 12
AD0 13
AD2 11
//B_CD1 15
B_CAD0//B_D3 16
B_CAD1//B_D4 18
B_CAD2//B_D11 17
B_CAD4//B_D12 19
B_CCD1
GND 24
B_CAD3//B_D5 20
B_CAD5//B_D6 22
B_CAD6//B_D13 21
B_RSVD//B_D14 23
B_CAD7//B_D7 25
//B_CE1 27
B_CAD8//B_D15 26
B_CC/BE0
VR_EN 29
B_CAD9//B_A10 28
B_CAD10//B_CE2
B_CAD11//B_OE
B_CAD12//B_A11 32
B_CAD13//B_IORD
B_CAD15//B_IOWR
B_CAD14//B_A9 35
//B_A8 37
B_CC/BE1
B_CAD16//B_A17 36
CC
V
//B_A14 42
//B_A19 41
B_CPAR//B_A13 40
B_RSVD//B_A18 38
B_CPERR
B_CBLOCK
GND 43
//B_A20 44
B_CSTOP
//B_WE 45
B_CGNT
CCB
V
//B_A21 46
B_CCLK//B_A16 48
B_CTRDY//B_A22 49
B_CDEVSEL
//B_A23 51
//B_A15 50
B_CIRDY
B_CFRAME
//B_A12 52
B_CC/BE2
Figure 2−2. PCI1620 PDV Terminal Diagram
The following tables show the correspondence between signal names and their respective terminal assignments. In
Table 2−1, PDV-package entries are listed in order by terminal number, with signal names for CardBus PC Cards and
16-bit PC Cards. In Table 2−2, GHK-package entries are listed in alphanumeric order by terminal number, with signal
2−2
names for CardBus PC Cards and 16-bit PC Cards. In Table 2−3, entries are listed in alphanumeric order by CardBus
TERM.
TERM.
TERM.
TERM.
PC Card signal names, with corresponding terminal numbers. In Table 2−4, entries are listed in alphanumeric order
by 16-bit PC Card signal names, with corresponding terminal numbers.
Table 2−1. Signal Names by PDV Terminal Number
SIGNAL NAME
NO.
10 AD3 AD3 50 B_CIRDY B_A15
11 AD2 AD2 51 B_CFRAME B_A23
12 AD1 AD1 52 B_CC/BE2 B_A12
13 AD0 AD0 53 B_CAD17 B_A24
14 V
15 B_CCD1 B_CD1 55 B_CAD19 B_A25
16 B_CAD0 B_D3 56 B_CVS2 B_VS2
17 B_CAD2 B_D11 57 B_CAD20 B_A6
18 B_CAD1 B_D4 58 B_CRST B_RESET
19 B_CAD4 B_D12 59 B_CAD21 B_A5
20 B_CAD3 B_D5 60 B_CAD22 B_A4
21 B_CAD6 B_D13 61 B_CREQ B_INPACK
22 B_CAD5 B_D6 62 GND GND
23 B_RSVD B_D14 63 B_CAD23 B_A3
24 GND GND 64 B_CC/BE3 B_REG
25 B_CAD7 B_D7 65 B_CAD24 B_A2
26 B_CAD8 B_D15 66 B_CAD25 B_A1
27 B_CC/BE0 B_CE1 67 B_CAD26 B_A0
28 B_CAD9 B_A10 68 B_CVS1 B_VS1
29 VR_EN VR_EN 69 B_CINT B_READY(IREQ)
30 B_CAD10 B_CE2 70 V
31 B_CAD11 B_OE 71 B_CSERR B_WAIT
32 B_CAD12 B_A11 72 B_CAUDIO B_BVD2(SPKR)
33 B_CAD13 B_IORD 73 B_CSTSCHG B_BVD1(STSCHG/RI)
34 B_CAD15 B_IOWR 74 B_CCLKRUN B_WP(IOIS16)
35 B_CAD14 B_A9 75 B_CCD2 B_CD2
36 B_CAD16 B_A17 76 B_CAD27 B_D0
37 B_CC/BE1 B_A8 77 B_CAD28 B_D8
38 B_RSVD B_A18 78 B_CAD29 B_D1
39 V
40 B_CPAR B_A13 80 B_RSVD B_D2
CardBus PC Card 16-Bit PC Card
1 AD10 AD10 41 B_CBLOCK B_A19
2 AD9 AD9 42 B_CPERR B_A14
3 AD8 AD8 43 GND GND
4 C/BE0 C/BE0 44 B_CSTOP B_A20
5 AD7 AD7 45 B_CGNT B_WE
6 GND GND 46 B_CDEVSEL B_A21
7 AD6 AD6 47 V
8 AD5 AD5 48 B_CCLK B_A16
9 AD4 AD4 49 B_CTRDY B_A22
CC
CC
V
CC
V
CC
NO.
CardBus PC Card 16-Bit PC Card
54 B_CAD18 B_A7
79 B_CAD30 B_D9
CCB
CC
SIGNAL NAME
V
V
CCB
CC
2−3
Table 2−1. Signal Names by PDV Terminal Number (Continued)
TERM.
TERM.
TERM.
TERM.
SIGNAL NAME
NO.
81 CLK48 CLK48 123 A_CAD19 A_A25
82 B_CAD31 B_D10 124 A_CVS2 A_VS2
83 A_CCD1 A_CD1 125 A_CAD20 A_A6
84 A_CAD0 A_D3 126 A_CRST A_RESET
85 A_CAD2 A_D11 127 A_CAD21 A_A5
86 A_CAD1 A_D4 128 VR_OUT VR_OUT
87 A_CAD4 A_D12 129 A_CAD22 A_A4
88 A_CAD3 A_D5 130 A_CREQ A_INPACK
89 A_CAD6 A_D13 131 A_CAD23 A_A3
90 A_CAD5 A_D6 132 A_CC/BE3 A_REG
91 V
92 A_RSVD A_D14 134 A_CAD24 A_A2
93 A_CAD7 A_D7 135 A_CAD25 A_A1
94 A_CAD8 A_D15 136 A_CAD26 A_A0
95 GND GND 137 A_CVS1 A_VS1
96 A_CC/BE0 A_CE1 138 A_CINT A_READY(IREQ)
97 A_CAD9 A_A10 139 A_CSERR A_WAIT
98 A_CAD10 A_CE2 140 A_CAUDIO A_BVD2(SPKR)
99 A_CAD11 A_OE 141 A_CSTSCHG A_BVD1(STSCHG/RI)
100 A_CAD12 A_A11 142 A_CCLKRUN A_WP(IOIS16)
101 A_CAD13 A_IORD 143 V
102 A_CAD15 A_IOWR 144 A_CCD2 A_CD2
103 A_CAD14 A_A9 145 A_CAD27 A_D0
104 A_CAD16 A_A17 146 A_CAD28 A_D8
105 A_CC/BE1 A_A8 147 GND GND
106 A_RSVD A_A18 148 A_CAD29 A_D1
107 A_CPAR A_A13 149 A_CAD30 A_D9
108 A_CBLOCK A_A19 150 A_RSVD A_D2
109 A_CPERR A_A14 151 A_CAD31 A_D10
110 GND GND 152 SPKROUT SPKROUT
111 A_CSTOP A_A20 153 LATCH LATCH
112 A_CGNT A_WE 154 CLOCK CLOCK
113 A_CDEVSEL A_A21 155 DATA DATA
114 V
115 A_CCLK A_A16 157 MFUNC1 MFUNC1
116 A_CTRDY A_A22 158 SUSPEND SUSPEND
117 A_CIRDY A_A15 159 MFUNC2 MFUNC2
118 V
119 A_CFRAME A_A23 161 MFUNC4 MFUNC4
120 A_CC/BE2 A_A12 162 MFUNC5 MFUNC5
121 A_CAD17 A_A24 163 MFUNC6/CLKRUN MFUNC6/CLKRUN
122 A_CAD18 A_A7 164 C/BE3 C/BE3
CardBus PC Card 16-Bit PC Card
CC
CCA
CC
V
V
V
CC
CCA
CC
NO.
133 V
156 MFUNC0 MFUNC0
160 MFUNC3 MFUNC3
CardBus PC Card 16-Bit PC Card
CC
CC
SIGNAL NAME
V
CC
V
CC
2−4
Table 2−1. Signal Names by PDV Terminal Number (Continued)
TERM.
TERM.
TERM.
TERM.
.
.
TERM.
TERM.
SIGNAL NAME
NO.
165 RI_OUT/PME RI_OUT/PME 187 AD21 AD21
166 GND GND 188 AD20 AD20
167 AD25 AD25 189 AD19 AD19
168 PRST PRST 190 AD18 AD18
169 GNT GNT 191 AD17 AD17
170 REQ REQ 192 AD16 AD16
171 AD31 AD31 193 C/BE2 C/BE2
172 AD30 AD30 194 FRAME FRAME
173 AD11 AD11 195 V
174 V
175 AD29 AD29 197 TRDY TRDY
176 AD28 AD28 198 DEVSEL DEVSEL
177 GRST GRST 199 GND GND
178 AD27 AD27 200 STOP STOP
179 AD26 AD26 201 PERR PERR
180 V
181 AD24 AD24 203 PAR PAR
182 PCLK PCLK 204 C/BE1 C/BE1
183 IDSEL IDSEL 205 AD15 AD15
184 AD23 AD23 206 AD14 AD14
185 GND GND 207 AD13 AD13
186 AD22 AD22 208 AD12 AD12
CardBus PC Card 16-Bit PC Card
CC
CCP
V
V
CC
CCP
NO.
196 IRDY IRDY
202 SERR SERR
CardBus PC Card 16-Bit PC Card
CC
SIGNAL NAME
V
CC
Table 2−2. Signal Names by GHK Terminal Number
TERM
NO.
A04 AD12 AD12 B12 AD11 AD11
A05 PAR PAR B13 GNT GNT
A06 GND GND B14 C/BE3 C/BE3
A07 V
A08 AD18 AD18 C05 AD13 AD13
A09 GND GND C06 SERR SERR
A10 V
A11 AD29 AD29 C08 AD16 AD16
A12 V
A13 REQ REQ C10 PCLK PCLK
A14 GND GND C11 GRST GRST
A15 MFUNC5 MFUNC5 C12 AD30 AD30
A16 MFUNC1 MFUNC1 C13 PRST PRST
B05 AD15 AD15 C14 MFUNC6/CLKRUN MFUNC6/CLKRUN
B06 STOP STOP C15 SUSPEND SUSPEND
B07 IRDY IRDY D01 AD10 AD10
B08 AD17 AD17 D19 MFUNC0 MFUNC0
B09 AD22 AD22 E01 GND GND
B10 AD24 AD24 E02 AD7 AD7
B11 AD28 AD28 E03 AD9 AD9
CardBus PC Card 16-Bit PC Card
CC
CCP
CC
SIGNAL NAME
V
V
V
CC
CCP
CC
TERM
NO.
B15 MFUNC4 MFUNC4
C07 TRDY TRDY
C09 AD21 AD21
CardBus PC Card 16-Bit PC Card
SIGNAL NAME
2−5
Table 2−2. Signal Names by GHK Terminal Number (Continued)
.
.
TERM.
TERM.
TERM
NO.
E05 NC NC H05 B_CCD1 B_CD1
E06 AD14 AD14 H06 AD2 AD2
E07 PERR PERR H14 A_CSTSCHG A_BVD1(STSCHG/RI)
E08 FRAME FRAME H15 A_CCLKRUN A_WP(IOIS16)
E09 AD19 AD19 H17 A_CAUDIO A_BVD2(SPKR)
E10 IDSEL IDSEL H18 A_CSERR A_WAIT
E11 AD27 AD27 H19 A_CINT A_READY(IREQ)
E12 AD31 AD31 J01 B_CAD4 B_D12
E13 RI_OUT/PME RI_OUT/PME J02 B_CAD3 B_D5
E14 MFUNC2 MFUNC2 J03 B_CAD6 B_D13
E17 DATA DATA J05 B_CAD5 B_D6
E18 LATCH LATCH J06 B_RSVD B_D14
E19 A_CAD31 A_D10 J14 A_CAD26 A_A0
F01 AD3 AD3 J15 A_CVS1 A_VS1
F02 AD5 AD5 J17 A_CAD25 A_A1
F03 AD6 AD6 J18 A_CAD24 A_A2
F05 AD8 AD8 J19 V
F06 C/BE1 C/BE1 K01 GND GND
F07 DEVSEL DEVSEL K02 B_CAD7 B_D7
F08 C/BE2 C/BE2 K03 B_CAD8 B_D15
F09 AD20 AD20 K05 B_CC/BE0 B_CE1
F10 AD23 AD23 K06 B_CAD9 B_A10
F11 AD26 AD26 K14 A_CC/BE3 A_REG
F12 AD25 AD25 K15 A_CAD23 A_A3
F13 MFUNC3 MFUNC3 K17 A_CREQ A_INPACK
F14 SPKROUT SPKROUT K18 A_CAD22 A_A4
F15 CLOCK CLOCK K19 VR_OUT VR_OUT
F17 A_RSVD A_D2 L01 VR_EN VR_EN
F18 A_CAD29 A_D1 L02 B_CAD10 B_CE2
F19 GND GND L03 B_CAD11 B_OE
G01 V
G02 AD0 AD0 L06 B_CAD12 B_A11
G03 AD1 AD1 L14 A_CAD21 A_A5
G05 AD4 AD4 L15 A_CRST A_RESET
G06 C/BE0 C/BE0 L17 A_CAD20 A_A6
G14 A_CAD28 A_D8 L18 A_CVS2 A_VS2
G15 A_CAD30 A_D9 L19 A_CAD19 A_A25
G17 A_CAD27 A_D0 M01 B_CAD15 B_IOWR
G18 A_CCD2 A_CD2 M02 B_CAD14 B_A9
G19 V
H01 B_CAD1 B_D4 M05 B_RSVD B_A18
H02 B_CAD2 B_D11 M06 B_CC/BE1 B_A8
H03 B_CAD0 B_D3 M14 A_CCLK A_A16
CardBus PC Card 16-Bit PC Card
CC
CC
SIGNAL NAME
V
CC
V
CC
TERM
NO.
L05 B_CAD13 B_IORD
M03 B_CAD16 B_A17
CardBus PC Card 16-Bit PC Card
CC
SIGNAL NAME
V
CC
2−6
Table 2−2. Signal Names by GHK Terminal Number (Continued)
.
.
TERM.
TERM.
TERM
NO.
M15 A_CFRAME A_A23 R14 A_CAD15 A_IOWR
M17 A_CC/BE2 A_A12 R17 A_RSVD A_A18
M18 A_CAD17 A_A24 R18 A_CPERR A_A14
M19 A_CAD18 A_A7 R19 GND GND
N01 V
N02 B_CPAR B_A13 T19 A_CC/BE1 A_A8
N03 B_CBLOCK B_A19 U05 B_CAD18 B_A7
N05 B_CGNT B_WE U06 B_CAD21 B_A5
N06 B_CPERR B_A14 U07 B_CC/BE3 B_REG
N14 A_CBLOCK A_A19 U08 B_CVS1 B_VS1
N15 A_CDEVSEL A_A21 U09 B_CSTSCHG B_BVD1(STSCHG/RI)
N17 A_CTRDY A_A22 U10 B_CAD29 B_D1
N18 A_CIRDY A_A15 U11 A_CCD1 A_CD1
N19 V
P01 GND GND U13 A_CAD7 A_D7
P02 B_CSTOP B_A20 U14 A_CAD10 A_CE2
P03 B_CDEVSEL B_A21 U15 A_CAD14 A_A9
P05 B_CIRDY B_A15 V05 B_CAD20 B_A6
P06 B_CCLK B_A16 V06 B_CAD22 B_A4
P07 B_CVS2 B_VS2 V07 B_CAD24 B_A2
P08 B_CAD23 B_A3 V08 B_CINT B_READY(IREQ)
P09 B_CCD2 B_CD2 V09 B_CAUDIO B_BVD2(SPKR)
P10 B_RSVD B_D2 V10 B_CAD28 B_D8
P11 A_CAD0 A_D3 V11 B_CAD31 B_D10
P12 A_CAD6 A_D13 V12 A_CAD4 A_D12
P13 A_CAD8 A_D15 V13 A_RSVD A_D14
P14 A_CAD12 A_A11 V14 A_CC/BE0 A_CE1
P15 A_CPAR A_A13 V15 A_CAD13 A_IORD
P17 A_CSTOP A_A20 W04 B_CAD17 B_A24
P18 A_CGNT A_WE W05 B_CRST B_RESET
P19 V
R01 V
R02 B_CTRDY B_A22 W08 V
R03 B_CFRAME B_A23 W09 B_CSERR B_WAIT
R06 B_CAD19 B_A25 W10 B_CAD27 B_D0
R07 B_CREQ B_INPACK W11 CLK48 CLK48
R08 B_CAD26 B_A0 W12 A_CAD1 A_D4
R09 B_CCLKRUN B_WP(IOIS16) W13 V
R10 B_CAD30 B_D9 W14 GND GND
R11 A_CAD2 A_D11 W15 A_CAD11 A_OE
R12 A_CAD5 A_D6 W16 A_CAD16 A_A17
R13 A_CAD9 A_A10
CardBus PC Card 16-Bit PC Card
CC
CC
CCA
CCB
SIGNAL NAME
V
V
V
V
CC
CC
CCA
CCB
TERM
NO.
T01 B_CC/BE2 B_A12
U12 A_CAD3 A_D5
W06 GND GND
W07 B_CAD25 B_A1
CardBus PC Card 16-Bit PC Card
CC
CC
SIGNAL NAME
V
V
CC
CC
2−7
Table 2−3. CardBus PC Card Signal Names Sorted Alphabetically
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
TERM NO.
PDV GHK
A_CAD0 84 P11 A_CC/BE1 105 T19 AD10 1 D01 B_CAD13 33 L05
A_CAD1 86 W12 A_CC/BE2 120 M17 AD11 173 B12 B_CAD14 35 M02
A_CAD2 85 R11 A_CC/BE3 132 K14 AD12 208 A04 B_CAD15 34 M01
A_CAD3 88 U12 A_CCD1 83 U11 AD13 207 C05 B_CAD16 36 M03
A_CAD4 87 V12 A_CCD2 144 G18 AD14 206 E06 B_CAD17 53 W04
A_CAD5 90 R12 A_CCLK 115 M14 AD15 205 B05 B_CAD18 54 U05
A_CAD6 89 P12 A_CCLKRUN 142 H15 AD16 192 C08 B_CAD19 55 R06
A_CAD7 93 U13 A_CDEVSEL 113 N15 AD17 191 B08 B_CAD20 57 V05
A_CAD8 94 P13 A_CFRAME 119 M15 AD18 190 A08 B_CAD21 59 U06
A_CAD9 97 R13 A_CGNT 112 P18 AD19 189 E09 B_CAD22 60 V06
A_CAD10 98 U14 A_CINT 138 H19 AD20 188 F09 B_CAD23 63 P08
A_CAD11 99 W15 A_CIRDY 117 N18 AD21 187 C09 B_CAD24 65 V07
A_CAD12 100 P14 A_CPAR 107 P15 AD22 186 B09 B_CAD25 66 W07
A_CAD13 101 V15 A_CPERR 109 R18 AD23 184 F10 B_CAD26 67 R08
A_CAD14 103 U15 A_CREQ 130 K17 AD24 181 B10 B_CAD27 76 W10
A_CAD15 102 R14 A_CRST 126 L15 AD25 167 F12 B_CAD28 77 V10
A_CAD16 104 W16 A_CSERR 139 H18 AD26 179 F11 B_CAD29 78 U10
A_CAD17 121 M18 A_CSTOP 111 P17 AD27 178 E11 B_CAD30 79 R10
A_CAD18 122 M19 A_CSTSCHG 141 H14 AD28 176 B11 B_CAD31 82 V11
A_CAD19 123 L19 A_CTRDY 116 N17 AD29 175 A11 B_CAUDIO 72 V09
A_CAD20 125 L17 A_CVS1 137 J15 AD30 172 C12 B_CBLOCK 41 N03
A_CAD21 127 L14 A_CVS2 124 L18 AD31 171 E12 B_CC/BE0 27 K05
A_CAD22 129 K18 A_RSVD 106 R17 B_CAD0 16 H03 B_CC/BE1 37 M06
A_CAD23 131 K15 A_RSVD 92 V13 B_CAD1 18 H01 B_CC/BE2 52 T01
A_CAD24 134 J18 A_RSVD 150 F17 B_CAD2 17 H02 B_CC/BE3 64 U07
A_CAD25 135 J17 AD0 13 G02 B_CAD3 20 J02 B_CCD1 15 H05
A_CAD26 136 J14 AD1 12 G03 B_CAD4 19 J01 B_CCD2 75 P09
A_CAD27 145 G17 AD2 11 H06 B_CAD5 22 J05 B_CCLK 48 P06
A_CAD28 146 G14 AD3 10 F01 B_CAD6 21 J03 B_CCLKRUN 74 R09
A_CAD29 148 F18 AD4 9 G05 B_CAD7 25 K02 B_CDEVSEL 46 P03
A_CAD30 149 G15 AD5 8 F02 B_CAD8 26 K03 B_CFRAME 51 R03
A_CAD31 151 E19 AD6 7 F03 B_CAD9 28 K06 B_CGNT 45 N05
A_CAUDIO 140 H17 AD7 5 E02 B_CAD10 30 L02 B_CINT 69 V08
A_CBLOCK 108 N14 AD8 3 F05 B_CAD11 31 L03 B_CIRDY 50 P05
A_CC/BE0 96 V14 AD9 2 E03 B_CAD12 32 L06 B_CPAR 40 N02
TERM. NO.
PDV GHK
TERM. NO.
PDV GHK
TERM NO.
PDV GHK
2−8
Table 2−3. CardBus PC Card Signal Names Sorted Alphabetically (Continued)
SIGNAL NAME
SIGNAL NAME
TERM NO.
PDV GHK
B_CPERR 42 N06 LATCH 153 E18
B_CREQ 61 R07 MFUNC0 156 D19
B_CRST 58 W05 MFUNC1 157 A16
B_CSERR 71 W09 MFUNC2 159 E14
B_CSTOP 44 P02 MFUNC3 160 F13
B_CSTSCHG 73 U09 MFUNC4 161 B15
B_CTRDY 49 R02 MFUNC5 162 A15
B_CVS1 68 U08 MFUNC6/CLKRUN 163 C14
B_CVS2 56 P07 NC — E05
B_RSVD 23 J06 PAR 203 A05
B_RSVD 38 M05 PCLK 182 C10
B_RSVD 80 P10 PERR 201 E07
C/BE0 4 G06 PRST 168 C13
C/BE1 204 F06 REQ 170 A13
C/BE2 193 F08 RI_OUT/PME 165 E13
C/BE3 164 B14 SERR 202 C06
CLK48 81 W11 SPKROUT 152 F14
CLOCK 154 F15 STOP 200 B06
DATA 155 E17 SUSPEND 158 C15
DEVSEL 198 F07 TRDY 197 C07
FRAME 194 E08 V
GND 6 A06 V
GND 24 A09 V
GND 43 A14 V
GND 62 E01 V
GND 95 K01 V
GND 110 P01 V
GND 147 R19 V
GND 166 W06 V
GND 185 F19 V
GND 199 W14 V
GNT 169 B13 V
GRST 177 C11 VR_EN 29 L01
IDSEL 183 E10 VR_OUT 128 K19
IRDY 196 B07
CC
CC
CC
CC
CC
CC
CC
CC
CC
CCA
CCB
CCP
TERM NO.
PDV GHK
14 A07
39 A12
70 G01
91 G19
118 J19
133 N01
143 N19
174 W08
195 W13
114 P19
47 R01
180 A10
2−9
Table 2−4. 16-Bit PC Card Signal Names Sorted Alphabetically
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
TERM. NO.
PDV GHK
A_A0 136 J14 A_D10 151 E19 AD24 181 B10
A_A1 135 J17 A_D11 85 R11 AD25 167 F12
A_A2 134 J18 A_D12 87 V12 AD26 179 F11
A_A3 131 K15 A_D13 89 P12 AD27 178 E11
A_A4 129 K18 A_D14 92 V13 AD28 176 B11
A_A5 127 L14 A_D15 94 P13 AD29 175 A11
A_A6 125 L17 A_INPACK 130 K17 AD30 172 C12
A_A7 122 M19 A_IORD 101 V15 AD31 171 E12
A_A8 105 T19 A_IOWR 102 R14 B_A0 67 R08
A_A9 103 U15 A_OE 99 W15 B_A1 66 W07
A_A10 97 R13 A_READY(IREQ) 138 H19 B_A2 65 V07
A_A11 100 P14 A_REG 132 K14 B_A3 63 P08
A_A12 120 M17 A_RESET 126 L15 B_A4 60 V06
A_A13 107 P15 A_VS1 137 J15 B_A5 59 U06
A_A14 109 R18 A_VS2 124 L18 B_A6 57 V05
A_A15 117 N18 A_WAIT 139 H18 B_A7 54 U05
A_A16 115 M14 A_WE 112 P18 B_A8 37 M06
A_A17 104 W16 A_WP(IOIS16) 142 H15 B_A9 35 M02
A_A18 106 R17 AD0 13 G02 B_A10 28 K06
A_A19 108 N14 AD1 12 G03 B_A11 32 L06
A_A20 111 P17 AD2 11 H06 B_A12 52 T01
A_A21 113 N15 AD3 10 F01 B_A13 40 N02
A_A22 116 N17 AD4 9 G05 B_A14 42 N06
A_A23 119 M15 AD5 8 F02 B_A15 50 P05
A_A24 121 M18 AD6 7 F03 B_A16 48 P06
A_A25 123 L19 AD7 5 E02 B_A17 36 M03
A_BVD1(STSCHG/RI) 141 H14 AD8 3 F05 B_A18 38 M05
A_BVD2(SPKR) 140 H17 AD9 2 E03 B_A19 41 N03
A_CD1 83 U11 AD10 1 D01 B_A20 44 P02
A_CD2 144 G18 AD11 173 B12 B_A21 46 P03
A_CE1 96 V14 AD12 208 A04 B_A22 49 R02
A_CE2 98 U14 AD13 207 C05 B_A23 51 R03
A_D0 145 G17 AD14 206 E06 B_A24 53 W04
A_D1 148 F18 AD15 205 B05 B_A25 55 R06
A_D2 150 F17 AD16 192 C08 B_BVD1(STSCHG/RI) 73 U09
A_D3 84 P11 AD17 191 B08 B_BVD2(SPKR) 72 V09
A_D4 86 W12 AD18 190 A08 B_CD1 15 H05
A_D5 88 U12 AD19 189 E09 B_CD2 75 P09
A_D6 90 R12 AD20 188 F09 B_CE1 27 K05
A_D7 93 U13 AD21 187 C09 B_CE2 30 L02
A_D8 146 G14 AD22 186 B09 B_D0 76 W10
A_D9 149 G15 AD23 184 F10 B_D1 78 U10
TERM. NO.
PDV GHK
TERM NO.
PDV GHK
2−10
Table 2−4. 16-Bit PC Card Signal Names Sorted Alphabetically (Continued)
SIGNAL NAME
SIGNAL NAME
TERM NO.
PDV GHK
B_D2 80 P10 GND 147 R19
B_D3 16 H03 GND 166 W06
B_D4 18 H01 GND 199 W14
B_D5 20 J02 GNT 169 B13
B_D6 22 J05 GRST 177 C11
B_D7 25 K02 IDSEL 183 E10
B_D8 77 V10 IRDY 196 B07
B_D9 79 R10 LATCH 153 E18
B_D10 82 V11 MFUNC0 156 D19
B_D11 17 H02 MFUNC1 157 A16
B_D12 19 J01 MFUNC2 159 E14
B_D13 21 J03 MFUNC3/IRQSER 160 F13
B_D14 23 J06 MFUNC4 161 B15
B_D15 26 K03 MFUNC5 162 A15
B_INPACK 61 R07 MFUNC6/CLKRUN 163 C14
B_IORD 33 L05 NC — E05
B_IOWR 34 M01 PAR 203 A05
B_OE 31 L03 PCLK 182 C10
B_READY(IREQ) 69 V08 PERR 201 E07
B_REG 64 U07 PRST 168 C13
B_RESET 58 W05 REQ 170 A13
B_VS1 68 U08 RI_OUT/PME 165 E13
B_VS2 56 P07 SERR 202 C06
B_WAIT 71 W09 SPKROUT 152 F14
B_WE 45 N05 STOP 200 B06
B_WP(IOIS16) 74 R09 SUSPEND 158 C15
C/BE0 4 G06 TRDY 197 C07
C/BE1 204 F06 V
C/BE2 193 F08 V
C/BE3 164 B14 V
CLK48 185 W11 V
CLOCK 154 F15 V
DATA 155 E17 V
DEVSEL 198 F07 V
FRAME 194 E08 V
GND 6 A06 V
GND 24 A09 V
GND 43 A14 V
GND 62 E01 V
GND 81 F19 VR_EN 29 L01
GND 95 K01 VR_OUT 128 K19
GND 110 P01
CC
CC
CC
CC
CC
CC
CC
CC
CC
CCA
CCB
CCP
TERM NO.
PDV GHK
14 A07
39 A12
70 G01
91 G19
118 J19
133 N01
143 N19
174 W08
195 W13
114 P19
47 R01
180 A10
2−11
The terminals are grouped in tables by functionality, such as PCI system function and power supply function, for quick
NAME
I/O
DESCRIPTION
NAME
I/O
DESCRIPTION
reference (see Table 2−5 through Table 2−15). The terminal names and numbers are also listed for convenient
reference.
Table 2−5. Power Supply Terminals
TERMINAL
NO.
PDV GHK
GND 6, 24, 43, 62,
V
CC
V
CCA
V
CCB
V
CCP
VR_EN 29 L01 I Internal voltage regulator enable. Active-low
VR_OUT 128 K19 O Internal voltage regulator output (1.8 V) for external bypass capacitor
95, 110, 147,
166, 185, 199
14, 39, 70, 91,
118, 133, 143,
174, 195
114 P19 − PC Card A signaling rail power input; clamped per PC Card specification
47 R01 − PC Card B signaling rail power input; clamped per PC Card specification
180 A10 − PCI signaling clamp rail power input; clamped per PCI specification
A06, A09, A14,
E01, F19, K01,
P01, R19, W06,
W14
A07, A12, G01,
G19, J19, N01,
N19, W08, W13
I/O DESCRIPTION
− Device ground terminals
− 3.3-V power terminals
Table 2−6. PC Card Power Switch Terminals
TERMINAL
NO.
PDV GHK
CLOCK 154 F15 I/O
DATA 155 E17 O
LATCH 153 E18 I/O
I/O DESCRIPTION
Power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK. CLOCK defaults
to an input, but can be changed to a PCI1620 output by using bit 27 (P2CCLK) in the system control register
(PCI offset 80h, see Section 4.31). For use with the TPS222X, the maximum frequency of this signal is limited
to 2 MHz. However, the PCI1620 requires a 16-KHz to 100-KHz frequency range. As an input, this terminal
requires an external 32-kHz clock. If a system design defines this terminal as an output, then this terminal
requires an external pulldown resistor. The frequency of the PCI1620 output CLOCK is derived from the
internal ring oscillator (16 kHz typical).
Power switch data. DATA is used to communicate socket power control information serially to the power
switch.
Power switch latch. LATCH is asserted by the PCI1620 to indicate to the power switch that the data on the
DATA line is valid. The LATCH terminal is also used to indicate the presence of an external EEPROM; when
a pulldown resistor is implemented on this terminal, the MFUNC1 and MFUNC4 terminals provide the serial
EEPROM SDA and SCL interface.
2−12
TERMINAL
NAME
I/O
DESCRIPTION
NO.
PDV GHK
GRST 177 C11 I
PCLK 182 C10 I
PRST
168 C13 I
Table 2−7. PCI System Terminals
I/O DESCRIPTION
Global reset. When the global reset is asserted, the GRST signal causes the PCI1620 to place all output
buffers in a high-impedance state and reset all internal registers. When GRST
completely in its default state. For systems that require wake-up from D3, GRST
during initial boot. PRST
that PME context is retained during the transition from D3 to D0. For systems that do not require wake-up
from D3, GRST
When the SUSPEND
registers are not reset, but all outputs are placed in a high-impedance state.
PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the
rising edge of PCLK.
PCI reset. When the PCI bus reset is asserted, PRST causes the PCI1620 to reset internal registers and
place all output buffers in a high-impedance state. When PRST
signal only if it is enabled. After PRST is deasserted, the PCI1620 is in a default state.
When the SUSPEND
internal registers are preserved, but all outputs are placed in a high-impedance state.
should be asserted during GRST and for resets subsequent to the initial GRST so
should be tied to PRST.
mode is enabled together with GRST, the device is protected from GRST; the internal
is asserted, the device can generate the PME
mode is enabled together with PRST, the device is protected from PRST and the
is asserted, the device is
normally is asserted only
2−13
TERMINAL
NAME
I/O
DESCRIPTION
NO.
PDV GHK
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
C/BE3
C/BE2
C/BE1
C/BE0
PAR 203 A05 I/O
171
172
175
176
178
179
167
181
184
186
187
188
189
190
191
192
205
206
207
208
173
1
2
3
5
7
8
9
10
11
12
13
164
193
204
4
E12
C12
A11
B11
E11
F11
F12
B10
F10
B09
C09
F09
E09
A08
B08
C08
B05
E06
C05
A04
B12
D01
E03
F05
E02
F03
F02
G05
F01
H06
G03
G02
B14
F08
F06
G06
Table 2−8. PCI Address and Data Terminals
I/O DESCRIPTION
PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary
interface. During the address phase of a primary bus PCI cycle, AD31−AD0 contain a 32-bit address or other
I/O
destination information. During the data phase, AD31−AD0 contain data.
PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During
the address phase of a primary bus PCI cycle, C/BE3
phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit
I/O
data bus carry meaningful data. C/BE0
C/BE2
applies to byte 2 (AD23−AD16), and C/BE3 applies to byte 3 (AD31−AD24).
PCI bus parity. In all PCI bus read and write cycles, the PCI1620 calculates even parity across the
AD31−AD0 and C/BE3
indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the parity
indicator of the initiator. A compare error results in the assertion of a parity error (PERR).
−C/BE0 buses. As an initiator during PCI cycles, the PCI1620 outputs this parity
applies to byte 0 (AD7−AD0), C/BE1 applies to byte 1 (AD15−AD8),
−C/BE0 define the bus command. During the data
2−14
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