TEXAS INSTRUMENTS PCI1520-EP Technical data
查询PCI1520-EP供应商
Data Manual
2003 PCIBus Solutions
SGLS168
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Contents
Section Title Page
1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Description 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Features 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Related Documents 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Trademarks 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Ordering Information 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 PCI1520-EP Data Manual Document History 1–3. . . . . . . . . . . . . . . . . . . .
2 Terminal Descriptions 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Feature/Protocol Descriptions 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Power Supply Sequencing 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 I/O Characteristics 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Clamping Voltages 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Peripheral Component Interconnect (PCI) Interface 3–2. . . . . . . . . . . . . .
3.4.1 PCI GRST
3.4.2 PCI Bus Lock (LOCK
3.4.3 Loading Subsystem Identification 3–3. . . . . . . . . . . . . . . . . . . . .
3.5 PC Card Applications 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1 PC Card Insertion/Removal and Recognition 3–4. . . . . . . . . . .
2
3.5.2 P
3.5.3 Zoomed Video Support 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.4 Standardized Zoomed-Video Register Model 3–7. . . . . . . . . . .
3.5.5 Internal Ring Oscillator 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.6 Integrated Pullup Resistors 3–8. . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.7 SPKROUT and CAUDPWM Usage 3–9. . . . . . . . . . . . . . . . . . .
3.5.8 LED Socket Activity Indicators 3–10. . . . . . . . . . . . . . . . . . . . . . . .
3.5.9 CardBus Socket Registers 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Serial-Bus Interface 3–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1 Serial-Bus Interface Implementation 3–11. . . . . . . . . . . . . . . . . . .
3.6.2 Serial-Bus Interface Protocol 3–11. . . . . . . . . . . . . . . . . . . . . . . . .
3.6.3 Serial-Bus EEPROM Application 3–13. . . . . . . . . . . . . . . . . . . . . .
3.6.4 Accessing Serial-Bus Devices Through Software 3–14. . . . . . .
3.7 Programmable Interrupt Subsystem 3–15. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.1 PC Card Functional and Card Status Change
3.7.2 Interrupt Masks and Flags 3–17. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.3 Using Parallel IRQ Interrupts 3–17. . . . . . . . . . . . . . . . . . . . . . . . .
3.7.4 Using Parallel PCI Interrupts 3–18. . . . . . . . . . . . . . . . . . . . . . . . .
C Power-Switch Interface (TPS222X) 3–4. . . . . . . . . . . . . . .
Interrupts 3–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
)3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iii
3.7.5 Using Serialized IRQSER Interrupts 3–18. . . . . . . . . . . . . . . . . . .
3.7.6 SMI Support in the PCI1520 3–18. . . . . . . . . . . . . . . . . . . . . . . . . .
3.8 Power Management Overview 3–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.1 Integrated Low-Dropout Voltage Regulator (LDO-VR) 3–19. . . .
3.8.2 Clock Run Protocol 3–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.3 CardBus PC Card Power Management 3–20. . . . . . . . . . . . . . . .
3.8.4 16-Bit PC Card Power Management 3–20. . . . . . . . . . . . . . . . . . .
3.8.5 Suspend Mode 3–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.6 Requirements for Suspend Mode 3–21. . . . . . . . . . . . . . . . . . . . .
3.8.7 Ring Indicate 3–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.8 PCI Power Management 3–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.9 CardBus Bridge Power Management 3–23. . . . . . . . . . . . . . . . . .
3.8.10 ACPI Support 3–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.11 Master List of PME
Context Bits and Global
Reset-Only Bits 3–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 PC Card Controller Programming Model 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 PCI Configuration Registers (Functions 0 and 1) 4–1. . . . . . . . . . . . . . . . .
4.2 Vendor ID Register 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Device ID Register 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Command Register 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Status Register 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 Revision ID Register 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 PCI Class Code Register 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8 Cache Line Size Register 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9 Latency Timer Register 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10 Header Type Register 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.11 BIST Register 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12 CardBus Socket/ExCA Base-Address Register 4–7. . . . . . . . . . . . . . . . . .
4.13 Capability Pointer Register 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14 Secondary Status Register 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.15 PCI Bus Number Register 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.16 CardBus Bus Number Register 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.17 Subordinate Bus Number Register 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.18 CardBus Latency Timer Register 4–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.19 Memory Base Registers 0, 1 4–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.20 Memory Limit Registers 0, 1 4–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.21 I/O Base Registers 0, 1 4–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.22 I/O Limit Registers 0, 1 4–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.23 Interrupt Line Register 4–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.24 Interrupt Pin Register 4–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.25 Bridge Control Register 4–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.26 Subsystem Vendor ID Register 4–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.27 Subsystem ID Register 4–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.28 PC Card 16-Bit I/F Legacy-Mode Base Address Register 4–15. . . . . . . . .
iv
4.29 System Control Register 4–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.30 Multifunction Routing Register 4–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.31 Retry Status Register 4–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.32 Card Control Register 4–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.33 Device Control Register 4–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.34 Diagnostic Register 4–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.35 Capability ID Register 4–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.36 Next-Item Pointer Register 4–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.37 Power-Management Capabilities Register 4–26. . . . . . . . . . . . . . . . . . . . . .
4.38 Power-Management Control/Status Register 4–27. . . . . . . . . . . . . . . . . . . .
4.39 Power-Management Control/Status Register Bridge
Support Extensions 4–28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.40 Power-Management Data Register 4–28. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.41 General-Purpose Event Status Register 4–29. . . . . . . . . . . . . . . . . . . . . . . .
4.42 General-Purpose Event Enable Register 4–30. . . . . . . . . . . . . . . . . . . . . . .
4.43 General-Purpose Input Register 4–31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.44 General-Purpose Output Register 4–32. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.45 Serial-Bus Data Register 4–32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.46 Serial-Bus Index Register 4–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.47 Serial-Bus Slave Address Register 4–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.48 Serial-Bus Control and Status Register 4–34. . . . . . . . . . . . . . . . . . . . . . . . .
5 ExCA Compatibility Registers (Functions 0 and 1) 5–1. . . . . . . . . . . . . . . . . .
5.1 ExCA Identification and Revision Register 5–5. . . . . . . . . . . . . . . . . . . . . .
5.2 ExCA Interface Status Register 5–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 ExCA Power Control Register 5–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 ExCA Interrupt and General Control Register 5–8. . . . . . . . . . . . . . . . . . .
5.5 ExCA Card Status-Change Register 5–9. . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6 ExCA Card Status-Change Interrupt Configuration Register 5–10. . . . . . .
5.7 ExCA Address Window Enable Register 5–11. . . . . . . . . . . . . . . . . . . . . . . .
5.8 ExCA I/O Window Control Register 5–12. . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers 5–13. . . .
5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers 5–13. . . .
5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers 5–14. . . . .
5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers 5–14. . . .
5.13 ExCA Memory Windows 0–4 Start-Address Low-Byte Registers 5–15. . .
5.14 ExCA Memory Windows 0–4 Start-Address High-Byte Registers 5–16. . .
5.15 ExCA Memory Windows 0–4 End-Address Low-Byte Registers 5–17. . . .
5.16 ExCA Memory Windows 0–4 End-Address High-Byte Registers 5–18. . .
5.17 ExCA Memory Windows 0–4 Offset-Address Low-Byte Registers 5–19. .
5.18 ExCA Memory Windows 0–4 Offset-Address High-Byte Registers 5–20.
5.19 ExCA Card Detect and General Control Register 5–21. . . . . . . . . . . . . . . .
5.20 ExCA Global Control Register 5–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers 5–23. . .
5.22 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers 5–23. . .
v
5.23 ExCA Memory Windows 0–4 Page Registers 5–24. . . . . . . . . . . . . . . . . . .
6 CardBus Socket Registers (Functions 0 and 1) 6–1. . . . . . . . . . . . . . . . . . . . . .
6.1 Socket Event Register 6–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Socket Mask Register 6–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Socket Present-State Register 6–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4 Socket Force Event Register 6–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5 Socket Control Register 6–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6 Socket Power-Management Register 6–9. . . . . . . . . . . . . . . . . . . . . . . . . .
7 Electrical Characteristics 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Absolute Maximum Ratings Over Operating Temperature Ranges 7–1.
7.2 Recommended Operating Conditions 7–2. . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 Electrical Characteristics Over Recommended
Operating Conditions 7–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4 PCI Clock/Reset Timing Requirements Over Recommended
Ranges of Supply Voltage and Operating Free-Air Temperature 7–3. . .
7.5 PCI Timing Requirements Over Recommended Ranges of
Supply Voltage and Operating Free-Air Temperature 7–4. . . . . . . . . . . . .
8 Mechanical Information 8–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
List of Illustrations
Figure Title Page
2–1 PCI1520 GHK-Package Terminal Diagram 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 PCI1520 Simplified Block Diagram 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 3-State Bidirectional Buffer 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 TPS222X Typical Application 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–4 Zoomed Video Implementation Using the PCI1520 3–6. . . . . . . . . . . . . . . . . . . .
3–5 Zoomed Video Switching Application 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–6 Sample Application of SPKROUT and CAUDPWM 3–10. . . . . . . . . . . . . . . . . . . .
3–7 Two Sample LED Circuits 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–8 Serial EEPROM Application 3–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–9 Serial-Bus Start/Stop Conditions and Bit Transfers 3–12. . . . . . . . . . . . . . . . . . . .
3–10 Serial-Bus Protocol Acknowledge 3–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–11 Serial-Bus Protocol – Byte Write 3–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–12 Serial-Bus Protocol – Byte Read 3–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–13 EEPROM Interface Doubleword Data Collection 3–13. . . . . . . . . . . . . . . . . . . . .
3–14 IRQ Implementation 3–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–15 Signal Diagram of Suspend Function 3–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–16 RI_OUT
3–17 Block Diagram of a Status/Enable Cell 3–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1 ExCA Register Access Through I/O 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 ExCA Register Access Through Memory 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–1 Accessing CardBus Socket Registers Through PCI Memory 6–1. . . . . . . . . . . .
Functional Diagram 3–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vii
List of Tables
Table Title Page
2–1 Signal Names by GHK Terminal Number 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 CardBus PC Card Signal Names Sorted Alphabetically 2–4. . . . . . . . . . . . . . . .
2–3 16-Bit PC Card Signal Names Sorted Alphabetically 2–9. . . . . . . . . . . . . . . . . . .
2–4 Power Supply Terminals 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 PC Card Power Switch Terminals 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 PCI System Terminals 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–7 PCI Address and Data Terminals 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–8 PCI Interface Control Terminals 2–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–9 Multifunction and Miscellaneous Terminals 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . .
2–10 16-Bit PC Card Address and Data Terminals (Slots A and B) 2–12. . . . . . . . . .
2–11 16-Bit PC Card Interface Control Terminals (Slots A and B) 2–13. . . . . . . . . . . .
2–12 CardBus PC Card Interface System Terminals (Slots A and B) 2–14. . . . . . . . .
2–13 CardBus PC Card Address and Data Terminals (Slots A and B) 2–15. . . . . . . .
2–14 CardBus PC Card Interface Control Terminals (Slots A and B) 2–16. . . . . . . . .
3–1 PC Card Card-Detect and Voltage-Sense Connections 3–4. . . . . . . . . . . . . . . .
3–2 Power Switch Options 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 Functionality of the ZV Output Signals 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–4 Zoomed-Video Card Interrogation 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–5 Integrated Pullup Resistors 3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–6 CardBus Socket Registers 3–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–7 Register- and Bit-Loading Map 3–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–8 PCI1520 Registers Used to Program Serial-Bus Devices 3–15. . . . . . . . . . . . . . .
3–9 Interrupt Mask and Flag Registers 3–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–10 PC Card Interrupt Events and Description 3–16. . . . . . . . . . . . . . . . . . . . . . . . . . .
3–11 Interrupt Pin Register Cross Reference 3–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–12 SMI Control 3–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–13 Requirements for Internal/External 2.5-V Core Power Supply 3–19. . . . . . . . . .
3–14 Power-Management Registers 3–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 PCI Configuration Registers (Functions 0 and 1) 4–1. . . . . . . . . . . . . . . . . . . . . .
4–2 Bit Field Access Tag Descriptions 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–3 Command Register Description 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–4 Status Register Description 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–5 Secondary Status Register Description 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–6 Interrupt Pin Register Cross Reference 4–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–7 Bridge Control Register Description 4–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–8 System Control Register Description 4–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–9 Multifunction Routing Register Description 4–19. . . . . . . . . . . . . . . . . . . . . . . . . . .
viii
4–10 Retry Status Register Description 4–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–11 Card Control Register Description 4–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–12 Device Control Register Description 4–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–13 Diagnostic Register Description 4–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–14 Power-Management Capabilities Register Description 4–26. . . . . . . . . . . . . . . .
4–15 Power-Management Control/Status Register Description 4–27. . . . . . . . . . . . . .
4–16 Power-Management Control/Status Register Bridge Support
Extensions Description 4–28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–17 General-Purpose Event Status Register Description 4–29. . . . . . . . . . . . . . . . . .
4–18 General-Purpose Event Enable Register Description 4–30. . . . . . . . . . . . . . . . .
4–19 General-Purpose Input Register Description 4–31. . . . . . . . . . . . . . . . . . . . . . . . .
4–20 General-Purpose Output Register Description 4–32. . . . . . . . . . . . . . . . . . . . . . .
4–21 Serial-Bus Data Register Description 4–32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–22 Serial-Bus Index Register Description 4–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–23 Serial-Bus Slave Address Register Description 4–33. . . . . . . . . . . . . . . . . . . . . .
4–24 Serial-Bus Control and Status Register Description 4–34. . . . . . . . . . . . . . . . . . .
5–1 ExCA Registers and Offsets 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 ExCA Identification and Revision Register Description 5–5. . . . . . . . . . . . . . . . .
5–3 ExCA Interface Status Register Description 5–6. . . . . . . . . . . . . . . . . . . . . . . . . .
5–4 ExCA Power Control Register Description—82365SL Support 5–7. . . . . . . . . .
5–5 ExCA Power Control Register Description—82365SL-DF Support 5–7. . . . . . .
5–6 ExCA Interrupt and General Control Register Description 5–8. . . . . . . . . . . . . .
5–7 ExCA Card Status-Change Register Description 5–9. . . . . . . . . . . . . . . . . . . . . .
5–8 ExCA Card Status-Change Interrupt Configuration
Register Description 5–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–9 ExCA Address Window Enable Register Description 5–11. . . . . . . . . . . . . . . . . . .
5–10 ExCA I/O Window Control Register Description 5–12. . . . . . . . . . . . . . . . . . . . . .
5–11 ExCA Memory Windows 0–4 Start-Address High-Byte Registers
Description 5–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–12 ExCA Memory Windows 0–4 End-Address High-Byte Registers
Description 5–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–13 ExCA Memory Windows 0–4 Offset-Address High-Byte Registers
Description 5–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–14 ExCA Card Detect and General Control Register Description 5–21. . . . . . . . . .
5–15 ExCA Global Control Register Description 5–22. . . . . . . . . . . . . . . . . . . . . . . . . .
6–1 CardBus Socket Registers 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–2 Socket Event Register Description 6–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–3 Socket Mask Register Description 6–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–4 Socket Present-State Register Description 6–4. . . . . . . . . . . . . . . . . . . . . . . . . . .
6–5 Socket Force Event Register Description 6–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–6 Socket Control Register Description 6–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–7 Socket Power-Management Register Description 6–9. . . . . . . . . . . . . . . . . . . . .
ix
1 Introduction
1.1 Description
The Texas Instruments PCI1520, a 208-terminal dual-slot CardBus controller designed to meet the PCI Bus Power
Management Interface Specification for PCI to CardBus Bridges, is an ultralow-power high-performance
PCI-to-CardBus controller that supports two independent card sockets compliant with the PC Card Standard (rev.
7.1). The PCI1520 provides features that make it the best choice for bridging between PCI and PC Cards in both
notebook and desktop computers. The 1997 PC Card Standard retains the 16-bit PC Card specification defined in
PCI Local Bus Specification and defines the new 32-bit PC Card, CardBus, capable of full 32-bit data transfers at
33 MHz. The PCI1520 supports any combination of 16-bit and CardBus PC Cards in the two sockets, powered at
5 V or 3.3 V, as required.
The PCI1520 is compliant with the PCI Local Bus Specification, and its PCI interface can act as either a PCI master
device or a PCI slave device. The PCI bus mastering is initiated during CardBus PC Card bridging transactions. The
PCI1520 is also compliant with PCI Bus Power Management Interface Specification (rev. 1.1).
All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1520 is
register-compatible with the Intel 82365SL-DF and 82365SL ExCA controllers. The PCI1520 internal data path logic
allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent
buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The
PCI1520 can also be programmed to accept fast posted writes to improve system-bus utilization.
Multiple system-interrupt signaling options are provided, including parallel PCI, parallel ISA, serialized ISA, and
serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to implement
sideband functions. Many other features designed into the PCI1520, such as socket activity light-emitting diode (LED)
outputs, are discussed in detail throughout the design specification.
An advanced complementary metal-oxide semiconductor (CMOS) process achieves low system power consumption
while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power management
system to further reduce power consumption.
1.2 Features
The PCI1520-EP supports the following features:
• Controlled Baseline
– One Assembly/Test Site, One Fabrication Site
• Extended Temperature Performance of –40°C to 85°C
• Enhanced Diminishing Manufacturing Sources (DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree
• A 209-terminal MicroStar BGA ball-grid array (GHK) package
• 2.5-V core logic and 3.3-V I/O with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling
environments
• Integrated low-dropout voltage regulator (LDO-VR) eliminates the need for an external 2.5-V power supply
†
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range.
This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this
component beyond specified performance and environmental limits.
†
1–1
• Mix-and-match 5-V/3.3-V 16-bit PC Cards and 3.3-V CardBus Cards
• Two PC Card or CardBus slots with hot insertion and removal
• Serial interface to TI TPS222X dual-slot PC Card power switch
• Burst transfers to maximize data throughput with CardBus Cards
• Interrupt configurations: parallel PCI, serialized PCI, parallel ISA, and serialized ISA
• Serial EEPROM interface for loading subsystem ID and subsystem vendor ID
• Pipelined architecture for greater than 130-Mbps throughput from CardBus-to-PCI and from
PCI-to-CardBus
• Up to five general-purpose I/Os
• Programmable output select for CLKRUN
• Multifunction PCI device with separate configuration space for each socket
• Five PCI memory windows and two I/O windows available for each 16-bit interface
• Two I/O windows and two memory windows available to each CardBus socket
• Exchangeable-card-architecture- (ExCA-) compatible registers are mapped in memory and I/O space
• Intel 82365SL-DF and 82365SL register compatible
• Ring indicate, SUSPEND
• Socket activity LED terminals
• PCI bus lock (LOCK
• Advanced quarter-micron, ultralow-power CMOS technology
• Internal ring oscillator
, PCI CLKRUN, and CardBus CCLKRUN
)
1.3 Related Documents
• Advanced Configuration and Power Interface (ACPI) Specification (revision 1.1)
• PCI Bus Power Management Interface Specification (revision 1.1)
• PCI Bus Power Management Interface Specification for PCI to CardBus Bridges (revision 0.6)
• PCI to PCMCIA CardBus Bridge Register Description (Yenta) (revision 2.1)
• PCI Local Bus Specification (revision 2.2)
• PCI Mobile Design Guide (revision 1.0)
• PC Card Standard (revision 7.1)
• PC 2001
• Serialized IRQ Support for PCI Systems (revision 6)
1.4 Trademarks
Intel is a trademark of Intel Corporation.
TI and MicroStar BGA are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.
1.5 Ordering Information
TEMPERATURE PACKAGE ORDERING NUMBER TOP-SIDE MARKING
–40°C to 85°C 209-ball PBGA PCI1520IGHKEP PCI1520IEP
1–2
1.6 PCI1520-EP Data Manual Document History
DATE PAGE NUMBER REVISION
05/2003 Original draft
1–3
2 Terminal Descriptions
The PCI1520 is available in a 209-terminal MicroStar BGA package (GHK). The terminal layout for the GHK
package is shown in Figure 2–1.
GHK PLASTIC BALL GRID ARRAY (PBGA) PACKAGE
BOTTOM VIEW
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
2
1
75634
18
19171613 14 1511 129810
Figure 2–1. PCI1520 GHK-Package Terminal Diagram
Table 2–1 lists the terminal assignments arranged in terminal-number order, with corresponding signal names for
both CardBus and 16-bit PC Cards; Table 2–1 is for terminals on the GHK package. Table 2–2 and Table 2–3 list
the terminal assignments arranged in alphanumerical order by signal name, with corresponding terminal numbers
for GHK package; Table 2–2 is for CardBus signal names and Table 2–3 is for 16-bit PC Card signal names.
Terminal E5 on the GHK package is an identification ball used for device orientation; it has no internal connection
within the device.
2–1
Table 2–1. Signal Names by GHK Terminal Number
TERM.
NO.
A04 AD12 AD12 E07 PERR PERR H06 AD2 AD2
A05 PAR PAR E08 FRAME FRAME H14 A_CSTSCHG A_BVD1(STSCHG/RI)
A06 GND GND E09 AD19 AD19 H15 A_CCLKRUN A_WP(IOIS16)
A07 V
A08 AD18 AD18 E11 AD27 AD27 H18 A_CSERR A_WAIT
A09 GND GND E12 AD31 AD31 H19 A_CINT A_READY(IREQ)
A10 V
A11 AD29 AD29 E14 MFUNC2 MFUNC2 J02 B_CAD3 B_D5
A12 V
A13 REQ REQ E18 LATCH LATCH J05 B_CAD5 B_D6
A14 GND GND E19 A_CAD31 A_D10 J06 B_RSVD B_D14
A15 MFUNC5 MFUNC5 F01 AD3 AD3 J14 A_CAD26 A_A0
A16 MFUNC1 MFUNC1 F02 AD5 AD5 J15 A_CVS1 A_VS1
B05 AD15 AD15 F03 AD6 AD6 J17 A_CAD25 A_A1
B06 STOP STOP F05 AD8 AD8 J18 A_CAD24 A_A2
B07 IRDY IRDY F06 C/BE1 C/BE1 J19 V
B08 AD17 AD17 F07 DEVSEL DEVSEL K01 GND GND
B09 AD22 AD22 F08 C/BE2 C/BE2 K02 B_CAD7 B_D7
B10 AD24 AD24 F09 AD20 AD20 K03 B_CAD8 B_D15
B11 AD28 AD28 F10 AD23 AD23 K05 B_CC/BE0 B_CE1
B12 AD11 AD11 F11 AD26 AD26 K06 B_CAD9 B_A10
B13 GNT GNT F12 AD25 AD25 K14 A_CC/BE3 A_REG
B14 C/BE3 C/BE3 F13 MFUNC3/IRQSER MFUNC3/IRQSER K15 A_CAD23 A_A3
B15 MFUNC4 MFUNC4 F14 SPKROUT SPKROUT K17 A_CREQ A_INPACK
C05 AD13 AD13 F15 CLOCK CLOCK K18 A_CAD22 A_A4
C06 SERR SERR F17 A_RSVD A_D2 K19 VR_PORT VR_PORT
C07 TRDY TRDY F18 A_CAD29 A_D1 L01 VR_EN VR_EN
C08 AD16 AD16 F19 GND GND L02 B_CAD10 B_CE2
C09 AD21 AD21 G01 V
C10 PCLK PCLK G02 AD0 AD0 L05 B_CAD13 B_IORD
C11 GRST GRST G03 AD1 AD1 L06 B_CAD12 B_A11
C12 AD30 AD30 G05 AD4 AD4 L14 A_CAD21 A_A5
C13 PRST PRST G06 C/BE0 C/BE0 L15 A_CRST A_RESET
C14 MFUNC6/
C15 SUSPEND SUSPEND G15 A_CAD30 A_D9 L18 A_CVS2 A_VS2
D01 AD10 AD10 G17 A_CAD27 A_D0 L19 A_CAD19 A_A25
D19 MFUNC0 MFUNC0 G18 A_CCD2 A_CD2 M01 B_CAD15 B_IOWR
E01 GND GND G19 V
E02 AD7 AD7 H01 B_CAD1 B_D4 M03 B_CAD16 B_A17
E03 AD9 AD9 H02 B_CAD2 B_D11 M05 B_RSVD B_A18
E05 NC NC H03 B_CAD0 B_D3 M06 B_CC/BE1 B_A8
E06 AD14 AD14 H05 B_CCD1 B_CD1 M14 A_CCLK A_A16
SIGNAL NAME
CardBus
PC Card
CC
CCP
CC
CLKRUN
16-Bit
PC Card
V
CC
V
CCP
V
CC
MFUNC6/
CLKRUN
TERM.
NO.
E10 IDSEL IDSEL H17 A_CAUDIO A_BVD2(SPKR)
E13 RI_OUT/PME RI_OUT/PME J01 B_CAD4 B_D12
E17 DATA DATA J03 B_CAD6 B_D13
G14 A_CAD28 A_D8 L17 A_CAD20 A_A6
CardBus
PC Card
CC
CC
SIGNAL NAME
16-Bit
PC Card
V
CC
V
CC
TERM.
NO.
L03 B_CAD11 B_OE
M02 B_CAD14 B_A9
CardBus
PC Card
SIGNAL NAME
CC
16-Bit
PC Card
V
CC
2–2
Table 2–1. Signal Names by GHK Terminal Number (Continued)
TERM.
NO.
M15 A_CFRAME A_A23 P17 A_CSTOP A_A20 U13 A_CAD7 A_D7
M17 A_CC/BE2 A_A12 P18 A_CGNT A_WE U14 A_CAD10 A_CE2
M18 A_CAD17 A_A24 P19 V
M19 A_CAD18 A_A7 R01 V
N01 V
N02 B_CPAR B_A13 R03 B_CFRAME B_A23 V07 B_CAD24 B_A2
N03 B_CBLOCK B_A19 R06 B_CAD19 B_A25 V08 B_CINT B_READY(IREQ)
N05 B_CGNT B_WE R07 B_CREQ B_INPACK V09 B_CAUDIO B_BVD2(SPKR)
N06 B_CPERR B_A14 R08 B_CAD26 B_A0 V10 B_CAD28 B_D8
N14 A_CBLOCK A_A19 R09 B_CCLKRUN B_WP(IOIS16) V11 B_CAD31 B_D10
N15 A_CDEVSEL A_A21 R10 B_CAD30 B_D9 V12 A_CAD4 A_D12
N17 A_CTRDY A_A22 R11 A_CAD2 A_D11 V13 A_RSVD A_D14
N18 A_CIRDY A_A15 R12 A_CAD5 A_D6 V14 A_CC/BE0 A_CE1
N19 V
P01 GND GND R14 A_CAD15 A_IOWR W04 B_CAD17 B_A24
P02 B_CSTOP B_A20 R17 A_RSVD A_A18 W05 B_CRST B_RESET
P03 B_CDEVSEL B_A21 R18 A_CPERR A_A14 W06 GND GND
P05 B_CIRDY B_A15 R19 GND GND W07 B_CAD25 B_A1
P06 B_CCLK B_A16 T01 B_CC/BE2 B_A12 W08 V
P07 B_CVS2 B_VS2 T19 A_CC/BE1 A_A8 W09 B_CSERR B_WAIT
P08 B_CAD23 B_A3 U05 B_CAD18 B_A7 W10 B_CAD27 B_D0
P09 B_CCD2 B_CD2 U06 B_CAD21 B_A5 W11 NC
P10 B_RSVD B_D2 U07 B_CC/BE3 B_REG W12 A_CAD1 A_D4
P11 A_CAD0 A_D3 U08 B_CVS1 B_VS1 W13 V
P12 A_CAD6 A_D13 U09 B_CSTSCHG B_BVD1(STSCHG/RI) W14 GND GND
P13 A_CAD8 A_D15 U10 B_CAD29 B_D1 W15 A_CAD11 A_OE
P14 A_CAD12 A_A11 U11 A_CCD1 A_CD1 W16 A_CAD16 A_A17
P15 A_CPAR A_A13 U12 A_CAD3 A_D5
†
Terminal W11 is an NC on the PCI1520 to allow for terminal compatibility with the next generation of devices.
SIGNAL NAME
CardBus
PC Card
CC
CC
16-Bit
PC Card
V
CC
V
CC
TERM.
NO.
R02 B_CTRDY B_A22 V06 B_CAD22 B_A4
R13 A_CAD9 A_A10 V15 A_CAD13 A_IORD
CardBus
PC Card
SIGNAL NAME
CCA
CCB
16-Bit
PC Card
V
CCA
V
CCB
TERM.
NO.
U15 A_CAD14 A_A9
V05 B_CAD20 B_A6
SIGNAL NAME
CardBus
PC Card
CC
†
CC
16-Bit
PC Card
V
NC
V
CC
†
CC
2–3
Table 2–2. CardBus PC Card Signal Names Sorted Alphabetically
SIGNAL NAME
A_CAD0 P11 A_CDEVSEL N15 AD24 B10
A_CAD1 W12 A_CFRAME M15 AD25 F12
A_CAD2 R11 A_CGNT P18 AD26 F11
A_CAD3 U12 A_CINT H19 AD27 E11
A_CAD4 V12 A_CIRDY N18 AD28 B11
A_CAD5 R12 A_CPAR P15 AD29 A11
A_CAD6 P12 A_CPERR R18 AD30 C12
A_CAD7 U13 A_CREQ K17 AD31 E12
A_CAD8 P13 A_CRST L15 B_CAD0 H03
A_CAD9 R13 A_CSERR H18 B_CAD1 H01
A_CAD10 U14 A_CSTOP P17 B_CAD2 H02
A_CAD11 W15 A_CSTSCHG H14 B_CAD3 J02
A_CAD12 P14 A_CTRDY N17 B_CAD4 J01
A_CAD13 V15 A_CVS1 J15 B_CAD5 J05
A_CAD14 U15 A_CVS2 L18 B_CAD6 J03
A_CAD15 R14 A_RSVD R17 B_CAD7 K02
A_CAD16 W16 A_RSVD V13 B_CAD8 K03
A_CAD17 M18 A_RSVD F17 B_CAD9 K06
A_CAD18 M19 AD0 G02 B_CAD10 L02
A_CAD19 L19 AD1 G03 B_CAD11 L03
A_CAD20 L17 AD2 H06 B_CAD12 L06
A_CAD21 L14 AD3 F01 B_CAD13 L05
A_CAD22 K18 AD4 G05 B_CAD14 M02
A_CAD23 K15 AD5 F02 B_CAD15 M01
A_CAD24 J18 AD6 F03 B_CAD16 M03
A_CAD25 J17 AD7 E02 B_CAD17 W04
A_CAD26 J14 AD8 F05 B_CAD18 U05
A_CAD27 G17 AD9 E03 B_CAD19 R06
A_CAD28 G14 AD10 D01 B_CAD20 V05
A_CAD29 F18 AD11 B12 B_CAD21 U06
A_CAD30 G15 AD12 A04 B_CAD22 V06
A_CAD31 E19 AD13 C05 B_CAD23 P08
A_CAUDIO H17 AD14 E06 B_CAD24 V07
A_CBLOCK N14 AD15 B05 B_CAD25 W07
A_CC/BE0 V14 AD16 C08 B_CAD26 R08
A_CC/BE1 T19 AD17 B08 B_CAD27 W10
A_CC/BE2 M17 AD18 A08 B_CAD28 V10
A_CC/BE3 K14 AD19 E09 B_CAD29 U10
A_CCD1 U11 AD20 F09 B_CAD30 R10
A_CCD2 G18 AD21 C09 B_CAD31 V11
A_CCLK M14 AD22 B09 B_CAUDIO V09
A_CCLKRUN H15 AD23 F10 B_CBLOCK N03
TERM NO.
GHK
SIGNAL NAME
TERM. NO.
GHK
SIGNAL NAME
TERM. NO.
GHK
2–4
Table 2–2. CardBus PC Card Signal Names Sorted Alphabetically (Continued)
SIGNAL NAME
B_CC/BE0 K05 C/BE2 F08 NC E05
B_CC/BE1 M06 C/BE3 B14 NC
B_CC/BE2 T01 CLOCK F15 PAR A05
B_CC/BE3 U07 DATA E17 PCLK C10
B_CCD1 H05 DEVSEL F07 PERR E07
B_CCD2 P09 FRAME E08 PRST C13
B_CCLK P06 GND A06 REQ A13
B_CCLKRUN R09 GND A09 RI_OUT/PME E13
B_CDEVSEL P03 GND A14 SERR C06
B_CFRAME R03 GND E01 SPKROUT F14
B_CGNT N05 GND K01 STOP B06
B_CINT V08 GND P01 SUSPEND C15
B_CIRDY P05 GND R19 TRDY C07
B_CPAR N02 GND W06 V
B_CPERR N06 GND F19 V
B_CREQ R07 GND W14 V
B_CRST W05 GNT B13 V
B_CSERR W09 GRST C11 V
B_CSTOP P02 IDSEL E10 V
B_CSTSCHG U09 IRDY B07 V
B_CTRDY R02 LATCH E18 V
B_CVS1 U08 MFUNC0 D19 V
B_CVS2 P07 MFUNC1 A16 V
B_RSVD J06 MFUNC2 E14 V
B_RSVD M05 MFUNC3/IRQSER F13 V
B_RSVD P10 MFUNC4 B15 VR_EN L01
C/BE0 G06 MFUNC5 A15 VR_PORT K19
C/BE1 F06 MFUNC6/CLKRUN C14
†
Terminals 81 and W11 are NC on the PCI1520 to allow for terminal compatibility with the next generation of devices.
TERM NO.
GHK
SIGNAL NAME
TERM NO.
GHK
SIGNAL NAME
†
CC
CC
CC
CC
CC
CC
CC
CC
CC
CCA
CCB
CCP
TERM NO.
GHK
W11
A07
A12
G01
G19
J19
N01
N19
W08
W13
P19
R01
A10
2–5
Table 2–3. 16-Bit PC Card Signal Names Sorted Alphabetically
SIGNAL NAME
A_A0 J14 A_D10 E19 AD24 B10
A_A1 J17 A_D11 R11 AD25 F12
A_A2 J18 A_D12 V12 AD26 F11
A_A3 K15 A_D13 P12 AD27 E11
A_A4 K18 A_D14 V13 AD28 B11
A_A5 L14 A_D15 P13 AD29 A11
A_A6 L17 A_INPACK K17 AD30 C12
A_A7 M19 A_IORD V15 AD31 E12
A_A8 T19 A_IOWR R14 B_A0 R08
A_A9 U15 A_OE W15 B_A1 W07
A_A10 R13 A_READY(IREQ) H19 B_A2 V07
A_A11 P14 A_REG K14 B_A3 P08
A_A12 M17 A_RESET L15 B_A4 V06
A_A13 P15 A_VS1 J15 B_A5 U06
A_A14 R18 A_VS2 L18 B_A6 V05
A_A15 N18 A_WAIT H18 B_A7 U05
A_A16 M14 A_WE P18 B_A8 M06
A_A17 W16 A_WP(IOIS16) H15 B_A9 M02
A_A18 R17 AD0 G02 B_A10 K06
A_A19 N14 AD1 G03 B_A11 L06
A_A20 P17 AD2 H06 B_A12 T01
A_A21 N15 AD3 F01 B_A13 N02
A_A22 N17 AD4 G05 B_A14 N06
A_A23 M15 AD5 F02 B_A15 P05
A_A24 M18 AD6 F03 B_A16 P06
A_A25 L19 AD7 E02 B_A17 M03
A_BVD1(STSCHG/RI) H14 AD8 F05 B_A18 M05
A_BVD2(SPKR) H17 AD9 E03 B_A19 N03
A_CD1 U11 AD10 D01 B_A20 P02
A_CD2 G18 AD11 B12 B_A21 P03
A_CE1 V14 AD12 A04 B_A22 R02
A_CE2 U14 AD13 C05 B_A23 R03
A_D0 G17 AD14 E06 B_A24 W04
A_D1 F18 AD15 B05 B_A25 R06
A_D2 F17 AD16 C08 B_BVD1(STSCHG/RI) U09
A_D3 P11 AD17 B08 B_BVD2(SPKR) V09
A_D4 W12 AD18 A08 B_CD1 H05
A_D5 U12 AD19 E09 B_CD2 P09
A_D6 R12 AD20 F09 B_CE1 K05
A_D7 U13 AD21 C09 B_CE2 L02
A_D8 G14 AD22 B09 B_D0 W10
A_D9 G15 AD23 F10 B_D1 U10
TERM. NO.
GHK
SIGNAL NAME
TERM. NO.
GHK
SIGNAL NAME
TERM NO.
GHK
2–6
Table 2–3. 16-Bit PC Card Signal Names Sorted Alphabetically (Continued)
SIGNAL NAME
B_D2 P10 C/BE2 F08 NC E05
B_D3 H03 C/BE3 B14 NC
B_D4 H01 CLOCK F15 PAR A05
B_D5 J02 DATA E17 PCLK C10
B_D6 J05 DEVSEL F07 PERR E07
B_D7 K02 FRAME E08 PRST C13
B_D8 V10 GND A06 REQ A13
B_D9 R10 GND A09 RI_OUT/PME E13
B_D10 V11 GND A14 SERR C06
B_D11 H02 GND E01 SPKROUT F14
B_D12 J01 GND K01 STOP B06
B_D13 J03 GND P01 SUSPEND C15
B_D14 J06 GND R19 TRDY C07
B_D15 K03 GND W06 V
B_INPACK R07 GND F19 V
B_IORD L05 GND W14 V
B_IOWR M01 GNT B13 V
B_OE L03 GRST C11 V
B_READY(IREQ) V08 IDSEL E10 V
B_REG U07 IRDY B07 V
B_RESET W05 LATCH E18 V
B_VS1 U08 MFUNC0 D19 V
B_VS2 P07 MFUNC1 A16 V
B_WAIT W09 MFUNC2 E14 V
B_WE N05 MFUNC3/IRQSER F13 V
B_WP(IOIS16) R09 MFUNC4 B15 VR_EN L01
C/BE0 G06 MFUNC5 A15 VR_PORT K19
C/BE1 F06 MFUNC6/CLKRUN C14
†
Terminals 81 and W11 are NC on the PCI1520 to allow for terminal compatibility with the next generation of devices.
TERM NO.
GHK
SIGNAL NAME
TERM NO.
GHK
SIGNAL NAME
†
CC
CC
CC
CC
CC
CC
CC
CC
CC
CCA
CCB
CCP
TERM NO.
GHK
W11
A07
A12
G01
G19
J19
N01
N19
W08
W13
P19
R01
A10
2–7
The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The
I/O
DESCRIPTION
I/O
DESCRIPTION
I/O
DESCRIPTION
terminal numbers are also listed for convenient reference.
Table 2–4. Power Supply Terminals
TERMINAL
NAME
GND
V
CC
V
CCA
V
CCB
V
CCP
VR_EN L01 I Internal voltage regulator enable. Active-low
VR_PORT K19 I/O
NO.
GHK
A06, A09, A14,
E01, F19, K01,
P01, R19, W06,
W14
A07, A12, G01,
G19, J19, N01,
N19, W08, W13
P19 – Clamp voltage for PC Card A interface. Matches card A signaling environment, 5 V or 3.3 V
R01 – Clamp voltage for PC Card B interface. Matches card B signaling environment, 5 V or 3.3 V
A10 – Clamp voltage for PCI and miscellaneous I/O, 5 V or 3.3 V
I/O DESCRIPTION
Device ground terminals
–
Power supply terminal for I/O and internal voltage regulator
–
Internal voltage regulator input/output. When VR_EN is low, the regulator is enabled and this terminal
is an output. An external bypass capacitor is required on this terminal. When VR_EN is high, the regulator is disabled and this terminal is an input for an external 2.5-V core power source.
Table 2–5. PC Card Power Switch Terminals
TERMINAL
NO.
NAME
CLOCK F15 I/O
DATA E17 O Power switch data. DATA is used to communicate socket power control information serially to the power switch.
LATCH E18 I/O
GHK
I/O DESCRIPTION
Power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK. CLOCK defaults to an
input, but can be changed to a PCI1520 output by using bit 27 (P2CCLK) in the system control register (offset 80h, see
Section 4.29). The TPS222X defines the maximum frequency of this signal to be 2 MHz. However, PCI1520 requires a
16-KHz to 100-KHz frequency range. If a system design defines this terminal as an output, then this terminal requires
an external pulldown resistor. The frequency of the PCI1520 output CLOCK is derived from the internal ring oscillator
(16 KHz typical).
Power switch latch. LA TCH is asserted by the PCI1520 to indicate to the power switch that the data on the DAT A line is
valid. When a pulldown resistor is implemented on this terminal, the MFUNC1 and MFUNC4 terminals provide the
serial EEPROM SDA and SCL interface.
TERMINAL
NAME
GRST C11 I
PCLK C10 I
PRST
2–8
NO.
GHK
C13 I
Table 2–6. PCI System Terminals
I/O DESCRIPTION
Global reset. When the global reset is asserted, the GRST signal causes the PCI1520 to place all output buffers in
a high-impedance state and reset all internal registers. When GRST
state. For systems that require wake-up from D3, GRST
be asserted following initial boot so that PME context is retained during the transition from D3 to D0. For systems
that do not require wake-up from D3, GRST
When the SUSPEND
All outputs are placed in a high-impedance state.
PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising
edge of PCLK.
PCI reset. When the PCI bus reset is asserted, PRST causes the PCI1520 to place all output buffers in a
high-impedance state and reset internal registers. When PRST
only if it is enabled. After PRST
When the SUSPEND
All outputs are placed in a high-impedance state.
mode is enabled, the device is protected from GRST , and the internal registers are preserved.
is deasserted, the PCI1520 is in a default state.
mode is enabled, the device is protected from PRST , and the internal registers are preserved.
should be tied to PRST.
normally is asserted only during initial boot. PRST should
is asserted, the device is completely in its default
is asserted, the device can generate the PME signal
TERMINAL
I/O
DESCRIPTION
NAME
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
C/BE3
C/BE2
C/BE1
C/BE0
PAR A05 I/O
NO.
GHK
E12
C12
A11
B11
E11
F11
F12
B10
F10
B09
C09
F09
E09
A08
B08
C08
B05
E06
C05
A04
B12
D01
E03
F05
E02
F03
F02
G05
F01
H06
G03
G02
B14
F08
F06
G06
Table 2–7. PCI Address and Data Terminals
I/O DESCRIPTION
PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary interface.
During the address phase of a primary-bus PCI cycle, AD31–AD0 contain a 32-bit address or other destination
I/O
information. During the data phase, AD31–AD0 contain data.
PCI-bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address
phase of a primary-bus PCI cycle, C/BE3
used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data.
I/O
C/BE0 applies to byte 0 (AD7–AD0), C/BE1 applies to byte 1 (AD15–AD8), C/BE2 applies to byte 2 (AD23–AD16),
and C/BE3
PCI-bus parity. In all PCI-bus read and write cycles, the PCI1520 calculates even parity across the AD31–AD0 and
C/BE3
delay. As a target during PCI cycles, the PCI1520 compares its calculated parity to the parity indicator of the initiator.
A compare error results in the assertion of a parity error (PERR).
applies to byte 3 (AD31–AD24).
–C/BE0 buses. As an initiator during PCI cycles, the PCI1520 outputs this parity indicator with a one-PCLK
–C/BE0 define the bus command. During the data phase, this 4-bit bus is
2–9
TERMINAL
I/O
DESCRIPTION
NAME
DEVSEL
FRAME
GNT
IDSEL E10 I
IRDY
PERR
REQ
SERR
STOP
TRDY
NO.
GHK
F07 I/O
E08 I/O
B13 I
B07 I/O
E07 I/O
A13 O PCI bus request. REQ is asserted by the PCI1520 to request access to the PCI bus as an initiator.
C06 O
B06 I/O
C07 I/O
Table 2–8. PCI Interface Control Terminals
I/O DESCRIPTION
PCI device select. The PCI1520 asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator on the
bus, the PCI1520 monitors DEVSEL
PCI1520 terminates the cycle with an initiator abort.
PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus transaction
is beginning, and data transfers continue while this signal is asserted. When FRAME
transaction is in the final data phase.
PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1520 access to the PCI bus after the current data
transaction has completed. GNT
algorithm.
Initialization device select. IDSEL selects the PCI1520 during configuration space accesses. IDSEL can be
connected to one of the upper 24 PCI address lines on the PCI bus.
PCI initiator ready. IRDY indicates the ability of the PCI bus initiator to complete the current data phase of the
transaction. A data phase is completed on a rising edge of PCLK where both IRDY
and TRDY are both sampled asserted, wait states are inserted.
PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not match P AR when
PERR
is enabled through bit 6 of the command register (PCI offset 04h, see Section 4.4).
PCI system error. SERR is an output that is pulsed from the PCI1520 when enabled through bit 8 of the command
register (PCI offset 04h, see Section 4.4) indicating a system error has occurred. The PCI1520 need not be the target
of the PCI cycle to assert this signal. When SERR
indicating that an address parity error has occurred on a CardBus interface.
PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus transaction.
STOP
is used for target disconnects and is commonly asserted by target devices that do not support burst data
transfers.
PCI target ready. TRDY indicates the ability of the primary bus target to complete the current data phase of the
transaction. A data phase is completed on a rising edge of PCLK when both IRDY
and TRDY are asserted, wait states are inserted.
IRDY
until a target responds. If no target responds before timeout occurs, then the
is deasserted, the PCI bus
may or may not follow a PCI bus request, depending on the PCI bus parking
and TRDY are asserted. Until IRDY
is enabled in the command register, this signal also pulses,
and TRDY are asserted. Until both
2–10
TERMINAL
I/O
DESCRIPTION
NAME
MFUNC0 D19 I/O
MFUNC1 A16 I/O
MFUNC2 E14 I/O
MFUNC3/
IRQSER
MFUNC4 B15 I/O
MFUNC5 A15 I/O
MFUNC6/
CLKRUN
NC
RI_OUT/PME E13 O
SPKROUT
SUSPEND C15 I
NO.
GHK
F13 I/O
C14 I/O
E05
W11
F14 O
Table 2–9. Multifunction and Miscellaneous Terminals
I/O DESCRIPTION
Multifunction terminal 0. MFUNC0 can be configured as parallel PCI interrupt INT A, GPI0, GPO0, socket activity
LED output, ZV switching output, CardBus audio PWM, GPE
Routing Register, for configuration details.
Multifunction terminal 1. MFUNC1 can be configured as parallel PCI interrupt INTB, GPI1, GPO1, socket activity
LED output, ZV switching output, CardBus audio PWM, GPE
Routing Register, for configuration details.
Serial data (SDA). When LATCH is detected low after the deassertion of GRST
the SDA signaling for the serial bus interface. The two-terminal serial interface loads the subsystem identification
and other register defaults from an EEPROM after a PCI reset. See Section 3.6.1, Serial Bus Interface
Implementation, for details on other serial bus applications.
Multifunction terminal 2. MFUNC2 can be configured as GPI2, GPO2, socket activity LED output, ZV switching
output, CardBus audio PWM, GPE
Routing Register, for configuration details.
Multifunction terminal 3. MFUNC3 can be configured as a parallel IRQ or the serialized interrupt signal IRQSER.
This terminal is IRQSER by default. See Section 4.30, Multifunction Routing Register, for configuration details.
Multifunction terminal 4. MFUNC4 can be configured as PCI LOCK, GPI3, GPO3, socket activity LED output,
ZV switching output, CardBus audio PWM, GPE
Multifunction Routing Register , for configuration details.
Serial clock (SCL). When LATCH is detected low after the deassertion of GRST
the SCL signaling for the serial bus interface. The two-terminal serial interface loads the subsystem identification
and other register defaults from an EEPROM after a PCI reset. See Section 3.6.1, Serial Bus Interface
Implementation, for details on other serial bus applications.
Multifunction terminal 5. MFUNC5 can be configured as GPI4, GPO4, socket activity LED output, ZV switching
output, CardBus audio PWM, D3_STAT
Register, for configuration details.
Multifunction terminal 6. MFUNC6 can be configured as a PCI CLKRUN or a parallel IRQ. See Section 4.30,
Multifunction Routing Register , for configuration details.
No connect. These terminals have no connection anywhere within the package. Terminal E05 on the GHK
package is used as a key to indicate the location of the A1 corner of the BGA package. Terminals W11 on the
GHK package and 81 on the PDV package will be used as a 48-MHz clock input on future-generation devices.
Ring indicate out and power management event output. This terminal provides an output for ring-indicate or PME
signals.
Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO through the
PCI1520 from the PC Card interface. SPKROUT is driven as the exclusive-OR combination of card
SPKR//CAUDIO inputs.
Suspend. SUSPEND protects the internal registers from clearing when the GRST or PRST signal is asserted.
See Section 3.8.5, Suspend Mode, for details.
, RI_OUT, D3_STAT, or a parallel IRQ. See Section 4.30, Multifunction
, D3_STAT, RI_OUT, or a parallel IRQ. See Section 4.30,
, GPE, or a parallel IRQ. See Section 4.30, Multifunction Routing
, or a parallel IRQ. See Section 4.30, Multifunction
, or a parallel IRQ. See Section 4.30, Multifunction
, the MFUNC1 terminal provides
, the MFUNC4 terminal provides
2–11
Table 2–10. 16-Bit PC Card Address and Data Terminals (Slots A and B)
TERMINAL
NUMBER
NAME
†
Terminal name for slot A is preceded with A_. For example, the full name for terminals 123 and L19 is A_A25.
‡
Terminal name for slot B is preceded with B_. For example, the full name for terminals 55 and R06 is B_A25.
SLOT
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SLOT
†
A
B
GHK GHK
L19
N17
N15
P17
N14
R17
N18
R18
P15
P14
R13
U15
T19
L17
L14
K18
K15
J18
J17
J14
P13
V13
P12
V12
R11
E19
U13
R12
U12
P11
F17
F18
R06
W04
R03
R02
P03
P02
N03
M05
M03
P06
P05
N06
N02
T01
L06
K06
M02
M06
U05
V05
U06
V06
P08
V07
W07
R08
K03
J06
J03
J01
H02
V11
R10
V10
K02
J05
J02
H01
H03
P10
U10
W10
M18
M15
W16
M14
M17
M19
G15
G14
W12
G17
I/O DESCRIPTION
‡
O PC Card address. 16-bit PC Card address lines. A25 is the most significant bit.
I/O PC Card data. 16-bit PC Card data lines. D15 is the most significant bit.
2–12
Table 2–11. 16-Bit PC Card Interface Control Terminals (Slots A and B)
TERMINAL
NUMBER
SLOT
NAME
BVD1
(STSCHG
†
Terminal name for slot A is preceded with A_. For example, the full name for terminals 130 and K17 is A_INPACK
‡
Terminal name for slot B is preceded with B_. For example, the full name for terminals 61 and R07 is B_INPACK
/RI)
BVD2
(SPKR
)
CD1
CD2
CE1
CE2
INPACK K17 R07 I
IORD
IOWR
SLOT
†
A
GHK GHK
H14 U09 I
H17 V09 I
U11
H05
G18
P09
V14
K05
U14
V15 L05 O
R14 M01 O
L02
I/O DESCRIPTION
‡
B
Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries. BVD1
is used with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both BVD1
and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak
and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the
memory PC Card is lost. See Section 5.6, ExCA Card Status-Change Interrupt Configuration
Register, for enable bits. See Section 5.5, ExCA Card Status-Change Register, and Section 5.2,
ExCA Interface Status Register, for the status bits for this signal.
Status change. STSCHG
battery voltage dead condition of a 16-bit I/O PC Card.
Ring indicate. RI
Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include batteries. BVD2
is used with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both BVD1
and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak
and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the
memory PC Card is lost. See Section 5.6, ExCA Card Status-Change Interrupt Configuration
Register, for enable bits. See Section 5.5, ExCA Card Status-Change Register, and Section 5.2,
ExCA Interface Status Register, for the status bits for this signal.
Speaker. SPKR
configured for the 16-bit I/O interface. The audio signals from cards A and B are combined by the
PCI1520 and are output on SPKROUT.
Card detect 1 and card detect 2. CD1 and CD2 are internally connected to ground on the PC Card.
When a PC Card is inserted into a socket, CD1
I
Section 5.2, ExCA Interface Status Register.
Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address bytes. CE1
O
enables even-numbered address bytes, and CE2 enables odd-numbered address bytes.
Input acknowledge. INPACK is asserted by the PC Card when it can respond to an I/O read cycle
at the current address.
I/O read. IORD is asserted by the PCI1520 to enable 16-bit I/O PC Card data output during host I/O
read cycles.
I/O write. IOWR is driven low by the PCI1520 to strobe write data into 16-bit I/O PC Cards during host
I/O write cycles.
is used by 16-bit modem cards to indicate a ring detection.
is an optional binary audio signal available only when the card and socket have been
is used to alert the system to a change in the READY, write protect, or
and CD2 are pulled low. For signal status, see
.
.
2–13
Table 2–11. 16-Bit PC Card Interface Control Terminals (Slots A and B) (Continued)
TERMINAL
NUMBER
SLOT
NAME
OE W15 L03 O
READY
(IREQ
)
REG
RESET L15 W05 O PC Card reset. RESET forces a hard reset to a 16-bit PC Card.
VS1
VS2
WAIT
WE P18 N05 O
WP
(IOIS16
)
†
Terminal name for slot A is preceded with A_. For example, the full name for terminals 112 and P18 is A_WE
‡
Terminal name for slot B is preceded with B_. For example, the full name for terminals 45 and N05 is B_WE.
SLOT
†
A
GHK GHK
H19 V08 I
K14 U07 O
J15
L18
H18 W09 I
H15 R09 I
I/O DESCRIPTION
‡
B
Output enable. OE is driven low by the PCI1520 to enable 16-bit memory PC Card data output during host
memory read cycles.
Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket are
configured for the memory-only interface. READY is driven low by 16-bit memory PC Cards to indicate
that the memory card circuits are busy processing a previous write command. READY is driven high when
the 16-bit memory PC Card is ready to accept a new data transfer command.
U08
P07
Interrupt request. IREQ
I/O PC Card requires service by the host software. IREQ
requested.
Attribute memory select. REG remains high for all common memory accesses. When REG is asserted,
access is limited to attribute memory (OE
Attribute memory is a separately accessed section of card memory and is generally used to record card
capacity and other configuration and attribute information.
Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other , determine
I/O
the operating voltage of the PC Card.
Bus cycle wait. WAIT is driven by a 16-bit PC Card to extend the completion of the memory or I/O cycle
in progress.
Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also used for
memory PC Cards that employ programmable memory technologies.
Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch
on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16
I/O is 16 bits. IOIS16
address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that
is addressed is capable of 16-bit accesses.
is asserted by a 16-bit I/O PC Card to indicate to the host that a device on the 16-bit
applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card when the
is high (deasserted) when no interrupt is
or WE active) and to the I/O space (IORD or IOWR active).
) function.
.
Table 2–12. CardBus PC Card Interface System Terminals (Slots A and B)
TERMINAL
NUMBER
NAME
CCLK M14 P06 O
CCLKRUN
CRST
†
Terminal name for slot A is preceded with A_. For example, the full name for terminals 115 and M14 is A_CCLK.
‡
Terminal name for slot B is preceded with B_. For example, the full name for terminals 48 and P06 is B_CCLK.
2–14
SLOT
SLOT
†
A
GHK GHK
H15 R09 I/O
L15 W05 O
I/O DESCRIPTION
‡
B
CardBus clock. CCLK provides synchronous timing for all transactions on the CardBus interface. All
signals except CRST
sampled on the rising edge of CCLK, and all timing parameters are defined with the rising edge of this
signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the low state or slowed
down for power savings.
CardBus clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the CCLK
frequency, and by the PCI1520 to indicate that the CCLK frequency is going to be decreased.
CardBus reset. CRST brings CardBus PC Card-specific registers, sequencers, and signals to a known
state. When CRST
the PCI1520 drives these signals to a valid logic level. Assertion can be asynchronous to CCLK, but
deassertion must be synchronous to CCLK.
, CCLKRUN, CINT, CSTSCHG, CAUDIO, CCD2, CCD1, CVS2, and CVS1 are
is asserted, all CardBus PC Card signals are placed in a high-impedance state, and
Table 2–13. CardBus PC Card Address and Data Terminals (Slots A and B)
TERMINAL
NUMBER
SLOT
NAME
CAD31
CAD30
CAD29
CAD28
CAD27
CAD26
CAD25
CAD24
CAD23
CAD22
CAD21
CAD20
CAD19
CAD18
CAD17
CAD16
CAD15
CAD14
CAD13
CAD12
CAD11
CAD10
CAD9
CAD8
CAD7
CAD6
CAD5
CAD4
CAD3
CAD2
CAD1
CAD0
CC/BE3
CC/BE2
CC/BE1
CC/BE0
CPAR P15 N02 I/O
†
Terminal name for slot A is preceded with A_. For example, the full name for terminals 107 and P15 is A_CPAR.
‡
Terminal name for slot B is preceded with B_. For example, the full name for terminals 40 and N02 is B_CPAR.
SLOT
†
A
GHK GHK
E19
G15
F18
G14
G17
K15
K18
L14
L17
L19
M19
M18
W16
R14
U15
V15
P14
W15
U14
R13
P13
U13
P12
R12
V12
U12
R11
W12
P11
K14
M17
T19
V14
J14
J17
J18
V11
R10
U10
V10
W10
R08
W07
V07
P08
V06
U06
V05
R06
U05
W04
M03
M01
M02
L05
L06
L03
L02
K06
K03
K02
J03
J05
J01
J02
H02
H01
H03
U07
T01
M06
K05
I/O DESCRIPTION
‡
B
CardBus address and data. These signals make up the multiplexed CardBus address and data bus on
the CardBus interface. During the address phase of a CardBus cycle, CAD31–CAD0 contain a 32-bit
I/O
address. During the data phase of a CardBus cycle, CAD31–CAD0 contain data. CAD31 is the most
significant bit.
CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the same CardBus
terminals. During the address phase of a CardBus cycle, CC/BE3
During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths
I/O
of the full 32-bit data bus carry meaningful data. CC/BE0 applies to byte 0 (CAD7–CAD0), CC/BE1 applies
to byte 1 (CAD15–CAD8), CC/BE2
(CAD31–CAD24).
CardBus parity. In all CardBus read and write cycles, the PCI1520 calculates even parity across the CAD
and CC/BE
delay. As a target during CardBus cycles, the PCI1520 compares its calculated parity to the parity indicator
of the initiator; a compare error results in a parity error assertion.
buses. As an initiator during CardBus cycles, the PCI1520 outputs CPAR with a one-CCLK
applies to byte 2 (CAD23–CAD16), and CC/BE3 applies to byte 3
–CC/BE0 define the bus command.
2–15
Table 2–14. CardBus PC Card Interface Control Terminals (Slots A and B)
CCD1
U11
H05
CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with CVS1 and
TERMINAL
NUMBER
NAME
CAUDIO H17 V09 I
CBLOCK
CCD1
CCD2
CDEVSEL
CFRAME
CGNT
CINT
CIRDY
CPERR
CREQ
CSERR
CSTOP
CSTSCHG
CTRDY
CVS1
CVS2
†
Terminal name for slot A is preceded with A_. For example, the full name for terminals 140 and H18 is A_CAUDIO.
‡
Terminal name for slot B is preceded with B_. For example, the full name for terminals 72 and V09 is B_CAUDIO.
SLOT
SLOT
†
A
GHK GHK
N14 N03 I/O
U11 H05
G18
M15 R03 I/O
P09
N15 P03 I/O
P18 N05 O
H19 V08 I
N18 P05 I/O
R18 N06 I/O
K17 R07 I
H18 W09 I
P17 P02 I/O
H14 U09 I
N17 R02 I/O
J15
U08
L18
P07
I/O DESCRIPTION
‡
B
CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The PCI1520
supports the binary audio mode and outputs a binary signal from the card to SPKROUT.
CardBus lock. CBLOCK is used to gain exclusive access to a target.
CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with CVS1 and
I
CVS2 to identify card insertion and interrogate cards to determine the operating voltage and card type.
CardBus device select. The PCI1520 asserts CDEVSEL to claim a CardBus cycle as the target device.
As a CardBus initiator on the bus, the PCI1520 monitors CDEVSEL
responds before timeout occurs, then the PCI1520 terminates the cycle with an initiator abort.
CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME is asserted
to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted.
When CFRAME
CardBus bus grant. CGNT is driven by the PCI1520 to grant a CardBus PC Card access to the CardBus
bus after the current data transaction has been completed.
CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the
host.
CardBus initiator ready. CIRDY indicates the ability of the CardBus initiator to complete the current data
phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY
CTRDY
CardBus parity error. CPERR reports parity errors during CardBus transactions, except during special
cycles. It is driven low by a target two clocks following the data cycle during which a parity error is
detected.
CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus
bus as an initiator.
CardBus system error. CSERR reports address parity errors and other system errors that could lead
to catastrophic results. CSERR
pullup; deassertion may take several CCLK periods. The PCI1520 can report CSERR
by assertion of SERR
CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus
transaction. CSTOP
do not support burst data transfers.
CardBus status change. CSTSCHG alerts the system to a change in the card status, and is used as
a wake-up mechanism.
CardBus target ready. CTRDY indicates the ability of the CardBus target to complete the current data
phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY
CTRDY
CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in conjunction with
I/O
CCD1
and CCD2 to identify card insertion and interrogate cards to determine the operating voltage and
card type.
is deasserted, the CardBus bus transaction is in the final data phase.
are asserted. Until CIRDY and CTRDY are both sampled asserted, wait states are inserted.
is driven by the card synchronous to CCLK, but deasserted by a weak
on the PCI interface.
is used for target disconnects, and is commonly asserted by target devices that
are asserted; until this time, wait states are inserted.
until a target responds. If no target
and
to the system
and
2–16
3 Feature/Protocol Descriptions
The following sections give an overview of the PCI1520. Figure 3–1 shows a simplified block diagram of the PCI1520.
The PCI interface includes all address/data and control signals for PCI protocol. The interrupt interface includes
terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling. Miscellaneous system interface
terminals include multifunction terminals: SUSPEND
SPKROUT.
, RI_OUT/PME (power management control signal), and
PCI Bus
INTA
Activity LEDs
INTB
Interrupt
Controller
TPS222X
Power Switch
PC Card
Socket A
PC Card
Socket B
External ZV Port
NOTE: The PC Card interface is 68 terminals for CardBus and 16-bit PC Cards. In zoomed video mode 23 terminals are used for routing the
zoomed video signals to the VGA controller and audio subsystem.
3
68
68
PCI1520
68 68
23
23
23
IRQSER
3
Multiplexer
PCI950
IRQSER
Deserializer
Zoomed Video
19
Zoomed Video
4
IRQ2–15
VGA
Controller
Audio
Subsystem
Figure 3–1. PCI1520 Simplified Block Diagram
3.1 Power Supply Sequencing
The PCI1520 contains 3.3-V I/O buffers with 5-V tolerance requiring an I/O power supply and an LDO-VR power
supply for core logic. The core power supply , which is always 2.5 V , can be supplied through the VR_POR T terminal
(when VR_EN
terminals. The clamping voltages (V
following power-up and power-down sequences are recommended.
is high) or from the integrated LDO-VR. The LDO-VR needs a 3.3-V power supply via the V
CCA
, V
CCB
, and V
) can be either 3.3 V or 5 V , depending on the interface. The
CCP
CC
The power-up sequence is:
1. Assert GRST
to the device to disable the outputs during power up. Output drivers must be powered up in
the high-impedance state to prevent high current levels through the clamp diodes to the 5-V clamping rails
(V
CCA
, V
CCB
, and V
2. Apply 3.3-V power to V
3. Apply the clamp voltage.
CCP
CC
).
.
3–1
The power-down sequence is:
1. Assert GRST
to the device to disable the outputs during power down. Output drivers must be powered down
in the high-impedance state to prevent high current levels through the clamp diodes to the 5-V clamping
rails (V
CCA
, V
CCB
, and V
CCP
).
2. Remove the clamp voltage.
3. Remove the 3.3-V power from V
CC
.
NOTE: The clamp voltage can be ramped up or ramped down along with the 3.3-V power. The
voltage difference between V
and the clamp voltage must remain within 3.6 V.
CC
3.2 I/O Characteristics
Figure 3–2 shows a 3-state bidirectional buffer. Section 7.2, Recommended Operating Conditions, provides the
electrical characteristics of the inputs and outputs.
NOTE: The PCI1520 meets the ac specifications of the 1997 PC Card Standard and PCI Local
Bus Specification.
V
Tied for Open Drain
OE
Figure 3–2. 3-State Bidirectional Buffer
CCP
Pad
NOTE: Unused terminals (input or I/O) must be held high or low to prevent them from floating.
3.3 Clamping Voltages
The clamping voltages are set to match whatever external environment the PCI1520 is interfaced with, 3.3 V or 5 V.
The I/O sites can be pulled through a clamping diode to a voltage rail that protects the core from external signals.
The core power supply is always 3.3 V and is independent of the clamping voltages. For example, PCI signaling can
be either 3.3 V or 5 V, and the PCI1520 must reliably accommodate both voltage levels. This is accomplished by using
a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping voltage applied. If a system designer desires a
5-V PCI bus, then V
can be connected to a 5-V power supply.
CCP
The PCI1520 requires three separate clamping voltages because it supports a wide range of features. The three
voltages are listed and defined in Section 7.2, Recommended Operating Conditions. GRST
, SUSPEND, PME, and
CSTSCHG are not clamped to any of them.
3.4 Peripheral Component Interconnect (PCI) Interface
The PCI1520 is fully compliant with the PCI Local Bus Specification. The PCI1520 provides all required signals for
PCI master or slave operation, and may operate in either a 5-V or 3.3-V signaling environment by connecting the V
terminal to the desired voltage level. In addition to the mandatory PCI signals, the PCI1520 provides the optional
interrupt signals INTA
and INTB.
3.4.1 PCI GRST Signal
During the power-up sequence, GRST and PRST must be asserted. GRST can only be deasserted 100 µs after PCLK
is stable. PRST
can be deasserted at the same time as GRST or any time thereafter.
CCP
3–2
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