Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Intel is a trademark of Intel Corporation.
PC Card is a trademark of Personal Computer Memory Card International Association (PCMCIA).
TI is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
The TI PCI1250A is a high-performance PC Card controller with a 32-bit PCI interface. The device supports two
independent PC Card sockets compliant with the 1995 PC Card Standard. The PCI1250A provides a rich
feature set that makes it the best choice for bridging between PCI and PC Cards in both notebook and desktop
computers. The 1995 PC Card Standard retains the 16-bit PC Card specification defined in PCMCIA
Release 2.1, and defines the new 32-bit PC Card, CardBus, capable of full 32-bit data transfers at 33 MHz. The
PCI1250A supports any combination of 16-bit and CardBus PC Cards in the two sockets, powered at 5 V or
3.3 V, as required.
The PCI1250A is compliant with the latest PCI Bus Power Management Specification. It is also compliant with
the PCI Local Bus Specification 2.1, and its PCI interface can act as either a PCI master device or a PCI slave
device. The PCI bus mastering is initiated during 16-bit PC Card direct memory access (DMA) transfers or
CardBus PC Card bridging transactions.
Multiple system-interrupt signaling options are provided and they include:
D
Parallel PCI interrupts
D
Parallel ISA interrupts
D
Serialized ISA interrupts
D
Serialized ISA and PCI interrupts
Additionally, general-purpose inputs and outputs are provided for the board designer to implement sideband
functions.
All card signals are internally buffered to allow hot insertion and removal without external buffering. The
PCI1250A is register compatible with the Intel 82365SL-DF ExCA controller . The PCI1250A internal data path
logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance.
Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained
bursting. The PCI1250A can also be programmed to accept fast posted writes to improve system-bus utilization.
The PCI1250A provides an internally buffered zoom video (ZV) path. This reduces the design effort of PC board
manufacturers to add a ZV-compatible solution and guarantees compliance with the CardBus loading
specifications. Many other features are designed into the PCI1250A, such as socket activity light-emitting diode
(LED) outputs, and are discussed in detail throughout the design specification.
An advanced complementary metal-oxide semiconductor (CMOS) process is used to achieve low
system-power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes enable
the host power management system to further reduce power consumption.
Unused PCI1250A inputs must be pulled up using a 43 kW resistor.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PC CARD CONTROLLER
XCPS014 – DECEMBER 1997
system block diagram
A simplified system block diagram using the PCI1250A is provided below. The zoomed video (ZV) capability
can be used to route the ZV data directly to the VGA controller.
The PCI interface includes all address/data and control signals for PCI protocol. The 68-pin PC Card interface
includes all address/data and control signals for CardBus and 16-bit (R2) protocols. When zoomed video (ZV)
is enabled (in 16-bit PC Card mode) 23 of the 68 signals are redefined to support the ZV protocol.
The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling.
The ring indicate terminal is included in the interrupt interface because its function is to perform system wake
up on incoming PC Card modem rings. Other miscellaneous system interface terminals are available on the
PCI1250A that include:
D
Programmable general purpose multifunction terminals
D
SUSPEND, RI_OUT/PME (power management control signal)
D
SPKROUT.
PCI Bus
Activity LED’s
PCI1250A
CLKRUN
TPS2206
Power
Switch
PC Card
Socket A
PC Card
Socket B
NOTE: The PC Card interface is 68 pins for CardBus and 16-bit PC Cards. In zoomed-video
mode 23 pins are used for routing the zoomed video signals too the VGA controller.
3
23 for ZV
(See Note)
23 for ZV
68
68
PCI1250A
Enable
ZV
IRQSER
†
DMA
PME
Zoom Video
South Bridge
19 Video
4 Audio
†
Interrupt Routing Options:
1) Serialized, including PCI and ISA
2) Serialized ISA and parallel PCI
3) Parallel PCI and parallel ISA
4) Parallel PCI interrupts only
Embedded
Controller
VGA
Controller
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
PCI1250A
PC CARD CONTROLLER
XCPS014 – DECEMBER 1997
terminal groups and locations
20 19 18 17 16 15 14 13 12 11 10987654321
GFN PACKAGE
(BOTTOM VIEW)
CCCCCCCCCCCC
CCCCCCCCCCCC
CCCCCCCCCCCC
CCC
CCCC
CCC
CCCC
CCC
PPPP
PPPP
PPP
PPPP
PPP
PPPP
PPP
PPPP
PPPP
CCCCC
P
CC
CC
C
ZZZZZ
ZZZZZZ
ZZZZZZZ
ZZ
C
ZZZ
ZZZZ
ZZZ
CCC
Z
CCC
CCCC
CCC
CCCC
CCCC
CCC
CCCC
CCC
CCCC
CCCC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
PPPPPPP
PPPPPPP
PPPPPPP
V
CC
GND
Power Switch
Interrupt and MiscellaneousPCI Signals
CCCCCCCC
CCCCCCCC
CCC
C
CardBus Signals
P
Z
Zoom Video Signals
CCCC
V
W
Y
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION
FUNCTION
FUNCTION
PCI1250A
PC CARD CONTROLLER
XCPS014 – DECEMBER 1997
Terminal Functions
The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The
terminal numbers are also listed for convenient reference.
power supply
TERMINAL
NAMENO.
A1, D4, D8, D13, D17, H4,
GND
V
V
CCA
V
CCB
V
CCI
V
CCP
V
CCZ
CC
H17, N4, N17, U4, U8, U13,
U17
D6, D11, D15, F4, F17, K4,
L17, R4, R17, U6, U10, U15
K2, R3, W5Rail power input for PC Card A interface. Indicates Card A signaling environment.
B16, C10, F18,Rail power input for PC Card B interface. Indicates Card B signaling environment.
V10
K20, P18, V15, W20Rail power input for PCI signaling (3.3 V or 5 V)
A4, D1Rail power input for zoom video interface (3.3 V or 5 V)
Device ground terminals
Power supply terminal for core logic (3.3 V)
Rail power input for interrupt subsystem interface and miscellaneous I/O. Indicates signaling level
of the following inputs and shared outputs: IRQSER, PCGNT
GPIO1:0, IRQMUX7–IRQMUX0, INTA
, INTB, CLOCK, DATA, LATCH, and RI_OUT.
, PCREQ, SUSPEND, SPKROUT,
PCI system
TERMINAL
NAMENO.
CLKRUN
PCLKJ17I
PRST
J18I/O
J19I
I/O
TYPE
PC Card power switch
TERMINAL
NAMENO.
CLOCKU12I/O
DATAV12O
LATCHW12O
I/O
TYPE
PCI clock run. CLKRUN is used by the central resource to request permission to stop the PCI clock or to slow
it down, and the PCI1250A responds accordingly.
PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising
edge of PCLK.
PCI reset. When the PCI bus reset is asserted, PRST causes the PCI1250A to place all output buffers in a
high-impedance state and reset all internal registers. When PRST
nonfunctional. After PRST
enabled, the device is protected from the PRST
a high-impedance state, but the contents of the registers are preserved.
3-line power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK. CLOCK
defaults to an input, but can be changed to a PCI1250A output by using the P2CCLK bit in the system control
register. The TPS2206 defines the maximum frequency of this signal to be 2 MHz. If a system design defines
this terminal as an output, CLOCK requires an external pullup resistor. The frequency of the PCI1250A output
CLOCK is derived by dividing the PCI CLK by 36.
3-line power switch data. DAT A is used to serially communicate socket power-control information to the power
switch.
3-line power switch latch. LA TCH is asserted by the PCI1250A to indicate to the PC Card power switch that the
data on the DATA line is valid.
is deasserted, the PCI1250A is in its default state. When the SUSPEND mode is
, and the internal registers are cleared. All outputs are placed in
PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary interface.
During the address phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit address or other destination
information. During the data phase, AD31–AD0 contain data.
PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the
address phase of a primary bus PCI cycle, C/BE3
4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry
meaningful data. C/BE0
byte 2 (AD23–AD16), and C/BE3
PCI bus parity. In all PCI bus read and write cycles, the PCI1250A calculates even parity across the AD31–AD0
and C/BE3
one-PCLK delay . As a target during PCI cycles, the calculated parity is compared to the initiator’s parity indicator.
A compare error results in the assertion of a parity error (PERR
–C/BE0 buses. As an initiator during PCI cycles, the PCI1250A outputs this parity indicator with a
Terminal Functions (Continued)
–C/BE0 define the bus command. During the data phase, this
applies to byte 0 (AD7–AD0), C/BE1 applies to byte 1 (AD15–AD8), C/BE2 applies to
applies to byte 3 (AD31–AD24).
).
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION
PCI interface control
TERMINAL
NAMENO.
DEVSEL
FRAME
GNT
GPIO2/LOCK
IDSELN20I
IRDY
PERR
REQ
SERR
STOP
TRDY
V20I/O
T19I/O
J20I
V19I/O
T18I/O
U18I/O
K17OPCI bus request. REQ is asserted by the PCI1250A to request access to the PCI bus as an initiator.
U19O
T17I/O
U20I/O
I/O
TYPE
PCI1250A
PC CARD CONTROLLER
XCPS014 – DECEMBER 1997
Terminal Functions (Continued)
PCI device select. The PCI1250A asserts DEVSEL to claim a PCI cycle as the target device. As a PCI
initiator on the bus, the PCI1250A monitors DEVSEL
timeout occurs, the PCI1250A terminates the cycle with an initiator abort.
PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus
transaction is beginning, and data transfers continue while this signal is asserted. When FRAME
deasserted, the PCI bus transaction is in the final data phase.
PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1250A access to the PCI bus after the
current data transaction has completed. GNT
PCI bus parking algorithm.
PCI bus general-purpose I/O pins or PCI bus lock. GPIO2/LOCK can be configured as PCI LOCK and used
to gain exclusive access downstream. Since this functionality is not typically used, a general-purpose I/O
may be accessed through this terminal. GPIO2/LOCK
configured through the GPIO2 control register.
Initialization device select. IDSEL selects the PCI1250A during configuration space accesses. IDSEL can
be connected to one of the upper 24 PCI address lines on the PCI bus.
PCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data phase of the
transaction. A data phase is completed on a rising edge of PCLK where both IRDY
Until IRDY
PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not match
PAR when PERR is enabled through bit 6 of the command register.
PCI system error. SERR is an output that is pulsed from the PCI1250A when enabled through the command
register, indicating a system error has occurred. The PCI1250A need not be the target of the PCI cycle to
assert this signal. When SERR
that an address parity error has occurred on a CardBus interface.
PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus
transaction. STOP
support burst data transfers.
PCI target ready. TRDY indicates the primary bus target’s ability to complete the current data phase of the
transaction. A data phase is completed on a rising edge of PCLK when both IRDY
Until both IRDY
and TRDY are both sampled asserted, wait states are inserted.
is enabled in the bridge control register, this signal also pulses, indicating
is used for target disconnects and is commonly asserted by target devices that do not
and TRDY are asserted, wait states are inserted.
until a target responds. If no target responds before
is
may or may not follow a PCI bus request, depending on the
Parallel PCI interrupt. GPIO3/INT A can be connected to an available PCI interrupt if parallel PCI interrupts
are used, and the PCI1250A outputs PCI INTA through this terminal. GPIO3/INTA
general-purpose input.
Serial interrupt signal/parallel PCI interrupt. When IRQSER/INTB is configured as IRQSER, it provides the
IRQSER-style serial interrupting scheme. Serialized PCI interrupts can also be sent in the IRQSER stream.
IRQSER/INTB
because this is the default interrupt signaling method.
Interrupt request/secondary functions multiplexed. The primary function of these terminals is to provide the
ISA-type IRQ signaling supported by the PCI1250A. These interrupt multiplexer outputs can be mapped to
any of 15 IRQs. The device control register must be programmed for the ISA IRQ interrupt mode and the
IRQMUX routing register must have the IRQ routing programmed before these terminals are enabled.
All of these terminals have secondary functions, such as PC/PCI DMA request/grant, ring indicate output,
and zoom video status, that can be selected with the appropriate programming of this register. When the
secondary functions are enabled, the respective terminals are not available for IRQ routing.
See the IRQMUX routing register for programming options.
Ring indicate output/power management event. RI_OUT allows the RI input from a PC Card to pass through
to the system. This pin can be configured as the PME
pin is RI_OUT
register. This pin is PME
IRQMUX4 or IRQMUX3 can be used to route the RI_OUT
and a ring indicate signal is still required.
Terminal Functions (Continued)
defaults to a
can be configured as the parallel PCI INTB interrupt. IRQSER/INTB defaults to IRQSER
pin by setting bit 0 in the system control register. This
when RIENB is enabled in the card control register and ExCA interrupt and general control
when RIENB is disabled and bit 1 of the system control register is 1.
signal when the PME signal is routed on pin Y13
PC/PCI DMA
TERMINAL
NAMENO.
PCGNT/
IRQMUX6
PCREQ/
IRQMUX7
U11I/O
Y12O
I/O
TYPE
PC/PCI DMA grant. PCGNT is used to grant the DMA channel to a requester in a system supporting the PC/PCI
DMA scheme.
Interrupt request MUX 6. When configured for IRQMUX6, this terminal provides the IRQMUX6 interrupt output
of the interrupt multiplexer, and can be mapped to any of 15 ISA-type IRQs. IRQMUX6 takes precedence over
PCGNT
, and should not be enabled in a system using PC/PCI DMA.
This terminal is also used for the serial EEPROM interface.
PC/PCI DMA request. PCREQ is used to request DMA transfers as DREQ in a system supporting the PC/PCI
DMA scheme.
Interrupt request MUX 7. When configured for IRQMUX7, this terminal provides the IRQMUX7 interrupt output
of the interrupt multiplexer, and can be mapped to any of 15 ISA-type IRQs. IRQMUX7 takes precedence over
PCREQ
, and should not be enabled in a system using PC/PCI DMA.
This terminal is also used for the serial EEPROM interface.
ZV_PCLKE1IOIS16OPixel clock to the zoom video port
ZV_LRCLKE3INPACKOAudio LRCLK PCM
ZV_SDATAE2SPKROAudio SDATA PCM
ZV_RSVDF1, F2, F3, G4OReserved. No connection.
ZV_RSV1
ZV_RSV0
A6A10O
C7A11O
A3
B4
C5
B5
C6
D7
A5
B6
D2
C3
B1
B2
A2
C4
B3
D5
C1
E4
I/O AND MEMORY
SIGNAL
A20
A14
A19
A13
A18
A8
A17
A9
A25
A12
A24
A15
A23
A16
A22
A21
A5
A4
I/O
TYPE
Horizontal sync to the zoom video port
Vertical sync to the zoom video port
OVideo data to the zoom video port in YV:4:2:2 format
OVideo data to the zoom video port in YV:4:2:2 format
Reserved. No connection in the PC Card. ZV_RSVD1 and ZV_RSVD0 are
O
put into the high-impedance state by host adapter.
miscellaneous
TERMINAL
NAMENO.
GPIO0/LEDA1V11I/O
GPIO1/LEDA2W11I/O
SPKROUT
SUSPEND
Y10O
Y11I
I/O
TYPE
GPIO0/socket activity LED indicator 1. When GPIO0/LEDA1 is configured as LEDA1, it provides an output
indicating PC Card socket 0 activity. Otherwise, GPIO0/LEDA1 can be configured as a general-purpose
input and output, GPIO0. The zoom video enable signal (ZV_STAT) can also be routed to this signal
through the GPIO0 control register. GPIO0/LEDA1 defaults to a general-purpose input.
GPIO1/socket activity LED indicator 2. When GPIO1/LEDA2 is configured as LEDA2, it provides an output
indicating PC Card socket 1 activity. Otherwise, GPIO1/LEDA2 can be configured as a general-purpose
input and output, GPIO1. A CSC interrupt can be generated on a GPDATA change, and this input can be
used for power switch overcurrent (OC) sensing. See
GPIO1/LEDA2 defaults to a general-purpose input.
Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO through the
PCI1250A from the PC Card interface. SPKROUT is driven as the exclusive-OR combination of card
SPKR
//CAUDIO inputs.
Suspend. SUSPEND is used to protect the internal registers from clearing when PRST is asserted. See
SUSPEND mode
for details.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
GPIO1 control register
for programming details.
9
PCI1250A
FUNCTION
PC CARD CONTROLLER
XCPS014 – DECEMBER 1997
Terminal Functions (Continued)
16-bit PC Card address and data (slots A and B)
TERMINAL
NO.
NAME
D15
D14
D13
D12
D10
†
Terminal name for slot A is preceded with A_. For example, the full name for terminal T4 is A_A25.
‡
Terminal name for slot B is preceded with B_. For example, the full name for terminal C14 is B_A25.
OPC Card address. 16-bit PC Card address lines. A25 is the most-significant bit.
I/OPC Card data. 16-bit PC Card data lines. D15 is the most-significant bit.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION
Terminal Functions (Continued)
16-bit PC Card interface control (slots A and B)
TERMINAL
B
C9
I/O
TYPE
‡
Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries.
BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card.
Both BVD1 and BVD2 are kept high when the battery is good. When BVD2 is low and BVD1 is high,
the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable
and the data in the memory PC Card is lost.
Status change. STSCHG
battery voltage dead condition of a 16-bit I/O PC Card.
Ring indicate. RI
Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include batteries.
BVD2 is used with BVD1 as an indication of the condition of the batteries on a memory PC Card.
Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the
battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable
and the data in the memory PC Card is lost.
Speaker. SPKR
been configured for the 16-bit I/O interface. The audio signals from cards A and B are combined
by the PCI1250A and are output on SPKROUT.
DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit
PC Card that supports DMA. The PC Card asserts BVD2 to indicate a request for a DMA operation.
PC Card detect 1 and PC Card detect 2. CD1 and CD2 are internally connected to ground on the
I
PC Card. When a PC Card is inserted into a socket, CD1
Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address bytes.
O
CE1
enables even-numbered address bytes, and CE2 enables odd-numbered address bytes.
Input acknowledge. INP ACK is asserted by the PC Card when it can respond to an I/O read cycle
at the current address.
DMA request. INPACK can be used as the DMA request signal during DMA operations from a 16-bit
PC Card that supports DMA. If used as a strobe, the PC Card asserts this signal to indicate a
request for a DMA operation.
I/O read. IORD is asserted by the PCI1250A to enable 16-bit I/O PC Card data output during host
I/O read cycles.
DMA write. IORD is used as the DMA write strobe during DMA operations from a 16-bit PC Card
that supports DMA. The PCI1250A asserts IORD
memory.
I/O write. IOWR is driven low by the PCI1250A to strobe write data into 16-bit I/O PC Cards during
host I/O write cycles.
DMA read. IOWR
that supports DMA. The PCI1250A asserts IOWR
Card.
Output enable. OE is driven low by the PCI1250A to enable 16-bit memory PC Card data output
during host memory read cycles.
DMA terminal count. OE
that supports DMA. The PCI1250A asserts OE
is used by 16-bit modem cards to indicate a ring detection.
is an optional binary audio signal available only when the card and socket have
is used to alert the system to a change in the READY, write protect, or
during DMA transfers from the PC Card to host
is used as the DMA write strobe during DMA operations from a 16-bit PC Card
during transfers from host memory to the PC
is used as terminal count (TC) during DMA operations to a 16-bit PC Card
to indicate TC for a DMA write operation.
NO.
NAME
BVD1
(STSCHG
BVD2
(SPKR
CD1
CD2
CE1
CE2
INPACKY1D12I
IORD
IOWR
OEL3C20O
†
Terminal name for slot A is preceded with A_. For example, the full name for terminal Y1 is A_INPACK.
‡
Terminal name for slot B is preceded with B_. For example, the full name for terminal D12 is B_INPACK
SLOT
A
V6A9I
/RI)
Y5D10I
)
G3W6H20
K1L2D20
L4E17O
M2C19O
SLOT
†
D19
PCI1250A
PC CARD CONTROLLER
XCPS014 – DECEMBER 1997
and CD2 are pulled low.
.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
PCI1250A
FUNCTION
PC CARD CONTROLLER
XCPS014 – DECEMBER 1997
Terminal Functions (Continued)
16-bit PC Card interface control (slots A and B) (continued)
TERMINAL
NUMBER
NAME
READY
(IREQ
REG
RESETW1C13OPC Card reset. RESET forces a hard reset to a 16-bit PC Card.
WAIT
WEP3D16O
WP
(IOIS16
VS1
VS2
†
Terminal name for slot A is preceded with A_. For example, the full name for terminal P3 is A_WE.
‡
Terminal name for slot B is preceded with B_. For example, the full name for terminal D16 is B_WE
SLOT
A
Y4A10I
)
Y2B12O
V5B10I
U7B9I
)
Y3U3A11
SLOT
†
B14
I/O
TYPE
‡
B
Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket are
configured for the memory-only interface. READY is driven low by the 16-bit memory PC Cards to
indicate that the memory card circuits are busy processing a previous write command. READY is
driven high when the 16-bit memory PC Card is ready to accept a new data transfer command.
Interrupt request. IREQ
the 16-bit I /O PC Card requires service by the host software. IREQ
interrupt is requested.
Attribute memory select. REG remains high for all common memory accesses. When REG is
asserted, access is limited to attribute memory (OE
active). Attribute memory is a separately accessed section of card memory and is generally
IOWR
used to record card capacity and other configuration and attribute information.
DMA acknowledge. REG is used as a DMA acknowledge (DACK) during DMA operations to a
16-bit PC Card that supports DMA. The PCI1250A asserts REG
is used in conjunction with the DMA read (IOWR) or DMA write (IORD) strobes to transfer data.
Bus cycle wait. WAIT is driven by a 16-bit PC Card to delay the completion of (i.e., extend) the
memory or I/O cycle in progress.
Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also
used for memory PC Cards that employ programmable memory technologies.
DMA terminal count. WE
DMA. The PC1250 asserts WE
Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect
switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16
function.
I/O is 16 bits. IOIS16
the address on the bus corresponds to an address to which the 16-bit PC Card responds, and the
I/O port that is addressed is capable of 16-bit accesses.
DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit
PC Card that supports DMA. If used, the PC Card asserts WP to indicate a request for a DMA
operation.
Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other,
I/O
determine the operating voltage of the 16-bit PC Card.
is asserted by a 16-bit I/O PC Card to indicate to the host that a device on
or WE active) and to the I/O space (IORD or
is used as TC during DMA operations to a 16-bit PC Card that supports
to indicate TC for a DMA read operation.
applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card when
is high (deasserted) when no
to indicate a DMA operation. REG
)
.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION
Terminal Functions (Continued)
CardBus PC Card interface system (slots A and B)
TERMINAL
NO.
NAME
CCLKT1A17O
CCLKRUN
CRST
†
Terminal name for slot A is preceded with A_. For example, the full name for terminal T1 is A_CCLK.
‡
Terminal name for slot B is preceded with B_. For example, the full name for terminal A17 is B_CCLK.
SLOT
SLOT
†
A
U7B9O
W1C13I/O
I/O
TYPE
‡
B
CardBus PC Card clock. CCLK provides synchronous timing for all transactions on the CardBus
interface. All signals except CRST
CVS2–CVS1 are sampled on the rising edge of CCLK, and all timing parameters are defined with the
rising edge of this signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the
low state or slowed down for power savings.
CardBus PC Card clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the
CCLK frequency, and by the PCI1250A to indicate that the CCLK frequency is decreased.
CardBus PC Card reset. CRST is used to bring CardBus PC Card-specific registers, sequencers,
and signals to a known state. When CRST
and the PCI1250A drives these signals to a valid logic level. Assertion can be asynchronous to CCLK,
but deassertion must be synchronous to CCLK.
, CCLKRUN, CINT, CSTSCHG, CAUDIO, CCD2:1, and
is asserted, all CardBus PC Card signals must be 3-stated,
PCI1250A
PC CARD CONTROLLER
XCPS014 – DECEMBER 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
PCI1250A
FUNCTION
PC CARD CONTROLLER
XCPS014 – DECEMBER 1997
Terminal Functions (Continued)
CardBus PC Card address and data (slots A and B)
TERMINAL
B
B7
C8
B8
A8
D9
I/O
TYPE
‡
PC Card address and data. These signals make up the multiplexed CardBus address and data bus on
the CardBus interface. During the address phase of a CardBus cycle, CAD31–CAD0 contain a 32-bit
I/O
address. During the data phase of a CardBus cycle, CAD31–CAD0 contain data. CAD31 is the
most-significant bit.
CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the same CardBus
terminals. During the address phase of a CardBus cycle, CC/BE3
During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte
I/O
paths of the full 32-bit data bus carry meaningful data. CC/BE0
applies to byte 1 (CAD15–CAD8), CC/BE2 applies to byte 2 (CAD23–CAD8), and CC/BE3 applies to
byte 3 (CAD31–CAD24).
CardBus parity. In all CardBus read and write cycles, the PCI1250A calculates even parity across the
CAD and CC/BE
one-CCLK delay. As a target during CardBus cycles, the calculated parity is compared to the initiator’s
parity indicator; a compare error results in a parity error assertion.
buses. As an initiator during CardBus cycles, the PCI1250A outputs CPAR with a
Terminal name for slot A is preceded with A_. For example, the full name for terminal Y5 is A_CAUDIO.
‡
Terminal name for slot B is preceded with B_. For example, the full name for terminal D10 is B_CAUDIO.
SLOT
SLOT
†
A
P1B18I/O
G3H20
W6C9
R2A18I/O
U1C15I/O
P3D16I
Y4A10I
T2A16I/O
P2B17I/O
Y1D12I
V5B10I
R1C17I/O
V6A9I
P4C16I/O
I/O
TYPE
‡
B
CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The
PCI1250A supports the binary audio mode and outputs a binary signal from the card to SPKROUT.
CardBus lock. CBLOCK is used to gain exclusive access to a target.
CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with CVS1 and
CVS2 to identify card insertion and interrogate cards to determine the operating voltage and card
type.
CardBus device select. The PCI1250A asserts CDEVSEL to claim a CardBus cycle as the target
device. As a CardBus initiator on the bus, the PCI1250A monitors CDEVSEL
If no target responds before timeout occurs, the PCI1250A terminates the cycle with an initiator abort.
CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME is asserted
to indicate that a bus transaction is beginning, and data transfers continue while this signal is
asserted. When CFRAME
CardBus bus grant. CGNT is driven by the PCI1250A to grant a CardBus PC Card access to the
CardBus bus after the current data transaction has been completed.
CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from
the host.
CardBus initiator ready. CIRDY indicates the CardBus initiator’s ability to complete the current data
phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY
CTRDY
are asserted. Until CIRDY and CTRDY are both sampled asserted, wait states are inserted.
CardBus parity error. CPERR is used to report parity errors during CardBus transactions, except
during special cycles. It is driven low by a target two clocks following that data when a parity error
is detected.
CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the
CardBus bus as an initiator.
CardBus system error. CSERR reports address parity errors and other system errors that could lead
to catastrophic results. CSERR
pullup, and may take several CCLK periods. The PCI1250A can report CSERR
assertion of SERR
CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current
CardBus transaction. CSTOP
devices that do not support burst data transfers.
CardBus status change. CSTSCHG is used to alert the system to a change in the card’s status, and
is used as a wake-up mechanism.
CardBus target ready. CTRDY indicates the CardBus target’s ability to complete the current data
phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY
and CTRDY are asserted; until this time, wait states are inserted.
CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in conjunction
with
voltage and card type.
and
is deasserted, the CardBus bus transaction is in the final data phase.
is driven by the card synchronous to CCLK, but deasserted by a weak
on the PCI interface.
is used for target disconnects, and is commonly asserted by target
to identify card insertion and interrogate cards to determine the operating
PCI1250A
PC CARD CONTROLLER
XCPS014 – DECEMBER 1997
until a target responds.
and
to the system by
p
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
15
PCI1250A
PC CARD CONTROLLER
XCPS014 – DECEMBER 1997
absolute maximum ratings over operating temperature ranges (unless otherwise noted)
Supply voltage range, V
Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Storage temperature range, T
Virtual junction temperature, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Applies for external input and bidirectional buffers. VI > VCC does not apply to fail-safe terminals. PCI terminals are measured with
respect to V
respect to V
2. Applies for external output and bidirectional buffers. VO > VCC does not apply to fail-safe terminals. PCI terminals are measured
with respect to V
with respect to V
instead of VCC. PC Card terminals are measured with respect to V
CCP
, and miscellaneous signals are measured with respect to V
Pulse duration, RSTINt
Setup time, PCLK active at end of RSTINt
ALTERNATE
SYMBOL
cyc
high
low
f
rst
rst-clk
PCI timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 4 and Figures 19 and 22)
PARAMETER
PCLK-to-shared signal
pd
t
en
t
dis
t
su
t
h
NOTES: 7. This data sheet uses the following conventions to describe time ( t ) intervals. The format is tA, where
Propagation delay time,
See Note 6
Enable time,
high impedance-to-active delay time from PCLK
Disable time,
active-to-high impedance delay time from PCLK
Setup time before PCLK validt
Hold time after PCLK hight
6. PCI shared signals are AD31–0, C/BE3–0, FRAME, TRDY, IRDY, ST OP, IDSEL, DEVSEL, and P AR.
type of dynamic parameter being represented. One of the following is used: tpd = propagation delay time, td = delay time,
tsu = setup time, and th = hold time.
valid delay time
PCLK-to-shared signal
invalid delay time
ALTERNATE
SYMBOL
t
val
t
inv
t
on
t
off
su
h
TEST CONDITIONSMINMAXUNIT
=
L
TEST
CONDITIONS
p
ee Note
MINMAXUNIT
30ns
11ns
11ns
14V/ns
1ms
100
11
2
2ns
28ns
7ns
0ns
subscript A
indicates the
m
ns
s
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
19
PCI1250A
PC CARD CONTROLLER
XCPS014 – DECEMBER 1997
PARAMETER MEASUREMENT INFORMATION
LOAD CIRCUIT PARAMETERS
†
PARAMETER
t
en
t
dis
t
pd
†
C
LOAD
V
LOAD–VOL
‡
I
OL
TIMING
t
PZH
t
PZL
t
PHZ
t
PLZ
includes the typical load-circuit distributed capacitance.
C
LOAD
(pF)
50
508–8
508
= 50 Ω, where VOL = 0.6 V, IOL = 8 mA
I
OL
(mA)
8
I
OH
(mA)
–8
–8
V
LOAD
(V)
1.5
I
OL
0
3
From Output
Under Test
‡
Test
Point
C
LOAD
LOAD CIRCUIT
I
OH
V
LOAD
Timing
Input
(see Note A)
Data
Input
(see Note A)
Out-of-Phase
90% V
10% V
Input
In-Phase
Output
Output
50% V
CC
t
su
CC
50% V
50% V
CC
CC
50% V
50% V
CC
t
r
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
INPUT RISE AND FALL TIMES
t
pd
t
pd
t
50% V
50% V
CC
CC
h
t
f
CC
CC
t
pd
50% V
t
pd
50% V
V
0 V
V
0 V
CC
CC
V
0 V
V
V
V
V
CC
OH
CC
OL
OH
CC
OL
High-Level
Input
Low-Level
Input
Output
Control
(low-level
enabling)
Waveform 1
(see Notes
Band C)
Waveform 2
(see Notes B
and C)
50% V
50% V
VOLTAGE WAVEFORMS
PULSE DURATION
50% V
t
PZL
t
PZH
t
PLZ
50% V
t
PHZ
50% V
t
CC
V
CC
CC
CC
50% V
50% V
50% V
VOL+ 0.3 V
VOH– 0.3 V
CC
CC
CC
0 V
V
0 V
CC
V
CC
0 V
V
CC
≅ 50% V
V
OL
V
OH
≅ 50% V
0 V
CC
CC
CC
w
CC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by pulse generators having the
following characteristics: PRR = 1 MHz, ZO = 50 Ω, tr = 6 ns.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. For t
PLZ
and t
, VOL and VOH are measured values.
PHZ
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
Figure 1. Load Circuit and Voltage Waveforms
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI1250A
PC CARD CONTROLLER
XCPS014 – DECEMBER 1997
PCI BUS PARAMETER MEASUREMENT INFORMATION
t
high
t
low
t
f
2 V MIN Peak-to-Peak
t
rst
PCLK
RSTIN
0.8 V
t
r
2 V
t
cyc
Figure 2. PCLK Timing Waveform
PCLK
PCI Output
PCI Input
t
srst-clk
Figure 3. RSTIN Timing Waveforms
1.5 V
t
val
1.5 V
Valid
t
on
Valid
t
su
t
inv
t
off
t
h
Figure 4. Shared Signals Timing Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
21
PCI1250A
PC CARD CONTROLLER
XCPS014 – DECEMBER 1997
PC Card cycle timing
The PC Card cycle timing is controlled by the wait-state bits in the Intel 82365SL-DF compatible memory and
I/O window registers. The PC Card cycle generator uses the PCI clock to generate the correct card address
setup and hold times and the PC Card command active (low) interval. This allows the cycle generator to output
PC Card cycles that are as close to the Intel 82365SL-DF timing as possible while always slightly exceeding
the Intel 82365SL-DF values. This ensures compatibility with existing software and maximizes throughput.
The PC Card address setup and hold times are a function of the wait-state bits. Table 1 shows address setup
time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 2 and Table 3 show command active
time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 4 shows address hold time in PCLK
cycles and nanoseconds for I/O and memory cycles.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature, memory cycles (for 100-ns common memory) (see Note 5 and Figure 5)
ALTERNATE
SYMBOL
t
su
t
su
t
su
t
pd
t
w
t
h
t
h
t
su
t
h
t
h
t
su
t
h
NOTE 8: These times are dependent on the register settings associated with ISA wait states and data size. They are also dependent on cycle
Setup time, CE1 and CE2 before WE/OE lowT160ns
Setup time, CA25–CA0 before WE/OE lowT2t
Setup time, REG before WE/OE lowT390ns
Propagation delay time, WE/OE low to WAIT lowT4ns
Pulse duration, WE/OE lowT5200ns
Hold time, WE/OE low after WAIT highT6ns
Hold time, CE1 and CE2 after WE/OE highT7120ns
Setup time (read), CDATA15–CDATA0 valid before OE highT8ns
Hold time (read), CDATA15–CDATA0 valid after OE highT90ns
Hold time, CA25–CA0 and REG after WE/OE highT10t
Setup time (write), CDATA15–CDATA0 valid before WE lowT1160ns
Hold time (write), CDATA15–CDATA0 valid after WE lowT12240ns
type (read/write, memory/I/O) and WAIT
observed if programmed for zero wait state, 16-bit cycles) with a 33-MHz PCI clock.
from PC Card. The times listed here represent absolute minimums (the times that would be
su(A)
h(A)
MINMAXUNIT
+2PCLKns
+1PCLKns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature, I/O cycles (see Figure 6)
ALTERNATE
SYMBOL
t
su
t
su
t
su
t
pd
t
pd
t
w
t
h
t
h
t
h
t
h
t
su
t
h
t
su
t
h
Setup time, REG before IORD/IOWR lowT1360ns
Setup time, CE1 and CE2 before IORD/IOWR lowT1460ns
Setup time, CA25–CA0 valid before IORD/IOWR lowT15t
Propagation delay time, IOIS16 low after CA25–CA0 validT1635ns
Propagation delay time, IORD low to WAIT lowT1735ns
Pulse duration, IORD/IOWR lowT18T
Hold time, IORD low after WAIT highT19ns
Hold time, REG low after IORD highT200ns
Hold time, CE1 and CE2 after IORD/IOWR highT21120ns
Hold time, CA25–CA0 after IORD/IOWR highT22t
Setup time (read), CDATA15–CDATA0 valid before IORD highT2310ns
Hold time (read), CDATA15–CDATA0 valid after IORD highT240ns
Setup time (write), CDATA15–CDATA0 valid before IOWR lowT2590ns
Hold time (write), CDATA15–CDATA0 valid after IOWR highT2690ns
su(A)
h(A)
MINMAXUNIT
+2PCLKns
cA
+1PCLKns
ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
23
PCI1250A
T27
tpdP
T28
PC CARD CONTROLLER
XCPS014 – DECEMBER 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, miscellaneous (see Figure 7)
ALTERNATE
SYMBOL
T10
MINMAXUNIT
30
30
ns
30
30
p
ropagation delay time
PC Card PARAMETER MEASUREMENT INFORMATION
CA25–CA0
REG
PARAMETER
BVD2 low to SPKROUT low
BVD2 high to SPKROUT high
IREQ
to IRQ15–IRQ3
STSCHG to IRQ15–IRQ3
CE1, CE2
WE, OE
WAIT
CDATA15–CDATA0
(write)
CDATA15–CDATA0
(read)
With no wait state
With wait state
T2
T1
T3
T4
T11
T5
Figure 5. PC Card Memory Cycle
T7
T6
T12
T8
T9
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI1250A
PC CARD CONTROLLER
XCPS014 – DECEMBER 1997
PC Card PARAMETER MEASUREMENT INFORMATION
CA25–CA0
IOIS16
REG
CE1, CE2
T16
T14
T18
T22
T20
T21
IORD, IOWR
WAIT
CDATA15–CDATA0
(write)
CDATA15–CDATA0
(read)
With no wait state
With wait state
T15
BVD2
SPKROUT
IREQ
T13
T17
T25
Figure 6. PC Card I/O Cycle
T27
T28
T19
T26
T23
T24
IRQ15–IRQ3
Figure 7. Miscellaneous PC Card Delay Times
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
25
PCI1250A
PC CARD CONTROLLER
XCPS014 – DECEMBER 1997
MECHANICAL DATA
GFN (S-PBGA-N256)PLASTIC BALL GRID ARRAY
1,17
45° 4 Places
27,00 SQ
24,00 SQ
16,10 SQ
1,435 TYP
2,13
0,90
Dia Solder Balls
0,60
256 Places
1,27
A
1
0,60 Seating Plane
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
0,36
0,15
4040185/A 04/95
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor
product or service without notice, and advises its customers to obtain the latest version of relevant information
to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications applicable at
the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each
device is not necessarily performed, except those mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury, or
severe property or environmental damage (“Critical Applications”).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED
TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI
products in such applications requires the written approval of an appropriate TI officer . Questions concerning
potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license, either
express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or process in which such semiconductor products
or services might be or are used.
Copyright 1997, Texas Instruments Incorporated
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