TEXAS INSTRUMENTS PCI1250A Technical data

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Peripheral Component Interconnect (PCI) Power Management Compliant

ACPI 1.0 Compliant

Packaged in 256-Pin BGA

PCI Local Bus Specification Revision 2.1 Compliant

1995 PC Card Standard Compliant

3.3-V Core Logic With Universal PCI Interfaces Compatible With 3.3-V and 5-V PCI Signaling Environments

Mix-and-Match 5-V/3.3-V PC Card16 Cards and 3.3-V CardBus Cards

Supports Two PC Card or CardBus Slots With Hot Insertion and Removal

Uses Serial Interface to TI TPS2206 Dual Power Switch

Supports Burst Transfers to Maximize Data Throughput on Both PCI Buses

Supports Serialized Interrupt request (IRQ) With PCI Interrupts

8-Way Legacy IRQ Multiplexing

System Interrupts Can Be Programmed as PCI Style or Industry Standard Archeticture (ISA-IRQ) Style

ISA-IRQ Interrupts Can Be Serialized Onto a Single IRQ Serial (IRQSER) Pin

EEPROM Interface for Loading Subsystem ID and Subsystem Vendor ID

Pipelined Architecture Allows Greater Than 130M-Bytes-Per-Second Throughput From CardBus to PCI and From PCI to CardBus

PC CARD CONTROLLER

XCPS014 – DECEMBER 1997

Supports Zoom Video With Internal Buffering

Programmable Output Select for CLKRUN

Four General Purpose I/Os

Multifunction PCI Device With Separate Configuration Space for Each Socket

Five PCI Memory Windows and Two I/O Windows Available for Each PC Card16 Socket

Two I/O Windows and Two Memory Windows Available to Each CardBus Socket

Exchangeable Card Architecture (ExCA) Compatible Registers Are Mappable in Memory and I/O Space

Supports Distributed DMA (DDMA) and PC/PCI DMA

Intel 82365SL-DF Register Compatible

Supports 16-Bit DMA on Both PC Card Sockets

Supports Ring Indicate, SUSPEND, PCI CLKRUN

Advanced Submicron, Low-Power CMOS T echnology

Provides VGA/Palette Memory and I/O and Subtractive Decoding Options

LED Activity Pins

Supports PCI Bus Lock (LOCK)

For the Complete Data Sheet for PCI1250A, Please See Literature #SCPS014B

, and CardBus CCLKRUN

PCI1250A

Table of Contents

Description 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System Block Diagram 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Terminal Assignments 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Terminal Functions 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Absolute Maximum Ratings 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Recommended Operating Conditions 17. . . . . . . . . . . . . . . . . . . .

Electrical Characteristics 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Intel is a trademark of Intel Corporation. PC Card is a trademark of Personal Computer Memory Card International Association (PCMCIA). TI is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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PCI Clock/Reset Timing Requirements 19. . . . . . . . . . . . . . . . . . . . . .

PCI Timing Requirements 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parameter Measurement Information 20. . . . . . . . . . . . . . . . . . . . . . . .

PCI Bus Parameter Measurement Information 21. . . . . . . . . . . . . . . .

PC Card Cycle Timing 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Mechanical Data 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCI1250A PC CARD CONTROLLER

XCPS014 – DECEMBER 1997

description

The TI PCI1250A is a high-performance PC Card controller with a 32-bit PCI interface. The device supports two independent PC Card sockets compliant with the 1995 PC Card Standard. The PCI1250A provides a rich feature set that makes it the best choice for bridging between PCI and PC Cards in both notebook and desktop computers. The 1995 PC Card Standard retains the 16-bit PC Card specification defined in PCMCIA Release 2.1, and defines the new 32-bit PC Card, CardBus, capable of full 32-bit data transfers at 33 MHz. The PCI1250A supports any combination of 16-bit and CardBus PC Cards in the two sockets, powered at 5 V or

3.3 V, as required. The PCI1250A is compliant with the latest PCI Bus Power Management Specification. It is also compliant with

the PCI Local Bus Specification 2.1, and its PCI interface can act as either a PCI master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card direct memory access (DMA) transfers or CardBus PC Card bridging transactions.

Multiple system-interrupt signaling options are provided and they include:

Parallel PCI interrupts

Parallel ISA interrupts

Serialized ISA interrupts

Serialized ISA and PCI interrupts

Additionally, general-purpose inputs and outputs are provided for the board designer to implement sideband functions.

All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1250A is register compatible with the Intel 82365SL-DF ExCA controller . The PCI1250A internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI1250A can also be programmed to accept fast posted writes to improve system-bus utilization.

The PCI1250A provides an internally buffered zoom video (ZV) path. This reduces the design effort of PC board manufacturers to add a ZV-compatible solution and guarantees compliance with the CardBus loading specifications. Many other features are designed into the PCI1250A, such as socket activity light-emitting diode (LED) outputs, and are discussed in detail throughout the design specification.

An advanced complementary metal-oxide semiconductor (CMOS) process is used to achieve low system-power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power management system to further reduce power consumption.

Unused PCI1250A inputs must be pulled up using a 43 kW resistor.

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PC CARD CONTROLLER

XCPS014 – DECEMBER 1997

system block diagram

A simplified system block diagram using the PCI1250A is provided below. The zoomed video (ZV) capability can be used to route the ZV data directly to the VGA controller.

The PCI interface includes all address/data and control signals for PCI protocol. The 68-pin PC Card interface includes all address/data and control signals for CardBus and 16-bit (R2) protocols. When zoomed video (ZV) is enabled (in 16-bit PC Card mode) 23 of the 68 signals are redefined to support the ZV protocol.

The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling. The ring indicate terminal is included in the interrupt interface because its function is to perform system wake up on incoming PC Card modem rings. Other miscellaneous system interface terminals are available on the PCI1250A that include:

Programmable general purpose multifunction terminals

SUSPEND, RI_OUT/PME (power management control signal)

SPKROUT.

PCI Bus

Activity LED’s

PCI1250A

CLKRUN

TPS2206

Power

Switch

PC Card

Socket A

PC Card

Socket B

NOTE: The PC Card interface is 68 pins for CardBus and 16-bit PC Cards. In zoomed-video

mode 23 pins are used for routing the zoomed video signals too the VGA controller.

23 for ZV

(See Note)

23 for ZV

PCI1250A

Enable

IRQSER

†

DMA PME

Zoom Video

South Bridge

19 Video

4 Audio

†

Interrupt Routing Options:

1) Serialized, including PCI and ISA

2) Serialized ISA and parallel PCI

3) Parallel PCI and parallel ISA

4) Parallel PCI interrupts only

Embedded

Controller

VGA

Controller

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PCI1250A PC CARD CONTROLLER

XCPS014 – DECEMBER 1997

terminal groups and locations

20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

GFN PACKAGE

(BOTTOM VIEW)

CCCCCCCCCCCC CCCCCCCCCCCC CCCCCCCCCCCC CCC

CCCC CCC CCCC

CCC PPPP PPPP

PPP PPPP PPP PPPP PPP PPPP

PPP P

CCCCC

CC CC C

ZZZZZ ZZZZZZ

ZZZZZZZ

ZZZ

ZZZZ

ZZZ CCC

CCC

CCCC

CCC CCCC CCCC

CCC CCCC

CCCC

A B C D

E F G

H J K

L M N P R T

U PPPPPPP PPPPPPP PPPPPPP

GND

Power Switch Interrupt and Miscellaneous PCI Signals

CCCCCCCC CCCCCCCC

CCC

CardBus Signals

P Z

Zoom Video Signals

CCCC

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FUNCTION

PCI1250A

PC CARD CONTROLLER

XCPS014 – DECEMBER 1997

Terminal Functions

The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The terminal numbers are also listed for convenient reference.

power supply

TERMINAL

NAME NO.

A1, D4, D8, D13, D17, H4,

GND

CCA

CCB

CCI

CCP

CCZ

H17, N4, N17, U4, U8, U13,

U17

D6, D11, D15, F4, F17, K4,

L17, R4, R17, U6, U10, U15

K2, R3, W5 Rail power input for PC Card A interface. Indicates Card A signaling environment.

B16, C10, F18, Rail power input for PC Card B interface. Indicates Card B signaling environment.

V10

K20, P18, V15, W20 Rail power input for PCI signaling (3.3 V or 5 V)

A4, D1 Rail power input for zoom video interface (3.3 V or 5 V)

Device ground terminals

Power supply terminal for core logic (3.3 V)

Rail power input for interrupt subsystem interface and miscellaneous I/O. Indicates signaling level of the following inputs and shared outputs: IRQSER, PCGNT GPIO1:0, IRQMUX7–IRQMUX0, INTA

, INTB, CLOCK, DATA, LATCH, and RI_OUT.

, PCREQ, SUSPEND, SPKROUT,

PCI system

TERMINAL

NAME NO.

CLKRUN

PCLK J17 I

PRST

J18 I/O

J19 I

I/O

TYPE

PC Card power switch

TERMINAL

NAME NO.

CLOCK U12 I/O

DATA V12 O

LATCH W12 O

I/O

TYPE

PCI clock run. CLKRUN is used by the central resource to request permission to stop the PCI clock or to slow it down, and the PCI1250A responds accordingly.

PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCLK.

PCI reset. When the PCI bus reset is asserted, PRST causes the PCI1250A to place all output buffers in a high-impedance state and reset all internal registers. When PRST nonfunctional. After PRST enabled, the device is protected from the PRST a high-impedance state, but the contents of the registers are preserved.

3-line power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK. CLOCK defaults to an input, but can be changed to a PCI1250A output by using the P2CCLK bit in the system control register. The TPS2206 defines the maximum frequency of this signal to be 2 MHz. If a system design defines this terminal as an output, CLOCK requires an external pullup resistor. The frequency of the PCI1250A output CLOCK is derived by dividing the PCI CLK by 36.

3-line power switch data. DAT A is used to serially communicate socket power-control information to the power switch.

3-line power switch latch. LA TCH is asserted by the PCI1250A to indicate to the PC Card power switch that the data on the DATA line is valid.

is deasserted, the PCI1250A is in its default state. When the SUSPEND mode is

, and the internal registers are cleared. All outputs are placed in

is asserted, the device is completely

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PCI1250A

FUNCTION

PC CARD CONTROLLER

XCPS014 – DECEMBER 1997

PCI address and data

TERMINAL

NAME NO.

AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10

AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

C/BE3 C/BE2 C/BE1 C/BE0

PAR Y20 I/O

K18 K19 L20 L18

L19 M20 M19 M18 N19 N18

P20

P19 R20 R19

P17 R18

V18

Y19 W18

V17 U16

Y18 W17

V16 W16 U14

Y16 W15

V14

Y15 W14

Y14 M17

T20 W19

Y17

I/O

TYPE

I/O

PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary interface. During the address phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit address or other destination information. During the data phase, AD31–AD0 contain data.

PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address phase of a primary bus PCI cycle, C/BE3 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. C/BE0 byte 2 (AD23–AD16), and C/BE3

PCI bus parity. In all PCI bus read and write cycles, the PCI1250A calculates even parity across the AD31–AD0 and C/BE3 one-PCLK delay . As a target during PCI cycles, the calculated parity is compared to the initiator’s parity indicator. A compare error results in the assertion of a parity error (PERR

–C/BE0 buses. As an initiator during PCI cycles, the PCI1250A outputs this parity indicator with a

Terminal Functions (Continued)

–C/BE0 define the bus command. During the data phase, this

applies to byte 0 (AD7–AD0), C/BE1 applies to byte 1 (AD15–AD8), C/BE2 applies to

applies to byte 3 (AD31–AD24).

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FUNCTION

PCI interface control

TERMINAL

NAME NO.

DEVSEL

FRAME

GNT

GPIO2/LOCK

IDSEL N20 I

IRDY

PERR

REQ

SERR

STOP

TRDY

V20 I/O

T19 I/O

J20 I

V19 I/O

T18 I/O

U18 I/O K17 O PCI bus request. REQ is asserted by the PCI1250A to request access to the PCI bus as an initiator.

U19 O

T17 I/O

U20 I/O

I/O

TYPE

PCI1250A

PC CARD CONTROLLER

XCPS014 – DECEMBER 1997

Terminal Functions (Continued)

PCI device select. The PCI1250A asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator on the bus, the PCI1250A monitors DEVSEL timeout occurs, the PCI1250A terminates the cycle with an initiator abort.

PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME deasserted, the PCI bus transaction is in the final data phase.

PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1250A access to the PCI bus after the current data transaction has completed. GNT PCI bus parking algorithm.

PCI bus general-purpose I/O pins or PCI bus lock. GPIO2/LOCK can be configured as PCI LOCK and used to gain exclusive access downstream. Since this functionality is not typically used, a general-purpose I/O may be accessed through this terminal. GPIO2/LOCK configured through the GPIO2 control register.

Initialization device select. IDSEL selects the PCI1250A during configuration space accesses. IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus.

PCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK where both IRDY Until IRDY

PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not match PAR when PERR is enabled through bit 6 of the command register.

PCI system error. SERR is an output that is pulsed from the PCI1250A when enabled through the command register, indicating a system error has occurred. The PCI1250A need not be the target of the PCI cycle to assert this signal. When SERR that an address parity error has occurred on a CardBus interface.

PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus transaction. STOP support burst data transfers.

PCI target ready. TRDY indicates the primary bus target’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY Until both IRDY

and TRDY are both sampled asserted, wait states are inserted.

is enabled in the bridge control register, this signal also pulses, indicating

is used for target disconnects and is commonly asserted by target devices that do not

and TRDY are asserted, wait states are inserted.

until a target responds. If no target responds before

may or may not follow a PCI bus request, depending on the

defaults to a general-purpose input and can be

and TRDY are asserted.

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PCI1250A

FUNCTION

PC CARD CONTROLLER

XCPS014 – DECEMBER 1997

system interrupt

TERMINAL

NAME NO.

GPIO3/INTA

IRQSER/INTB W13 I/O

IRQMUX7 IRQMUX6 IRQMUX5 IRQMUX4 IRQMUX3 IRQMUX2 IRQMUX1 IRQMUX0

RI_OUT/PME Y13 O

V13 I/O

Y12 U11

W10

V9 U9 Y8

I/O

TYPE

Parallel PCI interrupt. GPIO3/INT A can be connected to an available PCI interrupt if parallel PCI interrupts are used, and the PCI1250A outputs PCI INTA through this terminal. GPIO3/INTA general-purpose input.

Serial interrupt signal/parallel PCI interrupt. When IRQSER/INTB is configured as IRQSER, it provides the IRQSER-style serial interrupting scheme. Serialized PCI interrupts can also be sent in the IRQSER stream. IRQSER/INTB because this is the default interrupt signaling method.

Interrupt request/secondary functions multiplexed. The primary function of these terminals is to provide the ISA-type IRQ signaling supported by the PCI1250A. These interrupt multiplexer outputs can be mapped to any of 15 IRQs. The device control register must be programmed for the ISA IRQ interrupt mode and the IRQMUX routing register must have the IRQ routing programmed before these terminals are enabled.

All of these terminals have secondary functions, such as PC/PCI DMA request/grant, ring indicate output, and zoom video status, that can be selected with the appropriate programming of this register. When the secondary functions are enabled, the respective terminals are not available for IRQ routing.

See the IRQMUX routing register for programming options. Ring indicate output/power management event. RI_OUT allows the RI input from a PC Card to pass through

to the system. This pin can be configured as the PME pin is RI_OUT register. This pin is PME

IRQMUX4 or IRQMUX3 can be used to route the RI_OUT and a ring indicate signal is still required.

Terminal Functions (Continued)

defaults to a

can be configured as the parallel PCI INTB interrupt. IRQSER/INTB defaults to IRQSER

pin by setting bit 0 in the system control register. This

when RIENB is enabled in the card control register and ExCA interrupt and general control

when RIENB is disabled and bit 1 of the system control register is 1.

signal when the PME signal is routed on pin Y13

PC/PCI DMA

TERMINAL

NAME NO.

PCGNT/

IRQMUX6

PCREQ/

IRQMUX7

U11 I/O

Y12 O

I/O

TYPE

PC/PCI DMA grant. PCGNT is used to grant the DMA channel to a requester in a system supporting the PC/PCI DMA scheme.

Interrupt request MUX 6. When configured for IRQMUX6, this terminal provides the IRQMUX6 interrupt output of the interrupt multiplexer, and can be mapped to any of 15 ISA-type IRQs. IRQMUX6 takes precedence over PCGNT

, and should not be enabled in a system using PC/PCI DMA. This terminal is also used for the serial EEPROM interface. PC/PCI DMA request. PCREQ is used to request DMA transfers as DREQ in a system supporting the PC/PCI

DMA scheme. Interrupt request MUX 7. When configured for IRQMUX7, this terminal provides the IRQMUX7 interrupt output

of the interrupt multiplexer, and can be mapped to any of 15 ISA-type IRQs. IRQMUX7 takes precedence over PCREQ

, and should not be enabled in a system using PC/PCI DMA.

This terminal is also used for the serial EEPROM interface.

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INTERFACE

FUNCTION

zoom video

PCI1250A

PC CARD CONTROLLER

XCPS014 – DECEMBER 1997

Terminal Functions (Continued)

TERMINAL

NAME NO.

ZV_HREF

ZV_VSYNC

ZV_Y7 ZV_Y6 ZV_Y5 ZV_Y4 ZV_Y3 ZV_Y2 ZV_Y1 ZV_Y0

ZV_UV7 ZV_UV6 ZV_UV5 ZV_UV4 ZV_UV3 ZV_UV2 ZV_UV1 ZV_UV0

ZV_SCLK C2 A7 O Audio SCLK PCM

ZV_MCLK D3 A6 O Audio MCLK PCM

ZV_PCLK E1 IOIS16 O Pixel clock to the zoom video port ZV_LRCLK E3 INPACK O Audio LRCLK PCM ZV_SDATA E2 SPKR O Audio SDATA PCM

ZV_RSVD F1, F2, F3, G4 O Reserved. No connection.

ZV_RSV1

ZV_RSV0

A6 A10 O C7 A11 O A3

B4 C5 B5 C6 D7 A5 B6

D2 C3 B1 B2 A2 C4 B3 D5

C1 E4

I/O AND MEMORY

SIGNAL

A20 A14 A19 A13 A18

A17

A25 A12 A24 A15 A23 A16 A22 A21

A5 A4

I/O

TYPE

Horizontal sync to the zoom video port Vertical sync to the zoom video port

O Video data to the zoom video port in YV:4:2:2 format

Reserved. No connection in the PC Card. ZV_RSVD1 and ZV_RSVD0 are

put into the high-impedance state by host adapter.

miscellaneous

TERMINAL

NAME NO.

GPIO0/LEDA1 V11 I/O

GPIO1/LEDA2 W11 I/O

SPKROUT

SUSPEND

Y10 O

Y11 I

I/O

TYPE

GPIO0/socket activity LED indicator 1. When GPIO0/LEDA1 is configured as LEDA1, it provides an output indicating PC Card socket 0 activity. Otherwise, GPIO0/LEDA1 can be configured as a general-purpose input and output, GPIO0. The zoom video enable signal (ZV_STAT) can also be routed to this signal through the GPIO0 control register. GPIO0/LEDA1 defaults to a general-purpose input.

GPIO1/socket activity LED indicator 2. When GPIO1/LEDA2 is configured as LEDA2, it provides an output indicating PC Card socket 1 activity. Otherwise, GPIO1/LEDA2 can be configured as a general-purpose input and output, GPIO1. A CSC interrupt can be generated on a GPDATA change, and this input can be used for power switch overcurrent (OC) sensing. See GPIO1/LEDA2 defaults to a general-purpose input.

Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO through the PCI1250A from the PC Card interface. SPKROUT is driven as the exclusive-OR combination of card SPKR

//CAUDIO inputs.

Suspend. SUSPEND is used to protect the internal registers from clearing when PRST is asserted. See

SUSPEND mode

for details.

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GPIO1 control register

for programming details.

+ 18 hidden pages

TEXAS INSTRUMENTS PCI1250A Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual