Texas Instruments PCI1211GGU, PCI1211PGE Datasheet

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PC 98/99 Compliant

PCI Bus Power Management Interface Specification 1.0 Compliant

Advanced Configuration and Power Interface (ACPI) 1.0 Compliant

Fully Compatible With the Intel 430TX (Mobile Triton II) Chipset

PCI Local Bus Specification Revision 2.2 Compliant

1997 PC Card Standard Compliant

3.3-V Core Logic With Universal PCI Interfaces Compatible With 3.3-V and 5-V PCI Signaling Environments

Mix-and-Match 5-V/3.3-V PC Card16 Cards and 3.3-V CardBus Cards

Supports a Single PC Card or CardBus Slot With Hot Insertion and Removal

Provides Interface to Parallel Single-Slot PC Card Power-Interface Switches like the TI TPS2211

Supports Burst Transfers to Maximize Data Throughput on the PCI Bus and the CardBus Bus

Supports Parallel PCI Interrupts, Parallel ISA IRQ and Parallel PCI Interrupts, Serial ISA IRQ With Parallel PCI Interrupts, and Serial ISA IRQ and PCI Interrupts

Pin-to-Pin Compatible with PCI1210

Serial EEPROM Interface for Loading Subsystem ID and Subsystem Vendor ID

PCI1211 GGU/PGE

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

Pipelined Architecture Allows Greater Than 130M-Bytes-Per-Second Throughput From CardBus to PCI and From PCI to CardBus

Supports Up to Five General-Purpose I/Os

Five PCI Memory Windows and Two I/O Windows Available to the PC Card16 Socket

Two I/O Windows and Two Memory Windows Available to the CardBus Socket

Exchangeable Card Architecture (ExCA) Compatible Registers Are Mapped in Memory and I/O Space

Intel 82365SL-DF Register Compatible

Supports Distributed DMA (DDMA) and PC/PCI DMA

Supports 16-Bit DMA on the PC Card Socket

Supports Ring Indicate, SUSPEND, PCI CLKRUN

Supports PCI Bus Lock (LOCK)

LED Activity Pin

Advanced Submicron, Low-Power CMOS T echnology

Choice of Surface-Mount Packaging: – PGE Low-Profile Plastic Quad Flat

Package (LQFP)

– GGU High Density Ball Grid Array (BGA)

, and CardBus CCLKRUN

Table of Contents

Description 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System Block Diagram 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Terminal Assignments 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signal Name/Terminal Assignments 6. . . . . . . . . . . . . . . . . . . . . . .

Terminal Functions 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Supply Sequencing 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O Characteristics 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clamping Voltages 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peripheral Component Interconnect (PCI) Interface 22. . . . . . . .

PC Card Applications 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial Bus Interface 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Programmable Interrupt Subsystem 34. . . . . . . . . . . . . . . . . . . . . .

Power Management Overview 38. . . . . . . . . . . . . . . . . . . . . . . . . .

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Intel is a trademark of Intel Corporation. PC Card is a trademark of Personal Computer Memory Card International Association (PCMCIA). TI is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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PC Card Controller Programming Model 43. . . . . . . . . . . . . . . . . . . . .

PCI Configuration Registers 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ExCA Compatibility Registers 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CardBus Socket Registers 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Distributed DMA (DDMA) Registers 112. . . . . . . . . . . . . . . . . . . . . . . .

Absolute Maximum Ratings 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Recommended Operating Conditions 119. . . . . . . . . . . . . . . . . . . . . .

Electrical Characteristics 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCI Clock/Reset Timing Requirements 121. . . . . . . . . . . . . . . . . . . . .

PCI Timing Requirements 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parameter Measurement Information 122. . . . . . . . . . . . . . . . . . . . . . .

PCI Bus Parameter Measurement Information 123. . . . . . . . . . . . . . .

Mechanical Data 128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCI1211 GGU/PGE PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

description

The Texas Instruments PCI1211 is a high-performance PCI-to-PC Card controller that supports a single PC Card socket compliant with the 1995 PC Card Standard. The PCI1211 provides a rich feature set that makes it the best choice for bridging between PCI and PC Cards in both notebook and desktop computers. The 1997 PC Card Standard retains the 16-bit PC Card specification defined in PCMCIA Release 2.2, and defines the new 32-bit PC Card, CardBus, capable of full 32-bit data transfers at 33 MHz. The PCI121 1 supports both 16-bit and CardBus PC Cards, powered at 5 V or 3.3 V, as required.

The PCI121 1 is compliant with the either a PCI master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card direct memory access (DMA) transfers or CardBus PC Card bridging transactions. The PCI121 1 is also compliant with the latest

All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI121 1 is register compatible with the Intel 82365SL-DF ExCA controller. The PCI1211 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI1211 can also be programmed to accept fast posted writes to improve system-bus utilization.

Multiple system-interrupt signaling options are provided, including: parallel PCI, parallel ISA, serialized ISA, and serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to implement sideband functions. Many other features are designed into the PCI1211, such as socket activity light-emitting diode (LED) output, that are discussed in detail throughout the design specification.

An advanced complementary metal-oxide semiconductor (CMOS) process achieves low system-power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power management system to further reduce power consumption.

Unused PCI1211 inputs must be pulled up using a 43 kW resistor.

PCI Bus Power Management Interface Specification, Revision 1.0

PCI Local Bus Specification, Revision 2.2

, and its PCI interface can act as

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PCI1211 GGU/PGE

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

system block diagram

A simplified system block diagram using the PCI1211 is provided below. The PCI950 IRQ deserializer and the PCI930 zoomed video (ZV) switch are optional functions that can be used when the system requires that capability.

The PCI interface includes all address/data and control signals for PCI protocol. The 68-pin PC Card interface includes all address/data and control signals for CardBus and 16-bit (R2) protocols. When ZV is enabled (in 16-bit PC Card mode) 23 of the 68 signals are redefined to support the ZV protocol.

The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling. Other miscellaneous system interface terminals are available on the PCI1211 that include:

Programmable multifunction terminals

SUSPEND, RI_OUT/PME (power management control signal)

SPKROUT

PCI Bus

INTA

Activity LED

Interrupt

Controller

TPS2211

Power

Switch

PC Card

Socket

External ZV Port

NOTE: The PC Card interface is 68 pins for CardBus and 16-bit PC Cards. In ZV mode 23 pins are used for routing the ZV signals to the VGA

controller.

PCI1211

IRQSER

PCI930

ZV Switch

PCI950

IRQSER

Deserializer

Zoom Video

IRQ2–15

VGA

Controller

Audio

Sub-System

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PCI1211 GGU/PGE PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

terminal assignments

CTRDY

CIRDY

CFRAME

CC/BE2

CAD17

GND CAD18 CAD19

CVS2

CAD20

CRST

CAD21 CAD22

CREQ

CAD23

CC/BE3

CCCB CAD24 CAD25

CAD26

GND

CVS1

CINT

CSERR

CAUDIO

CSTSCHG

CCLKRUN

CCD2

CC CAD27 CAD28 CAD29 CAD30

RSVD

CAD31

PGE LOW-PROFILE QUAD FLAT PACKAGE

(BOTTOM VIEW)

CSTOP

105

CBLOCK

CPERR

103

104

102

CPAR

101

RSVD

100

CAD14

CAD16

CC/BE1

CAD12

CAD15

GND

CCLK

CGNT

CDEVSEL

106

107

108 109 110

111 112 113 114 115 116 117 118 119 120 121 122

123 124

125 126

127 128 129 130

131 132 133 134 135 136 137 138 139 140 141 142 143 144

1234567891011121314151617181920212223242526272829303132333435

CAD11

CAD13

CCCB

CAD10

CAD9

CC/BE0

CAD8

RSVD

CAD7

CAD6

CAD5

CAD4

CAD3

GND

CAD1

CAD2

CAD0

CCD1

VCCD0

VCCD1

72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37

VPPD1 VPPD0

SUSPEND MFUNC6 MFUNC5 MFUNC4

MFUNC3 MFUNC2 V

CCI

SPKROUT MFUNC1

MFUNC0 RI_OUT/PME GND AD0 AD1 AD2 AD3 AD4 AD5 AD6AD6

CC AD7 C/BE0 AD8

AD9 AD10 V

CCP AD11 GND AD12 AD13 AD14 AD15

C/BE1

REQ

GNT

AD31

AD30

GND

AD29

AD28

AD27

AD26

AD25

AD24

C/BE3

IDSEL

AD22

AD23

AD21

CCP

AD20

RST

GND

PCLK

AD19

AD18

AD17

AD16

C/BE2

FRAME

IRDY

TRDY

DEVSEL

STOP

PERR

SERR

PAR

PCI-to-CardBus Pin Diagram

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terminal assignments (continued)

PCI1211 GGU/PGE

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

A22 A15 A23 A12

A24

GND

A7 A25 VS2

RESET

INPACK

REG

CCCB

GND

VS1

READY(IREQ

WAIT

BVD2(SPKR

BVD1(STSCHG/RI)

WP(IOIS16)

CD2 V

D8 D1 D9 D2

D10

A5 A4

PGE LOW-PROFILE QUAD FLAT PACKAGE

(BOTTOM VIEW)

A20

105

A14

104

A19

103

102

A13

101

A18

100

GND

A11

IOWR

A17

A16

A21

106

107

108 109 110

111 112 113 114

115 116 117 118

119 120 121 122 123 124 125 126 127 128 129 130 131 132

)

133

)

134 135 136 137

138 139 140 141

142 143 144

1234567891011121314151617181920212223242526272829303132333435

IORD

CCCB

CE2

A10

CE1

D15

D14

D13

D12

GND

CD1

D11

VCCD0

VCCD1

72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53

52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37

VPPD1 VPPD0

SUSPEND MFUNC6 MFUNC5 MFUNC4

MFUNC3 MFUNC2 V

CCI

SPKROUT MFUNC1

MFUNC0 RI_OUT/PME GND AD0 AD1 AD2 AD3 AD4 AD5 AD6AD6

AD7 C/BE0 AD8 AD9 AD10 V

CCP AD11 GND AD12 AD13 AD14 AD15

C/BE1

REQ

GNT

AD31

AD30

GND

AD29

AD28

AD27

AD26

AD25

AD24

C/BE3

IDSEL

AD22

AD23

AD21

CCP

PCI-to-PC Card (16-Bit) Diagram

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AD20

RST

GND

PCLK

AD19

AD18

AD17

AD16

C/BE2

FRAME

IRDY

TRDY

DEVSEL

STOP

PERR

SERR

PAR

PCI1211 GGU/PGE PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

terminal assignments (continued)

GGU BALL GRID ARRAY PACKAGE

PCI Signals Interrupt

(BOTTOM VIEW)

Power

Switch

and Misc.

GND

CCC

CardBus Signals

423

Power Switch Interrupt and Miscellaneous

CCC

Clamping Voltages

CardBus Signals

PCI Signals

12 1310 118967

PCI-to-CardBus and PCI-to-PC Card (16-Bit) Diagram

signal names and terminal assignments

Signal names and their terminal assignments are shown in Table 1 through Table 4. Table 1 and Table 2 show the terminal assignments for the CardBus PC Card, and Table 3 and Table 4 show the terminal assignments for the 16-bit PC Card. Table 2 and Table 4 show the CardBus PC Card and the 16-bit PC Card terminals sorted alphanumerically by the signal name and its associated terminal number.

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SIGNAL NAME

PCI1211 GGU/PGE

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

Table 1. CardBus PC Card Signal Names – Sorted by BGA Terminal Number

PIN NO.

GGU PGE

A1 1 REQ A2 143 RSVD C12 105 CSTOP G11 91 CAD10 L5 46 AD9 A3 140 CAD28 C13 104 CPERR G12 89 CAD9 L6 50 V

A4 137 CCD2 D1 8 AD27 G13 90 V A5 133 CSERR D2 7 AD28 H1 21 PCLK L8 59 RI_OUT/PME A6 129 CAD26 D3 6 GND H2 22 GND L9 63 V A7 126 V A8 124 CAD23 D5 136 CCLKRUN H4 24 AD18 L11 70 SUSPEND

A9 120 CAD21 D6 132 CINT H10 85 CAD7 L12 75 CCD1 A10 116 CAD19 D7 128 CAD25 H11 86 V A11 112 CC/BE2 D8 121 CAD22 H12 87 CAD8 M1 35 SERR A12 110 CIRDY D9 117 CVS2 H13 88 CC/BE0 M2 36 PAR A13 109 CTRDY D10 113 CAD17 J1 25 AD17 M3 39 AD14

B1 2 GNT D11 103 CBLOCK J2 26 AD16 M4 43 AD11

B2 144 CAD31 D12 102 V

B3 141 CAD29 D13 101 CPAR J4 28 FRAME M6 51 AD6

B4 138 V

B5 134 CAUDIO E2 11 AD24 J11 82 CAD6 M8 58 GND

B6 130 GND E3 10 AD25 J12 83 CAD5 M9 62 SPKROUT

B7 125 CC/BE3 E4 9 AD26 J13 84 RSVD M10 66 V

B8 123 CREQ E10 100 RSVD K1 29 IRDY M11 69 MFUNC6

B9 119 CRST E11 99 CC/BE1 K2 30 V B10 115 CAD18 E12 98 CAD16 K3 31 TRDY M13 74 VCCD1 B11 111 CFRAME E13 97 CAD14 K4 41 AD12 N1 37 C/BE1 B12 108 CCLK F1 16 AD22 K5 45 AD10 N2 38 AD15 B13 107 CDEVSEL F2 15 AD23 K6 49 AD7 N3 40 AD13

C1 4 AD30 F3 14 V

C2 3 AD31 F4 13 IDSEL K8 60 MFUNC0 N5 48 C/BE0

C3 142 CAD30 F10 96 CAD15 K9 64 MFUNC2 N6 52 AD5 C4 139 CAD27 F11 95 CAD12 K10 77 CAD2 N7 54 AD3 C5 135 CSTSCHG F12 94 GND K11 78 GND N8 57 AD0 C6 131 CVS1 F13 93 CAD13 K12 79 CAD1 N9 61 MFUNC1 C7 127 CAD24 G1 18 V C8 122 V C9 118 CAD20 G3 19 AD20 L2 33 STOP N12 71 VPPD0

C10 114 GND G4 20 RST L3 34 PERR N13 73 VCCD0

†

The PGE (LQFP) pin numbers are shown also.

CCCB

PIN NO.

GGU PGE

C11 106 CGNT G10 92 CAD11 L4 42 GND

D4 5 AD29 H3 23 AD19 L10 67 MFUNC4

E1 12 C/BE3 J10 81 CAD3 M7 53 AD4

CCP

G2 17 AD21 L1 32 DEVSEL N11 68 MFUNC5

PIN NO.

GGU PGE

CCCB

J3 27 C/BE2 M5 47 AD8

K7 56 AD1 N4 44 V

K13 80 CAD4 N10 65 MFUNC3

PIN NO.

GGU PGE

L7 55 AD2

L13 76 CAD0

M12 72 VPPD1

†

CCI

CCP

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PCI1211 GGU/PGE

SIGNAL NAME

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

Table 2. CardBus PC Card Signal Names – Sorted Alphabetically

PIN NO.

PGE GGU

AD0 57 N8 CAD0 76 L13 CC/BE2 112 A11 AD1 56 K7 CAD1 79 K12 CC/BE3 125 B7 MFUNC3 65 N10 AD2 55 L7 CAD2 77 K10 CCLK 108 B12 MFUNC4 67 L10 AD3 54 N7 CAD3 81 J10 CCD1 75 L12 MFUNC5 68 N11 AD4 53 M7 CAD4 80 K13 CCD2 137 A4 MFUNC6 69 M11 AD5 52 N6 CAD5 83 J12 CCLKRUN 136 D5 PAR 36 M2 AD6 51 M6 CAD6 82 J11 CDEVSEL 107 B13 PCLK 21 H1 AD7 49 K6 CAD7 85 H10 CFRAME 111 B11 PERR 34 L3 AD8 47 M5 CAD8 87 H12 CGNT 106 C11 REQ 1A1 AD9 46 L5 CAD9 89 G12 CINT 132 D6 RI_OUT/PME 59 L8 AD10 45 K5 CAD10 91 G11 CIRDY 110 A12 RST 20 G4 AD11 43 M4 CAD11 92 G10 CPAR 101 D13 SERR 35 M1 AD12 41 K4 CAD12 95 F11 CPERR 104 C13 RSVD 84 E10 AD13 40 N3 CAD13 93 F13 CREQ 123 B8 RSVD 100 J13 AD14 39 M3 CAD14 97 E13 CRST 119 B9 RSVD 143 A2 AD15 38 N2 CAD15 96 F10 CSERR 133 A5 SPKROUT 62 M9 AD16 26 J2 CAD16 98 E12 CSTOP 105 C12 STOP 33 L2 AD17 25 J1 CAD17 113 D10 CSTSCHG 135 C5 SUSPEND 70 L11 AD18 24 H4 CAD18 115 B10 CTRDY 109 A13 TRDY 31 K3 AD19 23 H3 CAD19 116 A10 CVS1 131 C6 V AD20 19 G3 CAD20 118 C9 CVS2 117 D9 V AD21 17 G2 CAD21 120 A9 DEVSEL 32 L1 V AD22 16 F1 CAD22 121 D8 FRAME 28 J4 V AD23 15 F2 CAD23 124 A8 GND 6D3V AD24 11 E2 CAD24 127 C7 GND 22 H2 V AD25 10 E3 CAD25 128 D7 GND 42 L4 V AD26 9 E4 CAD26 129 A6 GND 58 M8 V AD27 8 D1 CAD27 139 C4 GND 78 K11 V AD28 7 D2 CAD28 140 A3 GND 94 F12 V AD29 5 D4 CAD29 141 B3 GND 114 C10 VCCD0 73 N13 AD30 4 C1 CAD30 142 C3 GND 130 B6 VCCD1 74 M13 AD31 3 C2 CAD31 144 B2 GNT 2B1V C/BE0 48 N5 CAUDIO 134 B5 IDSEL 13 F4 V C/BE1 37 N1 CBLOCK 103 D11 IRDY 29 K1 V C/BE2 27 J3 CC/BE0 88 H13 MFUNC0 60 K8 VPPD0 71 N12 C/BE3 12 E1 CC/BE1 99 E11 MFUNC1 61 N9 VPPD1 72 M12

PIN NO.

PGE GGU

PIN NO.

PGE GGU

PIN NO.

PGE GGU

MFUNC2 64 K9

CC CC CC CC CC CC CC CC CCCB CCCB

CCI CCP CCP

14 F3 30 K2 50 L6 66 M10

86 H11 102 D12 122 C8 138 B4

90 G13 126 A7

63 L9

18 G1

44 N4

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SIGNAL NAME

PCI1211 GGU/PGE

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

Table 3. 16-Bit PC Card Signal Names – Sorted by BGA Terminal Number

PIN NO.

GGU PGE

A1 1 REQ A2 143 D2 C12 105 A20 G11 91 CE2 L5 46 AD9 A3 140 D8 C13 104 A14 G12 89 A10 L6 50 V A4 137 CD2 D1 8 AD27 G13 90 V A5 133 WAIT D2 7 AD28 H1 21 PCLK L8 59 RI_OUT/PME A6 129 A0 D3 6 GND H2 22 GND L9 63 V A7 126 V A8 124 A3 D5 136 WP(IOIS16)H424 AD18 L11 70 SUSPEND

A9 120 A5 D6 132 READY(IREQ) H10 85 D7 L12 75 CD1 A10 116 A25 D7 128 A1 H11 86 V A11 112 A12 D8 121 A4 H12 87 D15 M1 35 SERR A12 110 A15 D9 117 VS2 H13 88 CE1 M2 36 PAR A13 109 A22 D10 113 A24 J1 25 AD17 M3 39 AD14

B1 2 GNT D11 103 A19 J2 26 AD16 M4 43 AD11

B2 144 D10 D12 102 V

B3 141 D1 D13 101 A13 J4 28 FRAME M6 51 AD6

B4 138 V

B5 134 BVD2(SPKR)E211 AD24 J11 82 D13 M8 58 GND

B6 130 GND E3 10 AD25 J12 83 D6 M9 62 SPKROUT

B7 125 REG E4 9 AD26 J13 84 D14 M10 66 V

B8 123 INPACK E10 100 A18 K1 29 IRDY M11 69 MFUNC6

B9 119 RESET E11 99 A8 K2 30 V B10 115 A7 E12 98 A17 K3 31 TRDY M13 74 VCCD1 B11 111 A23 E13 97 A9 K4 41 AD12 N1 37 C/BE1 B12 108 A16 F1 16 AD22 K5 45 AD10 N2 38 AD15 B13 107 A21 F2 15 AD23 K6 49 AD7 N3 40 AD13

C1 4 AD30 F3 14 V C2 3 AD31 F4 13 IDSEL K8 60 MFUNC0 N5 48 C/BE0

C3 142 D9 F10 96 IOWR K9 64 MFUNC2 N6 52 AD5

C4 139 D0 F11 95 A11 K10 77 D11 N7 54 AD3

C5 135

C6 131 VS1 F13 93 IORD K12 79 D4 N9 61 MFUNC1

C7 127 A2 G1 18 V

C8 122 V

C9 118 A6 G3 19 AD20 L2 33 STOP N12 71 VPPD0

C10 114 GND G4 20 RST L3 34 PERR N13 73 VCCD0

†

The PGE (LQFP) pin numbers are shown also.

CCCB

BVD1(STSCHG/RI)

PIN NO.

GGU PGE

C11 106 WE G10 92 OE L4 42 GND

D4 5 AD29 H3 23 AD19 L10 67 MFUNC4

E1 12 C/BE3 J10 81 D5 M7 53 AD4

F12 94 GND K11 78 GND N8 57 AD0

CCP

G2 17 AD21 L1 32 DEVSEL N11 68 MFUNC5

PIN NO.

GGU PGE

CCCB

J3 27 C/BE2 M5 47 AD8

K7 56 AD1 N4 44 V

K13 80 D12 N10 65 MFUNC3

PIN NO.

GGU PGE

L7 55 AD2

L13 76 D3

M12 72 VPPD1

†

CCI

CCP

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PCI1211 GGU/PGE

SIGNAL NAME

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

Table 4. 16-Bit PC Card Signal Names – Sorted Alphabetically

PIN NO.

PGE GGU

A0 129 A6 AD10 45 K5 D4 79 K12 PAR 36 M2 A1 128 D7 AD11 43 M4 D5 81 J10 PCLK 21 H1 A2 127 C7 AD12 41 K4 D6 83 J12 PERR 34 L3 A3 124 A8 AD13 40 N3 D7 85 H10 REQ 1A1 A4 121 D8 AD14 39 M3 D8 140 A3 READY(IREQ) 132 D6 A5 120 A9 AD15 38 N2 D9 142 C3 REG 125 B7 A6 118 C9 AD16 26 J2 D10 144 B2 RESET 119 B9 A7 115 B10 AD17 25 J1 D11 77 K10 RI_OUT/PME 59 L8 A8 99 E11 AD18 24 H4 D12 80 K13 RST 20 G4 A9 97 E13 AD19 23 H3 D13 82 J1 1 SERR 35 M1 A10 89 G12 AD20 19 G3 D14 84 J13 SPKROUT 62 M9 A11 95 F11 AD21 17 G2 D15 87 H12 STOP 33 L2 A12 112 A11 AD22 16 F1 DEVSEL 32 L1 SUSPEND 70 L11 A13 101 D13 AD23 15 F2 FRAME 28 J4 TRDY 31 K3 A14 104 C13 AD24 11 E2 GND 6D3V A15 110 A12 AD25 10 E3 GND 22 H2 V A16 108 B12 AD26 9 E4 GND 42 L4 V A17 98 E12 AD27 8 D1 GND 58 M8 V A18 100 E10 AD28 7 D2 GND 78 K11 V A19 103 D11 AD29 5 D4 GND 94 F12 V A20 105 C12 AD30 4 C1 GND 114 C10 V A21 107 B13 AD31 3 C2 GND 130 B6 V A22 109 A13 A23 111 B11 BVD2(SPKR) 134 B5 IDSEL 13 F4 V A24 113 D10 C/BE0 48 N5 INPACK 123 B8 VCCD0 73 N13 A25 116 A10 C/BE1 37 N1 IORD 93 F13 VCCD1 74 M13 AD0 57 N8 C/BE2 27 J3 IOWR 96 F10 V AD1 56 K7 C/BE3 12 E1 IRDY 29 K1 V AD2 55 L7 CD1 75 L12 MFUNC0 60 K8 V AD3 54 N7 CD2 137 A4 MFUNC1 61 N9 VPPD0 71 N12 AD4 53 M7 CE1 88 H13 MFUNC2 64 K9 VPPD1 72 M12 AD5 52 N6 CE2 91 G11 MFUNC3 65 N10 VS1 131 C6 AD6 51 M6 D0 139 C4 MFUNC4 67 L10 VS2 117 D9 AD7 49 K6 D1 141 B3 MFUNC5 68 N11 WAIT 133 A5 AD8 47 M5 D2 143 A2 MFUNC6 69 M11 WE 106 C11 AD9 46 L5 D3 76 L13 OE 92 G10 WP(IOIS16) 136 D5

BVD1(STSCHG/RI)

PIN NO.

PGE GGU

135 C5 GNT 2B1V

PIN NO.

PGE GGU

CC CC CC CC CC CC CC CC CCCB CCCB

CCI CCP CCP

PIN NO.

PGE GGU

14 F3 30 K2 50 L6 66 M10

86 H1 1 102 D12 122 C8 138 B4

90 G13 126 A7

63 L9

18 G1

44 N4

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FUNCTION

NAME

TYPE

NAME

TYPE

PCI1211 GGU/PGE

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

Terminal Functions

The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The terminal numbers are also listed for convenient reference. Terminal numbers are shown for both the PGE LQF package and the GGU ball grid array package.

power supply

TERMINAL

NAME PGE NUMBER GGU NUMBER

GND 6, 22, 42, 58, 78, 94, 114, 130

CCCB

CCI

CCP

14, 30, 50, 66, 86, 102, 122,

138

90, 126 A7, G13

63 L9 Clamping voltage for multifunction terminals (5 V or 3.3 V)

18, 44 G1, N4 Clamping voltage for PCI signaling (5 V or 3.3 V)

PC Card power switch

VCCD0 VCCD1

VPPD0 VPPD1

TERMINAL

PIN NUMBER

PGE GGU

7374N13

M13

7172N12

M12

I/O

B6, C10, D3, F12, H2, K11, L4,

B4, C8, D12, F3, H11, K2, L6,

M10

Logic controls to the TPS2211 PC Card power interface switch to control AVCC.

Logic controls to the TPS2211 PC Card power interface switch to control AVPP.

Device ground terminals

Power supply terminal for core logic (3.3 V) Clamping voltage for PC Card interface. Indicates card

signaling environment of 5 V or 3.3 V.

FUNCTION

PCI system

TERMINAL

PIN NUMBER

PGE GGU

PCLK 21 H1 I

RST

20 G4 I

I/O

PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCLK.

PCI reset. When the PCI bus reset is asserted, RST causes the PCI1211 to place all output buffers in a high-impedance state and reset all internal registers. When RST completely nonfunctional. After RST

When SUSPEND registers. All outputs are placed in a high-impedance state, but the contents of the registers are preserved.

and RST are asserted, the device is protected from RST clearing the internal

FUNCTION

is asserted, the device is

is deasserted, the PCI1211 is in its default state.

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PCI address and data

TERMINAL

PIN NUMBER

PGE GGU

AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10

AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

C/BE3 C/BE2 C/BE1 C/BE0

PAR 36 M2 I/O

3 4 5 7 8 9

11 15 16 17 19 23 24 25 26 38 39 40 41 43 45 46 47 49 51 52 53 54 55 56 57

12 27 37 48

C2 C1 D4 D2 D1 E4 E3 E2

F1 G2 G3 H3 H4

J2 N2 M3 N3 K4 M4 K5

L5 M5 K6 M6 N6 M7 N7

L7 K7 N8

J3 N1 N5

I/O

Terminal Functions (Continued)

FUNCTION

PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary interface. During the address phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit address or other destination information. During the data phase, AD31–AD0 contain data.

PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address phase of a primary bus PCI cycle, C/BE3 phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. C/BE0 (AD15–AD8), C/BE2

PCI bus parity. In all PCI bus read and write cycles, the PCI1211 calculates even parity across the AD31–AD0 and C/BE3 indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator’s parity indicator. A compare error results in the assertion of a parity error (PERR

applies to byte 2 (AD23–AD16), and C/BE3 applies to byte 3 (AD31–AD24).

–C/BE0 buses. As an initiator during PCI cycles, the PCI1211 outputs this parity

–C/BE0 define the bus command. During the data

applies to byte 0 (AD7–AD0), C/BE1 applies to byte 1

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NAME

TYPE

PCI interface control

TERMINAL

PIN NUMBER

PGE GGU

DEVSEL

FRAME

GNT

IDSEL 13 F4 I

IRDY

PERR

REQ

SERR

STOP

TRDY

32 L1 I/O

28 J4 I/O

2 B1 I

29 K1 I/O

34 L3 I/O

1 A1 O PCI bus request. REQ is asserted by the PCI1211 to request access to the PCI bus as an initiator .

35 M1 O

33 L2 I/O

31 K3 I/O

PCI1211 GGU/PGE

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

Terminal Functions (Continued)

I/O

PCI device select. The PCI1211 asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator on the bus, the PCI1211 monitors DEVSEL responds before timeout occurs, the PCI1211 terminates the cycle with an initiator abort.

PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME

is deasserted, the PCI bus transaction is in the final data phase.

PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1211 access to the PCI bus after the current data transaction has completed. GNT depending on the PCI bus parking algorithm.

Initialization device select. IDSEL selects the PCI1211 during configuration space accesses. IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus.

PCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK where both IRDY are asserted. Until IRDY and TRDY are both sampled asserted, wait states are inserted.

PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not match PAR when PERR

PCI system error. SERR is an output that is pulsed from the PCI1211 when enabled through the command register indicating a system error has occurred. The PCI121 1 need not be the target of the PCI cycle to assert this signal. When SERR pulses, indicating that an address parity error has occurred on a CardBus interface.

PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus transaction. STOP that do not support burst data transfers.

PCI target ready. TRDY indicates the primary bus target’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY are asserted. Until both IRDY and TRDY are asserted, wait states are inserted.

is enabled through bit 6 of the command register.

is used for target disconnects and is commonly asserted by target devices

FUNCTION

until a target responds. If no target

may or may not follow a PCI bus request,

is enabled in the control register, this signal also

and TRDY

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Terminal Functions (Continued)

multifunction and miscellaneous pins

TERMINAL

PIN NUMBER

PGE GGU

MFUNC0 60 K8 I/O

MFUNC1 61 N9 I/O

MFUNC2 64 K9 I/O

MFUNC3 65 N10 I/O

MFUNC4 67 L10 I/O

MFUNC5 68 N1 1 I/O

MFUNC6 69 M11 I/O

RI_OUT/PME 59 L8 O

SUSPEND 70 L11 I

SPKROUT 62 M9 O

I/O

FUNCTION

Multifunction Terminal 0. MFUNC0 can be configured as parallel PCI interrupt INTA, GPI0, GPO0, GPE

, socket activity LED output, ZV output select, CardBus audio PWM, or a parallel IRQ. Refer

to the

multifunction routing register

Multifunction Terminal 1. MFUNC1 can be configured as GPI1, GPO1, GPE, socket activity LED output, ZV output select, CardBus audio PWM, or a parallel IRQ. Refer to the

routing register

Serial Data (SDA). When the serial bus mode is implemented by pulling up the SCA and SCL terminals, the MFUNC1 terminal provides the SDA signaling. The two-pin serial interface is used to load the subsystem identification and other register defaults from an EEPROM after a PCI reset. Refer to the bus applications.

Multifunction Terminal 2. MFUNC2 can be configured as PC/PCI DMA Request, GPI2, GPO2, socket activity LED output, ZV output select, CardBus audio PWM, GPE IRQ. Refer to the

Multifunction Terminal 3. MFUNC3 can be configured as a parallel IRQ or the serialized interrupt signal IRQSER. Refer to the details.

Multifunction Terminal 4. MFUNC4 can be configured as PCI LOCK, GPI3, GPO3, socket activity LED, RI_OUT

multifunction routing register

Serial Clock (SCL). When the serial bus mode is implemented by pulling the SDA and SCL terminals, the MFUNC4 terminal provides the SCL signaling. The two-pin serial interface is used to load the subsystem identification and other register defaults from an EEPROM after a PCI reset. Refer to the bus applications.

Multifunction Terminal 5. MFUNC5 can be configured as PC/PCI DMA Grant, GPI4, GPO4, socket activity LED output, ZV output select, CardBus audio PWM, GPE to the

multifunction routing register

Multifunction Terminal 6. MFUNC6 can be configured as a PCI CLKRUN or a parallel IRQ. Refer to the

multifunction routing register

Ring Indicate Out and Power Management Event Output. Provides output for either RI_OUT or PME

signals.

Suspend. SUSPEND is used to protect the internal registers from clearing when the RST signal is asserted. See

Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO through the PCI1211 from the PC Card interface. SPKROUT is driven as the exclusive-OR combination of card SPKR

description on page 61 for configuration details.

serial bus interface protocol

multifunction routing register

output, ZV output select, CardBus audio PWM, GPE, or a parallel IRQ. Refer to the

serial bus interface protocol

suspend mode

description on page 61 for configuration details.

description on page 30 for details on other serial

description on page 61 for configuration details.

multifunction routing register

description on page 61 for configuration details.

description on page 30 for details on other serial

description on page 61 for configuration details.

on page 39 for details.

//CAUDIO inputs.

description on page 61 for configuration

multifunction

, RI_OUT, or a parallel

, or a parallel IRQ. Refer

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TYPE

PCI1211 GGU/PGE

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

Terminal Functions (Continued)

The address and data and interface control terminals for the 16-bit PC Card are shown in the following two tables.

16-bit PC Card address and data

TERMINAL

A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D15 D14 D13 D12 D11 D10

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

PIN NUMBER

PGE GGU

116

A10

113

D10

111

B11

109

A13

107

B13

105

C12

103

D11

100

E10

E12

108

B12

110

A12

104

C13

101

D13

112

A11

F11

G12

E13

E11

115

B10

118 120 121 124 127 128 129

H12

J13

J11

K13

K10 144 142 140

H10

J12

J10

K12

L13 143 141 139

I/O

O PC Card address. 16-bit PC Card address lines. A25 is the most-significant bit.

C9 A9 D8 A8 C7 D7 A6

B2 C3 A3

I/O PC Card data. 16-bit PC Card data lines. D15 is the most-significant bit.

A2 B3 C4

FUNCTION

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PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

16-bit PC Card interface control

TERMINAL

PIN NUMBER

PGE GGU

BVD1

(STSCHG

BVD2

(SPKR

CD1 CD2

CE1 CE2

INPACK 123 B8 I

IORD

IOWR

OE 92 G10 O

135 C5 I

/RI)

134 B5 I

)

137

8891H13

93 F13 O

96 F10 O

L12

G11

I/O

Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are kept high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See

Status change. STSCHG is used to alert the system to a change in the READY, write protect, or battery voltage dead condition of a 16-bit I/O PC Card.

Ring indicate. RI Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include batteries.

BVD2 is used with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See

Speaker. SPKR been configured for the 16-bit I/O interface. The audio signals from cards A and B are combined by the PCI1211 and are output on SPKROUT.

DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. The PC Card asserts BVD2 to indicate a request for a DMA operation.

PC Card detect 1 and PC Card detect 2. CD1 and CD2 are internally connected to ground on the PC Card. When a PC Card is inserted into a socket, CD1

see Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address bytes.

CE1 Input acknowledge. INP ACK is asserted by the PC Card when it can respond to an I/O read cycle

at the current address. DMA request. INPACK

PC Card that supports DMA. If used as a strobe, the PC Card asserts this signal to indicate a request for a DMA operation.

I/O read. IORD is asserted by the PCI1211 to enable 16-bit I/O PC Card data output during host I/O read cycles.

DMA write. IORD that supports DMA. The PCI1211 asserts IORD memory.

I/O write. IOWR is driven low by the PCI1211 to strobe write data into 16-bit I/O PC Cards during host I/O write cycles.

DMA read. IOWR that supports DMA. The PCI1211 asserts IOWR

Output enable. OE is driven low by the PCI1211 to enable 16-bit memory PC Card data output during host memory read cycles.

DMA terminal count. OE that supports DMA. The PCI1211 asserts OE

Terminal Functions (Continued)

FUNCTION

on page 89 for enable bits. See

on page 85 for the status bits for this signal.

is used by 16-bit modem cards to indicate a ring detection.

on page 89 for enable bits. See

on page 85 for the status bits for this signal.

is an optional binary audio signal available only when the card and socket have

interface status register.

enables even-numbered address bytes, and CE2 enables odd-numbered address bytes.

can be used as the DMA request signal during DMA operations from a 16-bit

is used as the DMA write strobe during DMA operations from a 16-bit PC Card

is used as terminal count (TC) during DMA operations to a 16-bit PC Card

ExCA card status-change interrupt configuration

ExCA card status-change register

ExCA card status-change interrupt configuration

ExCA card status-change register

and CD2 are pulled low. For signal status,

during DMA transfers from the PC Card to host

during transfers from host memory to the PC Card.

to indicate TC for a DMA write operation.

on page 88 and the

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NAME

TYPE

Terminal Functions (Continued)

16-bit PC Card interface control (continued)

TERMINAL

PIN NUMBER

PGE GGU

READY

(IREQ

REG

RESET 119 B9 O PC Card reset. RESET forces a hard reset to a 16-bit PC Card.

WAIT

WE 106 C11 O

(IOIS16

VS1 VS2

132 D6 I

)

125 B7 O

133 A5 I

136 D5 I

)

131

117C6D9

I/O

Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket are configured for the memory-only interface. READY is driven low by the 16-bit memory PC Cards to indicate that the memory card circuits are busy processing a previous write command. READY is driven high when the 16-bit memory PC Card is ready to accept a new data transfer command.

Interrupt request. IREQ the 16-bit I /O PC Card requires service by the host software. IREQ interrupt is requested.

Attribute memory select. REG remains high for all common memory accesses. When REG is asserted, access is limited to attribute memory (OE

active). Attribute memory is a separately accessed section of card memory and is generally

IOWR used to record card capacity and other configuration and attribute information.

DMA acknowledge. REG is used as a DMA acknowledge (DACK) during DMA operations to a 16-bit PC Card that supports DMA. The PCI121 1 asserts REG is used in conjunction with the DMA read (IOWR) or DMA write (IORD) strobes to transfer data.

Bus cycle wait. WAIT is driven by a 16-bit PC Card to delay the completion of (i.e., extend) the memory or I/O cycle in progress.

Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also used for memory PC Cards that employ programmable memory technologies.

DMA terminal count. WE DMA. The PC1211 asserts WE

Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16 function.

I/O is 16 bits. IOIS16 the address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that is addressed is capable of 16-bit accesses.

DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, the PC Card asserts WP to indicate a request for a DMA operation.

Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other,

I/O

determine the operating voltage of the 16-bit PC Card.

is asserted by a 16-bit I/O PC Card to indicate to the host that a device on

is used as TC during DMA operations to a 16-bit PC Card that supports

to indicate TC for a DMA read operation.

applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card when

FUNCTION

or WE active) and to the I/O space (IORD or

PCI1211 GGU/PGE

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

is high (deasserted) when no

to indicate a DMA operation. REG

)

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PCI1211 GGU/PGE

NAME

TYPE

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

Terminal Functions (Continued)

The interface system, address and data, and interface control terminals for the CardBus PC Card system are shown in the following three tables.

CardBus PC Card interface system

TERMINAL

PIN NUMBER

PGE GGU

CCLK 108 B12 O

CCLKRUN

CRST

136 D5 O

119 B9 I/O

I/O

CardBus PC Card clock. CCLK provides synchronous timing for all transactions on the CardBus interface. All signals except CRST CVS2–CVS1 are sampled on the rising edge of CCLK, and all timing parameters are defined with the rising edge of this signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the low state or slowed down for power savings.

CardBus PC Card clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the CCLK frequency, and by the PCI121 1 to indicate that the CCLK frequency is going to be decreased.

CardBus PC Card reset. CRST is used to bring CardBus PC Card-specific registers, sequencers, and signals to a known state. When CRST and the PCI1211 drives these signals to a valid logic level. Assertion can be asynchronous to CCLK, but deassertion must be synchronous to CCLK.

FUNCTION

, CLKRUN, CINT, CSTSCHG, CAUDIO, CCD1, CCD2, and

is asserted, all CardBus PC Card signals must be 3-stated,

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Terminal Functions (Continued)

CardBus PC Card address and data

TERMINAL

PIN NUMBER

PGE GGU

CAD31 CAD30 CAD29 CAD28 CAD27 CAD26 CAD25 CAD24 CAD23 CAD22 CAD21 CAD20 CAD19 CAD18 CAD17 CAD16 CAD15 CAD14 CAD13 CAD12 CAD11 CAD10

CAD9 CAD8 CAD7 CAD6 CAD5 CAD4 CAD3 CAD2 CAD1 CAD0

CC/BE3 CC/BE2 CC/BE1 CC/BE0

CPAR 101 D13 I/O

144 142 141 140 139 129 128 127 124 121 120 118 116 115 113

98 96 97 93 95 92 91 89 87 85 82 83 80 81 77 79 76

12 27 37 48

A10 B10

D10

E12 F10 E13 F13

F11 G10 G11 G12 H12 H10

J11 J12 K13 J10 K10 K12 L13

B2 C3 B3 A3 C4 A6 D7 C7 A8 D8 A9 C9

J3 N1 N5

I/O

PC Card address and data. These signals make up the multiplexed CardBus address and data bus on the CardBus interface. During the address phase of a CardBus cycle, CAD31–CAD0 contain a 32-bit

I/O

address. During the data phase of a CardBus cycle, CAD31–CAD0 contain data. CAD31 is the most-significant bit.

CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the same CardBus terminals. During the address phase of a CardBus cycle, CC/BE3 During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte

I/O

paths of the full 32-bit data bus carry meaningful data. CC/BE0 applies to byte 1 (CAD15–CAD8), CC/BE2 applies to byte 2 (CAD23–CAD16), and CC/BE3 applies to byte 3 (CAD31–CAD24).

CardBus parity. In all CardBus read and write cycles, the PCI121 1 calculates even parity across the CAD and CC/BE delay. As a target during CardBus cycles, the calculated parity is compared to the initiator’s parity indicator; a compare error results in a parity error assertion.

buses. As an initiator during CardBus cycles, the PCI1211 outputs CPAR with a one-CCLK

PCI1211 GGU/PGE

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

FUNCTION

–CC/BE0 defines the bus command.

applies to byte 0 (CAD7–CAD0), CC/BE1

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NAME

TYPE

CVS2 to identif

I/O

ith CCD1

CCD2 to identif

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

Terminal Functions (Continued)

CardBus PC Card interface control

TERMINAL

PIN NUMBER

PGE GGU

CAUDIO 134 B5 I

CBLOCK

CCD1 CCD2

CDEVSEL

CFRAME

CGNT

CINT

CIRDY

CPERR

CREQ

CSERR

CSTOP

CSTSCHG

CTRDY

CVS1 131 C6 CVS2 117 D9

103 D11 I/O

75 L12

137 A4

107 B13 I/O

111 B11 I/O

106 C11 I

132 D6 I

110 A12 I/O

104 C13 I/O

123 B8 I

133 A5 I

105 C12 I/O

135 C5 I

109 A13 I/O

I/O

CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The PCI121 1 supports the binary audio mode and outputs a binary signal from the card to SPKROUT.

CardBus lock. CBLOCK is used to gain exclusive access to a target. CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with CVS1 and

type. CardBus device select. The PCI1211 asserts CDEVSEL to claim a CardBus cycle as the target

device. As a CardBus initiator on the bus, the PCI1211 monitors CDEVSEL If no target responds before timeout occurs, the PCI1211 terminates the cycle with an initiator abort.

CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When CFRAME

CardBus bus grant. CGNT is driven by the PCI1211 to grant a CardBus PC Card access to the CardBus bus after the current data transaction has been completed.

CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the host.

CardBus initiator ready. CIRDY indicates the CardBus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY CTRDY

CardBus parity error. CPERR is used to report parity errors during CardBus transactions, except during special cycles. It is driven low by a target two clocks following that data when a parity error is detected.

CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus bus as an initiator.

CardBus system error. CSERR reports address parity errors and other system errors that could lead to catastrophic results. CSERR pullup, and may take several CCLK periods. The PCI1211 can report CSERR assertion of SERR

CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus transaction. CSTOP devices that do not support burst data transfers.

CardBus status change. CSTSCHG is used to alert the system to a change in the card’s status, and is used as a wake-up mechanism.

CardBus target ready. CTRDY indicates the CardBus target’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY and CTRDY are asserted; until this time, wait states are inserted.

CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in conjunction w voltage and card type.

FUNCTION

y card insertion and interrogate cards to determine the operating voltage and car

until a target responds.

is deasserted, the CardBus bus transaction is in the final data phase.

are asserted. Until CIRDY and CTRDY are both sampled asserted, wait states are inserted.

on the PCI interface.

and

is driven by the card synchronous to CCLK, but deasserted by a weak

is used for target disconnects, and is commonly asserted by target

y card insertion and interrogate cards to determine the operating

to the system by

and

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power supply sequencing

The PCI1211 contains 3.3-V I/O buffers with 5-V tolerance requiring a core power supply and clamp voltage. The core power supply is always 3.3 V . The clamp voltage can be either 3.3 V or 5 V , depending on the interface. The following power-up and power-down sequences are recommended.

The power-up sequence is:

1. Apply 3.3-V power to the core.

2. Assert PRST

to the device to disable the outputs during power up. Output drivers must be powered up in

the high-impedance state to prevent high current levels through the clamp diodes to the 5-V supply.

3. Apply the clamp voltage. The power-down sequence is:

1. Use PRST

to switch outputs to a high-impedance state.

2. Remove the clamp voltage.

3. Remove the 3.3-V power from the core.

I/O characteristics

Figure 1 shows a 3-state bidirectional buffer. The provides the electrical characteristics of the inputs and outputs.

NOTE:

The PCI1211 meets the ac specifications of the

Specification Revision 2.2.

Tied for Open Drain

recommended operating conditions

1997 PC Card Standard

CCP

Pad

and

PCI Local Bus

table, on page 119,

Figure 1. 3-State Bidirectional Buffer

NOTE:

Unused pins (input or I/O) must be held high or low to prevent them from floating.

clamping voltages

The clamping voltages are set to match whatever external environment the PCI1211 will be working with: 3.3 V or 5 V. The I/O sites can be pulled through a clamping diode to a voltage that protects the core from external signals. The core power supply is always 3.3 V and is independent of the clamping voltages. For example, PCI signaling can be either 3.3 V or 5 V, and the PCI1211 must reliably accommodate both voltage levels. This is accomplished by using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping voltage applied. If a system designer desires a 5-V PCI bus, V

The PCI1211 requires three separate clamping voltages because it supports a wide range of features. The three voltages are listed and defined in the

recommended operating conditions

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can be connected to a 5-V power supply.

CCP

, on page 119.

PCI1211 GGU/PGE PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

peripheral component interconnect (PCI) interface

The PCI1211 is fully compliant with the required signals for PCI master or slave operation, and may operate in either a 5-V or 3.3-V signaling environment by connecting the V signals the PCI1211 provides the optional interrupt signal INTA

PCI bus lock (LOCK)

The bus-locking protocol defined in the PCI specification is not highly recommended, but is provided on the PCI1211 as an additional compatibility feature. The PCI LOCK via the multifunction routing register, see the Note that the use of LOCK the processor).

PCI LOCK asserted, nonexclusive transactions can proceed to an address that is not currently locked. A grant to start a transaction on the PCI bus does not guarantee control of LOCK protocol. It is possible for different initiators to use the PCI bus while a single master retains ownership of LOCK Note that the CardBus signal for this protocol is CBLOCK

An agent may need to do an exclusive operation because a critical access to memory might be broken into several transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock is defined by PCI to be 16 bytes, aligned. The lock protocol defined by PCI allows a resource lock without interfering with nonexclusive real-time data transfer, such as video.

The PCI bus arbiter may be designed to support only complete bus locks using the LOCK scenario, the arbiter will not grant the bus to any other agent (other than the LOCK asserted. A complete bus lock may have a significant impact on the performance of the video. The arbiter that supports complete bus lock must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked operation is in progress.

indicates an atomic operation that may require multiple transactions to complete. When LOCK is

is only supported by PCI-to-CardBus bridges in the downstream direction (away from

CCP

PCI Local Bus Specification, Revision 2.2

terminals to the desired voltage level. In addition to the mandatory PCI

signal can be routed to the MFUNC4 terminal

multifunction routing register description

; control of LOCK is obtained under its own

to avoid confusion with the bus clock.

. The PCI1211 provides all

on page 61 for details.

protocol. In this

master) while LOCK is

The PCI1211 supports all LOCK PCI-to-CardBus bridges. This includes disabling write posting while a locked operation is in progress, which can solve a potential deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can occur if a CardBus target supports delayed transactions and blocks access to the target until it completes a delayed read. This target characteristic is prohibited by the resolved by the PCI master using LOCK

loading subsystem identification

The subsystem vendor ID register and subsystem ID register make up a doubleword of PCI configuration space located at offset 40h. This doubleword register is used for system and option card (mobile dock) identification purposes and is required by some operating systems. Implementation of this unique identifier register is a PC ’97 requirement.

The PCI1211 offers two mechanisms to load a read-only value into the subsystem registers. The first mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the subsystem registers is read-only, but can be made read/write by setting the SUBSYSRW bit in the system control register (bit 5, at PCI offset 80h). Once this bit is set, the BIOS can write a subsystem identification value into the registers at offset 40h. The BIOS must clear the SUBSYSRW bit such that the subsystem vendor ID register and subsystem ID register is limited to read-only access. This approach saves the added cost of implementing the serial electrically erasable programmable ROM (EEPROM).

protocol associated with PCI-to-PCI bridges, as also defined for

PCI Local Bus Specification, Revision 2.2

, and the issue is

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loading subsystem identification (continued)

In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID register must be loaded with a unique identifier via a serial EEPROM. The PCI121 1 loads the data from the serial EEPROM after a reset of the primary bus. The SUSPEND core, including the serial bus state machine (see

suspend mode

The PCI1211 provides a two-line serial bus host controller that can be used to interface to a serial EEPROM. Refer to

serial bus interface

on page 30 for details on the two-wire serial bus controller and applications.

PC Card applications

This section describes the PC Card interfaces of the PCI1211. Discussions are provided for:

Card insertion/removal and recognition

P2C power-switch interface

Zoom video support

Speaker and audio applications

LED socket activity indicator

PC Card 16-distributed DMA support

PC Card controller programming model

CardBus socket registers

input gates the PCI reset from the entire PCI1211

, on page 39, for details on using SUSPEND).

PC Card insertion/removal and recognition

The 1997 PC Card Standard addresses the card-detection and recognition process through an interrogation procedure that the socket must initiate on card insertion into a cold, unpowered socket. Through this interrogation, card voltage requirements and interface (16-bit versus CardBus) are determined.

The scheme uses the CD1

, CD2, VS1, and VS2 signals (CCD1, CCD2, CVS1, and CVS2 for CardBus). The configuration of these four terminals identifies the card type and voltage requirements of the PC Card interface. The encoding scheme is defined in the 1995 PC Card Standard and is shown in Table 5.

Table 5. PC Card Card-Detect and Voltage-Sense Connections

CD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1 KEY INTERFACE VOLTAGE

Ground Ground Open Open 5 V 16-bit PC Card 5 V Ground Ground Open Ground 5 V 16-bit PC Card 5 V and 3.3 V Ground Ground Ground Ground 5 V 16-bit PC Card 5 V, 3.3 V, and X.X V Ground Ground Open Ground LV 16-bit PC Card 3.3 V Ground Connect to CVS1 Open Connect to CCD1 LV CardBus PC Card 3.3 V Ground Ground Ground Ground LV 16-bit PC Card 3.3 V and X.X V

Connect to CVS2 Ground Connect to CCD2 Ground LV CardBus PC Card 3.3 V and X.X V Connect to CVS1 Ground Ground Connect to CCD2 LV CardBus PC Card 3.3 V, X.X V, and Y.Y V

Ground Ground Ground Open LV 16-bit PC Card Y .Y V

Connect to CVS2 Ground Connect to CCD2 Open LV CardBus PC Card Y.Y V

Ground Connect to CVS2 Connect to CCD1 Open LV CardBus PC Card X.X V and Y.Y V

Connect to CVS1 Ground Open Connect to CCD2 LV CardBus PC Card Y.Y V

Ground Connect to CVS1 Ground Connect to CCD1 Reserved Ground Connect to CVS2 Connect to CCD1 Ground Reserved

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P2C power-switch interface (TPS2211)

The PCI1211 provides a P The VCCD

and VPPD terminals are used with the TI TPS2211 single slot PC Card power interface switch to provide power switch support. Figure 2 shows the terminal assignments for the TPS2211. Figure 3 illustrates a typical application, where the PCI1211 represents the PC Card controller.

C (PCMCIA peripheral control) interface for control of the PC Card power switch.

VCCD0 VCCD1

3.3V

3.3V 5V 5V GND

1 2 3 4 5 6 7 8

16 15 14 13 12

SHDN VPPD0 VPPD1 AVCC AVCC AVCC AVPP 12V

Figure 2. TPS2211 Terminal Assignments

The PCI121 1 also includes support for the Maxim 1602 single-channel CardBus and PCMCIA power-switching network. Application of this power switch would be similar to the TPS2211.

Power Supply

12 V

5 V

3.3 V

Supervisor

PCI1211

(PCMCIA

Controller)

12V 5V

3.3V

SHDN SHDN

VCCD0 VCCD1 VPPD0 VPPD1

TPS2211

AVPP

AVCC

V V V V

PP1 PP2 CC CC

PC Card

Figure 3. TPS2211 Typical Application

zoom video support

The PCI1211 allows for the implementation of zoom video for PC Cards. Zoom video is supported by setting the ZVENABLE bit in the card control register. Setting this bit puts PC Card-16 address lines A25–A4 of the PC Card interface in the high-impedance state. These lines can then be used to transfer video and audio data directly to the appropriate controller. Card address lines A3–A0 can still be used to access PC Card CIS registers for PC Card configuration. Figure 4 illustrates a PCI1211 ZV implementation.

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zoom video support (continued)

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Audio

Codec

PCM Audio Input

Speakers

PC Card

PC Card Interface

Video

Audio

CRT

Motherboard

PCI Bus

VGA

Controller

Zoom Video

Port

19 4

PCI1211

Figure 4. Zoom Video Implementation Using PCI1211

Not shown in Figure 4 is the multiplexing scheme used to route either a socket ZV source or an external ZV source to the graphics controller. A typical external source might be provided from a high-speed serial bus like IEEE1394. The PCI1211 provides ZVSTAT, ZVSEL0

signals on the multifunction terminals to switch external

bus drivers. Figure 5 shows an implementation for switching between two ZV streams using external logic.

PCI1211

ZVSTAT

ZVSEL0

Figure 5. Zoom Video Switching Application

The example shown in Figure 5 illustrates an implementation using standard 3-state bus drivers with active-low output enables. ZVSEL0

is an active-low output indicating that the Socket ZV mode is enabled. ZVST AT is an active-high output indicating the PCI121 1 socket is enabled for ZV mode. The implementation shown in Figure 5 can be used if PC Card ZV is prioritized over other sources.

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SPKROUT and CAUDPWM usage

SPKROUT carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card is configured for I/O mode, the BVD2 pin becomes SPKR and is referred to as CAUDIO. SPKR CAUDIO signal also can pass a single-amplitude binary waveform. The binary audio signals from the PC Card socket is used in the PCI121 1 to produce SPKROUT . This output is enabled by the SPKROUTEN bit in the card control register.

Older controllers support CAUDIO in binary or PWM mode but use the same pin (SPKROUT). Some audio chips may not support both modes on one pin and may have a separate pin for binary and PWM. The PCI1211 implementation includes a signal for PWM, CAUDPWM, which can be routed to a MFUNC terminal. The AUD2MUX bit located in the card control register is programmed to route a CardBus CAUDIO PWM terminal to CAUDPWM. Refer to the

multifunction routing register

MFUNC terminals. Figure 6 provides an illustration of a sample application using SPKROUT and CAUDPWM.

System

Core Logic

SPKROUT

PCI1211

CAUDPWM

. This terminal is also used in CardBus binary audio applications,

passes a TTL level digital audio signal to the PCI1211. The CardBus

description on page 61 for details on configuring the

BINARY_SPKR

Speaker

Subsystem

PWM_SPKR

Figure 6. Sample Application of SPKROUT and CAUDPWM

LED socket activity indicators

A socket activity LED indicates when a PC Card is being accessed. The LED_SKT signal can be routed to the multifunction terminals. When configured for LED output, this terminal outputs an active high signal to indicate socket activity. Refer to the

multifunction routing register

description on page 61 for details on configuring the

multifunction terminals. The LED signal is active high and is driven for 64-ms durations. When the LED is not being driven high, it is driven

to a low state. Either of the two circuits shown in Figure 7 can be implemented to provide LED signaling, and it is left for the board designer to implement the circuit that best fits the application.

The LED activity signal is valid when a card is inserted, powered, and not in reset. For PC Card 16, the LED activity signal is pulsed when READY/IREQ CFRAME

, CIRDY, or CREQ is active.

is low. For CardBus cards, the LED activity signal is pulsed if

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Reserved

Page

Reserved

LED socket activity indicators (continued)

PCI1211 GGU/PGE

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SCPS033A – OCTOBER 1998

Current Limiting

R ≈ 500 Ω

PCI1211

Application-

Specific Delay

Current Limiting

R ≈ 500 Ω

LED

Figure 7. T wo Sample LED Circuits

As indicated, the LED signal is driven for 64 ms by a counter circuit. T o avoid the possibility of the LED appearing to be stuck when the PCI clock is stopped, the LED signaling is cut-off when the SUSPEND when the PCI clock is to be stopped during the CLKRUN

protocol, or when in the D2 or D1 power state.

signal is asserted,

If any additional socket activity occurs during this counter cycle, the counter is reset and the LED signal remains driven. If socket activity is frequent (at least once every 64 ms), the LED signal remains driven.

PC Card16 Distributed DMA support

The PCI121 1 supports a distributed DMA slave engine for 16-bit PC Card DMA support. The distributed DMA (DDMA) slave register set provides the programmability necessary for the slave DDMA engine. T able 6 shows the DDMA register configuration.

Two critical PCI configuration header registers for DDMA are the socket DMA register 0 and the socket DMA register 1. Distributed DMA is enabled through socket DMA register 0 and the contents of this register configure the PC Card-16 terminal (SPKR

, IOIS16, or INPACK) which is used for the DMA request signal, DREQ. The base address of the DDMA slave registers and the transfer size (bytes or words) are programmed through the socket DMA register 1. Refer to the

PC Card controller programming model

on page 43 and the accompanying

Table 6. Distributed DMA Registers

DMA

TYPE REGISTER NAME

R W R W R N/A W Mode R Multichannel W Mask

Master clear

Current address 00

Base address Current count 04

Base count

N/A Status 08

Request Command

N/A

BASE ADDRESS

OFFSET (HEX)

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PC Card16 Distributed DMA support (continued)

The DDMA registers contain control and status information consistent with the 8237 DMA controller; however, the register locations are reordered and expanded in some cases. While the DDMA register definitions are identical to those in the 8237 DMA controller of the same name, some register bits defined in the 8237 DMA controller do not apply to distributed DMA in a PCI environment. In such cases, the PCI121 1 implements these obsolete register bits as read-only , nonfunctional bits. The reserved registers shown in T able 6 are implemented as read-only and return zeros when read. Writes to reserved registers have no effect.

The DDMA transfer is prefaced by several configuration steps that are specific to the PC Card and must be completed after the PC Card is inserted and interrogated. These steps include setting the proper DREQ assignment, setting the data transfer width, and mapping and enabling the DDMA register set. As discussed above, this is done through socket DMA register 0 programmed similarly to an 8237 controller, and the PCI1211 awaits a DREQ requesting a DMA transfer.

DMA writes transfer data from the PC Card to PCI memory addresses. The PCI121 1 accepts data 8 or 16 bits at a time, depending on the programmed data width, and then requests access to the PCI bus by asserting its REQ

signal. Once granted, the PCI bus and the bus returns to an idle state. The PCI121 1 initiates a PCI memory write command to the current memory address and transfers the data in a single data phase. After terminating the PCI cycle, the PCI1211 accepts the next byte(s) from the PC Card until the transfer count expires.

and socket DMA register 1. The DMA register set is then

assertion from the PC Card

signal

DMA reads transfer data from PCI memory addresses to the PC Card application. Upon the assertion of DREQ the PCI121 1 asserts REQ a PCI memory read operation to the current memory address and accepts 8 or 16 bits of data, depending on the programmed data width. After terminating the PCI cycle, the data is passed on to the PC Card. After terminating the PC Card cycle, the PCI121 1 requests access to the PCI bus again until the transfer count has expired.

The PCI121 1 target interface acts normally during this procedure, and accepts I/O reads and writes to the DDMA registers. While a DDMA transfer is in progress and the host resets the DMA channel, the PCI121 1 asserts TC and ends the PC Card cycle(s). TC is indicated in the DDMA status register. At the PC Card interface, the PCI1211 supports demand mode transfers. The PCI1211 asserts DACK during the transfer unless DREQ deasserted before TC. TC is mapped to the OE WE

PC Card terminal for DMA read operations. The DACK signal is mapped to the PC Card REG signal in all transfers, and the DREQ register 0.

PC Card-16 PC/PCI DMA

Some chipsets provide a way for legacy I/O devices to do DMA transfers on the PCI bus. In the PC/PCI DMA protocol, the PCI121 1 acts as a PCI target device to certain DMA related I/O addresses. The PCI121 1 PCREQ and PCGNT signals are provided as a point-to-point connection to a chipset supporting PC/PCI DMA. The PCREQ

and PCGNT signals may be routed to the MFUNC2 and MFUNC5 terminals, respectively . Refer to the

multifunction routing register

Under the PC/PCI protocol, a PCI DMA slave device (such as the PCI1211) requests a DMA transfer on a particular channel using a serialized protocol on PCREQ and grants the channel through a serialized protocol on PCGNT and memory cycles are then presented on the PCI bus which perform the DMA transfers similarly to legacy DMA master devices.

to acquire the PCI bus. Once granted the bus and the bus is idle, the PCI121 1 initiates

PC Card terminal for DMA write operations, and is mapped to

terminal is routed to one of three options which is programmed through socket DMA

description on page 61 for details on configuring the multifunction terminals.

. The I/O DMA bus master arbitrates for the PCI bus,

when it is ready for the transfer. The I/O cycle

PC/PCI DMA is enabled for the PC Card-16 slot by setting bit 19 in the respective system control register . On power-up this bit is reset and the card PC/PCI DMA is disabled. Bit 3 of the system control register is a global enable for PC/PCI DMA, and is set at power-up and never cleared if the PC/PCI DMA mechanism is implemented. The desired DMA channel for the PC Card-16 slot must be configured through bits 18–16 in the system control register. The channels are configured as indicated in Table 7.

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DMA CHANNEL

CHANNEL TRANSFER DATA WIDTH

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Table 7. PC/PCI Channel Assignments

SYSTEM CONTROL REGISTER

BIT 18 BIT 17 BIT16

0 0 0 Channel 0 8-bit DMA transfers 0 0 1 Channel 1 8-bit DMA transfers 0 1 0 Channel 2 8-bit DMA transfers 0 1 1 Channel 3 8-bit DMA transfers 1 0 0 Channel 4 Not used 1 0 1 Channel 5 16-bit DMA transfers 1 1 0 Channel 6 16-bit DMA transfers 1 1 1 Channel 7 16-bit DMA transfers

As in distributed DMA, the PC Card terminal mapped to DREQ must be configured through socket DMA register 0. The data transfer width is a function of channel number , and the DDMA slave registers are not used. When a DREQ addresses listed in Table 8 and performs actions dependent upon the address.

is received from a PC Card, and the channel has been granted, the PCI121 1 decodes the I/O

Table 8. I/O Addresses Used for PC/PCI DMA

DMA I/O ADDRESS DMA CYCLE TYPE TERMINAL COUNT PCI CYCLE TYPE

00h Normal 0 I/O read/write 04h Normal TC 1 I/O read/write C0h Verify 0 I/O read C4h Verify TC 1 I/O read

The PC/PCI DMA as a PC Card-16 DMA mechanism may not provide the performance levels of DDMA; however, the design of a PCI target implementing PC/PCI DMA is considerably less complex. No bus master state machine is required to support PC/PCI DMA since the DMA control is centralized in the chipset. This DMA scheme is often referred to as centralized DMA for this reason.

CardBus socket registers

The PCI1211 contains all registers for compatibility with the latest PCI-to-PCMCIA CardBus bridge specification. These registers exist as the CardBus socket registers, and are listed in Table 9.

Table 9. CardBus Socket Registers

Socket event 00h Socket mask 04h Socket present state 08h Socket force event 0Ch Socket control 10h Reserved 14h Reserved 18h Reserved 1Ch

Socket power management 20h

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serial bus interface

The PCI1211 provides a serial bus interface to accommodate loading subsystem identification and select register defaults through a serial EEPROM. The PCI1211 serial bus interface is compatible with various I SMBus components.

serial bus interface implementation

The PCI121 1 defaults to serial bus interface disabled. T o enable the serial interface, appropriate pullup resistors must be implemented on the SDA and SCL signals, i.e., the MFUNC1 and MFUNC4 terminals. In addition, pullup resistors must be implemented on VCCD0

and VCCD1. When the interface is detected, the SBDETECT

bit in the system control register is set. The SBDETECT bit is cleared by a write back of 1. The PCI121 1 implements a two-pin serial interface with one clock signal (SCL) and one data signal (SDA). The

SCL signal is mapped to the MFUNC4 terminal and the SDA signal is mapped to the MFUNC1 terminal. The PCI1211 drives SCL at nearly 100 kHz during data transfers, which is the maximum specified frequency for

VCCD0

VCCD1 MFUNC4 MFUNC1

C. Figure 8 illustrates an example application implementing the two-wire serial bus.

and

5 V

Serial

EEPROM

A2 A1 A0

SCL SDA

Pullup resistors are required on the SCL and SDA signals.

Other Serial

Device

SCL

SDA

standard mode I

PCI1211

A weak (43 kW) pullup resistor is implemented on VCCD0 VCCD1

terminals to enable the

serial EEPROM interface.

C and

Figure 8. Serial EEPROM Application

Some serial device applications may include PC Card power switches, ZV source switches, card ejectors, or other devices that may enhance the user’s PC Card experience. The serial EEPROM device and PC Card power switches are discussed in the sections that follow.

serial bus interface protocol

The SCL and SDA signals are bidirectional, open-drain signals and require pullup resistors as shown in Figure 8. The PCI1211 supports up to 100 kb/s data transfer rate and is compatible with standard mode I using seven-bit addressing.

All data transfers are initiated by the serial bus master. The beginning of a data transfer is indicated by a start condition, which is signalled when the SDA line transitions to a low state while SCL is in the high state as illustrated in Figure 9. The end of a requested data transfer is indicated by a stop condition, which is signalled by a low-to-high transition of SDA while SCL is in the high state as shown in Figure 9. Data on SDA must remain stable during the high state of the SCL signal as changes on the SDA signal during the high state of SCL is interpreted as control signals, that is, a start or a stop condition.

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serial bus interface protocol (continued)

SDA

SCL

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Start

Condition

Stop

Condition

Change of

Data Allowed

Data Line Stable,

Data Valid

Figure 9. Serial Bus Start/Stop Conditions and Bit Transfers

Data is transferred serially in 8-bit bytes. The number of bytes that may be transmitted during a data transfer is unlimited, however, each byte must be completed with an acknowledge bit. An acknowledge (ACK) is indicated by the receiver pulling the SDA signal low so that it remains low during the high state of the SCL signal. Figure 10 illustrates the acknowledge protocol.

SCL From

Master

SDA Output

By Transmitter

SDA Output By Receiver

123 789

Figure 10. Serial Bus Protocol Acknowledge

The PCI1211 is a serial bus master; all other devices connected to the serial bus external to the PCI1211 are slave devices. As the bus master, the PCI1211 drives the SCL clock at nearly 100 kHz during bus cycles, and 3-states SCL (zero frequency) during idle states.

Typically, the PCI1211 masters byte reads and byte writes under software control. Doubleword reads are performed by the serial EEPROM initialization circuitry upon a PCI reset, and may not be generated under software control. Refer to

serial bus EEPROM application

on page 32 for details on how the PCI1211

automatically loads the subsystem identification and other register defaults through a serial bus EEPROM. Figure 11 illustrates a byte write operation. The PCI1211 issues a start condition and sends the seven-bit slave

device address and the command bit zero. A zero in the R/W

command bit indicates that the data transfer is a write. The slave device acknowledges if it recognizes the address. If there is no acknowledgment received by the PCI1211, then an appropriate status bit is set in the serial bus control and status register. The word address byte is then sent by the PCI1211 and another slave acknowledgment is expected. Then the PCI1211 delivers the data byte MSB first and expects a final acknowledgment before issuing the stop condition.

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serial bus interface protocol (continued)

Slave Address Word Address

Sb6 b4b5 b3 b2 b1 b0 0 b7 b6 b5 b4 b3 b2 b1 b0AA

R/W

S/P = Start/stop conditionA = Slave acknowledgement

b7 b6 b4b5 b3 b2 b1 b0 A P

Data Byte

Figure 11. Serial Bus Protocol – Byte Write

Figure 12 illustrates a byte read operation. The read protocol is very similar to the write protocol except the R/W command bit must be set to one to indicate a read-data transfer. In addition, the PCI1211 master must acknowledge reception of the read bytes from the slave transmitter. The slave transmitter drives the SDA signal during read data transfers. The SCL signal remains driven by the PCI1211 master.

Slave Address Word Address

Sb6 b4b5 b3 b2 b1 b0 1 b7 b6 b5 b4 b3 b2 b1 b0AA

R/W

M = Master acknowledgement

b7 b6 b4b5 b3 b2 b1 b0 M P

S/P = Start/stop conditionA = Slave acknowledgement

Data Byte

Figure 12. Serial Bus Protocol – Byte Read

serial bus EEPROM application

When the PCI bus is reset, and the serial bus interface is detected, the PCI1211 attempts to read the subsystem identification and other register defaults from a serial EEPROM. The registers and corresponding bits that may be loaded with defaults through the EEPROM are provided in Table 10.

Table 10. Registers and Bits Loadable Through Serial EEPROM

PCI OFFSET

40h 01h Subsystem identification 31–0 80h 02h System control register 31–30, 27, 26, 24, 15–14, 6–3, 1 8Ch 03h Multifunction routing register 27–0 90h 04h Retry status, Card control, device control, diagnostic 31, 28–24, 22, 19–16, 15, 7–6

OFFSET

REFERENCE

Figure 13 details the EEPROM data format. This format must be followed for the PCI1211 to properly load initializations from a serial EEPROM. Any undefined condition results in a terminated load and sets the ROM_ERR bit in the serial bus control and status register.

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serial bus EEPROM application (continued)

Slave Address = 1010 000

Reference(0) Word Address 00h

Byte 3 (0) Word Address 01h Byte 2 (0) Word Address 02h Byte 1 (0) Word Address 03h Byte 0 (0) Word Address 04h

RSVD RSVD RSVD

Reference(1) Word Address 08h

Figure 13. EEPROM Data Format

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Reference(n) Word Address 8 × (n–1)

Byte 3 (n) Word Address 8 × (n–1) + 1 Byte 2 (n) Word Address 8 × (n–1) + 2 Byte 1 (n) Word Address 8 × (n–1) + 3 Byte 0 (n) Word Address 8 × (n–1) + 4

RSVD RSVD RSVD

EOL Word Address 8 × (n)

The byte at the EEPROM word address 00h must either contain a valid PCI offset, as listed in Table 10, or an end-of-list (EOL) indicator. The EOL indicator is a byte value of FFh, and indicates the end of the data to load from the EEPROM. Only doubleword registers are loaded from the EEPROM, and all bit fields must be considered when programming the EEPROM.

The serial EEPROM is addressed at slave address 1010000b by the PCI1211. All hardware address bits for the EEPROM should be tied to the appropriate level to achieve this address. The serial EEPROM chip in the sample application circuit (Figure 8) assumes the 1010b high address nibble. The lower three address bits are terminal inputs to the chip, and the sample application shows these terminal inputs tied to GND.

When a valid offset reference is read, four bytes are read from the EEPROM, MSB first, as illustrated in Figure 14. The address auto-increments after every byte transfer according to the doubleword read protocol. The word addresses align with the data format illustrated in Figure 13. The PCI1211 continues to load data from the serial EEPROM until an end-of-list indicator is read. Three reserved bytes are stuffed to maintain eight-byte data structures.

The eight-byte data structure is important to provide correct addressing per the doubleword read format shown in Figure 14. In addition, the reference offsets must be loaded in the EEPROM in sequential order, that is 01h, 02h, 03h, 04h. If the offsets are not sequential, then the registers may be loaded incorrectly.

Slave Address Word Address

S1 10 0 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0AA

Start

R/W

S1 10 00001A

Restart

Slave Address

R/W

Data Byte 3 M

Figure 14. EEPROM Interface Doubleword Data Collection

Data Byte 2 Data Byte 1 Data Byte 0 M PMM

M = Master acknowledgement

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accessing serial bus devices through software

The PCI1211 provides a programming mechanism to control serial bus devices through software. The programming is accomplished through a doubleword of PCI configuration space at offset B0h. Table 11 illustrates the registers used to program a serial bus device through software.

Table 11. PCI1211 Registers Used to Program Serial Bus Devices

PCI OFFSET REGISTER NAME DESCRIPTION

B0H Serial bus data

B1H Serial bus index

B2H

B3H

Serial bus slave address

Serial bus control and status

programmable interrupt subsystem

Interrupts provide a way for I/O devices to let the microprocessor know that they require servicing. The dynamic nature of PC Cards, and the abundance of PC Card I/O applications require substantial interrupt support from the PCI121 1. The PCI1211 provides several interrupt signaling schemes to accommodate the needs of a variety of platforms. The different mechanisms for dealing with interrupts in this device are based on various specifications and industry standards. The ExCA register set provides interrupt control for some 16-bit PC Card functions, and the CardBus socket register set provides interrupt control for the CardBus PC Card functions. The PCI1211 is, therefore, backward compatible with existing interrupt control register definitions, and new registers have been defined where required.

Contains the data byte to send on write commands or the received data byte on read commands.

The content of this register is sent as the word address on byte writes or reads. This register is not used in the quick command protocol.

Writes to this register initiate a serial bus transaction. The slave device address and the R/W command selector are programmed through this register.

Read data valid, general busy, and general error status are communicated through this register . In addition, the protocol select bit is programmed through this register.

The PCI1211 detects PC Card interrupts and events at the PC Card interface and notifies the host controller using one of several interrupt signaling protocols. To simplify the discussion of interrupts in the PCI1211, PC Card interrupts are classified as either card status change (CSC) or as functional interrupts.

The method by which any type of PCI121 1 interrupt is communicated to the host interrupt controller varies from system to system. The PCI1211 offers system designers the choice of using parallel PCI interrupt signaling, parallel ISA-type IRQ interrupt signaling, or the IRQSER serialized ISA and/or PCI interrupt protocol. It is possible to use the parallel PCI interrupts in combination with either parallel IRQs or serialized IRQs, as detailed in the sections that follow. All interrupt signalling is provided through the seven multifunction terminals, MFUNC0–MFUNC6.

PC Card functional and card status change interrupts

PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and are indicated by asserting specially-defined signals on the PC Card interface. Functional interrupts are generated by 16-bit I/O PC Cards and by CardBus PC Cards.

Card status change (CSC)-type interrupts are defined as events at the PC Card interface that are detected by the PCI1211 and may warrant notification of host card and socket services software for service. CSC events include both card insertion and removal from PC Card sockets, as well as transitions of certain PC Card signals.

Table 12 summarizes the sources of PC Card interrupts and the type of card associated with them. CSC and functional interrupt sources are dependent on the type of card inserted in the PC Card socket. The three types of cards that can be inserted into any PC Card socket are:

16-bit memory card

16-bit I/O card

CardBus cards

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16-bit I/O

CardBus

CSC

memory

PC Card functional and card status change interrupts (continued)

Table 12. Interrupt Mask and Flag Registers

CARD TYPE EVENT MASK FLAG

16-bit memory

All 16-bit PC Cards

Battery conditions

(BVD1, BVD2)

Wait states

(READY)

Change in card status

(STSCHG

Interrupt request

Power cycle complete Change in card status

(CSTSCHG)

Interrupt request

Power cycle complete

Card insertion or

removal

(IREQ

(CINT

)

ExCA offset 05h/805h

bits 1 and 0

ExCA offset 05h/805h

bit 2

ExCA offset 05h/805h

bit 0

Always enabled

ExCA offset 05h/805h

bit 3

Socket mask

bit 0

Always enabled

Socket mask

bit 3

Socket mask

bits 2 and 1

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ExCA offset 04h/804h

bits 1 and 0

ExCA offset 04h/804h

bit 2

ExCA offset 04h/804h

bit 0

PCI configuration offset 91h

bit 0

ExCA offset 04h/804h

bit 3

Socket event

bit 0

PCI configuration offset 91h

bit 0

Socket event

bit 3

Socket event

bits 2 and 1

Functional interrupt events are valid only for 16-bit I/O and CardBus cards; that is, the functional interrupts are not valid for 16-bit memory cards. Furthermore, card insertion and removal-type CSC interrupts are independent of the card type. Table 13 describes the PC Card interrupt events.

Table 13. PC Card Interrupt Events and Description

CARD TYPE EVENT TYPE SIGNAL DESCRIPTION

A transition on BVD1 indicates a change in the PC Card battery conditions.

A transition on BVD2 indicates a change in the PC Card battery conditions.

A transition on READY indicates a change in the ability of the memory PC Card to accept or provide data.

The assertion of STSCHG indicates a status change on the PC Card.

The assertion of IREQ indicates an interrupt request from the PC Card.

The assertion of CSTSCHG indicates a status change on the PC Card.

The assertion of CINT indicates an interrupt request from the PC Card.

A transition on either CD1//CCD1 or CD2

//CCD2 indicates an insertion or removal

of a 16-bit//CardBus PC Card. An interrupt is generated when a PC Card

power-up cycle has completed.

16-bit

16-bit I/O

CardBus

All PC Cards

Battery conditions

(BVD1, BVD2)

Wait states

(READY)

Change in card status (STSCHG)

Interrupt request

(IREQ)

Change in card status

(CSTSCHG)

Interrupt request

(CINT

)

Card insertion

or removal

Power cycle

complete

BVD1(STSCHG)//CSTSCHG

BVD2(SPKR)//CAUDIO

CSC READY(IREQ)//CINT

CSC BVD1(STSCHG)//CSTSCHG

Functional READY(IREQ)//CINT

CSC BVD1(STSCHG)//CSTSCHG

Functional READY(IREQ)//CINT

CSC

CSC N/A

CD1//CCD1,

CD2

//CCD2

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PC Card functional and card status change interrupts (continued)

The naming convention for PC Card signals describes the function for 16-bit memory and I/O cards, as well as CardBus. For example, READY(IREQ cards, and CINT second, enclosed in parentheses. The CardBus signal name follows after a forward double slash (//).

The PC Card standard describes the power-up sequence that must be followed by the PCI1211 when an insertion event occurs and the host requests that the socket V power-up sequence, the PCI1211 interrupt scheme can be used to notify the host system (see Table 13), denoted by the power cycle complete event. This interrupt source is considered a PCI1211 internal event because it does not depend on a signal change at the PC Card interface, but rather the completion of applying power to the socket.

interrupt masks and flags

Host software may individually mask (or disable) most of the potential interrupt sources listed in Table 13 by setting the appropriate bits in the PCI1211. By individually masking the interrupt sources listed, software can control those events that cause a PCI121 1 interrupt. Host software has some control over the system interrupt the PCI1211 asserts by programming the appropriate routing registers. The PCI1211 allows host software to route PC Card CSC and PC Card functional interrupts to separate system interrupts. A discussion of interrupt routing is somewhat specific to the interrupt signaling method used, and is discussed in more detail in the following sections.

for CardBus cards. The 16-bit memory card signal name is first, with the I/O card signal name

)//CINT includes READY for 16-bit memory cards, IREQ for 16-bit I/O

and VPP be powered. Upon completion of this

When an interrupt is signaled by the PCI121 1, the interrupt service routine must determine which of the events in Table 12 caused the interrupt. Internal registers in the PCI1211 provide flags that report the source of an interrupt. By reading these status bits, the interrupt service routine can determine the action to be taken.

T able 12 details the registers and bits associated with masking and reporting potential interrupts. All interrupts can be masked except the functional PC Card interrupts, and an interrupt status flag is available for all types of interrupts.

Notice that there is not a mask bit to stop the PCI1211 from passing PC Card functional interrupts through to the appropriate interrupt scheme. These interrupts are not valid until the card is properly powered, and there should never be a card interrupt that does not require service after proper initialization.

There are various methods of clearing the interrupt flag bits listed in T able 12. The flag bits in the ExCA registers (16-bit PC Card-related interrupt flags) can be cleared using two different methods. One method is an explicit write of 1 to the flag bit to clear, and the other is by reading the flag bit register . The selection of flag bit clearing is made by bit 2 in the global control register (ExCA offset 1Eh/81Eh), and defaults to the

read

method.

The CardBus-related interrupt flags can be cleared by an explicit write of 1 to the interrupt flag in the socket event register. Although some of the functionality is shared between the CardBus registers and the ExCA registers, software should not program the chip through both register sets when a CardBus card is functioning.

using parallel IRQ interrupts

The seven multifunction terminals, MFUNC6–MFUNC0, implemented in the PCI121 1 may be routed to obtain a subset of the ISA IRQs. The IRQ choices provide ultimate flexibility in PC Card host interruptions. T o use the parallel ISA type IRQ interrupt signaling, software must program the device control register, located at PCI of fset 92h, to select the parallel IRQ signaling scheme. Refer to the 61 for details on configuring the multifunction terminals.

multifunction routing register

flag cleared on

description on page

A system using parallel IRQs requires (at a minimum) one PCI terminal, INTA requirement is dictated by certain card and socket services software. The INTA the MFUNC0 terminal for INT A PC Card functions.

signaling. This leaves (at a maximum) six different IRQs to support legacy 16-bit

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, to signal CSC events. This requirement calls for routing

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using parallel IRQ interrupts (continued)

As an example, suppose the six IRQs used by legacy PC Card applications are IRQ3, IRQ4, IRQ5, IRQ10, IRQ11, and IRQ15. The multifunction control register must be programmed to a value of 0x0FBA5432. This value routes the MFUNC0 terminal to INTA Figure 15. Not shown is that INTA

must also be routed to the programmable interrupt controller (PIC), or to some

circuitry that provides parallel PCI interrupts to the host.

PCI1211 PIC

MFUNC1 MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6

Figure 15. Example of IRQ Implementation

Power-on software is responsible for programming the multifunction routing register to reflect the IRQ configuration of a system implementing the PCI121 1. Refer to the page 61 for details on configuring the multifunction terminals.

signaling, and routes the remaining terminals as illustrated in

IRQ3 IRQ4 IRQ5 IRQ10 IRQ11 IRQ15

multifunction routing register

description on

The parallel ISA type IRQ signaling from the MFUNC6–MFUNC0 terminals is compatible with those input directly into the 8259 PIC. The parallel IRQ option is provided for system designs that require legacy ISA IRQs. There may be design constraints that demand more MFUNC6–MFUNC0 IRQ terminals than the PCI1211 makes available. A system designer may choose to implement an IRQSER deserializer companion chip, such as the T exas Instruments PCI950. To use a deserializer, the MFUNC3 terminal must be configured as IRQSER and connected to the deserializer, which outputs all 15 ISA IRQ’ s and four PCI interrupts as decoded from the IRQSER stream.

using parallel PCI interrupts

Parallel PCI interrupts are available when exclusively in parallel PCI interrupt mode, parallel ISA IRQ signaling mode, and when only IRQs are serialized with the IRQSER protocol. The socket function interrupts are routed to INTA

(MFUNC0).

using serialized IRQSER interrupts

The serialized interrupt protocol implemented in the PCI121 1 uses a single terminal to communicate all interrupt status information to the host controller. The protocol defines a serial packet consisting of a start cycle, multiple interrupt indication cycles, and a stop cycle. All data in the packet is synchronous with the PCI clock. The packet data describes 16 parallel ISA IRQ signals and the optional 4 PCI interrupts INT A details on the IRQSER protocol refer to the document

Serialized IRQ Support for PCI Systems

, INTB, INTC, and INTD. For

SMI support in the PCI1211

The PCI1211 provides a mechanism of interrupting the system when power changes have been made to the PC Card socket interface. The interrupt mechanism is designed to fit into a system maintenance interrupt (SMI) scheme. SMI interrupts are generated by the PCI1211, when enabled, after a write cycle to either the socket control register of the CardBus register set or the power control register of the ExCA register set causes a power cycle change sequence sent on the power switch interface.

The SMI control is programmed through three bits in the system control register. These bits are SMIROUTE, SMISTATUS, and SMIENB. The SMI control bits function as described in Table 14.

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SMI support in the PCI1211 (continued)

Table 14. SMI Control

BIT NAME FUNCTION

SMIROUTE SMI route. This shared bit controls whether the SMI interrupts are sent as a CSC interrupt or as IRQ2. SMISTAT SMI status. This bit is set when an SMI interrupt is pending. This status flag is cleared by writing back a 1. SMIENB SMI interrupt mode enable. When set, SMI interrupt generation is enabled.

If CSC SMI interrupts are selected, then the SMI interrupt is sent as the CSC. The CSC interrupt can be either level or edge mode depending upon the CSCMODE bit in the ExCA global control register.

If IRQ2 is selected by SMIROUTE, the IRQSER signaling protocol supports SMI signaling in the IRQ2 IRQ/Data slot. In a parallel ISA IRQ system, the support for an active low IRQ2 is provided only if IRQ2 is routed to either MFUNC1, MFUNC3, or MFUNC6 through the multifunction routing register.

power management overview

In addition to the low-power CMOS technology process used for the PCI1211, various features are designed into the device to allow implementation of popular power-saving techniques. These features and techniques are discussed in this section.

CLKRUN

CardBus PC Card Power Management

protocol

The PCI CLKRUN feature is the primary method of power management on the PCI interface of the PCI1211. CLKRUN CLKRUN For details on the CLKRUN

The PCI121 1 does not permit the central resource to stop the PCI clock under any of the following conditions:

D D D D D D

The PCI1211 restarts the PCI clock using the clockk run protocol under any of the following conditions:

D D D D D

The PCI121 1 implements its own card power management engine that can be used to turn off the CCLK to the socket when there is no activity to the CardBus PC Card. The PCI CCLKRUN CardBus interface to control this clock management.

signalling is provided through the MFUNC6 terminal. Since some chipsets do not implement , this is not always available to the system designer, alternate power savings features are provided.

protocol refer to the

The KEEPCLK bit in the system control register is set. The PC Card-16 resource manager is busy. The PCI1211 CardBus master state machine is busy. A cycle may be in progress on CardBus. The PCI1211 master is busy. There may be posted data from CardBus to PCI in the PCI1211. There are pending interrupts. The CardBus CCLK has not been stopped by the PCI1211 PCI CCLKRUN manager.

A PC Card-16 IREQ or a CardBus CINT has been asserted by either card. A CardBus wakeup (CSTSCHG) or PC Card-16 STSCHG/RI event occurs. A CardBus card attempts to start the CCLK using CCLKRUN. A CardBus card arbitrates for the CardBus bus using CREQ. A 16-bit DMA PC Card asserts DREQ.

PCI Mobile Design Guide

protocol is followed on the

16-Bit PC Card Power Management

The COE and PWRDOWN bits in the ExCA registers are provided for 16-bit PC Card power management. The COE bit three states the card interface to save power. The power savings when using this feature are minimal. The COE bit will reset the PC Card when used, and the PWRDOWN bit will not. Furthermore, the PWRDOWN bit is an automatic COE, that is, the PWRDOWN performs the COE function when there is no card activity.

NOTE:

The 16-bit PC Card must implement the proper pullup resistors for the COE and PWRDOWN modes.

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suspend mode

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The SUSPEND PCI1211. However, additional functionality has been defined for SUSPEND

signal is provided for backward compatibility, and gates the PCI reset (RST) signal from the

to provide additional

power-management options. SUSPEND

provides a mechanism to gate the PCLK from the PCI121 1, as well as gate RST . This can potentially save power while in an idle state; however, it requires substantial design effort to implement. Some issues to consider are:

What if a card is present in the socket?

What if the card in the socket is powered?

How to pass CSC (insertion/removal) events.

Even without the PCI clock to the PCI121 1 core, there are asynchronous-type functions (such as RI_OUT

) that can pass CSC events, wake-up events, etc., back to the system. Figure 16 is a functional implementation diagram for SUSPEND

SUSPEND

RST

GNT

PCLK

RSTIN

SUSPENDIN

PCLKIN

INTERNAL SIGNALSEXTERNAL SIGNALS

PCI1211

Core

Figure 16. SUSPEND Functional Implementation

Figure 17 is a signal diagram of the suspend function.

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suspend mode (continued)

RST

GNT

SUSPEND

PCLK

RSTIN

External T erminals

Internal Signals

SUSPENDIN

PCLKIN

Figure 17. Signal Diagram of Suspend Function

ring indicate

The RI_OUT go into a suspended mode and wake up on modem rings and other card events. RI_OUT

output is an important feature in power management and is basically used so that a system can

on the PCI121 1 can

be asserted under any of the following conditions:

A 16-bit PC Card modem in a powered socket asserts RI to indicate to the system the presence of an incoming call.

A powered down CardBus card asserts CSTSCHG (CBWAKE) requesting system and interface wake up.

A CSC event occurs, such as insertion/removal of cards, battery voltage levels.

CSTSCHG from a powered CardBus card is indicated as a CSC event, not as a CBWAKE event. These two RI_OUT however, it does not show the masking of CSC events. See

events are enabled separately . Figure 15 shows various enable bits for the PCI121 1 RI_OUT function;

interrupt masks and flags

, on page 36, for a detailed

description of CSC interrupt masks and flags.

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ring indicate (continued)

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RI_OUT Function

CSTSMASK

PC Card

Socket

Card

I/F

Figure 18. RI_OUT Functional Diagram

from the 16-bit PC Card interface is masked by the ExCA control bit RINGEN in the interrupt and general

RI control register. This is programmed on a per-socket basis and is only applicable when a 16-bit card is powered in the socket.

The CBWAKE signaling to RI_OUT mask bit, CSTSMASK, is programmed through the socket mask register in the CardBus socket registers.

PCI power management (PCIPM)

The PCI power-management (PCIPM) specification establishes the infrastructure required to let the operating system control the power of PCI functions. This is done by defining a standard PCI interface and operations to manage the power of PCI functions on the bus. The PCI bus and the PCI functions can be assigned one of four software-visible power-management states that result in varying levels of power savings.

The four power-management states of PCI functions are:

is enabled through the same mask as the CSC event for CSTSCHG. The

RINGEN

CDRESUME

RIENB

RI_OUT

D0 – Fully-on state

D1 and D2 – Intermediate states

D3 – Off state

Similarly , bus power states of the PCI bus are B0–B3. The bus power states B0–B3 are derived from the device power state of the originating bridge device.

For the operating system (OS) to power manage the device power states on the PCI bus, the PCI function should support four power-management operations. These operations are:

Capabilities reporting

Power status reporting

Setting the power state

System wake up.

The OS identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of new capabilities is indicated by a 1 in the capabilities list (CAPLIST) bit in the status register (bit 4) and providing access to a capabilities list.

The capabilities pointer provides access to the first item in the linked list of capabilities. For the PCI1211, a CardBus bridge with PCI configuration space header type 2, the capabilities pointer is mapped to an offset of 14h. The first byte of each capability register block is required to be a unique ID of that capability. PCI power management has been assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of capabilities. If there are no more items in the list, the next item pointer should be set to 0. The registers following the next item pointer are specific to the function’s capability . The PCIPM capability implements the register block outlined in Table 15.

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PCI power management (PCIPM) (continued)

Table 15. Power-Management Registers

Power-management capabilities Next item pointer Capability ID 0h

Data PMCSR bridge support extensions Power-management control status (CSR) 4h

The power management capabilities register is a static read-only register that provides information on the capabilities of the function related to power management. The PMCSR register enables control of power-management states and enables/monitors power-management events. The data register is an optional register that can provide dynamic data.

For more information on PCI power management refer to the

Specification, Revision 1.0

PCI Bus Power Management Interface

ACPI Support

The

Advanced Configuration and Power Management (ACPI) Specification

provides a mechanism that allows unique pieces of hardware to be described to the ACPI driver. The PCI1211 offers a generic interface that is compliant with ACPI design rules.

Two doublewords of general purpose ACPI programming bits reside in the PCI1211 PCI configuration space at offset A8h. The programming model is broken into status and control functions. In compliance with ACPI, the top level event status and enable bits reside in GPE_STS and GPE_EN registers. The status and enable bits are implemented as defined by ACPI, and illustrated in Figure 19.

Status Bit

Event Input

Enable Bit

Event Output

Figure 19. Block Diagram of a Status/Enable Cell

The status and enable bits are used to generate an event that allows the ACPI driver to call a control method associated with the pending status bit. The control method can then control the hardware by manipulating the hardware control bits or by investigating child status bits and calling their respective control methods. A hierarchical implementation would be somewhat limiting, however, as upstream devices would have to remain in some level of power state to report events.

For more information on ACPI refer to the http://www.teleport.com/~acpi/

Advanced Configuration and Power Interface Specification

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at:

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PC Card controller programming model

This section describes the PCI1211 PCI configuration registers that make up the 256-byte PCI configuration header for each PCI1211 function.

PCI configuration registers

The configuration header is compliant with the PCI specification as a CardBus bridge header, and is PC98/99 compliant as well. Table 16 shows the PCI configuration header, which includes both the predefined portion of the configuration space and the user-definable registers.

Table 16. PCI Configuration Registers

Device ID Vendor ID 00h

Status Command 04h

Class code Revision ID 08h

BIST Header type Latency timer Cache line size 0Ch

CardBus socket/ExCA base address 10h

Secondary status Reserved Capability pointer 14h

CardBus latency timer Subordinate bus number CardBus bus number PCI bus number 18h

CardBus Memory base register 0 1Ch

CardBus Memory limit register 0 20h

CardBus Memory base register 1 24h

CardBus Memory limit register 1 28h

CardBus I/O base register 0 2Ch

CardBus I/O limit register 0 30h

CardBus I/O base register 1 34h

CardBus I/O limit register 1 38h Bridge control Interrupt pin Interrupt line 3Ch Subsystem ID Subsystem vendor ID 40h

PC Card 16-bit I/F legacy-mode base address 44h

Reserved 48h–7Ch

System control 80h

Reserved 84h–88h

Multifunction routing 8Ch

Diagnostic Device control Card control Retry status 90h

Socket DMA register 0 94h Socket DMA register 1 98h

Reserved 9Ch

Power-management capabilities Next-item pointer Capability ID A0h

PM data

General-purpose event enable General-purpose event status A8h

General-purpose output General-purpose input ACh

Serial bus control/status Serial bus slave address Serial bus index Serial bus data B0h

PMCSR bridge support

extensions

Power-management control/status A4h

Reserved B4h–FCh

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vendor ID register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Vendor ID Type R R R R R R R R R R R R R R R R Default 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0

Register: Vendor ID Type: Read-only Offset: 00h Default: 104Ch Description: This register contains a value allocated by the PCI SIG (special interest group) and identifies

the manufacturer of the PCI device. The vendor ID assigned to TI is 104Ch.

device ID register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Device ID Type R R R R R R R R R R R R R R R R Default 1 0 1 0 1 1 0 0 0 0 0 1 1 1 1 0

Register: Device ID Type: Read-only Offset: 02h Default: AC1Eh Description: This register contains a value assigned to the PCI1211 by TI. The device identification for the

PCI1211 is AC1E.

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command register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Command Type R R R R R R R R/W R R/W R R R R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Command Type: Read-only, Read/Write (see individual bit descriptions) Offset: 04h Default: 0000h Description: This register provides control over the PCI1211 interface to the PCI bus. All bit functions

adhere to the definitions in complete description of the register contents.

Table 17. Command Register

BIT SIGNAL TYPE FUNCTION

15–10 RSVD R Reserved. Bits 15–10 return 0s when read. Writes have no effect.

9 FBB_EN R

8 SERR_EN R/W

7 STEP_EN R

6 PERR_EN R/W

5 VGA_EN R

4 MWI_EN R

3 SPECIAL R

2 MAST_EN R/W

1 MEM_EN R/W

0 IO_EN R/W

Fast back-to-back enable. The PCI1211 does not generate fast back-to-back transactions; therefore, bit 9 returns 0 when read.

System Error (SERR) enable. Bit 8 controls the enable for the SERR driver on the PCI interface. SERR can be asserted after detecting an address parity error on the PCI bus. Both bit 8 and bit 6 must be set for the PCI1211 to report address parity errors.

Address/data stepping control. The PCI1211 does not support address/data stepping, and bit 7 is hardwired to 0. Writes to this bit have no effect.

Parity error response enable. Bit 6 controls the PCI1211’ s response to parity errors through PERR. Data parity errors are indicated by asserting PERR SERR

VGA palette snoop. Bit 5 controls how PCI devices handle accesses to video graphics array (VGA) palette registers. The PCI1211 does not support VGA palette snooping; therefore, this bit is hardwired to 0. Bit 5 returns 0 when read. Writes to this bit have no effect.

Memory write and invalidate enable. Bit 4 controls whether a PCI initiator device can generate memory write and Invalidate commands. The PCI1211 controller does not support memory write and invalidate commands, it uses memory write commands instead; therefore, this bit is hardwired to 0. Bit 4 returns 0 when read. Writes to this bit have no effect.

Special cycles. Bit 3 controls whether or not a PCI device ignores PCI special cycles. The PCI1211 does not respond to special cycle operations; therefore, this bit is hardwired to 0. Bit 3 returns 0 when read. Writes to this bit have no effect.

Bus master control. Bit 2 controls whether or not the PCI1211 can act as a PCI bus initiator (master). The PCI1211 can take control of the PCI bus only when this bit is set.

Memory space enable. Bit 1 controls whether or not the PCI1211 can claim cycles in PCI memory space.

I/O space control. Bit 0 controls whether or not the PCI1211 can claim cycles in PCI I/O space.

0 = Disable SERR 1 = Enable SERR

0 = PCI1211 ignores detected parity error (default) 1 = PCI1211 responds to detected parity errors

0 = Disables the PCI1211’s ability to generate PCI bus accesses (default) 1 = Enables the PCI1211’s ability to generate PCI bus accesses

0 = Disables the PCI1211’s response to memory space accesses (default) 1 = Enables the PCI1211’s response to memory space accesses

0 = Disables the PCI1211 from responding to I/O space accesses (default) 1 = Enables the PCI1211 to respond to I/O space accesses

PCI Local Bus Specification, Revision 2.2

output driver (default)

output driver

, whereas address parity errors are indicated by asserting

. See Table 17 for the

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status register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Status Type R/WC R/WC R/WC R/WC R/WC R R R/WC R R R R R R R R Default 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0

Register: Status Type: Read-only, Read/Write to Clear (see individual bit descriptions) Offset: 06h Default: 0210h Description: This register provides device information to the host system. Bits in this register may be read

normally. A bit in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. All bit functions adhere to the definitions in the

Specification, Revision 2.2

. PCI bus status is shown through each function. See T able 18 for

the complete description of the register contents.

Table 18. Status Register

BIT SIGNAL TYPE FUNCTION

15 PAR_ERR R/WC Detected parity error . Bit 15 is set when a parity error is detected (either address or data). 14 SYS_ERR R/WC

13 MABORT R/WC

12 TABT_REC R/WC

11 TABT_SIG R/WC

10–9 PCI_SPEED R

8 DATAPAR R/WC

7 FBB_CAP R

6 UDF R

5 66MHZ R

4 CAPLIST R

3–0 RSVD R Reserved. Bits 3–0 return 0s when read.

Signaled system error. Bit 14 is set when SERR is enabled and the PCI121 1 signals a system error to the host.

Received master abort. Bit 13 is set when a cycle initiated by the PCI1211 on the PCI bus has been terminated by a master abort.

Received target abort. Bit 12 is set when a cycle initiated by the PCI1211 on the PCI bus was terminated by a target abort.

Signaled target abort. Bit 11 is set by the PCI1211 when it terminates a transaction on the PCI bus with a target abort.

DEVSEL timing. These bits encode the timing of DEVSEL and are hardwired 01b, indicating that the PCI1211 asserts PCI_SPEED at a medium speed on nonconfiguration cycle accesses.

Data parity error detected.

Fast back-to-back capable. The PCI1211 cannot accept fast back-to-back transactions; thus, bit 7 is hardwired to 0.

User-definable feature support. The PCI121 1 does not support the user-definable features; thus, bit 6 is hardwired to 0.

66-MHz capable. The PCI1211 operates at a maximum PCLK frequency of 33 MHz; therefore, bit 5 is hardwired to 0.

Capabilities list. Bit 4 returns 1 when read. This bit indicates that capabilities in addition to standard PCI capabilities are implemented. The linked list of PCI power-management capabilities is implemented in this function.

0 = The conditions for setting bit 8 have not been met. 1 = A data parity error occurred, and the following conditions were met:

a. PERR b. The PCI1211 was the bus master during the data parity error. c. The parity error response bit is set in the command.

was asserted by any PCI device including the PCI1211.

PCI Local Bus

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revision ID register

Bit 7 6 5 4 3 2 1 0 Name Revision ID Type R R R R R R R R Default 0 0 0 0 0 0 0 0

Register: Revision ID Type: Read-only Offset: 08h Default: 00h Description: This register indicates the silicon revision of the PCI1211.

PCI class code register

Bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Class code

Base class Sub class Programming interface

Type R R R R R R R R R R R R R R R R R R R R R R R R Default 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0

Register: PCI Class code Type: Read-only Offset: 09h Default: 060700h Description: This register recognizes the PCI1211 as a bridge device (06h), and CardBus bridge device

(07h) with a 00h programming interface.

cache line size register

Bit 7 6 5 4 3 2 1 0 Name Cache line size Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: Cache line size Type: Read/Write Offset: 0Ch Default: 00h Description: This register is programmed by host software to indicate the system cache line size.

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latency timer register

Bit 7 6 5 4 3 2 1 0 Name Latency timer Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: Latency timer Type: Read/Write Offset: 0Dh Default: 00h Description: This register specifies the latency timer for the PCI1211 in units of PCI clock cycles. When the

PCI1211 is a PCI bus initiator and asserts FRAME zero. If the latency timer expires before the PCI1211 transaction has terminated, the PCI1211 terminates the transaction when its GNT

is deasserted.

header type register

Bit 7 6 5 4 3 2 1 0 Name Header type Type R R R R R R R R Default 0 0 0 0 0 0 1 0

, the latency timer begins counting from

Register: Header type Type: Read-only Offset: 0Eh Default: 02h Description: This register returns 02h when read, indicating that the PCI1211 configuration spaces adhere

to the CardBus bridge PCI header. The CardBus bridge PCI header ranges from PCI register 0 to 7Fh, leaving 80h–FFh is user-definable extension registers.

BIST register

Bit 7 6 5 4 3 2 1 0 Name BIST Type R R R R R R R R Default 0 0 0 0 0 0 0 0

Register: BIST Type: Read-only Offset: 0Fh Default: 00h Description: Because the PCI1211 does not support a built-in self-test (BIST), this register returns the

value of 00h when read.

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CardBus socket registers/ExCA registers base-address register

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name CardBus socket/ExCA registers base address Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name CardBus socket/ExCA registers base address Type R/W R/W R/W R/W R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: CardBus socket/ExCA registers base address Type: Read-only, Read/Write Offset: 10h Default: 0000 0000h Description: This register is programmed with a base address referencing the CardBus socket registers

and the memory-mapped ExCA register set. Bits 31–12 are read/write, and allow the base address to be located anywhere in the 32-bit PCI memory address space on a 4K-byte boundary. Bits 11–0 are read-only, returning 0s when read. When software writes all 1s to this register, the value readback is FFFF F000h, indicating that at least 4K bytes of memory address space are required. The CardBus registers start at offset 000h, and the memory-mapped ExCA registers begin at offset 800h.

capability pointer register

Bit 7 6 5 4 3 2 1 0 Name Capability pointer Type R R R R R R R R Default 1 0 1 0 0 0 0 0

Register: Capability pointer Type: Read-only Offset: 14h Default: A0h Description: This register provides a pointer into the PCI configuration header where the PCI power

management register block resides. PCI header doublewords at A0h and A4h provide the power management (PM) registers. The socket has its own capability pointer register. This register returns A0h when read.

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secondary status register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Secondary status Type R/WC R/WC R/WC R/WC R/WC R R R/WC R R R R R R R R Default 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0

Register: Secondary status Type: Read-only, Read/Write to Clear (see individual bit descriptions) Offset: 16h Default: 0200h Description: This register is compatible with the PCI-to-PCI bridge secondary status register, and indicates

CardBus-related device information to the host system. This register is very similar to the PCI status register (offset 06h), and status bits are cleared by writing a 1. See Table 19 for the complete description of the register contents.

Table 19. Secondary Status Register

BIT SIGNAL TYPE FUNCTION

15 CBPARITY R/WC Detected parity error. Bit 15 is set when a CardBus parity error is detected (either address or data). 14 CBSERR R/WC

13 CBMABORT R/WC

12 REC_CBTA R/WC

11 SIG_CBTA R/WC

10–9 CB_SPEED R

8 CB_DPAR R/WC

7 CBFBB_CAP R

6 CB_UDF R

5 CB66MHZ R

4–0 RSVD R Reserved. Bits 4–0 return 0s when read.

Signaled system error. Bit 14 is set when CSERR is signaled by a CardBus card. The PCI121 1 does not assert CSERR

Received master abort. Bit 13 is set when a cycle initiated by the PCI1211 on the CardBus bus has been terminated by a master abort.

Received target abort. Bit 12 is set when a cycle initiated by the PCI1211 on the CardBus bus is terminated by a target abort.

Signaled target abort. Bit 1 1 is set by the PCI121 1 when it terminates a transaction on the CardBus bus with a target abort.

CDEVSEL timing. These bits encode the timing of CDEVSEL and are hardwired 01b, indicating that the PCI1211 asserts CB_SPEED at a medium speed.

CardBus data parity error detected.

Fast back-to-back capable. The PCI1211 cannot accept fast back-to-back transactions; thus, bit 7 is hardwired to 0.

User-definable feature support. The PCI1211 does not support the user-definable features; thus, bit 6 is hardwired to 0.

66-MHz capable. The PCI1211 CardBus interface operates at a maximum CCLK frequency of 33 MHz; therefore, bit 5 is hardwired to 0.

0 = The conditions for setting bit 8 have not been met. 1 = A data parity error occurred and the following conditions were met:

a. CPERR b. The PCI1211 was the bus master during the data parity error. c. The parity error response bit is set in the bridge control.

was asserted on the CardBus interface.

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PCI bus number register

Bit 7 6 5 4 3 2 1 0 Name PCI bus number Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: PCI bus number Type: Read/Write Offset: 18h Default: 00h Description: This register is programmed by the host system to indicate the bus number of the PCI bus to

which the PCI1211 is connected. The PCI1211 uses this register in conjunction with the CardBus bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses.

CardBus bus number register

Bit 7 6 5 4 3 2 1 0 Name CardBus bus number Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: CardBus bus number Type: Read/Write Offset: 19h Default: 00h Description: This register is programmed by the host system to indicate the bus number of the CardBus

bus to which the PCI1211 is connected. The PCI1211 uses this register in conjunction with the PCI bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses.

subordinate bus number register

Bit 7 6 5 4 3 2 1 0 Name Subordinate bus number Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: Subordinate bus number Type: Read/Write Offset: 1Ah Default: 00h Description: This register is programmed by the host system to indicate the highest-numbered bus below

the CardBus bus. The PCI1211 uses this register in conjunction with the PCI bus number and CardBus bus number registers to determine when to forward PCI configuration cycles to its secondary buses.

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CardBus latency timer register

Bit 7 6 5 4 3 2 1 0 Name CardBus latency timer Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: CardBus latency timer Type: Read/Write Offset: 1Bh Default: 00h Description: This register is programmed by the host system to specify the latency timer for the PCI1211

CardBus interface in units of CCLK cycles. When the PCI1211 is a CardBus initiator and asserts CFRAME before the PCI1211 transaction has terminated, then the PCI1211 terminates the transaction at the end of the next data phase. A recommended minimum value for this register is 20h, which allows most transactions to be completed.

memory base registers 0, 1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Memory base registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Memory base registers 0, 1 Type R/W R/W R/W R/W R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

, the CardBus latency timer begins counting. If the latency timer expires

Register: Memory base registers 0, 1 Type: Read-only, Read/Write Offset: 1Ch, 24h Default: 0000 0000h Description: These registers indicate the lower address of a PCI memory address range and are used by

the PCI1211 to determine when to forward a memory transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to PCI. Bits 31–12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit PCI memory space on 4K-byte boundaries. Bits 11–0 always return 0s when read. Writes to these bits have no effect. Bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero for the PCI1211 to claim any memory transactions through CardBus memory windows (i.e., these windows are not enabled by default to pass the first 4K bytes of memory to CardBus).

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memory limit registers 0, 1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Memory limit registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Memory limit registers 0, 1 Type R/W R/W R/W R/W R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Memory limit registers 0, 1 Type: Read-only, Read/Write Offset: 20h, 28h Default: 0000 0000h Description: These registers indicate the upper address of a PCI memory address range and are used by

I/O base registers 0, 1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name I/O base registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name I/O base registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: I/O base registers 0, 1 Type: Read-only, Read/Write Offset: 2Ch, 34h Default: 0000 0000h Description: These registers indicate the lower address of a PCI I/O address range and are used by the

PCI121 1 to determine when to forward an I/O transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to the PCI bus. The lower 16 bits of this register locate the bottom of the I/O window within a 64K-byte page, and the upper 16 bits (31–16) are a page register which locates this 64K-byte page in 32-bit PCI I/O address space. Bits 31–2 are read/write. Bits 1–0 always return 0s when read, forcing I/O windows to be aligned on a natural doubleword boundary.

NOTE:

Either the I/O base or the I/O limit register must be nonzero to enable any I/O transactions.

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I/O limit registers 0, 1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name I/O limit registers 0, 1 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name I/O limit registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: I/O limit registers 0, 1 Type: Read-only, Read/Write Offset: 30h, 38h Default: 0000 0000h Description: These registers indicate the upper address of a PCI I/O address range and are used by the

PCI1211 to determine when to forward an I/O transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to PCI. The lower 16 bits of this register locate the top of the I/O window within a 64K-byte page, and the upper 16 bits are a page register which locates this 64K-byte page in 32-bit PCI I/O address space. Bits 15–2 are read/write and allow the I/O limit address to be located anywhere in the 64K-byte page (indicated by bits 31–16 of the appropriate I/O base) on doubleword boundaries.

Bits 31–16 always return 0s when read. The page is set in the I/O base register. Bits 1–0 always return 0s when read, forcing I/O windows to be aligned on a natural doubleword boundary. Writes to read-only bits have no effect. The PCI1211 assumes that the lower 2 bits of the limit address are 1s.

NOTE:

The I/O base or the I/O limit register must be nonzero to enable an I/O transaction.

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interrupt line register

Bit 7 6 5 4 3 2 1 0 Name Interrupt line Type R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 1 1 1 1 1 1

Register: Interrupt line Type: Read/Write Offset: 3Ch Default: FFh Description: This register is used to communicate interrupt line routing information.

interrupt pin register

Bit 7 6 5 4 3 2 1 0 Name Interrupt pin Type R R R R R R R R Default 0 0 0 0 0 0 0 1

Register: Interrupt pin Type: Read-only Offset: 3Dh Default: 01h Description: The value read from the interrupt pin register is function dependent and reflects the interrupt

signalling mode selected through the device control register (92h). The PCI121 1 defaults to serialized PCI and ISA interrupt mode.

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bridge control register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Bridge control Type R R R R R R/W R/W R/W R/W R/W R/W R R/W R/W R/W R Default 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0

Register: Bridge control Type: Read-only, Read/Write (see individual bit descriptions) Offset: 3Eh Default: 0340h Description: This register provides control over various PCI1211 bridging functions. See Table 20 for a

complete description of the register contents.

Table 20. Bridge Control Register

BIT SIGNAL TYPE FUNCTION

15–1 1 RSVD R Reserved. Bits 15–11 return 0s when read.

Write posting enable. Enables write posting to and from the CardBus sockets. Write posting enables

10 POSTEN R/W

9 PREFETCH1 R/W

8 PREFETCH0 R/W

7 INTR R/W

6 CRST R/W

5 MABTMODE R/W

4 RSVD R Reserved. Bit 4 returns 0 when read. 3 VGAEN R/W

2 ISAEN R/W

1 CSERREN R/W

0 CPERREN R

posting of write data on burst cycles. Operating with write posting disabled inhibits performance on burst cycles. Note that bursted write data can be posted, but various write transactions may not.

Memory window 1 type. Bit 9 specifies whether or not memory window 1 is prefetchable. This bit is socket dependent. Bit 9 is encoded as:

Memory window 0 type. Bit 8 specifies whether or not memory window 0 is prefetchable. This bit is encoded as:

PCI interrupt – IREQ routing enable. Bit 7 is used to select whether PC Card functional interrupts are routed to PCI interrupts or the IRQ specified in the ExCA registers.

CardBus reset. When bit 6 is set, CRST is asserted on the CardBus interface. CRST can also be asserted by passing a RST

Master abort mode. Bit 5 controls how the PCI1211 responds to a master abort when the PCI1211 is an initiator on the CardBus interface. This bit is common between each socket.

VGA enable. Bit 3 affects how the PCI121 1 responds to VGA addresses. When this bit is set, accesses to VGA addresses are forwarded.

ISA mode enable. Bit 2 affects how the PCI1211 passes I/O cycles within the 64K-byte ISA range. This bit is not common between sockets. When this bit is set, the PCI1211 does not forward the last 768 bytes of each 1K I/O range to CardBus.

CSERR enable. Bit 1 controls the response of the PCI1211 to CSERR signals on the CardBus bus. This bit is common between the two sockets.

CardBus parity error response enable. Bit 0 controls the response of the PCI1211 to CardBus parity errors. This bit is common between the two sockets.

0 = Memory window 1 is nonprefetchable. 1 = Memory window 1 is prefetchable (default).

0 = Memory window 0 is nonprefetchable. 1 = Memory window 0 is prefetchable (default).

0 = Functional interrupts routed to PCI interrupts (default) 1 = Functional interrupts routed by ExCAs

0 = CRST 1 = CRST

0 = Master aborts not reported (default) 1 = Signal target abort on PCI and SERR

0 = CSERR 1 = CSERR

0 = CardBus parity errors are ignored. 1 = CardBus parity errors are reported using CPERR

assertion to CardBus. deasserted asserted (default)

(if enabled)

is not forwarded to PCI SERR. is forwarded to PCI SERR.

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subsystem vendor ID register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Subsystem vendor ID Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Subsystem vendor ID Type: Read-only (read/write when bit 5 in the system control register is 0) Offset: 40h Default: 0000h Description: This register is used for system and option-card identification purposes, and may be required

for certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register. When bit 5 is 0, this register is read/write; when bit 5 is 1, this register is read-only. The default mode is read-only.

subsystem ID register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Subsystem ID Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Subsystem ID Type: Read-only (read/write when bit 5 in the system control register is 0) Offset: 42h Default: 0000h Description: This register is used for system and option-card identification purposes, and may be required

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PC Card 16-bit I/F legacy-mode base address register

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name PC Card 16-bit I/F legacy-mode base address Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name PC Card 16-bit I/F legacy-mode base address Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Register: PC Card 16-bit I/F legacy-mode base address Type: Read-only, Read/Write (see individual bit descriptions) Offset: 44h Default: 0000 0001h Description: The PCI1211 supports the index/data scheme of accessing the ExCA registers, which is

mapped by this register. An address written to this register is the address for the index register and the address + 1 is the data address. Using this access method, applications requiring index/data ExCA access can be supported. The base address can be mapped anywhere in 32-bit I/O space on a word boundary; hence, bit 0 is read-only, returning 1 when read. Refer to

ExCA compatibility registers

on page 80 for register offsets.

system control register

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name System control Type R/W R/W R R R R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name System control Type R/W R/W R R R R R R R R/W R/W R/W R/W R R/W R/W Default 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0

Register: System control Type: Read-only, Read/Write (see individual bit descriptions) Offset: 80h Default: 0044 9060h Description: System-level initializations are performed through programming this doubleword register.

See Table 21 for a complete description of the register contents.

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Table 21. System Control Register

BIT SIGNAL TYPE FUNCTION

Serialized PCI interrupt routing step. Bits 31–30 are used to configure the serialized PCI interrupt stream signaling, and accomplish an even distribution of interrupts signaled on the four PCI interrupt slots. Bits 31–30 are encoded as follows:

31–30 SER_STEP R/W

29–27 RSVD R Reserved. These bits return 0s when read.

SMI interrupt routing. Bit 26 selects whether IRQ2 or CSC is signaled when a write occurs to power

26 SMIROUTE R/W

25 SMISTA TUS R/W

24 SMIENB R/W 23 RSVD R Reserved. This bit returns 0 when read.

22 CBRSVD R/W

21 VCCPROT R/W

20 REDUCEZV R/W

19 CDREQEN R/W

18–16 CDMACHAN R/W

15 MRBURSTDN R/W

14 MRBURSTUP R/W

13 SOCACTIVE R

12 RSVD R Reserved. Bit 12 returns 1 when read. This is the power rail bit.

a PC Card socket.

SMI interrupt status. This socket-dependent bit is set when a write occurs to set the socket power, and the SMIENB bit is set. Writing a 1 to bit 25 clears the status.

SMI interrupt mode enable. When bit 24 is set, the SMI interrupt signaling is enabled and generates an interrupt when a write to the socket power control occurs. This bit defaults to 0 (disabled).

CardBus reserved terminals signaling. When bit 22 is set, the RSVD CardBus terminals are driven low when a CardBus card is inserted. When this bit is low (as default), these signals are 3-stated.

VCC protection enable.

Reduced Zoom Video Enable.When this bit is enabled, A25–A22 of the card interface for PC Card 16 cards is placed in the high impedance state. This bit should not be set for normal ZV operation. This bit is encoded as:

PC/PCI DMA card enable. When bit 19 is set, the PCI1211 allows 16-bit PC Cards to request PC/PCI DMA using the DREQ

PC/PCI DMA channel assignment. Bits 18–16 are encoded as:

Memory read burst enable downstream. When bit 15 is set, memory read transactions are allowed to burst downstream.

Memory read burst enable upstream. When bit 14 is set, the PCI1211 allows memory read transactions to burst upstream.

Socket activity status. When set, bit 13 indicates access has been performed to or from a PC card, and is cleared upon read of this status bit. This bit is socket dependent.

00 = INTA 01 = INTA 10 = INTA 11 = INTA

0 = PC Card power change interrupts routed to IRQ2 (default) 1 = A CSC interrupt is generated on PC Card power changes.

0= SMI interrupt signaled (default) 1 = SMI interrupt not signaled

0 = 3-state CardBus RSVD 1 = Drive Cardbus RSVD low (default)

0 = VCC protection enabled for 16-bit cards (default) 1 = VCC protection disabled for 16-bit cards

0 = Reduced zoom video disabled (default) 1 = Reduced zoom video enabled

0 = Ignore DREQ 1 = Signal DMA request on DREQ

0–3 = 8-bit DMA channels 4 = PCI master; not used (default). 5–7 = 16-bit DMA channels

0 = Downstream memory read burst is disabled. 1 = Downstream memory read burst is enabled (default).

0 = Upstream memory read burst is disabled (default). 1 = Upstream memory read burst is enabled.

0 = No socket activity (default) 1 = Socket activity

is signaled in the INTA IRQSER slot. is signaled in the INTB IRQSER slot. is signaled in the INTC IRQSER slot. is signaled in the INTD IRQSER slot.

signaling. DREQ is selected through the socket DMA register 0.

signaling from PC Cards (default)

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Table 21. System Control Register (Continued)

BIT SIGNAL TYPE FUNCTION

11 PWRSTREAM R

10 DELAYUP R

9 DELAYDOWN R

8 INTERROGATE R

7 RSVD R Reserved. Bit 7 returns 0 when read. 6 PWRSA VINGS R/W

5 SUBSYSRW R/W

4 CB_DPAR R/W

3 CDMA_EN R/W

2 RSVD R Reserved. Bit 2 returns 0 when read.

1 KEEPCLK R/W

0 RIMUX R/W

Power stream in progress status bit. When set, bit 11 indicates that a power stream to the power switch is in progress and a powering change has been requested. This bit is cleared when the power stream is complete.

Power-up delay in progress status. When set, bit 9 indicates that a power-up stream has been sent to the power switch and proper power may not yet be stable. This bit is cleared when the power-up delay has expired.

Power-down delay in progress status. When set, bit 10 indicates that a power-down stream has been sent to the power switch and proper power may not yet be stable. This bit is cleared when the power-down delay has expired.

Interrogation in progress. When set, bit 8 indicates an interrogation is in progress and clears when interrogation completes.

Power savings mode enable. When this bit is set, if a CB card is inserted, idle, and without a CB clock, the applicable CB state machine will not be clocked.

Subsystem ID (SSID), subsystem vendor ID (SSVID), ExCA ID, and revision register read/write enable.

CardBus data parity SERR signaling enable

PC/PCI DMA enable. Bit 3 enables PC/PCI DMA when set if MFUNC routing is configured for centralized DMA.

Keep clock. This bit works with PCI and CB CLKRUN protocols

RI_OUT/PME multiplex enable.

0 = Interrogation not in progress (default) 1 = Interrogation in progress

0 = SSID, SSVID, ExCA ID, and revision register are read/write. 1 = SSID, SSVID, ExCA ID, and revision register are read-only (default).

0 = CardBus data parity not signaled on PCI SERR 1 = CardBus data parity signaled on PCI SERR

0 = Centralized DMA disabled (default) 1 = Centralized DMA enabled

0 = Allows normal functioning of both CLKRUN 1 = Does not allow CB clock or PCI clock to be stopped using the CLKRUN

0 = RI_OUT

at the same time, RI_OUT

1 = Only PME

and PME are both routed to the RI_OUT/PME terminal. If both are enabled

has precedence over PME.

is routed to the RI_OUT/PME terminal.

protocols. (default)

protocols.

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multifunction routing register

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Multifunction routing Type R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Multifunction routing Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Multifunction routing Type: Read-only, Read/Write (see individual bit descriptions) Offset: 8Ch Default: 0000 0000h Description: This register is used to configure the MFUNC0–MFUNC6 terminals. These terminals may be

configured for various functions. All multifunction terminals default to the general-purpose input configuration. Pullup resistors are required for terminals configured as outputs. This register is intended to be programmed once at power-on initialization. The default value for this register may also be loaded through a serial bus EEPROM. See Table 22 for a complete description of the register contents.

Table 22. Multifunction Routing Register

BIT SIGNAL TYPE FUNCTION

31–28 RSVD R Reserved. These bits return 0s when read.

Multifunction terminal 6 configuration. These bits control the internal signal mapped to the MFUNC6 terminal as follows:

27–24 MFUNC6 R/W

0000 = RSVD, Reserved high impedance input (default) 0001 = CLKRUN 0010 = IRQ2, Parallel ISA type 0011 = IRQ3, Parallel ISA type 0100 = IRQ4, Parallel ISA type 0101 = IRQ5, Parallel ISA type 0110 = IRQ6, Parallel ISA type 0111 = IRQ7, Parallel ISA type 1000 = IRQ8, Parallel ISA type 1001 = IRQ9, Parallel ISA type 1010 = IRQ10, Parallel ISA type 1011 = IRQ11, Parallel ISA type 1100 = IRQ12, Parallel ISA type 1101 = IRQ13, Parallel ISA type 1110 = IRQ14, Parallel ISA type 1111 = IRQ15, Parallel ISA type

, PCI clock control signal

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Table 22. Multifunction Routing Register (Continued)

BIT SIGNAL TYPE FUNCTION

Multifunction terminal 5 configuration. These bits control the internal signal mapped to the MFUNC5 terminal as follows:

23–20 MFUNC5 R/W

Multifunction terminal 4 configuration. These bits control the internal signal mapped to the MFUNC4 terminal as follows:

0000 = GPI4, General-purpose input (default) 0001 = GPO4, General-purpose output 0010 = PCGNT 0011 = IRQ3, Parallel ISA type 0100 = IRQ4, Parallel ISA type 0101 = IRQ5, Parallel ISA type 0110 = ZVSTAT, Zoom video status output 0111 = ZVSEL0 1000 = CAUDPWM, PWM output of CAUDIO CardBus terminal 1001 = IRQ9, Parallel ISA type 1010 = IRQ10, Parallel ISA type 1011 = IRQ11, Parallel ISA type 1100 = LED_SKT, Socket activity LED 1101 = LED_SKT, Socket activity LED 1110 = GPE 1111 = IRQ15, Parallel ISA type

, PC/PCI (centralized) DMA grant

, Zoom video select output

, General-Purpose event signal

19–16 MFUNC4 R/W

15–12 MFUNC3 R/W

NOTE: When the serial bus mode is implemented by pulling up the VPPD0 and VPPD1 terminals, the MFUNC4 terminal provides the SCL signaling.

0000 = GPI3, General-purpose input (default) 0001 = GPO3, General-purpose output 0010 = LOCK 0011 = IRQ3, Parallel ISA type 0100 = IRQ4, Parallel ISA type 0101 = IRQ5, Parallel ISA type 0110 = ZVSTAT, Zoom video status output 0111 = ZVSEL0 1000 = CAUDPWM, PWM output of CAUDIO CardBus terminal 1001 = IRQ9, Parallel ISA type 1010 = IRQ10, Parallel ISA type 1011 = IRQ11, Parallel ISA type 1100 = RI_OUT 1101 = LED_SKT, Socket activity LED 1110 = GPE 1111 = IRQ15, Parallel ISA type

Multifunction terminal 3 configuration. These bits control the internal signal mapped to the MFUNC3 terminal as follows:

0000 = RSVD, Reserved high impedance input (default) 0001 = IRQSER, Serial interrupt stream, IRQ and optional PCI 0010 = IRQ2, Parallel ISA type 0011 = IRQ3, Parallel ISA type 0100 = IRQ4, Parallel ISA type 0101 = IRQ5, Parallel ISA type 0110 = IRQ6, Parallel ISA type 0111 = IRQ7, Parallel ISA type 1000 = IRQ8, Parallel ISA type 1001 = IRQ9, Parallel ISA type 1010 = IRQ10, Parallel ISA type 1011 = IRQ11, Parallel ISA type 1100 = IRQ12, Parallel ISA type 1101 = IRQ13, Parallel ISA type 1110 = IRQ14, Parallel ISA type 1111 = IRQ15, Parallel ISA type

, PCI atomic transfer support mechanism

, Zoom video select output

, Ring-indicate output

, General-purpose event signal

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Table 22. Multifunction Routing Register (Continued)

BIT SIGNAL TYPE FUNCTION

Multifunction terminal 2 configuration. These bits control the internal signal mapped to the MFUNC2 terminal as follows:

11–8 MFUNC2 R/W

Multifunction terminal 1 configuration. These bits control the internal signal mapped to the MFUNC1 terminal as follows:

0000 = GPI2, General-purpose input (default) 0001 = GPO2, General-purpose output 0010 = PCREQ 0011 = IRQ3, Parallel ISA type 0100 = IRQ4, Parallel ISA type 0101 = IRQ5, Parallel ISA type 0110 = ZVSTAT, Zoom video status output 0111 = ZVSEL0 1000 = CAUDPWM, PWM output of CAUDIO CardBus terminal 1001 = IRQ9, Parallel ISA type 1010 = IRQ10, Parallel ISA type 1011 = IRQ11, Parallel ISA type 1100 = RI_OUT 1101 = IRQ13, Parallel ISA type 1110 = GPE 1111 = IRQ7, Parallel ISA type

, PC/PCI (centralized) DMA request

, Zoom video select output

, Ring-indicate output

, General-purpose event signal

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7–4 MFUNC1 R/W

3–0 MFUNC0 R/W

NOTE: When the serial bus mode is implemented by pulling up the VPPD0 and VPPD1 terminals, the MFUNC1 terminal provides the SDA signaling.

0000 = GPI1, General-purpose input (default) 0001 = GPO1, General-purpose output 0010 = IRQ2, Parallel ISA type 0011 = IRQ3, Parallel ISA type 0100 = IRQ4, Parallel ISA type 0101 = IRQ5, Parallel ISA type 0110 = ZVSTAT, Zoom video status output 0111 = ZVSEL0 1000 = CAUDPWM, PWM output of CAUDIO CardBus terminal 1001 = IRQ9, Parallel ISA type 1010 = IRQ10, Parallel ISA type 1011 = IRQ11, Parallel ISA type 1100 = LED_SKT, Socket activity LED 1101 = IRQ13, Parallel ISA type 1110 = GPE 1111 = IRQ15, Parallel ISA type

Multifunction terminal 0 configuration. These bits control the internal signal mapped to the MFUNC0 terminal as follows:

0000 = GPI0, General-purpose input (default) 0001 = GPO0, General-purpose output 0010 = INTA 0011 = IRQ3, Parallel ISA type 0100 = IRQ4, Parallel ISA type 0101 = IRQ5, Parallel ISA type 0110 = ZVSTAT, Zoom video status output 0111 = ZVSEL0 1000 = CAUDPWM, PWM output of CAUDIO CardBus terminal 1001 = IRQ9, Parallel ISA type 1010 = IRQ10, Parallel ISA type 1011 = IRQ11, Parallel ISA type 1100 = LED_SKT, Socket activity LED 1101 = IRQ13, Parallel ISA type 1110 = GPE 1111 = IRQ15, Parallel ISA type

, Zoom video select output

, General-purpose event signal

, PCI interrupt signal, INTA

, Zoom video select output

, General-purpose event signal

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retry status register

Bit 7 6 5 4 3 2 1 0 Name Retry status Type R/W R/W R R R/WC R R/WC R Default 1 1 0 0 0 0 0 0

Register: Retry status Type: Read-only, Read/Write, Read/Write to Clear (see individual bit descriptions) Offset: 90h Default: C0h Description: This register enables the retry timeout counters and displays the retry expiration status. The

flags are set when the PCI1211 retries a PCI or CardBus master request, and the master does not return within 2 are expected to be incorporated into the PCI command, PCI status, and bridge control registers by the PCI SIG. See Table 23 for a complete description of the register contents.

BIT SIGNAL TYPE FUNCTION

PCI retry timeout counter enable. Bit 7 is encoded:

7 PCIRETRY R/W

CardBus retry timeout counter enable. Bit 6 is encoded:

6 CBRETRY R/W

5–4 RSVD R Reserved. These bits return 0s when read.

CardBus target retry expired. Write a 1 to clear bit 3.

3 TEXP_CB R/WC

2 RSVD R Reserved. Bit 2 returns 0 when read.

PCI target retry expired. Write a 1 to clear bit 1.

1 TEXP_PCI R/WC

0 RSVD R Reserved. Bit 0 returns 0 when read.

PCI clock cycles. The flags are cleared by writing a 1 to the bit. These bits

Table 23. Retry Status Register

0 = PCI retry counter disabled 1 = PCI retry counter enabled (default)

0 = CardBus retry counter disabled 1 = CardBus retry counter enabled (default)

0 = Inactive (default) 1 = Retry has expired.

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card control register

Bit 7 6 5 4 3 2 1 0 Name Card control Type R/W R/W R/W R R R/W R/W R/WC Default 0 0 0 0 0 0 0 0

Register: Card control Type: Read-only, Read/Write, Read/Write to Clear (see individual bit descriptions) Offset: 91h Default: 00h Description: This register is provided for PCI1130 compatibility. RI_OUT

See Table 24 for a complete description of the register contents.

Table 24. Card Control Register

BIT SIGNAL TYPE FUNCTION

Ring-indicate output enable.

7 RIENB R/W

6 ZVENABLE R/W 5 No function R/W These bits have no assigned function.

4–3 RSVD R Reserved. Bits 4–3 default to 0.

2 AUD2MUX R/W

1 SPKROUTEN R/W

0 IFG R/WC

Compatibility ZV mode enable. When set, the PC Card socket interface ZV terminals enter a high-impedance state.

CardBus Audio-to-CAUDPWM. When set, the CAUDIO signal (PWM) is routed to the CAUDPWM signal which can be routed to a multifunction terminal.

Speaker out enable. This bit is the enable for routing PC Card SPKR through to the SPKROUT terminal. The SPKROUT terminal drives valid data only when the socket SPKROUTEN bit is set.

Interrupt flag. Bit 0 is the interrupt flag for 16-bit I/O PC Cards and for CardBus cards. Bit 0 is set when a functional interrupt is signaled from a PC Card interface. Write back a 1 to clear this bit.

0 = Disables any routing of RI_OUT 1 = Enables RI_OUT

to 0, or for routing to MFUNC2/4.

0 = SPKR 1 = SPKR

0 = No PC Card functional interrupt detected (default). 1 = PC Card functional interrupt detected.

to SPKROUT not enabled (default)

to SPKROUT enabled

signal for routing to the RI_OUT/PME terminal when RIMUX is set

signal (default).

is enabled through this register.

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device control register

Bit 7 6 5 4 3 2 1 0 Name Device control Type R R/W R/W R R/W R/W R/W R/W Default 0 1 1 0 0 1 1 0

Register: Device control Type: Read-only, Read/Write (see individual bit descriptions) Offset: 92h Default: 66h Description: This register is provided for PCI1130 compatibility The mode select and socket-capable force

bits are programmed through this register. See Table 25 for a complete description of the register contents.

Table 25. Device Control Register

BIT SIGNAL TYPE FUNCTION

7 RSVD R Reserved. Bit 7 returns 0 when read.

3-V socket capable force

6 3VCAPABLE R/W

5 IO16R2 R/W Diagnostic bit. 4 RSVD R Reserved. Bit 4 returns 0 when read. Writes have no effect. 3 TEST R/W TI test. Only a 0 should be written to bit 3. This bit can be set to shorten the interrogation counter.

Interrupt mode. Bits 2–1 select the interrupt signaling mode. The interrupt mode bits are encoded:

2–1 INTMODE R/W

0 RSVD R/W Reserved. This bit is reserved for test purposes. Only 0 should be written to this bit.

0 = Not 3-V capable 1 = 3-V capable (default)

00 = Parallel PCI interrupts only 01 = Parallel IRQ and parallel PCI interrupts 10 = IRQ serialized interrupts and parallel PCI interrupt 11 = IRQ and PCI serialized interrupts (default)

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diagnostic register

Bit 7 6 5 4 3 2 1 0 Name Diagnostic Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 1 1 0 0 0 0 1

Register: Diagnostic Type: Read/Write Offset: 93h Default: 61h Description: This register is provided for internal TI test purposes. It is a read/write register, but should not

be accessed during normal operation. See Table 26 for a complete description of the register contents.

Table 26. Diagnostic Register

BIT SIGNAL TYPE FUNCTION

True value. This bit defaults to 0 when read. This bit is encoded as:

7 TRUE_VAL R/W

6 RSVD R/W Reserved. This bit has no function.

CSC Interrupt Routing Control.

5 CSC R/W

4 DIAG4 R/W Diagnostic RETRY_DIS. Delayed transaction disable. 3 DIAG3 R/W Diagnostic RETRY_EXT. Extends the latency from 16 to 64. 2 DIAG2 R/W Diagnostic DISCARD_TIM_SEL_CB. Set = 210, reset = 215. 1 DIAG1 R/W Diagnostic DISCARD_TIM_SEL_PCI. Set = 210, reset = 215.

0 ASYNCINT R/W

Global asynchronous interrupt enable. When set to a 1, bit 0 enables the asynchronous generation of CSC interrupts.

0 = Reads true values in PCI vendor ID and PCI device ID registers (default) 1 = Reads all 1s in reads to the PCI vendor ID and PCI device ID registers

0 = CSC interrupts routed to PCI if ExCA 803 bit 4 = 1 1 = CSC interrupts routed to PCI if ExCA 805 bits 7:4 = 0000b. (default)

In this case, the setting of ExCA 803 bit 4 is a “don’t care”

socket DMA register 0

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Socket DMA register 0 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Socket DMA register 0 Type R R R R R R R R R R R R R R R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Socket DMA register 0 Type: Read-only, Read/Write (see individual bit descriptions) Offset: 94h Default: 0000 0000h Description: This register provides control over the PC Card DMA request (DREQ

) signaling. See Table 27

for a complete description of the register contents.

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Table 27. Socket DMA Register 0

BIT SIGNAL TYPE FUNCTION

31–2 RSVD R Reserved. Bits 31–2 return 0s when read.

DMA request (DREQ). Bits 1–0 indicate which pin on the 16-bit PC Card interface will be used as DREQ during DMA transfers. This field is encoded as:

1–0 DREQPIN R/W

socket DMA register 1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Socket DMA register 1 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Socket DMA register 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

00 = Socket not configured for DMA (default). 01 = DREQ 10 = DREQ 11 = DREQ

uses SPKR. uses IOIS16.

uses INPACK.

Register: Socket DMA register 1 Type: Read-only, Read/Write (see individual bit descriptions) Offset: 98h Default: 0000 0000h Description: This register provides control over the distributed DMA (DDMA) registers and the PCI portion

of DMA transfers. The DMA base address locates the DDMA registers in a 16-byte region within the first 64K bytes of PCI I/O address space. See Table 28 for a complete description of the register contents.

NOTE:

32-bit transfers are not supported; the maximum transfer possible for 16-bit PC Cards is 16 bits.

Table 28. Socket DMA Register 1

BIT SIGNAL TYPE FUNCTION

31–16 RSVD R Reserved. Bits 31–16 return 0s when read.

DMA base address. Locates the socket’s DMA registers in PCI I/O space. This field represents a 16-bit

15–4 DMABASE R/W

3 EXTMODE R Extended addressing. This feature is not supported by the PCI1211 and always returns a 0.

2–1 XFERSIZE R/W

0 DDMAEN R/W

PCI I/O address. The upper 16 bits of the address are hardwired to 0, forcing this window to within the lower 64K bytes of I/O address space. The lower 4 bits are hardwired to 0 and are included in the address decode. Thus, the window is aligned to a natural 16-byte boundary .

Transfer size. Bits 2–1 specify the width of the DMA transfer on the PC Card interface and are encoded as:

00 = Transfers are 8 bits (default). 01 = Transfers are 16 bits. 10 = Reserved 11 = Reserved

DDMA registers decode enable. Enables the decoding of the distributed DMA registers based on the value of DMABASE.

0 = Disabled (default) 1 = Enabled

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capability ID register

Bit 7 6 5 4 3 2 1 0 Name Capability ID Type R R R R R R R R Default 0 0 0 0 0 0 0 1

Register: Capability ID Type: Read-only Offset: A0h Default: 01h Description: This register identifies the linked list item as the register for PCI power management. The

register returns 01h when read, which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and the value.

next-item pointer register

Bit 7 6 5 4 3 2 1 0 Name Next-item pointer Type R R R R R R R R Default 0 0 0 0 0 0 0 0

Register: Next-item pointer Type: Read-only Offset: A1h Default: 00h Description: This register is used to indicate the next item in the linked list of the PCI power management

capabilities. Because the PCI1211 functions include only one capabilities item, this register returns 0s when read.

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power-management capabilities register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Power-management capabilities Type R R R R R R R R R R R R R R R R Default 0 1 1 1 1 1 1 0 0 0 1 0 0 0 0 1

Register: Power-management capabilities Type: Read-only (see individual bit descriptions) Offset: A2h Default: 7E21h Description: This register contains information on the capabilities of the PC Card function related to power

management. Both PCI1211 CardBus bridge functions support D0, D2, and D3 power states. See Table 29 for a complete description of the register contents.

Table 29. Power-Management Capabilities Register

BIT SIGNAL TYPE FUNCTION

PME support. This 5-bit field indicates the power states from which the PCI1211 supports asserting PME . A 0 for any bit indicates that the CardBus function cannot assert PME bits return 01111b when read. Each of these bits is described below:

15–1 1 PME_CAP R

10 D2_CAP R

9 D1_CAP R

8–6 RSVD R Reserved. These bits return 000b when read.

5 DSI R

4 AUX_PWR R

3 PMECLK R

2–0 VERSION R

D2 support. Bit 10 returns a 1 when read, indicating that the CardBus function supports the D2 device power state.

D1 support. Bit 9 returns a 1 when read, indicating that the CardBus function supports the D1 device power state.

Device-specific initialization. Bit 5 returns 1 when read, indicating that the CardBus controller function require special initialization (beyond the standard PCI configuration header) before the generic class device driver is able to use it.

Auxiliary power source. This bit returns 0 when read, indicating that the function supplies its own auxiliary power source.

PME clock. Bit 3 returns 0 when read, indicating that no host bus clock is required for the PCI1211 to generate PME

Version. Bits 2–0 return 001b when read, indicating that there are four bytes of general-purpose power management (PM) registers as described in the

Revision 1.0

Bit 15 contains the value 0, indicating that PME Bit 14 contains the value 1, indicating that PME Bit 13 contains the value 1, indicating that PME Bit 12 contains the value 1, indicating that PME Bit 11 contains the value 1, indicating that PME

can be asserted from the D0 state.

PCI Bus Power Management Interface Specification

from that power state. These five

cannot be asserted from D3 can be asserted from D3 can be asserted from D2 state. can be asserted from D1 state.

hot

cold state.

state.

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power-management control/status register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Power-management control/status Type R/WC R R R R R R R/W R R R R R R R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Power-management control/status Type: Read-only, Read/Write, Read/Write to Clear (see individual bit descriptions) Offset: A4h Default: 0000h Description: This register determines and changes the current power state of the PCI1211 CardBus

function. The contents of this register are not affected by the internally-generated reset caused by the transition from D3 register contents.

Table 30. Power-Management Control/Status Register

BIT SIGNAL TYPE FUNCTION

PME status. Bit 15 is set when the CardBus function would normally assert PME, independent

15 PMESTAT R/WC

14–13 DATASCALE R

12–9 DATASEL R

8 PME_EN R/W

7–5 RSVD R Reserved. Bits 7–5 return 0s when read.

4 DYN_DATA_PME_EN R

3–2 RSVD R Reserved. Bits 3–2 return 0s when read.

1–0 PWR_STATE R/W

of the state of the PME_EN bit. Bit 15 is cleared by a write back of 1, and this also clears the PME

signal if PME was asserted by this function. Writing a 0 to this bit has no effect.

Data scale. This 2-bit field returns 0s when read. The CardBus function does not return any dynamic data as indicated by the DYN_DATA bit.

Data select. This 4-bit field returns 0s when read. The CardBus function does not return any dynamic data as indicated by the DYN_DATA bit.

PME enable. Bit 8 enables the function to assert PME. If this bit is cleared, assertion of PME is disabled.

Dynamic data PME enable. Bit 4 returns 0 when read since the CardBus function does not report dynamic data.

Power state. This 2-bit field is used both to determine the current power state of a function, and to set the function into a new power state. This field is encoded as:

00 = D0 01 = D1 10 = D2 11 = D3

to D0 state. See Table 30 for a complete description of the

hot

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power-management control/status register bridge support extensions

Bit 7 6 5 4 3 2 1 0 Name Power-management control/status register bridge support extensions Type R R R R R R R R Default 1 1 0 0 0 0 0 0

Register: Power-management control/status register bridge support extensions Type: Read-only Offset: A6h Default: C0h Description: The power-management control/status register bridge support extensions supports PCI

bridge specific functionality . See Table 31 for a complete description of the register contents.

Table 31. Power-Management Control/Status Register Bridge Support Extensions

BIT SIGNAL TYPE FUNCTION

7 BPCC_EN R Bus power/clock control. When read, bit 7 returns a 1. 6 B2_B3 R B2/B3 support for D3

5–0 RSVD R Reserved. These bits return 0s when read.

. ThIs bit returns a 1 when read.

hot

power management data register

Bit 7 6 5 4 3 2 1 0 Name Power management data Type R R R R R R R R Default 0 0 0 0 0 0 0 0

Register: Power management data Type: Read-only Offset: A7h Default: 00h Description: This register returns zeros when read since the CardBus functions do not report dynamic

data.

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general-purpose event status register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Power-management control/status Type R/WC R R R R/WC R R R/WC R R R R/WC R/WC R/WC R/WC R/WC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: General-purpose event status Type: Read-only, Read/Write to Clear (see individual bit descriptions) Offset: A8h Default: 0000h Description: This register contains status bits that are set when events occur that are controlled by the

general-purpose control register. The bits in this register and the corresponding GPE cleared by writing a 1 to the corresponding bit location. The status bits in this register do not depend upon the state of a corresponding bit in the general-purpose enable register. See Table 32 for a complete description of the register contents.

Table 32. General-Purpose Event Status Register

BIT SIGNAL TYPE FUNCTION

15 ZV_STS R/WC

14–12 RSVD R Reserved. These bits return 0s when read.

11 PWR_STS R/WC

10–9 RSVD R Reserved. These bits return 0s when read.

8 VPP12_STS R/WC

7–5 RSVD R Reserved. These bits return 0s when read.

4 GP4_STS R/WC GPI4 Status. Bit 4 is set on a change in status of the MFUNC5 terminal input level. 3 GP3_STS R/WC GPI3 Status. Bit 3 is set on a change in status of the MFUNC4 terminal input level . 2 GP2_STS R/WC GPI2 Status. Bit 2 is set on a change in status of the MFUNC2 terminal input level. 1 GP1_STS R/WC GPI1 Status. Bit 1 is set on a change in status of the MFUNC1 terminal input level. 0 GP0_STS R/WC GPI0 Status. Bit 0 is set on a change in status of the MFUNC0 terminal input level.

PC card ZV Status. Bit 15 is set on a change in status of the ZVENABLE bit in the PC card controller function of the PCI121 1.

Power change status. Bit 11 is set when software has changed the power state the socket. A change in either VCC or VPP for the socket causes this bit to be set.

12 Volt VPP request status. Bit 8 is set when software has changed the requested Vpp level to or from 12 Volts for the PC Card socket.

are

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general-purpose event enable register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name General-purpose event enable Type R/W R R R R/W R R R/W R R R R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: General-purpose event enable Type: Read-only, Read/Write (see individual bit descriptions) Offset: AAh Default: 0000h Description: This register contains bits that are set to enable a GPE

the corresponding status bit is cleared and the event is serviced. The GPE only if one of the multifunction terminals, MFUNC6–MFUNC0, are configured for GPE signaling. See Table 33 for a complete description of the register contents.

Table 33. General-Purpose Event Enable Register

BIT SIGNAL TYPE FUNCTION

15 ZV_EN R/W

14–12 RSVD R Reserved. These bits return 0s when read.

11 PWR_EN R/W

10–9 RSVD R Reserved. These bits return 0s when read.

8 VPP12_EN R/W

7–5 RSVD R Reserved. These bits return 0s when read.

4 GP4_EN R/W

3 GP3_EN R/W

2 GP2_EN R/W

1 GP1_EN R/W

0 GP0_EN R/W

PC card socket ZV enable. When bit 15 is set, a GPE is signaled on a change in status of ZVENABLE in the PC Card controller function of the PCI1211.

Power change event enable. When bit 11 is set, a GPE is signaled on when software has changed the power state of the socket.

12 Volt VPP request event enable. When bit 8 is set, a GPE is signaled when software has changed the requested VPP level to or from 12 Volts for the card socket.

GPI4 event enable. When bit 4 is set, a GPE is signaled when there has been a change in status of the MFUNC5 terminal input level if configured as GPI4.

GPI3 event enable. When bit 3 is set, a GPE is signaled when there has been a change in status of the MFUNC4 terminal input level if configured as GPI3.

GPI2 event enable. When bit 2 is set, a GPE is signaled when there has been a change in status of the MFUNC2 terminal input if configured as GPI2.

GPI1 event enable. When bit 1 is set, a GPE is signaled when there has been a change in status of the MFUNC1 terminal input if configured as GPI1.

GPI0 event enable. When bit 0 is set, a GPE is signaled when there has been a change in status of the MFUNC0 terminal input if configured as GPI0.

signal. The GPE signal is driven until

can be signaled

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general-purpose input register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name General-purpose input Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 X X X X X

Register: General-purpose input Type: Read-only (see individual bit descriptions) Offset: ACh Default: 00XXh Description: This register provides the logical value of the data input from the GPI terminals,

MFUNC5–MFUNC4 and MFUNC2–MFUNC0. See Table 34 for a complete description of the register contents.

Table 34. General-Purpose Input Register

BIT SIGNAL TYPE FUNCTION

15–5 RSVD R Reserved. Bits 15–5 return 0s when read. Writes have no effect.

4 GPI4_DATA R

3 GPI3_DATA R

2 GPI2_DATA R

1 GPI1_DATA R

0 GPI0_DATA R

GPI4 Data Bit. The value read from bit 4 represents the logical value of the data input from the MFUNC5 terminal. Writes have no effect.

GPI3 Data Bit. The value read from bit 3 represents the logical value of the data input from the MFUNC4 terminal. Writes have no effect.

GPI2 Data Bit. The value read from bit 2 represents the logical value of the data input from the MFUNC2 terminal. Writes have no effect.

GPI1 Data Bit. The value read from bit 1 represents the logical value of the data input from the MFUNC1 terminal. Writes have no effect.

GPI0 Data Bit. The value read from bit 0 represents the logical value of the data input from the MFUNC0 terminal. Writes have no effect.

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general-purpose output register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name General-purpose output Type R R R R R R R R R R R R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: General-purpose output Type: Read-only, Read/Write (see individual bit descriptions) Offset: AEh Default: 0000h Description: This register is used for control of the general-purpose outputs. See Table 35 for a complete

description of the register contents.

Table 35. General-Purpose Output Register

BIT SIGNAL TYPE FUNCTION

15–5 RSVD R Reserved. Bits 15–5 return 0s when read. Writes have no effect.

4 GPO4_DATA R/W

3 GPO3_DATA R/W

2 GPO2_DATA R/W

1 GPO1_DATA R/W

0 GPO0_DATA R/W

GPO4 Data Bit. The value written to bit 4 represents the logical value of the data driven to the MFUNC5 terminal if configured as GPO4. Reads return the last data value written.

GPIO3 Data Bit. The value written to bit 3 represents the logical value of the data driven to the MFUNC4 terminal if configured as GPO3. Reads return the last data value written.

GPO2 Data Bit. The value written to bit 2 represents the logical value of the data driven to the MFUNC2 terminal if configured as GPO2. Reads return the last data value written.

GPO1 Data Bit. The value written to bit 1 represents the logical value of the data driven to the MFUNC1 terminal if configured as GPO1. Reads return the last data value written.

GPO0 Data Bit. The value written to bit 0 represents the logical value of the data driven to the MFUNC0 terminal if configured as GPO0. Reads return the last data value written.

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serial bus data register

Bit 7 6 5 4 3 2 1 0 Name Serial bus data Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: Serial bus data Type: Read/Write Offset: B0h Default: 00h Description: This register is for programmable serial bus byte reads and writes. This register represents

the data when generating cycles on the serial bus interface. To write a byte, this register must be programmed with the data, the serial bus index register must be programmed with the byte address, and the serial bus slave address must be programmed with both the 7-bit slave address and the read/write indicator bit must be reset.

On byte reads, the byte address is programmed into the serial bus index register

the serial bus slave address must be programmed with both the 7-bit slave address and the read/write indicator bit must be set, and the REQBUSY bit in the serial bus control and status register must be polled until clear. Then the contents of this register are valid read data from the serial bus interface. See Table 36 for a complete description of the register contents.

Table 36. Serial Bus Data Register

BIT SIGNAL TYPE FUNCTION

7–0 SBDATA R/W

Serial bus data. This bit field represents the data byte in a read or write transaction on the serial interface. On reads, the REQBUSY bit must be polled to verify that the contents of this register are valid.

serial bus index register

Bit 7 6 5 4 3 2 1 0 Name Serial bus index Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: Serial bus index Type: Read/Write Offset: B1h Default: 00h Description: This register is for programmable serial bus byte reads and writes. This register represents

the byte address when generating cycles on the serial bus interface. To write a byte, the serial bus data register must be programmed with the data, this register must be programmed with the byte address, and the serial bus slave address must be programmed with both the 7-bit slave address and the read/write indicator.

On byte reads, the word address is programmed into this register

the serial bus slave address must be programmed with both the 7-bit slave address and the read/write indicator bit must be set, and the REQBUSY bit in the serial bus control and status register must be polled until clear. Then the contents of the serial bus data register are valid read data from the serial bus interface. See Table 37 for a complete description of the register contents.

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Table 37. Serial Bus Index Register

BIT SIGNAL TYPE FUNCTION

7–0 SBINDEX R/W

serial bus slave address register

Bit 7 6 5 4 3 2 1 0 Name Serial bus slave address Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: Serial bus slave address Type: Read/Write Offset: B2h Default: 00h Description: This register is for programmable serial bus byte read and write transactions. To write a byte,

the serial bus data register must be programmed with the data, the serial bus index register must be programmed with the byte address, and this register must be programmed with both the 7-bit slave address and the read/write indicator bit.

Serial bus index. This bit field represents the byte address in a read or write transaction on the serial interface.

On byte reads, the byte address is programmed into the serial bus index register must be programmed with both the 7-bit slave address and the read/write indicator bit must be set, and the REQBUSY bit in the serial bus control and status register must be polled until clear. Then the contents of the serial bus data register are valid read data from the serial bus interface. See Table 38 for a complete description of the register contents.

Table 38. Serial Bus Slave Address Register

BIT SIGNAL TYPE FUNCTION

7–1 SLAVADDR R/W

0 RWCMD R/W

Serial bus slave address. This bit field represents the slave address of a read or write transaction on the serial interface.

Read/write command. Bit 0 indicates the read/write command bit presented to the serial bus on byte read and write accesses

0 = A byte write access is requested to the serial bus interface 1 = A byte read access is requested to the serial bus interface

this register

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serial bus control and status register

Bit 7 6 5 4 3 2 1 0 Name Serial bus control and status Type R/W R R R R/WC R/W R/WC R/WC Default 0 0 0 0 0 0 0 0

Register: Serial bus control and status Type: Read-only, Read/Write, Read/Write to Clear (see individual bit descriptions) Offset: B3h Default: 00h Description: This register is used to communicate serial bus status information and select the quick

command protocol. The REQBUSY bit in this register must be polled during serial bus byte reads to indicate when data is valid in the serial bus data register. See Table 39 for a complete description of the register contents.

Table 39. Serial Bus Control and Status Register

BIT SIGNAL TYPE FUNCTION

Protocol select. When bit 7 is set, the send byte protocol is used on write requests and the receive byte

7 PROT_SEL R/W

6 RSVD R Reserved. Bit 6 returns 0 when read.

5 REQBUSY R

4 ROMBUSY R

3 SBDETECT R/WC

2 SBTEST R/W

1 REQ_ERR R/WC

0 ROM_ERR R/WC

protocol is used on read commands. The word address byte in the serial bus index register is not output by the PCI1211 when bit 7 is set.

Requested serial bus access busy. Bit 5 indicates that a requested serial bus access (byte read or write) is in progress. A request is made, and bit 5 is set, by writing to the serial bus slave address register. Bit 5 must be polled on reads from the serial interface. After the byte read access has been requested, the read data is valid in the serial bus data register.

Serial EEPROM Busy status. Bit 4 indicates the status of the PCI1211 serial EEPROM circuitry. Bit 4 is set during the loading of the subsystem ID and other default values from the serial bus EEPROM.

Serial bus detect. When bit 3 is set, it indicates that the serial bus interface is detected. Pullup resistors must be implemented on the MFUNC1 and MFUNC4 (SDA and SCL) terminals for bit 3 to be set. If bit 3 is reset, then the MFUNC4 and MFUNC1 terminals can be used for alternate functions such as general-purpose inputs and outputs.

Serial bus test. When bit 2 is set, the serial bus clock frequency is increased for test purposes.

Requested serial bus access error. Bit 1 indicates when a data error occurs on the serial interface during a requested cycle, and may be set due to a missing acknowledge. Bit 1 is cleared by a write back of 1.

EEPROM data error status. Bit 0 indicates when a data error occurs on the serial interface during the auto-load from the serial bus EEPROM, and may be set due to a missing acknowledge. Bit 0 is also set on invalid EEPROM data formats. Refer to format. Bit 0 is cleared by a write back of 1.

0 = Serial EEPROM circuitry is not busy 1 = Serial EEPROM circuitry is busy

0 = Serial bus interface not detected 1 = Serial bus interface detected

0 = Serial bus clock at normal operating frequency, [100 kHz (default) 1 = Serial bus clock frequency increased for test purposes

0 = No error detected during user requested byte read or write cycle 1 = Data error detected during user requested byte read or write cycle

serial bus interface

0 = No error detected during auto-load from serial bus EEPROM 1 = Data error detected during auto-load from serial bus EEPROM

on page 30 for details on EEPROM data

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ExCA compatibility registers

The exchangeable card architecture (ExCA) registers implemented in the PCI121 1 are register-compatible with the Intel 82365SL–DF PCMCIA controller. ExCA registers are identified by an offset value that is compatible with the legacy I/O index/data scheme used on the Intel 82365 ISA controller. The ExCA registers are accessed through this scheme by writing the register offset value into the index register (I/O base) and reading or writing the data register (I/O base + 1). The I/O base address used in the index/data scheme is programmed in the PC Card 16-Bit I/F legacy mode base address register. The of fsets from this base address run contiguous from 00h to 3Fh for the socket. Refer to Figure 20 for an ExCA I/O mapping illustration.

PCI1211 Configuration Registers

CardBus Socket/ExCA Base Address

Offset

10h

Host I/O Space

Index

Data

PC Card

ExCA

Registers

Offset

00h

3Fh

16-Bit Legacy-Mode Base Address

44h

Figure 20. ExCA Register Access Through I/O

The TI PCI121 1 also provides a memory mapped alias of the ExCA registers by directly mapping them into PCI memory space. They are located through the CardBus socket registers/ExCA registers base address register (PCI register 10h) at memory offset 800h. Refer to Figure 21 for an ExCA memory mapping illustration. This illustration also identifies the CardBus socket register mapping, which is mapped into the same 4K window at memory offset 0h.

Host

PCI1211 Configuration Registers

CardBus Socket/ExCA Base Address

16-Bit Legacy-Mode Base Address

10h

44h

Memory Space

CardBus

Socket

Registers

ExCA

Registers

OffsetOffset

00h

20h

800h

844h

Figure 21. ExCA Register Access Through Memory

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ExCA compatibility registers (continued)

The interrupt registers, as defined by the 82365SL–DL Specification, in the ExCA register set control such card functions as reset, type, interrupt routing, and interrupt enables. Special attention must be paid to the interrupt routing registers and the host interrupt signaling method selected for the PCI1211 to ensure that all possible PCI121 1 interrupts can potentially be routed to the programmable interrupt controller . The ExCA registers that are critical to the interrupt signaling are at memory address ExCA offset 803h and 805h.

Access to I/O mapped 16-bit PC Cards is available to the host system via two ExCA I/O windows. These are regions of host I/O address space into which the card I/O space is mapped. These windows are defined by start, end, and offset addresses programmed in the ExCA registers described in this section. I/O windows have byte granularity .

Access to memory mapped 16-bit PC Cards is available to the host system via five ExCA memory windows. These are regions of host memory space into which the card memory space is mapped. These windows are defined by start, end, and offset addresses programmed in the ExCA registers described in this section. (Table 40 identifies each ExCA register and its respective ExCA offset.) Memory windows have 4K-byte granularity.

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EXCA REGISTER NAME

ExCA OFFSET (HEX)

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Identification and revision 800 00 Interface status 801 01 Power control 802 02 Interrupt and general control 803 03 Card status change 804 04 Card status-change-interrupt configuration 805 05 Address window enable 806 06 I / O window control 807 07 I / O window 0 start-address low byte 808 08 I / O window 0 start-address high byte 809 09 I / O window 0 end-address low byte 80A 0A I / O window 0 end-address high byte 80B 0B I / O window 1 start-address low byte 80C 0C I / O window 1 start-address high byte 80D 0D I / O window 1 end-address low byte 80E 0E I / O window 1 end-address high byte 80F 0F Memory window 0 start-address low byte 810 10 Memory window 0 start-address high byte 81 1 11 Memory window 0 end-address low byte 812 12 Memory window 0 end-address high byte 813 13 Memory window 0 offset-address low byte 814 14 Memory window 0 offset-address high byte 815 15 Card detect and general control 816 16 Reserved 817 17 Memory window 1 start-address low byte 818 18 Memory window 1 start-address high byte 819 19 Memory window 1 end-address low byte 81A 1A

Memory window 1 end-address high byte 81B 1B Memory window 1 offset-address low byte 81C 1C Memory window 1 offset-address high byte 81D 1D Global control 81E 1E Reserved 81F 1F

Table 40. ExCA Registers and Offsets

PCI MEMORY ADDRESS

OFFSET (HEX)

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ExCA OFFSET (HEX)

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Table 40. ExCA Registers and Offsets (Continued)

PCI MEMORY ADDRESS

OFFSET (HEX)

Memory window 2 start-address low byte 820 20 Memory window 2 start-address high byte 821 21 Memory window 2 end-address low byte 822 22 Memory window 2 end-address high byte 823 23 Memory window 2 offset-address low byte 824 24 Memory window 2 offset-address high byte 825 25 Reserved 826 26 Reserved 827 27 Memory window 3 start-address low byte 828 28 Memory window 3 start-address high byte 829 29 Memory window 3 end-address low byte 82A 2A Memory window 3 end-address high byte 82B 2B Memory window 3 offset-address low byte 82C 2C Memory window 3 offset-address high byte 82D 2D Reserved 82E 2E Reserved 82F 2F Memory window 4 start-address low byte 830 30 Memory window 4 start-address high byte 831 31 Memory window 4 end-address low byte 832 32 Memory window 4 end-address high byte 833 33 Memory window 4 offset-address low byte 834 34 Memory window 4 offset-address high byte 835 35 I/O window 0 offset-address low byte 836 36 I/O window 0 offset-address high byte 837 37 I/O window 1 offset-address low byte 838 38 I/O window 1 offset-address high byte 839 39 Reserved 83A 3A Reserved 83B 3B Reserved 83C 3C Reserved 83D 3D Reserved 83E 3E Reserved 83F 3F Memory window page 0 840 – Memory window page 1 841 – Memory window page 2 842 – Memory window page 3 843 – Memory window page 4 844 –

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ExCA identification and revision register (index 00h)

Bit 7 6 5 4 3 2 1 0 Name ExCA identification and revision Type R R R/W R/W R/W R/W R/W R/W Default 1 0 0 0 0 1 0 0

Register: ExCA identification and revision Type: Read-only, Read/Write (see individual bit descriptions) Offset: CardBus socket address + 800h; ExCA offset 00h Default: 84h Description: This register provides host software with information on 16-bit PC Card support and Intel

82365SL-DF compatibility . See Table 41 for a complete description of the register contents.

Table 41. ExCA Identification and Revision Register (Index 00h)

BIT SIGNAL TYPE FUNCTION

7–6 IFTYPE R 5–4 RSVD R/W Reserved. Bits 5–4 can be used for Intel 82365SL-DF emulation.

3–0 365REV R/W

Interface type. These bits, which are hardwired as 10b, identify the 16-bit PC Card support provided by the PCI1211. The PCI1211 supports both I/O and memory 16-bit PC cards.

Intel 82365SL-DF revision. This field stores the Intel 82365SL-DF revision supported by the PCI121 1. Host software can read this field to determine compatibility to the Intel to 0100b upon PCI1211 reset.

82365SL-DF register set. This field defaults

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ExCA interface status register (index 01h)

Bit 7 6 5 4 3 2 1 0 Name ExCA interface status Type R R R R R R R R Default 0 0 X X X X X X

Register: ExCA interface status Type: Read-only (see individual bit descriptions) Offset: CardBus socket address + 801h; ExCA offset 01h Default: 00XX XXXXb Description: This register provides information on the current status of the PC Card interface. An X in the

default bit value indicates that the value of the bit after reset depends on the state of the PC Card interface. See Table 42 for a complete description of the register contents.

Table 42. ExCA Interface Status Register (Index 01h)

BIT SIGNAL TYPE FUNCTION

7 RSVD R Reserved. Bit 7 returns 0 when read. Writes have no effect.

Card Power. Bit 6 indicates the current power status of the PC Card socket. This bit reflects how the power

6 CARDPWR R

5 READY R

4 CARDWP R

3 CDETECT2 R

2 CDETECT1 R

1–0 BVDSTAT R

control register is programmed. Bit 6 is encoded as:

Ready. Bit 5 indicates the current status of the READY signal at the PC Card interface.

Card write protect. Bit 4 indicates the current status of WP at the PC Card interface. This signal reports to the PCI1211 whether or not the memory card is write protected. Furthermore, write protection for an entire PCI1211 16-bit memory window is available by setting the appropriate bit in the memory window offset high-byte register.

Card detect 2. Bit 3 indicates the status of CD2 at the PC Card interface. Software may use this and CDETECT1 to determine if a PC Card is fully seated in the socket.

Card detect 1. Bit 2 indicates the status of CD1 at the PC Card interface. Software may use this and CDETECT2 to determine if a PC Card is fully seated in the socket.

Battery voltage detect. When a 16-bit memory card is inserted, the field indicates the status of the battery voltage detect signals (BVD1, BVD2) at the PC Card interface, where bit 1 reflects the BVD2 status and bit 0 reflects BVD1.

When a 16-bit I/O card is inserted, this field indicates the status of SPKR the PC Card interface. In this case, the two bits in this field directly reflect the current state of these card outputs.

0 = VCC and VPP to the socket turned off (default) 1 = VCC and VPP to the socket turned on

0 = PC Card not ready for data transfer 1 = PC Card ready for data transfer

0 = WP is 0. PC Card is R/W. 1 = WP is 1. PC Card is read-only.

0 = CD2 is 1. No PC Card is inserted. 1 = CD2 is 0. PC Card is at least partially inserted.

0 = CD1 is 1. No PC Card is inserted. 1 = CD1 is 0. PC Card is at least partially inserted.

00 = Battery dead 01 = Battery dead 10 = Battery low; warning 11 = Battery good

(bit 1) and STSCHG (bit 0) at

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ExCA power-control register (index 02h)

Bit 7 6 5 4 3 2 1 0 Name ExCA power control Type R/W R R R/W R/W R R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA power control Type: Read-only, Read/Write (see individual bit descriptions) Offset: CardBus socket address + 802h; ExCA offset 02h Default: 00h Description: This register provides PC Card power control. Bit 7 of this register controls the 16-bit output

enables on the socket interface, and can be used for power management in 16-bit PC Card applications. See Table 43 for a complete description of the register contents.

Table 43. ExCA Power-Control Register (Index 02h)

BIT SIGNAL TYPE FUNCTION

Card output enable. Bit 7 controls the state of all of the 16-bit outputs on the PCI1211. This bit is encoded as:

7 COE R/W

6–5 RSVD R Reserved. Bits 6–5 return 0s when read. Writes have no effect.

VCC. Bits 4–3 are used to request changes to card VCC. This field is encoded as:

4–3 EXCAVCC R/W

2 RSVD R Reserved. Bit 2 returns 0 when read. Writes have no effect.

VPP. Bits 1–0 are used to request changes to card VPP. The PCI1211 ignores this field unless VCC to the socket is enabled (i.e., 5 V or 3.3 V). This field is encoded as:

1–0 EXCAVPP R/W

0 = 16-bit PC Card outputs disabled (default) 1 = 16-bit PC Card outputs enabled

00 = 0 V (default) 01 = 0 V reserved 10 = 5 V 11 = 3 V

00 = 0 V (default) 01 = V

10 = 12 V 11 = 0 V reserved

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ExCA interrupt and general-control register (index 03h)

Bit 7 6 5 4 3 2 1 0 Name ExCA interrupt and general control Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA interrupt and general control Type: Read/Write (see individual bit descriptions) Offset: CardBus socket address + 803h; ExCA offset 03h Default: 00h Description: This register controls interrupt routing for I/O interrupts, as well as other critical 16-bit

PC Card functions. See Table 44 for a complete description of the register contents.

Table 44. ExCA Interrupt and General-Control Register (Index 03h)

BIT SIGNAL TYPE FUNCTION

7 RINGEN R/W

6 RESET R/W

5 CARDTYPE R/W

4 CSCROUTE R/W

3–0 INTSELECT R/W

Card ring indicate enable. Bit 7 enables the ring indicate function of BVD1/RI. This bit is encoded as:

Card reset. Bit 6 controls the 16-bit PC Card RESET, and allows host software to force a card reset. Bit 6 affects 16-bit cards only. This bit is encoded as

Card type. Bit 5 indicates the PC card type. This bit is encoded as:

PCI Interrupt CSC routing enable bit. When bit 4 is set (high), the card status change interrupts are routed to PCI interrupts. When low, the card status change interrupts are routed using bits 7–4 in the ExCA card status change interrupt configuration register. This bit is encoded as:

Card interrupt select for I/O PC Card functional interrupts. Bits 3–0 select the interrupt routing for I/O PC Card functional interrupts. This field is encoded as:

0 = Ring indicate disabled (default) 1 = Ring indicate enabled

0 = RESET signal asserted (default) 1 = RESET signal deasserted

0 = Memory PC Card installed (default) 1 = I/O PC Card installed

0 = CSC interrupts are routed by ExCA registers (default). 1 = CSC interrupts are routed to PCI interrupts.

0000 = No interrupt routing (default). CSC interrupts routed to PCI interrupts. This bit setting

is OR’ed with ExCA bit 4 for backwards compatibility. 0001 = IRQ1 enabled 0010 = SMI enabled 0011 = IRQ3 enabled 0100 = IRQ4 enabled 0101 = IRQ5 enabled 0100 = IRQ6 enabled 0111 = IRQ7 enabled 1000 = IRQ8 enabled 1001 = IRQ9 enabled 1010 = IRQ10 enabled 1011 = IRQ11 enabled 1100 = IRQ12 enabled 1101 = IRQ13 enabled 1110 = IRQ14 enabled 1111 = IRQ15 enabled

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ExCA card status-change register (index 04h)

Bit 7 6 5 4 3 2 1 0 Name ExCA card status change Type R R R R R R R R Default 0 0 0 0 0 0 0 0

Register: ExCA card status change Type: Read-only (see individual bit descriptions) Offset: CardBus socket address + 804h; ExCA offset 04h Default: 00h Description: This register controls interrupt routing for I/O interrupts as well as other critical 16–bit PC Card

functions. This register reflects the status of PC Card CSC interrupt sources. The card status change interrupt register enables these interrupt sources to generate an interrupt to the host. When the interrupt source is disabled, the corresponding bit in this register always reads 0. When an interrupt source is enabled and that particular event occurs, the corresponding bit in this register is set to indicate that the interrupt source is active. After generating the interrupt to the host, the interrupt service routine must read this register to determine the source of the interrupt. The interrupt service routine is responsible for resetting the bits in this register as well. Resetting a bit is accomplished by one of two methods: a read of this register or an explicit write back of 1 to the status bit. The choice of these two methods is based on the interrupt flag clear mode select, bit 2, in the global control register. See Table 45 for a complete description of the register contents.

Table 45. ExCA Card Status-Change Register (Index 04h)

BIT SIGNAL TYPE FUNCTION

7–4 RSVD R Reserved. Bits 7–4 return 0s when read. Writes have no effect.

Card detect change. Bit 3 indicates whether a change on CD1 or CD2 occurred at the PC Card

3 CDCHANGE R

2 READYCHANGE R

1 BATWARN R

0 BATDEAD R

interface. This bit is encoded as:

0 = No change detected on either CD1 or CD2 1 = Change detected on either CD1 or CD2

Ready change. When a 16-bit memory is installed in the socket, bit 2 includes whether the source of a PCI1211 interrupt was due to a change on READY at the PC Card interface, indicating that the PC Card is now ready to accept new data. This bit is encoded as:

0 = No low-to-high transition detected on READY (default)

1 = Detected low-to-high transition on READY When a 16-bit I/O card is installed, bit 2 is always 0. Battery warning change. When a 16-bit memory card is installed in the socket, bit 1 indicates whether

the source of a PCI1211 interrupt was due to a battery-low warning condition. This bit is encoded as:

0 = No battery warning condition (default)

1 = Detected battery warning condition When a 16-bit I/O card is installed, bit 1 is always 0. Battery dead or status change. When a 16-bit memory card is installed in the socket, bit 0 indicates

whether the source of a PCI121 1 interrupt was due to a battery dead condition. This bit is encoded as:

0 = STSCHG deasserted (default)

1 = STSCHG asserted Ring indicate. When the PCI1211 is configured for ring indicate operation, bit 0 indicates the status

of RI.

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ExCA card status-change-interrupt configuration register (index 05h)

Bit 7 6 5 4 3 2 1 0 Name ExCA status-change-interrupt configuration Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA card status-change-interrupt configuration Type: Read/Write (see individual bit descriptions) Offset: CardBus socket address + 805h; ExCA offset 05h Default: 00h Description: This register controls interrupt routing for card status-change interrupts, as well as masking

CSC interrupt sources. See Table 46 for a complete description of the register contents.

Table 46. ExCA Card Status-Change-Interrupt Configuration Register (Index 05h)

BIT SIGNAL TYPE FUNCTION

Interrupt select for card status change. Bits 7–4 select the interrupt routing for card status change interrupts. 0000 = CSC interrupts routed to PCI interrupts if bit 5 of the diagnostic register (PCI Offset 93h) is set to 1b. In this case bit 4 of ExCA 803 is a “don’t care”. This is the default setting. 0000 = No ISA interrupt routing if bit 5 of the diagnostic register (PCI Offset 93h) is set to 0b. In this case,

7–4 CSCSELECT R/W

3 CDEN R/W

2 READYEN R/W

1 BATWARNEN R/W

0 BATDEADEN R/W

CSC interrupts are routed to PCI interrupts by setting bit 4 of ExCA 803 to 1b. This field is encoded as:

Card detect enable. Bit 3 enables interrupts on CD1 or CD2 changes. This bit is encoded as:

Ready enable. Bit 2 enables/disables a low-to-high transition on PC Card READY to generate a host interrupt. This interrupt source is considered a card status change. This bit is encoded as:

Battery Warning Enable. Bit 1 enables/disables a battery warning condition to generate a CSC interrupt. This bit is encoded as:

Battery dead enable. Bit 0 enables/disables a battery dead condition on a memory PC Card or assertion of the STSCHG I/O PC Card signal to generate a CSC interrupt.

0000 = No interrupt routing (default) 0001 = IRQ1 enabled 0010 = SMI enabled 0011 = IRQ3 enabled 0100 = IRQ4 enabled 0101 = IRQ5 enabled 0110 = IRQ6 enabled 0111 = IRQ7 enabled 1000 = IRQ8 enabled 1001 = IRQ9 enabled 1010 = IRQ10 enabled 1011 = IRQ11 enabled 1100 = IRQ12 enabled 1101 = IRQ13 enabled 1110 = IRQ14 enabled 1111 = IRQ15 enabled

0 = Disables interrupts on CD1 or CD2 line changes (default) 1 = Enables interrupts on CD1 or CD2 line changes

0 = Disables host interrupt generation (default) 1 = Enables host interrupt generation

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ExCA address window enable register (index 06h)

Bit 7 6 5 4 3 2 1 0 Name ExCA address window enable Type R/W R/W R R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA address window enable Type: Read-only, Read/Write (see individual bit descriptions) Offset: CardBus socket address + 806h; ExCA offset 06h Default: 00h Description: This register enables/disables the memory and I/O windows to the 16-bit PC Card. By default,

all windows to the card are disabled. The PCI121 1 does not acknowledge PCI memory or I/O cycles to the card if the corresponding enable bit in this register is 0, regardless of the programming of the memory or I/O window start/end/offset address registers. See Table 47 for a complete description of the register contents.

Table 47. ExCA Address Window Enable Register (Index 06h)

BIT SIGNAL TYPE FUNCTION

I/O window 1 enable. Bit 7 enables/disables I/O window 1 for the card. This bit is encoded as:

7 IOWIN1EN R/W

I/O window 0 enable. Bit 6 enables/disables I/O window 0 for the card. This bit is encoded as:

6 IOWIN0EN R/W

5 RSVD R Reserved. Bit 5 returns 0 when read. Writes have no effect.

Memory window 4 enable. Bit 4 enables/disables memory window 4 for the card. This bit is encoded as:

4 MEMWIN4EN R/W

Memory window 3 enable. Bit 3 enables/disables memory window 3 for the card. This bit is encoded as:

3 MEMWIN3EN R/W

Memory window 2 enable. Bit 2 enables/disables memory window 2 for the card. This bit is encoded as:

2 MEMWIN2EN R/W

Memory window 1 enable. Bit 1 enables/disables memory window 1 for the card. This bit is encoded as:

1 MEMWIN1EN R/W

Memory window 0 enable. Bit 0 enables/disables memory window 0 for the card. This bit is encoded as:

0 MEMWIN0EN R/W

0 = I/O window 1 disabled (default) 1 = I/O window 1 enabled

0 = I/O window 0 disabled (default) 1 = I/O window 0 enabled

0 = Memory window 4 disabled (default) 1 = Memory window 4 enabled

0 = Memory window 3 disabled (default) 1 = Memory window 3 enabled

0 = Memory window 2 disabled (default) 1 = Memory window 2 enabled

0 = Memory window 1 disabled (default) 1 = Memory window 1 enabled

0 = Memory window 0 disabled (default) 1 = Memory window 0 enabled

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ExCA I/O window control register (index 07h)

Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window control Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA I/O window control Type: Read/Write (see individual bit descriptions) Offset: CardBus socket address + 807h; ExCA offset 07h Default: 00h Description: This register contains parameters related to I/O window sizing and cycle timing. See Table 48

for a complete description of the register contents.

Table 48. ExCA

BIT SIGNAL TYPE FUNCTION

I/O window 1 wait state. Bit 7 controls the I/O window 1 wait state for 16-bit I/O accesses. Bit 7 has no effect on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel

7 WAITSTATE1 R/W

6 ZEROWS1 R/W

5 IOSIS16W1 R/W

4 DATASIZE1 R/W

3 WAITSTATE0 R/W

2 ZEROWS0 R/W

1 IOSIS16W0 R/W

0 DATASIZE0 R/W

This bit is encoded as:

I/O window 1 zero wait state. Bit 6 controls the I/O window 1 wait state for 8-bit I/O accesses. Bit 6 has no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as:

I/O window 1 IOIS16 source. Bit 5 controls the I/O window automatic data sizing feature that uses IOIS16 from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as:

I/O window 1 data size. Bit 4 controls the I/O window 1 data size. Bit 4 is ignored if the I/O window 1 IOIS16

I/O window 0 wait state. Bit 3 controls the I/O window 0 wait state for 16-bit I/O accesses. Bit 3 has no effect on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel This bit is encoded as:

I/O window 0 zero wait state. Bit 2 controls the I/O window 0 wait state for 8-bit I/O accesses. Bit 2 has no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as:

I/O window 0 IOIS16 source. Bit 1 controls the I/O window 0 automatic data sizing feature that uses IOIS16

I/O window 0 data size. Bit 0 controls the I/O window 0 data size. Bit 0 is ignored if the I/O window 0 IOIS16

I/O Window Control Register (Index 07h)

0 = 16-bit cycles have standard length (default). 1 = 16-bit cycles are extended by one equivalent ISA wait state.

0 = 8-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles.

0 = Window data width determined by DATASIZE1, bit 4 (default). 1 = Window data width determined by IOIS16

source bit (bit 5) is set. This bit is encoded as:

0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits.

0 = 16-bit cycles have standard length (default). 1 = 16-bit cycles are extended by one equivalent ISA wait state.

0 = 8-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles.

from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as:

0 = Window data width is determined by DATASIZE0, bit 0 (default). 1 = Window data width is determined by IOIS16

source bit (bit 1) is set. This bit is encoded as:

0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits.

82365SL-DF .

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ExCA I/O window 0 and 1 start-address low-byte register (index 08h, 0Ch)

Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 and 1 start-address low byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA I/O window 0 start-address low byte Offset: CardBus socket address + 808h; ExCA offset 08h Register: ExCA I/O window 1 start-address low byte Offset: CardBus socket address + 80Ch; ExCA offset 0Ch Type: Read/Write Default: 00h Size: One byte Description: These registers contain the low byte of the 16-bit I/O window start address for I/O windows 0

and 1. The eight bits of these registers correspond to the lower eight bits of the start address.

ExCA I/O window 0 and 1 start-address high-byte register (index 09h, 0Dh)

Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 and 1 start-address high byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA I/O window 0 start-address high byte Offset: CardBus socket address + 809h; ExCA offset 09h Register: ExCA I/O window 1 start-address high byte Offset: CardBus socket address + 80Dh; ExCA offset 0Dh Type: Read/Write Default: 00h Size: One byte Description: These registers contain the high byte of the 16-bit I/O window start address for I/O windows 0

and 1. The eight bits of these registers correspond to the upper eight bits of the end address.

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ExCA I/O window 0 and 1 end-address low-byte register (index 0Ah, 0Eh)

Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 and 1 end-address low byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA I/O window 0 end-address low byte Offset: CardBus socket address + 80Ah; ExCA offset 0Ah Register: ExCA Offset: CardBus socket address + 80Eh; ExCA offset 0Eh Type: Read/Write Default: 00h Size: One byte Description: These registers contain the low byte of the 16-bit I/O window end address for I/O windows 0

and 1. The eight bits of these registers correspond to the lower eight bits of the end address.

ExCA I/O window 0 and 1 end-address high-byte register (index 0Bh, 0Fh)

Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 and 1 end-address high byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

I/O window 1 end-address low byte

I/O window 1 end-address high byte

Offset: CardBus socket address + 80Fh; ExCA offset 0Fh Type: Read/Write Default: 00h Size: One byte Description: These registers contain the high byte of the 16-bit I/O window end address for I/O windows 0

and 1. The eight bits of these registers correspond to the upper eight bits of the end address.

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ExCA memory window 0–4 start-address low-byte register (index 10h, 18h, 20h, 28h, 30h)

Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 start-address low byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA memory window 0 start-address low byte Offset: CardBus socket address + 810h; ExCA offset 10h Register: ExCA memory window 1 start-address low byte Offset: CardBus socket address + 818h; ExCA offset 18h Register: ExCA memory window 2 start-address low byte Offset: CardBus socket address + 820h; ExCA offset 20h

Register: ExCA memory window 3 start-address low byte Offset: CardBus socket address + 828h; ExCA offset 28h Register: ExCA memory window 4 start-address low byte Offset: CardBus socket address + 830h; ExCA offset 30h Type: Read/Write Default: 00h Size: One byte Description: These registers contain the low byte of the 16-bit memory window start address for memory

windows 0, 1, 2, 3, and 4. The eight bits of these registers correspond to bits A19–A12 of the start address.

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ExCA memory window 0–4 start-address high-byte register (index 11h, 19h, 21h, 29h, 31h)

Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 start-address high byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA memory window 0 start-address high byte Offset: CardBus socket address + 811h; ExCA offset 11h Register: ExCA memory window 1 start-address high byte Offset: CardBus socket address + 819h; ExCA offset 19h Register: ExCA memory window 2 start-address high byte Offset: CardBus socket address + 821h; ExCA offset 21h Register: ExCA memory window 3 start-address high byte Offset: CardBus socket address + 829h; ExCA offset 29h Register: ExCA memory window 4 start-address high byte Offset: CardBus socket address + 831h; ExCA offset 31h Type: Read/Write Default: 00h Size: One byte Description: These registers contain the high nibble of the 16-bit memory window start address for memory

windows 0, 1, 2, 3, and 4. The lower four bits of these registers correspond to bits A23–A20 of the start address. In addition, the memory window data width and wait states are set in this register. See Table 49 for a complete description of the register contents.

Table 49. ExCA Memory Window 0–4 Start-Address High-Byte Register (Index 11h, 19h, 21h, 29h, 31h)

BIT SIGNAL TYPE FUNCTION

Data size. Bit 7 controls the memory window data width. This bit is encoded as:

7 DATASIZE R/W

Zero wait state. Bit 6 controls the memory window wait state for 8- and 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel

6 ZEROWAIT R/W

5–4 SCRATCH R/W Scratch pad bits. Bits 5–4 have no effect on memory window operation. 3–0 STAHN R/W

Start-address high nibble. Bits 3–0 represent the upper address bits A23–A20 of the memory window start address.

0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits.

82365SL-DF. This bit is encoded as:

0 = 8- and 16-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles.

16-bit cycles are reduced to equivalent of two ISA cycles.

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ExCA memory window 0–4 end-address low-byte register (index 12h, 1Ah, 22h, 2Ah, 32h)

Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 end-address low byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA memory window 0 end-address low byte Offset: CardBus socket address + 812h; ExCA offset 12h Register: ExCA memory window 1 end-address low byte Offset: CardBus socket address + 81Ah; ExCA offset 1Ah Register: ExCA memory window 2 end-address low byte Offset: CardBus socket address + 822h; ExCA offset 22h Register: ExCA memory window 3 end-address low byte Offset: CardBus socket address + 82Ah; ExCA offset 2Ah Register: ExCA memory window 4 end-address low byte Offset: CardBus socket address + 832h; ExCA offset 32h Type: Read/Write Default: 00h Size: One byte Description: These registers contain the low byte of the 16-bit memory window end address for memory

windows 0, 1, 2, 3, and 4. The eight bits of these registers correspond to bits A19–A12 of the end address.

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ExCA memory window 0–4 end-address high-byte register (index 13h, 1Bh, 23h, 2Bh, 33h)

Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 end-address high byte Type R/W R/W R R R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA memory window 0 end-address high byte Offset: CardBus socket address + 813h; ExCA offset 13h Register: ExCA memory window 1 end-address high byte Offset: CardBus socket address + 81Bh; ExCA offset 1Bh Register: ExCA memory window 2 end-address high byte Offset: CardBus socket address + 823h; ExCA offset 23h Register: ExCA memory window 3 end-address high byte Offset: CardBus socket address + 82Bh; ExCA offset 2Bh Register: ExCA memory window 4 end-address high byte Offset: CardBus socket address + 833h; ExCA offset 33h Type: Read-only, Read/Write (see individual bit descriptions) Default: 00h Size: One byte Description: These registers contain the high nibble of the 16-bit memory window end address for memory

windows 0, 1, 2, 3, and 4. The lower four bits of these registers correspond to bits A23–A20 of the end address. In addition, the memory window wait states are set in this register. See Table 50 for a complete description of the register contents.

Table 50. ExCA Memory Window 0–4 End-Address High-Byte Register (Index 13h, 1Bh, 23h, 2Bh, 33h)

BIT SIGNAL TYPE FUNCTION

7–6 MEMWS R/W 5–4 RSVD R Reserved. Bits 5–4 return 0s when read. Writes have no effect. 3–0 ENDHN R/W

Wait state. Bits 7–6 specify the number of equivalent ISA wait states to be added to 16-bit memory accesses. The number of wait states added is equal to the binary value of these two bits.

End-address high nibble. Bits 3–0 represent the upper address bits A23–A20 of the memory window end address.

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ExCA memory window 0–4 offset-address low-byte register (index 14h, 1Ch, 24h, 2Ch, 34h)

Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 offset-address low byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA memory window 0 offset-address low byte Offset: CardBus socket address + 814h; ExCA offset 14h Register: ExCA memory window 1 offset-address low byte Offset: CardBus socket address + 81Ch; ExCA offset 1Ch Register: ExCA memory window 2 offset-address low byte Offset: CardBus socket address + 824h; ExCA offset 24h Register: ExCA memory window 3 offset-address low byte Offset: CardBus socket address + 82Ch; ExCA offset 2Ch Register: ExCA memory window 4 offset-address low byte Offset: CardBus socket address + 834h; ExCA offset 34h Type: Read/Write Default: 00h Size: One byte Description: These registers contain the low byte of the 16-bit memory window offset address for memory

windows 0, 1, 2, 3 and 4. The eight bits of these registers correspond to bits A19–A12 of the offset address.

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ExCA memory window 0–4 offset-address high-byte register (index 15h, 1Dh, 25h, 2Dh, 35h)

Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 offset-address high byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA memory window 0 offset-address high byte Offset: CardBus socket address + 815h; ExCA offset 15h Register: ExCA memory window 1 offset-address high byte Offset: CardBus socket address + 81Dh; ExCA offset 1Dh Register: ExCA memory window 2 offset-address high byte Offset: CardBus socket address + 825h; ExCA offset 25h Register: ExCA memory window 3 offset-address high byte Offset: CardBus socket address + 82Dh; ExCA offset 2Dh Register: ExCA memory window 4 offset-address high byte Offset: CardBus socket address + 835h; ExCA offset 35h Type: Read/Write (see individual bit descriptions) Default: 00h Size: One byte Description: These registers contain the high six bits of the 16-bit memory window offset address for

memory windows 0, 1, 2, 3 and 4. The lower six bits of these registers correspond to bits A25–A20 of the offset address. In addition, the write protection and common/attribute memory configurations are set in this register. See Table 51 for a complete description of the register contents.

Table 51. ExCA Memory Window 0–4 Offset-Address High-Byte Register (Index 15h, 1Dh, 25h, 2Dh, 35h)

BIT SIGNAL TYPE FUNCTION

Write protect. Bit 7 specifies whether write operations to this memory window are enabled. This bit is

7 WINWP R/W

6 REG R/W

5–0 OFFHB R/W

encoded as:

0 = Write operations are allowed (default). 1 = Write operations are not allowed.

Bit 6 specifies whether this memory window is mapped to card attribute or common memory. This bit is encoded as:

0 = Memory window is mapped to common memory (default). 1 = Memory window is mapped to attribute memory.

Offset-address high byte. Bits 5–0 represent the upper address bits A25–A20 of the memory window offset address.

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ExCA I/O window 0 and 1 offset-address low-byte register (index 36h, 38h)

Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 and 1 offset-address low byte Type R/W R/W R/W R/W R/W R/W R/W R Default 0 0 0 0 0 0 0 0

Register: ExCA I/O window 0 offset-address low byte Offset: CardBus socket address + 836h; ExCA offset 36h Register: ExCA I/O window 1 offset-address low byte Offset: CardBus socket address + 838h; ExCA offset 38h Type: Read-only, Read/Write (see description) Default: 00h Size: One byte Description: These registers contain the low byte of the 16-bit I/O window offset address for I/O windows 0

and 1. The eight bits of these registers correspond to the lower eight bits of the offset address, and bit 0 is always 0.

ExCA I/O window 0 and 1 offset-address high-byte register (index 37h, 39h)

Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 and 1 offset-address high byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA I/O window 0 offset-address high byte Offset: CardBus socket address + 837h; ExCA offset 37h Register: ExCA I/O window 1 offset-address high byte Offset: CardBus socket address + 839h; ExCA offset 39h Type: Read/Write Default: 00h Size: One byte Description: These registers contain the high byte of the 16-bit I/O window offset address for I/O windows 0

and 1. The eight bits of these registers correspond to the upper eight bits of the offset address.

100

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