Texas Instruments PCI1211GGU, PCI1211PGE Datasheet

D

PC 98/99 Compliant

D

PCI Bus Power Management Interface
Specification 1.0 Compliant

D

Advanced Configuration and Power
Interface (ACPI) 1.0 Compliant

D

Fully Compatible With the Intel 430TX
(Mobile Triton II) Chipset

D

PCI Local Bus Specification Revision 2.2
Compliant

D

1997 PC Card Standard Compliant

D

3.3-V Core Logic With Universal PCI
Interfaces Compatible With 3.3-V and 5-V
PCI Signaling Environments

D

Mix-and-Match 5-V/3.3-V PC Card16 Cards
and 3.3-V CardBus Cards

D

Supports a Single PC Card or CardBus Slot
With Hot Insertion and Removal

D

Provides Interface to Parallel Single-Slot
PC Card Power-Interface Switches like the
TI TPS2211

D

Supports Burst Transfers to Maximize Data
Throughput on the PCI Bus and the
CardBus Bus

D

Supports Parallel PCI Interrupts, Parallel
ISA IRQ and Parallel PCI Interrupts, Serial
ISA IRQ With Parallel PCI Interrupts, and
Serial ISA IRQ and PCI Interrupts

D

Pin-to-Pin Compatible with PCI1210

D

Serial EEPROM Interface for Loading
Subsystem ID and Subsystem Vendor ID

PCI1211 GGU/PGE

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

D

Pipelined Architecture Allows Greater Than
130M-Bytes-Per-Second Throughput From
CardBus to PCI and From PCI to CardBus

D

Supports Up to Five General-Purpose I/Os

D

Five PCI Memory Windows and Two I/O
Windows Available to the PC Card16
Socket

D

Two I/O Windows and Two Memory
Windows Available to the CardBus Socket

D

Exchangeable Card Architecture (ExCA)
Compatible Registers Are Mapped in
Memory and I/O Space

D

Intel 82365SL-DF Register Compatible

D

Supports Distributed DMA (DDMA) and
PC/PCI DMA

D

Supports 16-Bit DMA on the PC Card
Socket

D

Supports Ring Indicate, SUSPEND, PCI
CLKRUN

D

Supports PCI Bus Lock (LOCK)

D

LED Activity Pin

D

Advanced Submicron, Low-Power CMOS
T echnology

D

Choice of Surface-Mount Packaging:
– PGE Low-Profile Plastic Quad Flat

Package (LQFP)

– GGU High Density Ball Grid Array (BGA)

, and CardBus CCLKRUN

Table of Contents

Description 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System Block Diagram 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Terminal Assignments 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signal Name/Terminal Assignments 6. . . . . . . . . . . . . . . . . . . . . . .

Terminal Functions 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Supply Sequencing 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O Characteristics 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clamping Voltages 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peripheral Component Interconnect (PCI) Interface 22. . . . . . . .

PC Card Applications 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial Bus Interface 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Programmable Interrupt Subsystem 34. . . . . . . . . . . . . . . . . . . . . .

Power Management Overview 38. . . . . . . . . . . . . . . . . . . . . . . . . .

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Intel is a trademark of Intel Corporation.
PC Card is a trademark of Personal Computer Memory Card International Association (PCMCIA).
TI is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PC Card Controller Programming Model 43. . . . . . . . . . . . . . . . . . . . .

PCI Configuration Registers 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ExCA Compatibility Registers 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CardBus Socket Registers 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Distributed DMA (DDMA) Registers 112. . . . . . . . . . . . . . . . . . . . . . . .

Absolute Maximum Ratings 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Recommended Operating Conditions 119. . . . . . . . . . . . . . . . . . . . . .

Electrical Characteristics 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCI Clock/Reset Timing Requirements 121. . . . . . . . . . . . . . . . . . . . .

PCI Timing Requirements 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parameter Measurement Information 122. . . . . . . . . . . . . . . . . . . . . . .

PCI Bus Parameter Measurement Information 123. . . . . . . . . . . . . . .

Mechanical Data 128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Copyright  1998, Texas Instruments Incorporated

1

PCI1211 GGU/PGE
PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

description

The Texas Instruments PCI1211 is a high-performance PCI-to-PC Card controller that supports a single PC
Card socket compliant with the 1995 PC Card Standard. The PCI1211 provides a rich feature set that makes
it the best choice for bridging between PCI and PC Cards in both notebook and desktop computers. The 1997
PC Card Standard retains the 16-bit PC Card specification defined in PCMCIA Release 2.2, and defines the
new 32-bit PC Card, CardBus, capable of full 32-bit data transfers at 33 MHz. The PCI121 1 supports both 16-bit
and CardBus PC Cards, powered at 5 V or 3.3 V, as required.

The PCI121 1 is compliant with the
either a PCI master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card direct
memory access (DMA) transfers or CardBus PC Card bridging transactions. The PCI121 1 is also compliant with
the latest

All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI121 1
is register compatible with the Intel 82365SL-DF ExCA controller. The PCI1211 internal data path logic allows
the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent
buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The
PCI1211 can also be programmed to accept fast posted writes to improve system-bus utilization.

Multiple system-interrupt signaling options are provided, including: parallel PCI, parallel ISA, serialized ISA, and
serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to
implement sideband functions. Many other features are designed into the PCI1211, such as socket activity
light-emitting diode (LED) output, that are discussed in detail throughout the design specification.

An advanced complementary metal-oxide semiconductor (CMOS) process achieves low system-power
consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power
management system to further reduce power consumption.

Unused PCI1211 inputs must be pulled up using a 43 kW resistor.

PCI Bus Power Management Interface Specification, Revision 1.0

PCI Local Bus Specification, Revision 2.2

, and its PCI interface can act as

.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1211 GGU/PGE

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

system block diagram

A simplified system block diagram using the PCI1211 is provided below. The PCI950 IRQ deserializer and the
PCI930 zoomed video (ZV) switch are optional functions that can be used when the system requires that
capability.

The PCI interface includes all address/data and control signals for PCI protocol. The 68-pin PC Card interface
includes all address/data and control signals for CardBus and 16-bit (R2) protocols. When ZV is enabled (in
16-bit PC Card mode) 23 of the 68 signals are redefined to support the ZV protocol.

The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling.
Other miscellaneous system interface terminals are available on the PCI1211 that include:

D

Programmable multifunction terminals

D

SUSPEND, RI_OUT/PME (power management control signal)

D

SPKROUT

PCI Bus

INTA

Activity LED

Interrupt

Controller

TPS2211

Power

Switch

PC Card

Socket

External ZV Port

NOTE: The PC Card interface is 68 pins for CardBus and 16-bit PC Cards. In ZV mode 23 pins are used for routing the ZV signals to the VGA

controller.

4

PCI1211

68

23

IRQSER

3

PCI930

ZV Switch

PCI950

IRQSER

Deserializer

Zoom Video

19

Zoom Video

4

IRQ2–15

VGA

Controller

Audio

Sub-System

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

PCI1211 GGU/PGE
PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

terminal assignments

CTRDY

CIRDY

CFRAME

CC/BE2

CAD17

GND
CAD18
CAD19

CVS2

CAD20

CRST

CAD21
CAD22

V

CC

CREQ

CAD23

CC/BE3

V

CCCB
CAD24
CAD25

CAD26

GND

CVS1

CINT

CSERR

CAUDIO

CSTSCHG

CCLKRUN

CCD2

V

CC
CAD27
CAD28
CAD29
CAD30

RSVD

CAD31

PGE LOW-PROFILE QUAD FLAT PACKAGE

(BOTTOM VIEW)

CC

CSTOP

105

CBLOCK

CPERR

103

104

V

102

CPAR

101

RSVD

99

100

CAD14

CAD16

CC/BE1

97

98

CAD12

CAD15

95

96

GND

94

CCLK

CGNT

CDEVSEL

106

107

108
109
110

111
112
113
114
115
116
117
118
119
120
121
122

123
124

125
126

127
128
129
130

131
132
133
134
135
136
137
138
139
140
141
142
143
144

1234567891011121314151617181920212223242526272829303132333435

CAD11

CAD13

92

93

CCCB

V

CAD10

90

91

CAD9

CC/BE0

88

89

CC

V

CAD8

86

87

RSVD

CAD7

84

85

CAD6

CAD5

82

83

CAD4

CAD3

80

81

GND

CAD1

78

79

CAD2

CAD0

76

77

CCD1

74

75

VCCD0

VCCD1

73

72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37

36

VPPD1
VPPD0

SUSPEND
MFUNC6
MFUNC5
MFUNC4

V

CC

MFUNC3
MFUNC2
V

CCI

SPKROUT
MFUNC1

MFUNC0
RI_OUT/PME
GND
AD0
AD1
AD2
AD3
AD4
AD5
AD6AD6

V

CC
AD7
C/BE0
AD8

AD9
AD10
V

CCP
AD11
GND
AD12
AD13
AD14
AD15

C/BE1

REQ

GNT

AD31

AD30

GND

AD29

AD28

AD27

AD26

AD25

AD24

C/BE3

CC

V

IDSEL

AD22

AD23

AD21

V

CCP

AD20

RST

GND

PCLK

AD19

AD18

AD17

AD16

C/BE2

FRAME

V

IRDY

CC

TRDY

DEVSEL

STOP

PERR

SERR

PAR

PCI-to-CardBus Pin Diagram

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

terminal assignments (continued)

PCI1211 GGU/PGE

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

A22
A15
A23
A12

A24

GND

A7
A25
VS2

A6

RESET

V

CC

INPACK

A3

REG

V

CCCB

A2

A1

A0

GND

VS1

READY(IREQ

WAIT

BVD2(SPKR

BVD1(STSCHG/RI)

WP(IOIS16)

CD2
V

CC

D0

D8
D1
D9
D2

D10

A5
A4

PGE LOW-PROFILE QUAD FLAT PACKAGE

(BOTTOM VIEW)

CC

A20

105

A14

104

A19

103

V

102

A13

101

A18

100

GND

A11

IOWR

A9

A17

A8

94

95

96

97

98

99

A16

WE

A21

106

107

108
109
110

111
112
113
114

115
116
117
118

119
120
121
122
123
124
125
126
127
128
129
130
131
132

)

133

)

134
135
136
137

138
139
140
141

142
143
144

1234567891011121314151617181920212223242526272829303132333435

IORD

93

CCCB

V

CE2

OE

90

91

92

A10

89

CE1

88

D15

87

V

86

CC

D7

85

D14

84

D6

83

D13

82

D5

81

D12

80

D4

79

GND

78

CD1

D11

D3

VCCD0

VCCD1

73

74

75

76

77

72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53

52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37

36

VPPD1
VPPD0

SUSPEND
MFUNC6
MFUNC5
MFUNC4

V

CC

MFUNC3
MFUNC2
V

CCI

SPKROUT
MFUNC1

MFUNC0
RI_OUT/PME
GND
AD0
AD1
AD2
AD3
AD4
AD5
AD6AD6

V

CC

AD7
C/BE0
AD8
AD9
AD10
V

CCP
AD11
GND
AD12
AD13
AD14
AD15

C/BE1

REQ

GNT

AD31

AD30

GND

AD29

AD28

AD27

AD26

AD25

AD24

C/BE3

CC

V

IDSEL

AD22

AD23

AD21

V

CCP

PCI-to-PC Card (16-Bit) Diagram

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AD20

RST

GND

PCLK

AD19

AD18

AD17

AD16

C/BE2

FRAME

CC

V

IRDY

TRDY

DEVSEL

STOP

PERR

SERR

PAR

5

PCI1211 GGU/PGE
PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

terminal assignments (continued)

N

M

L

K

J

H

G

F

E

D

GGU BALL GRID ARRAY PACKAGE

PCI Signals Interrupt

P

P

P

P

P

P

P

P

P

P

P

P

P

P

P

P

P

P

P

P

P

P

P

P

P

P

P

P

P

P

P

P

P

(BOTTOM VIEW)

P

P

P

P

P

P

P

C

C

C

C

C

C

C

Power

Switch

C

C

C

C

C

C

C

and Misc.

P

P

P

P

P

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

B

A

P

P

P

1

V

CC

GND

P

C

C

C

C

CCC

C

CCC

C

C

C

CardBus Signals

5

423

Power Switch
Interrupt and Miscellaneous

C

CCC

Clamping Voltages

C

C

C

C

C

C

C

C

C

CardBus Signals

P

PCI Signals

C

C

C

C

C

C

12 1310 118967

PCI-to-CardBus and PCI-to-PC Card (16-Bit) Diagram

signal names and terminal assignments

Signal names and their terminal assignments are shown in Table 1 through Table 4. Table 1 and Table 2 show
the terminal assignments for the CardBus PC Card, and Table 3 and Table 4 show the terminal assignments
for the 16-bit PC Card. Table 2 and Table 4 show the CardBus PC Card and the 16-bit PC Card terminals sorted
alphanumerically by the signal name and its associated terminal number.

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

PCI1211 GGU/PGE

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

Table 1. CardBus PC Card Signal Names – Sorted by BGA Terminal Number

PIN NO.

GGU PGE

A1 1 REQ
A2 143 RSVD C12 105 CSTOP G11 91 CAD10 L5 46 AD9
A3 140 CAD28 C13 104 CPERR G12 89 CAD9 L6 50 V

A4 137 CCD2 D1 8 AD27 G13 90 V
A5 133 CSERR D2 7 AD28 H1 21 PCLK L8 59 RI_OUT/PME
A6 129 CAD26 D3 6 GND H2 22 GND L9 63 V
A7 126 V
A8 124 CAD23 D5 136 CCLKRUN H4 24 AD18 L11 70 SUSPEND

A9 120 CAD21 D6 132 CINT H10 85 CAD7 L12 75 CCD1
A10 116 CAD19 D7 128 CAD25 H11 86 V
A11 112 CC/BE2 D8 121 CAD22 H12 87 CAD8 M1 35 SERR
A12 110 CIRDY D9 117 CVS2 H13 88 CC/BE0 M2 36 PAR
A13 109 CTRDY D10 113 CAD17 J1 25 AD17 M3 39 AD14

B1 2 GNT D11 103 CBLOCK J2 26 AD16 M4 43 AD11

B2 144 CAD31 D12 102 V

B3 141 CAD29 D13 101 CPAR J4 28 FRAME M6 51 AD6

B4 138 V

B5 134 CAUDIO E2 11 AD24 J11 82 CAD6 M8 58 GND

B6 130 GND E3 10 AD25 J12 83 CAD5 M9 62 SPKROUT

B7 125 CC/BE3 E4 9 AD26 J13 84 RSVD M10 66 V

B8 123 CREQ E10 100 RSVD K1 29 IRDY M11 69 MFUNC6

B9 119 CRST E11 99 CC/BE1 K2 30 V
B10 115 CAD18 E12 98 CAD16 K3 31 TRDY M13 74 VCCD1
B11 111 CFRAME E13 97 CAD14 K4 41 AD12 N1 37 C/BE1
B12 108 CCLK F1 16 AD22 K5 45 AD10 N2 38 AD15
B13 107 CDEVSEL F2 15 AD23 K6 49 AD7 N3 40 AD13

C1 4 AD30 F3 14 V

C2 3 AD31 F4 13 IDSEL K8 60 MFUNC0 N5 48 C/BE0

C3 142 CAD30 F10 96 CAD15 K9 64 MFUNC2 N6 52 AD5
C4 139 CAD27 F11 95 CAD12 K10 77 CAD2 N7 54 AD3
C5 135 CSTSCHG F12 94 GND K11 78 GND N8 57 AD0
C6 131 CVS1 F13 93 CAD13 K12 79 CAD1 N9 61 MFUNC1
C7 127 CAD24 G1 18 V
C8 122 V
C9 118 CAD20 G3 19 AD20 L2 33 STOP N12 71 VPPD0

C10 114 GND G4 20 RST L3 34 PERR N13 73 VCCD0

†

The PGE (LQFP) pin numbers are shown also.

CCCB

CC

CC

PIN NO.

GGU PGE

C11 106 CGNT G10 92 CAD11 L4 42 GND

D4 5 AD29 H3 23 AD19 L10 67 MFUNC4

CC

E1 12 C/BE3 J10 81 CAD3 M7 53 AD4

CC

CCP

G2 17 AD21 L1 32 DEVSEL N11 68 MFUNC5

PIN NO.

GGU PGE

CCCB

CC

J3 27 C/BE2 M5 47 AD8

CC

K7 56 AD1 N4 44 V

K13 80 CAD4 N10 65 MFUNC3

PIN NO.

GGU PGE

L7 55 AD2

L13 76 CAD0

M12 72 VPPD1

†

CC

CCI

CC

CCP

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7

PCI1211 GGU/PGE

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

Table 2. CardBus PC Card Signal Names – Sorted Alphabetically

PIN NO.

PGE GGU

AD0 57 N8 CAD0 76 L13 CC/BE2 112 A11
AD1 56 K7 CAD1 79 K12 CC/BE3 125 B7 MFUNC3 65 N10
AD2 55 L7 CAD2 77 K10 CCLK 108 B12 MFUNC4 67 L10
AD3 54 N7 CAD3 81 J10 CCD1 75 L12 MFUNC5 68 N11
AD4 53 M7 CAD4 80 K13 CCD2 137 A4 MFUNC6 69 M11
AD5 52 N6 CAD5 83 J12 CCLKRUN 136 D5 PAR 36 M2
AD6 51 M6 CAD6 82 J11 CDEVSEL 107 B13 PCLK 21 H1
AD7 49 K6 CAD7 85 H10 CFRAME 111 B11 PERR 34 L3
AD8 47 M5 CAD8 87 H12 CGNT 106 C11 REQ 1A1
AD9 46 L5 CAD9 89 G12 CINT 132 D6 RI_OUT/PME 59 L8
AD10 45 K5 CAD10 91 G11 CIRDY 110 A12 RST 20 G4
AD11 43 M4 CAD11 92 G10 CPAR 101 D13 SERR 35 M1
AD12 41 K4 CAD12 95 F11 CPERR 104 C13 RSVD 84 E10
AD13 40 N3 CAD13 93 F13 CREQ 123 B8 RSVD 100 J13
AD14 39 M3 CAD14 97 E13 CRST 119 B9 RSVD 143 A2
AD15 38 N2 CAD15 96 F10 CSERR 133 A5 SPKROUT 62 M9
AD16 26 J2 CAD16 98 E12 CSTOP 105 C12 STOP 33 L2
AD17 25 J1 CAD17 113 D10 CSTSCHG 135 C5 SUSPEND 70 L11
AD18 24 H4 CAD18 115 B10 CTRDY 109 A13 TRDY 31 K3
AD19 23 H3 CAD19 116 A10 CVS1 131 C6 V
AD20 19 G3 CAD20 118 C9 CVS2 117 D9 V
AD21 17 G2 CAD21 120 A9 DEVSEL 32 L1 V
AD22 16 F1 CAD22 121 D8 FRAME 28 J4 V
AD23 15 F2 CAD23 124 A8 GND 6D3V
AD24 11 E2 CAD24 127 C7 GND 22 H2 V
AD25 10 E3 CAD25 128 D7 GND 42 L4 V
AD26 9 E4 CAD26 129 A6 GND 58 M8 V
AD27 8 D1 CAD27 139 C4 GND 78 K11 V
AD28 7 D2 CAD28 140 A3 GND 94 F12 V
AD29 5 D4 CAD29 141 B3 GND 114 C10 VCCD0 73 N13
AD30 4 C1 CAD30 142 C3 GND 130 B6 VCCD1 74 M13
AD31 3 C2 CAD31 144 B2 GNT 2B1V
C/BE0 48 N5 CAUDIO 134 B5 IDSEL 13 F4 V
C/BE1 37 N1 CBLOCK 103 D11 IRDY 29 K1 V
C/BE2 27 J3 CC/BE0 88 H13 MFUNC0 60 K8 VPPD0 71 N12
C/BE3 12 E1 CC/BE1 99 E11 MFUNC1 61 N9 VPPD1 72 M12

PIN NO.

PGE GGU

PIN NO.

PGE GGU

PIN NO.

PGE GGU

MFUNC2 64 K9

CC
CC
CC
CC
CC
CC
CC
CC
CCCB
CCCB

CCI
CCP
CCP

14 F3
30 K2
50 L6
66 M10

86 H11
102 D12
122 C8
138 B4

90 G13
126 A7

63 L9

18 G1

44 N4

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

PCI1211 GGU/PGE

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

Table 3. 16-Bit PC Card Signal Names – Sorted by BGA Terminal Number

PIN NO.

GGU PGE

A1 1 REQ
A2 143 D2 C12 105 A20 G11 91 CE2 L5 46 AD9
A3 140 D8 C13 104 A14 G12 89 A10 L6 50 V
A4 137 CD2 D1 8 AD27 G13 90 V
A5 133 WAIT D2 7 AD28 H1 21 PCLK L8 59 RI_OUT/PME
A6 129 A0 D3 6 GND H2 22 GND L9 63 V
A7 126 V
A8 124 A3 D5 136 WP(IOIS16)H424 AD18 L11 70 SUSPEND

A9 120 A5 D6 132 READY(IREQ) H10 85 D7 L12 75 CD1
A10 116 A25 D7 128 A1 H11 86 V
A11 112 A12 D8 121 A4 H12 87 D15 M1 35 SERR
A12 110 A15 D9 117 VS2 H13 88 CE1 M2 36 PAR
A13 109 A22 D10 113 A24 J1 25 AD17 M3 39 AD14

B1 2 GNT D11 103 A19 J2 26 AD16 M4 43 AD11

B2 144 D10 D12 102 V

B3 141 D1 D13 101 A13 J4 28 FRAME M6 51 AD6

B4 138 V

B5 134 BVD2(SPKR)E211 AD24 J11 82 D13 M8 58 GND

B6 130 GND E3 10 AD25 J12 83 D6 M9 62 SPKROUT

B7 125 REG E4 9 AD26 J13 84 D14 M10 66 V

B8 123 INPACK E10 100 A18 K1 29 IRDY M11 69 MFUNC6

B9 119 RESET E11 99 A8 K2 30 V
B10 115 A7 E12 98 A17 K3 31 TRDY M13 74 VCCD1
B11 111 A23 E13 97 A9 K4 41 AD12 N1 37 C/BE1
B12 108 A16 F1 16 AD22 K5 45 AD10 N2 38 AD15
B13 107 A21 F2 15 AD23 K6 49 AD7 N3 40 AD13

C1 4 AD30 F3 14 V
C2 3 AD31 F4 13 IDSEL K8 60 MFUNC0 N5 48 C/BE0

C3 142 D9 F10 96 IOWR K9 64 MFUNC2 N6 52 AD5

C4 139 D0 F11 95 A11 K10 77 D11 N7 54 AD3

C5 135

C6 131 VS1 F13 93 IORD K12 79 D4 N9 61 MFUNC1

C7 127 A2 G1 18 V

C8 122 V

C9 118 A6 G3 19 AD20 L2 33 STOP N12 71 VPPD0

C10 114 GND G4 20 RST L3 34 PERR N13 73 VCCD0

†

The PGE (LQFP) pin numbers are shown also.

CCCB

CC

BVD1(STSCHG/RI)

CC

PIN NO.

GGU PGE

C11 106 WE G10 92 OE L4 42 GND

D4 5 AD29 H3 23 AD19 L10 67 MFUNC4

CC

E1 12 C/BE3 J10 81 D5 M7 53 AD4

CC

F12 94 GND K11 78 GND N8 57 AD0

CCP

G2 17 AD21 L1 32 DEVSEL N11 68 MFUNC5

PIN NO.

GGU PGE

CCCB

CC

J3 27 C/BE2 M5 47 AD8

CC

K7 56 AD1 N4 44 V

K13 80 D12 N10 65 MFUNC3

PIN NO.

GGU PGE

L7 55 AD2

L13 76 D3

M12 72 VPPD1

†

CC

CCI

CC

CCP

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9

PCI1211 GGU/PGE

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

Table 4. 16-Bit PC Card Signal Names – Sorted Alphabetically

PIN NO.

PGE GGU

A0 129 A6 AD10 45 K5 D4 79 K12 PAR 36 M2
A1 128 D7 AD11 43 M4 D5 81 J10 PCLK 21 H1
A2 127 C7 AD12 41 K4 D6 83 J12 PERR 34 L3
A3 124 A8 AD13 40 N3 D7 85 H10 REQ 1A1
A4 121 D8 AD14 39 M3 D8 140 A3 READY(IREQ) 132 D6
A5 120 A9 AD15 38 N2 D9 142 C3 REG 125 B7
A6 118 C9 AD16 26 J2 D10 144 B2 RESET 119 B9
A7 115 B10 AD17 25 J1 D11 77 K10 RI_OUT/PME 59 L8
A8 99 E11 AD18 24 H4 D12 80 K13 RST 20 G4
A9 97 E13 AD19 23 H3 D13 82 J1 1 SERR 35 M1
A10 89 G12 AD20 19 G3 D14 84 J13 SPKROUT 62 M9
A11 95 F11 AD21 17 G2 D15 87 H12 STOP 33 L2
A12 112 A11 AD22 16 F1 DEVSEL 32 L1 SUSPEND 70 L11
A13 101 D13 AD23 15 F2 FRAME 28 J4 TRDY 31 K3
A14 104 C13 AD24 11 E2 GND 6D3V
A15 110 A12 AD25 10 E3 GND 22 H2 V
A16 108 B12 AD26 9 E4 GND 42 L4 V
A17 98 E12 AD27 8 D1 GND 58 M8 V
A18 100 E10 AD28 7 D2 GND 78 K11 V
A19 103 D11 AD29 5 D4 GND 94 F12 V
A20 105 C12 AD30 4 C1 GND 114 C10 V
A21 107 B13 AD31 3 C2 GND 130 B6 V
A22 109 A13
A23 111 B11 BVD2(SPKR) 134 B5 IDSEL 13 F4 V
A24 113 D10 C/BE0 48 N5 INPACK 123 B8 VCCD0 73 N13
A25 116 A10 C/BE1 37 N1 IORD 93 F13 VCCD1 74 M13
AD0 57 N8 C/BE2 27 J3 IOWR 96 F10 V
AD1 56 K7 C/BE3 12 E1 IRDY 29 K1 V
AD2 55 L7 CD1 75 L12 MFUNC0 60 K8 V
AD3 54 N7 CD2 137 A4 MFUNC1 61 N9 VPPD0 71 N12
AD4 53 M7 CE1 88 H13 MFUNC2 64 K9 VPPD1 72 M12
AD5 52 N6 CE2 91 G11 MFUNC3 65 N10 VS1 131 C6
AD6 51 M6 D0 139 C4 MFUNC4 67 L10 VS2 117 D9
AD7 49 K6 D1 141 B3 MFUNC5 68 N11 WAIT 133 A5
AD8 47 M5 D2 143 A2 MFUNC6 69 M11 WE 106 C11
AD9 46 L5 D3 76 L13 OE 92 G10 WP(IOIS16) 136 D5

BVD1(STSCHG/RI)

PIN NO.

PGE GGU

135 C5 GNT 2B1V

PIN NO.

PGE GGU

CC
CC
CC
CC
CC
CC
CC
CC
CCCB
CCCB

CCI
CCP
CCP

PIN NO.

PGE GGU

14 F3
30 K2
50 L6
66 M10

86 H1 1
102 D12
122 C8
138 B4

90 G13
126 A7

63 L9

18 G1

44 N4

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION

NAME

TYPE

O

NAME

TYPE

PCI1211 GGU/PGE

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

Terminal Functions

The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The
terminal numbers are also listed for convenient reference. Terminal numbers are shown for both the PGE LQF
package and the GGU ball grid array package.

power supply

TERMINAL

NAME PGE NUMBER GGU NUMBER

GND 6, 22, 42, 58, 78, 94, 114, 130

V

V

CCCB

V

V

CC

CCI

CCP

14, 30, 50, 66, 86, 102, 122,

138

90, 126 A7, G13

63 L9 Clamping voltage for multifunction terminals (5 V or 3.3 V)

18, 44 G1, N4 Clamping voltage for PCI signaling (5 V or 3.3 V)

PC Card power switch

VCCD0
VCCD1

VPPD0
VPPD1

TERMINAL

PIN NUMBER

PGE GGU

7374N13

M13

7172N12

M12

I/O

B6, C10, D3, F12, H2, K11, L4,

M8

B4, C8, D12, F3, H11, K2, L6,

M10

Logic controls to the TPS2211 PC Card power interface switch to control AVCC.

Logic controls to the TPS2211 PC Card power interface switch to control AVPP.

Device ground terminals

Power supply terminal for core logic (3.3 V)
Clamping voltage for PC Card interface. Indicates card

signaling environment of 5 V or 3.3 V.

FUNCTION

PCI system

TERMINAL

PIN NUMBER

PGE GGU

PCLK 21 H1 I

RST

20 G4 I

I/O

PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled
at the rising edge of PCLK.

PCI reset. When the PCI bus reset is asserted, RST causes the PCI1211 to place all output buffers
in a high-impedance state and reset all internal registers. When RST
completely nonfunctional. After RST

When SUSPEND
registers. All outputs are placed in a high-impedance state, but the contents of the registers are
preserved.

and RST are asserted, the device is protected from RST clearing the internal

FUNCTION

is asserted, the device is

is deasserted, the PCI1211 is in its default state.

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11

PCI1211 GGU/PGE

NAME

TYPE

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

PCI address and data

TERMINAL

PIN NUMBER

PGE GGU

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10

AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

C/BE3
C/BE2
C/BE1
C/BE0

PAR 36 M2 I/O

3
4
5
7
8
9

10

11
15
16
17
19
23
24
25
26
38
39
40
41
43
45
46
47
49
51
52
53
54
55
56
57

12
27
37
48

C2
C1
D4
D2
D1
E4
E3
E2

F2

F1
G2
G3
H3
H4

J1

J2
N2
M3
N3
K4
M4
K5

L5
M5
K6
M6
N6
M7
N7

L7
K7
N8

E1

J3
N1
N5

I/O

I/O

I/O

Terminal Functions (Continued)

FUNCTION

PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary
interface. During the address phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit address or
other destination information. During the data phase, AD31–AD0 contain data.

PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During
the address phase of a primary bus PCI cycle, C/BE3
phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full
32-bit data bus carry meaningful data. C/BE0
(AD15–AD8), C/BE2

PCI bus parity. In all PCI bus read and write cycles, the PCI1211 calculates even parity across the
AD31–AD0 and C/BE3
indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the
initiator’s parity indicator. A compare error results in the assertion of a parity error (PERR

applies to byte 2 (AD23–AD16), and C/BE3 applies to byte 3 (AD31–AD24).

–C/BE0 buses. As an initiator during PCI cycles, the PCI1211 outputs this parity

–C/BE0 define the bus command. During the data

applies to byte 0 (AD7–AD0), C/BE1 applies to byte 1

).

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

NAME

TYPE

PCI interface control

TERMINAL

PIN NUMBER

PGE GGU

DEVSEL

FRAME

GNT

IDSEL 13 F4 I

IRDY

PERR

REQ

SERR

STOP

TRDY

32 L1 I/O

28 J4 I/O

2 B1 I

29 K1 I/O

34 L3 I/O

1 A1 O PCI bus request. REQ is asserted by the PCI1211 to request access to the PCI bus as an initiator .

35 M1 O

33 L2 I/O

31 K3 I/O

PCI1211 GGU/PGE

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

Terminal Functions (Continued)

I/O

PCI device select. The PCI1211 asserts DEVSEL to claim a PCI cycle as the target device. As a
PCI initiator on the bus, the PCI1211 monitors DEVSEL
responds before timeout occurs, the PCI1211 terminates the cycle with an initiator abort.

PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that
a bus transaction is beginning, and data transfers continue while this signal is asserted. When
FRAME

is deasserted, the PCI bus transaction is in the final data phase.

PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1211 access to the PCI bus
after the current data transaction has completed. GNT
depending on the PCI bus parking algorithm.

Initialization device select. IDSEL selects the PCI1211 during configuration space accesses.
IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus.

PCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data phase
of the transaction. A data phase is completed on a rising edge of PCLK where both IRDY
are asserted. Until IRDY and TRDY are both sampled asserted, wait states are inserted.

PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does
not match PAR when PERR

PCI system error. SERR is an output that is pulsed from the PCI1211 when enabled through the
command register indicating a system error has occurred. The PCI121 1 need not be the target of
the PCI cycle to assert this signal. When SERR
pulses, indicating that an address parity error has occurred on a CardBus interface.

PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI
bus transaction. STOP
that do not support burst data transfers.

PCI target ready. TRDY indicates the primary bus target’s ability to complete the current data phase
of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY
are asserted. Until both IRDY and TRDY are asserted, wait states are inserted.

is enabled through bit 6 of the command register.

is used for target disconnects and is commonly asserted by target devices

FUNCTION

until a target responds. If no target

may or may not follow a PCI bus request,

is enabled in the control register, this signal also

and TRDY

and TRDY

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13

PCI1211 GGU/PGE

NAME

TYPE

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

Terminal Functions (Continued)

multifunction and miscellaneous pins

TERMINAL

PIN NUMBER

PGE GGU

MFUNC0 60 K8 I/O

MFUNC1 61 N9 I/O

MFUNC2 64 K9 I/O

MFUNC3 65 N10 I/O

MFUNC4 67 L10 I/O

MFUNC5 68 N1 1 I/O

MFUNC6 69 M11 I/O

RI_OUT/PME 59 L8 O

SUSPEND 70 L11 I

SPKROUT 62 M9 O

I/O

FUNCTION

Multifunction Terminal 0. MFUNC0 can be configured as parallel PCI interrupt INTA, GPI0, GPO0,
GPE

, socket activity LED output, ZV output select, CardBus audio PWM, or a parallel IRQ. Refer

to the

multifunction routing register

Multifunction Terminal 1. MFUNC1 can be configured as GPI1, GPO1, GPE, socket activity LED
output, ZV output select, CardBus audio PWM, or a parallel IRQ. Refer to the

routing register

Serial Data (SDA). When the serial bus mode is implemented by pulling up the SCA and SCL
terminals, the MFUNC1 terminal provides the SDA signaling. The two-pin serial interface is used
to load the subsystem identification and other register defaults from an EEPROM after a PCI
reset. Refer to the
bus applications.

Multifunction Terminal 2. MFUNC2 can be configured as PC/PCI DMA Request, GPI2, GPO2,
socket activity LED output, ZV output select, CardBus audio PWM, GPE
IRQ. Refer to the

Multifunction Terminal 3. MFUNC3 can be configured as a parallel IRQ or the serialized interrupt
signal IRQSER. Refer to the
details.

Multifunction Terminal 4. MFUNC4 can be configured as PCI LOCK, GPI3, GPO3, socket activity
LED, RI_OUT

multifunction routing register

Serial Clock (SCL). When the serial bus mode is implemented by pulling the SDA and SCL
terminals, the MFUNC4 terminal provides the SCL signaling. The two-pin serial interface is used
to load the subsystem identification and other register defaults from an EEPROM after a PCI
reset. Refer to the
bus applications.

Multifunction Terminal 5. MFUNC5 can be configured as PC/PCI DMA Grant, GPI4, GPO4,
socket activity LED output, ZV output select, CardBus audio PWM, GPE
to the

multifunction routing register

Multifunction Terminal 6. MFUNC6 can be configured as a PCI CLKRUN or a parallel IRQ. Refer
to the

multifunction routing register

Ring Indicate Out and Power Management Event Output. Provides output for either RI_OUT or
PME

signals.

Suspend. SUSPEND is used to protect the internal registers from clearing when the RST signal is
asserted. See

Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO
through the PCI1211 from the PC Card interface. SPKROUT is driven as the exclusive-OR
combination of card SPKR

description on page 61 for configuration details.

serial bus interface protocol

multifunction routing register

output, ZV output select, CardBus audio PWM, GPE, or a parallel IRQ. Refer to the

serial bus interface protocol

suspend mode

description on page 61 for configuration details.

description on page 30 for details on other serial

description on page 61 for configuration details.

multifunction routing register

description on page 61 for configuration details.

description on page 30 for details on other serial

description on page 61 for configuration details.

description on page 61 for configuration details.

on page 39 for details.

//CAUDIO inputs.

description on page 61 for configuration

multifunction

, RI_OUT, or a parallel

, or a parallel IRQ. Refer

14

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NAME

TYPE

PCI1211 GGU/PGE

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

Terminal Functions (Continued)

The address and data and interface control terminals for the 16-bit PC Card are shown in the following two
tables.

16-bit PC Card address and data

TERMINAL

A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10

A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

D15
D14
D13
D12
D11
D10

D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

PIN NUMBER

PGE GGU

116

A10

113

D10

111

B11

109

A13

107

B13

105

C12

103

D11

100

E10

98

E12

108

B12

110

A12

104

C13

101

D13

112

A11

95

F11

89

G12

97

E13

99

E11

115

B10

118
120
121
124
127
128
129

87

H12

84

J13

82

J11

80

K13

77

K10
144
142
140

85

H10

83

J12

81

J10

79

K12

76

L13
143
141
139

I/O

O PC Card address. 16-bit PC Card address lines. A25 is the most-significant bit.

C9
A9
D8
A8
C7
D7
A6

B2
C3
A3

I/O PC Card data. 16-bit PC Card data lines. D15 is the most-significant bit.

A2
B3
C4

FUNCTION

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15

PCI1211 GGU/PGE

NAME

TYPE

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

16-bit PC Card interface control

TERMINAL

PIN NUMBER

PGE GGU

BVD1

(STSCHG

BVD2

(SPKR

CD1
CD2

CE1
CE2

INPACK 123 B8 I

IORD

IOWR

OE 92 G10 O

135 C5 I

/RI)

134 B5 I

)

75

137

8891H13

93 F13 O

96 F10 O

L12

G11

A4

I/O

Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries.
BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card.
Both BVD1 and BVD2 are kept high when the battery is good. When BVD2 is low and BVD1 is high,
the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable
and the data in the memory PC Card is lost. See

register
ExCA interface status register

Status change. STSCHG is used to alert the system to a change in the READY, write protect, or
battery voltage dead condition of a 16-bit I/O PC Card.

Ring indicate. RI
Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include batteries.

BVD2 is used with BVD1 as an indication of the condition of the batteries on a memory PC Card.
Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the
battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable
and the data in the memory PC Card is lost. See

register
interface status register

Speaker. SPKR
been configured for the 16-bit I/O interface. The audio signals from cards A and B are combined
by the PCI1211 and are output on SPKROUT.

DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit
PC Card that supports DMA. The PC Card asserts BVD2 to indicate a request for a DMA operation.

PC Card detect 1 and PC Card detect 2. CD1 and CD2 are internally connected to ground on the
PC Card. When a PC Card is inserted into a socket, CD1

I

see
Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address bytes.

O

CE1
Input acknowledge. INP ACK is asserted by the PC Card when it can respond to an I/O read cycle

at the current address.
DMA request. INPACK

PC Card that supports DMA. If used as a strobe, the PC Card asserts this signal to indicate a
request for a DMA operation.

I/O read. IORD is asserted by the PCI1211 to enable 16-bit I/O PC Card data output during host
I/O read cycles.

DMA write. IORD
that supports DMA. The PCI1211 asserts IORD
memory.

I/O write. IOWR is driven low by the PCI1211 to strobe write data into 16-bit I/O PC Cards during
host I/O write cycles.

DMA read. IOWR
that supports DMA. The PCI1211 asserts IOWR

Output enable. OE is driven low by the PCI1211 to enable 16-bit memory PC Card data output
during host memory read cycles.

DMA terminal count. OE
that supports DMA. The PCI1211 asserts OE

Terminal Functions (Continued)

FUNCTION

on page 89 for enable bits. See

on page 85 for the status bits for this signal.

is used by 16-bit modem cards to indicate a ring detection.

on page 89 for enable bits. See

on page 85 for the status bits for this signal.

is an optional binary audio signal available only when the card and socket have

interface status register.

enables even-numbered address bytes, and CE2 enables odd-numbered address bytes.

can be used as the DMA request signal during DMA operations from a 16-bit

is used as the DMA write strobe during DMA operations from a 16-bit PC Card

is used as the DMA write strobe during DMA operations from a 16-bit PC Card

is used as terminal count (TC) during DMA operations to a 16-bit PC Card

ExCA card status-change interrupt configuration

ExCA card status-change register

ExCA card status-change interrupt configuration

ExCA card status-change register

and CD2 are pulled low. For signal status,

during DMA transfers from the PC Card to host

during transfers from host memory to the PC Card.

to indicate TC for a DMA write operation.

on page 88 and the

on page 88 and the

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

NAME

TYPE

Terminal Functions (Continued)

16-bit PC Card interface control (continued)

TERMINAL

PIN NUMBER

PGE GGU

READY

(IREQ

REG

RESET 119 B9 O PC Card reset. RESET forces a hard reset to a 16-bit PC Card.

WAIT

WE 106 C11 O

WP

(IOIS16

VS1
VS2

132 D6 I

)

125 B7 O

133 A5 I

136 D5 I

)

131

117C6D9

I/O

Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket are
configured for the memory-only interface. READY is driven low by the 16-bit memory PC Cards to
indicate that the memory card circuits are busy processing a previous write command. READY is
driven high when the 16-bit memory PC Card is ready to accept a new data transfer command.

Interrupt request. IREQ
the 16-bit I /O PC Card requires service by the host software. IREQ
interrupt is requested.

Attribute memory select. REG remains high for all common memory accesses. When REG is
asserted, access is limited to attribute memory (OE

active). Attribute memory is a separately accessed section of card memory and is generally

IOWR
used to record card capacity and other configuration and attribute information.

DMA acknowledge. REG is used as a DMA acknowledge (DACK) during DMA operations to a
16-bit PC Card that supports DMA. The PCI121 1 asserts REG
is used in conjunction with the DMA read (IOWR) or DMA write (IORD) strobes to transfer data.

Bus cycle wait. WAIT is driven by a 16-bit PC Card to delay the completion of (i.e., extend) the
memory or I/O cycle in progress.

Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also
used for memory PC Cards that employ programmable memory technologies.

DMA terminal count. WE
DMA. The PC1211 asserts WE

Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect
switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16
function.

I/O is 16 bits. IOIS16
the address on the bus corresponds to an address to which the 16-bit PC Card responds, and the
I/O port that is addressed is capable of 16-bit accesses.

DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit
PC Card that supports DMA. If used, the PC Card asserts WP to indicate a request for a DMA
operation.

Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other,

I/O

determine the operating voltage of the 16-bit PC Card.

is asserted by a 16-bit I/O PC Card to indicate to the host that a device on

is used as TC during DMA operations to a 16-bit PC Card that supports

to indicate TC for a DMA read operation.

applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card when

FUNCTION

or WE active) and to the I/O space (IORD or

PCI1211 GGU/PGE

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

is high (deasserted) when no

to indicate a DMA operation. REG

)

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17

PCI1211 GGU/PGE

NAME

TYPE

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

Terminal Functions (Continued)

The interface system, address and data, and interface control terminals for the CardBus PC Card system are
shown in the following three tables.

CardBus PC Card interface system

TERMINAL

PIN NUMBER

PGE GGU

CCLK 108 B12 O

CCLKRUN

CRST

136 D5 O

119 B9 I/O

I/O

CardBus PC Card clock. CCLK provides synchronous timing for all transactions on the CardBus
interface. All signals except CRST
CVS2–CVS1 are sampled on the rising edge of CCLK, and all timing parameters are defined with the
rising edge of this signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the
low state or slowed down for power savings.

CardBus PC Card clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the
CCLK frequency, and by the PCI121 1 to indicate that the CCLK frequency is going to be decreased.

CardBus PC Card reset. CRST is used to bring CardBus PC Card-specific registers, sequencers,
and signals to a known state. When CRST
and the PCI1211 drives these signals to a valid logic level. Assertion can be asynchronous to CCLK,
but deassertion must be synchronous to CCLK.

FUNCTION

, CLKRUN, CINT, CSTSCHG, CAUDIO, CCD1, CCD2, and

is asserted, all CardBus PC Card signals must be 3-stated,

18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

NAME

TYPE

Terminal Functions (Continued)

CardBus PC Card address and data

TERMINAL

PIN NUMBER

PGE GGU

CAD31
CAD30
CAD29
CAD28
CAD27
CAD26
CAD25
CAD24
CAD23
CAD22
CAD21
CAD20
CAD19
CAD18
CAD17
CAD16
CAD15
CAD14
CAD13
CAD12
CAD11
CAD10

CAD9
CAD8
CAD7
CAD6
CAD5
CAD4
CAD3
CAD2
CAD1
CAD0

CC/BE3
CC/BE2
CC/BE1
CC/BE0

CPAR 101 D13 I/O

144
142
141
140
139
129
128
127
124
121
120
118
116
115
113

98
96
97
93
95
92
91
89
87
85
82
83
80
81
77
79
76

12
27
37
48

A10
B10

D10

E12
F10
E13
F13

F11
G10
G11
G12
H12
H10

J11
J12
K13
J10
K10
K12
L13

B2
C3
B3
A3
C4
A6
D7
C7
A8
D8
A9
C9

E1

J3
N1
N5

I/O

PC Card address and data. These signals make up the multiplexed CardBus address and data bus on
the CardBus interface. During the address phase of a CardBus cycle, CAD31–CAD0 contain a 32-bit

I/O

address. During the data phase of a CardBus cycle, CAD31–CAD0 contain data. CAD31 is the
most-significant bit.

CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the same CardBus
terminals. During the address phase of a CardBus cycle, CC/BE3
During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte

I/O

paths of the full 32-bit data bus carry meaningful data. CC/BE0
applies to byte 1 (CAD15–CAD8), CC/BE2 applies to byte 2 (CAD23–CAD16), and CC/BE3 applies to
byte 3 (CAD31–CAD24).

CardBus parity. In all CardBus read and write cycles, the PCI121 1 calculates even parity across the CAD
and CC/BE
delay. As a target during CardBus cycles, the calculated parity is compared to the initiator’s parity
indicator; a compare error results in a parity error assertion.

buses. As an initiator during CardBus cycles, the PCI1211 outputs CPAR with a one-CCLK

PCI1211 GGU/PGE

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

FUNCTION

–CC/BE0 defines the bus command.

applies to byte 0 (CAD7–CAD0), CC/BE1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

19

PCI1211 GGU/PGE

NAME

TYPE

I

CVS2 to identif

d

I/O

ith CCD1

CCD2 to identif

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

Terminal Functions (Continued)

CardBus PC Card interface control

TERMINAL

PIN NUMBER

PGE GGU

CAUDIO 134 B5 I

CBLOCK

CCD1
CCD2

CDEVSEL

CFRAME

CGNT

CINT

CIRDY

CPERR

CREQ

CSERR

CSTOP

CSTSCHG

CTRDY

CVS1 131 C6
CVS2 117 D9

103 D11 I/O

75 L12

137 A4

107 B13 I/O

111 B11 I/O

106 C11 I

132 D6 I

110 A12 I/O

104 C13 I/O

123 B8 I

133 A5 I

105 C12 I/O

135 C5 I

109 A13 I/O

I/O

CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The PCI121 1
supports the binary audio mode and outputs a binary signal from the card to SPKROUT.

CardBus lock. CBLOCK is used to gain exclusive access to a target.
CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with CVS1 and

type.
CardBus device select. The PCI1211 asserts CDEVSEL to claim a CardBus cycle as the target

device. As a CardBus initiator on the bus, the PCI1211 monitors CDEVSEL
If no target responds before timeout occurs, the PCI1211 terminates the cycle with an initiator abort.

CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME is asserted
to indicate that a bus transaction is beginning, and data transfers continue while this signal is
asserted. When CFRAME

CardBus bus grant. CGNT is driven by the PCI1211 to grant a CardBus PC Card access to the
CardBus bus after the current data transaction has been completed.

CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from
the host.

CardBus initiator ready. CIRDY indicates the CardBus initiator’s ability to complete the current data
phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY
CTRDY

CardBus parity error. CPERR is used to report parity errors during CardBus transactions, except
during special cycles. It is driven low by a target two clocks following that data when a parity error
is detected.

CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the
CardBus bus as an initiator.

CardBus system error. CSERR reports address parity errors and other system errors that could lead
to catastrophic results. CSERR
pullup, and may take several CCLK periods. The PCI1211 can report CSERR
assertion of SERR

CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current
CardBus transaction. CSTOP
devices that do not support burst data transfers.

CardBus status change. CSTSCHG is used to alert the system to a change in the card’s status, and
is used as a wake-up mechanism.

CardBus target ready. CTRDY indicates the CardBus target’s ability to complete the current data
phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY
and CTRDY are asserted; until this time, wait states are inserted.

CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in conjunction
w
voltage and card type.

FUNCTION

y card insertion and interrogate cards to determine the operating voltage and car

until a target responds.

is deasserted, the CardBus bus transaction is in the final data phase.

are asserted. Until CIRDY and CTRDY are both sampled asserted, wait states are inserted.

on the PCI interface.

and

is driven by the card synchronous to CCLK, but deasserted by a weak

is used for target disconnects, and is commonly asserted by target

y card insertion and interrogate cards to determine the operating

to the system by

and

p

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SCPS033A – OCTOBER 1998

power supply sequencing

The PCI1211 contains 3.3-V I/O buffers with 5-V tolerance requiring a core power supply and clamp voltage.
The core power supply is always 3.3 V . The clamp voltage can be either 3.3 V or 5 V , depending on the interface.
The following power-up and power-down sequences are recommended.

The power-up sequence is:

1. Apply 3.3-V power to the core.

2. Assert PRST

to the device to disable the outputs during power up. Output drivers must be powered up in

the high-impedance state to prevent high current levels through the clamp diodes to the 5-V supply.

3. Apply the clamp voltage.
The power-down sequence is:

1. Use PRST

to switch outputs to a high-impedance state.

2. Remove the clamp voltage.

3. Remove the 3.3-V power from the core.

I/O characteristics

Figure 1 shows a 3-state bidirectional buffer. The
provides the electrical characteristics of the inputs and outputs.

NOTE:

The PCI1211 meets the ac specifications of the

Specification Revision 2.2.

Tied for Open Drain

OE

recommended operating conditions

1997 PC Card Standard

V

CCP

Pad

and

PCI Local Bus

table, on page 119,

Figure 1. 3-State Bidirectional Buffer

NOTE:

Unused pins (input or I/O) must be held high or low to prevent them from floating.

clamping voltages

The clamping voltages are set to match whatever external environment the PCI1211 will be working with: 3.3 V
or 5 V. The I/O sites can be pulled through a clamping diode to a voltage that protects the core from external
signals. The core power supply is always 3.3 V and is independent of the clamping voltages. For example, PCI
signaling can be either 3.3 V or 5 V, and the PCI1211 must reliably accommodate both voltage levels. This is
accomplished by using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping voltage applied. If
a system designer desires a 5-V PCI bus, V

The PCI1211 requires three separate clamping voltages because it supports a wide range of features. The three
voltages are listed and defined in the

recommended operating conditions

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

can be connected to a 5-V power supply.

CCP

, on page 119.

21

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SCPS033A – OCTOBER 1998

peripheral component interconnect (PCI) interface

The PCI1211 is fully compliant with the
required signals for PCI master or slave operation, and may operate in either a 5-V or 3.3-V signaling
environment by connecting the V
signals the PCI1211 provides the optional interrupt signal INTA

PCI bus lock (LOCK)

The bus-locking protocol defined in the PCI specification is not highly recommended, but is provided on the
PCI1211 as an additional compatibility feature. The PCI LOCK
via the multifunction routing register, see the
Note that the use of LOCK
the processor).

PCI LOCK
asserted, nonexclusive transactions can proceed to an address that is not currently locked. A grant to start a
transaction on the PCI bus does not guarantee control of LOCK
protocol. It is possible for different initiators to use the PCI bus while a single master retains ownership of LOCK
Note that the CardBus signal for this protocol is CBLOCK

An agent may need to do an exclusive operation because a critical access to memory might be broken into
several transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock
is defined by PCI to be 16 bytes, aligned. The lock protocol defined by PCI allows a resource lock without
interfering with nonexclusive real-time data transfer, such as video.

The PCI bus arbiter may be designed to support only complete bus locks using the LOCK
scenario, the arbiter will not grant the bus to any other agent (other than the LOCK
asserted. A complete bus lock may have a significant impact on the performance of the video. The arbiter that
supports complete bus lock must grant the bus to the cache to perform a writeback due to a snoop to a modified
line when a locked operation is in progress.

indicates an atomic operation that may require multiple transactions to complete. When LOCK is

is only supported by PCI-to-CardBus bridges in the downstream direction (away from

CCP

PCI Local Bus Specification, Revision 2.2

terminals to the desired voltage level. In addition to the mandatory PCI

.

signal can be routed to the MFUNC4 terminal

multifunction routing register description

; control of LOCK is obtained under its own

to avoid confusion with the bus clock.

. The PCI1211 provides all

on page 61 for details.

protocol. In this

master) while LOCK is

.

The PCI1211 supports all LOCK
PCI-to-CardBus bridges. This includes disabling write posting while a locked operation is in progress, which can
solve a potential deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can occur
if a CardBus target supports delayed transactions and blocks access to the target until it completes a delayed
read. This target characteristic is prohibited by the
resolved by the PCI master using LOCK

loading subsystem identification

The subsystem vendor ID register and subsystem ID register make up a doubleword of PCI configuration space
located at offset 40h. This doubleword register is used for system and option card (mobile dock) identification
purposes and is required by some operating systems. Implementation of this unique identifier register is a PC
’97 requirement.

The PCI1211 offers two mechanisms to load a read-only value into the subsystem registers. The first
mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the
subsystem registers is read-only, but can be made read/write by setting the SUBSYSRW bit in the system
control register (bit 5, at PCI offset 80h). Once this bit is set, the BIOS can write a subsystem identification value
into the registers at offset 40h. The BIOS must clear the SUBSYSRW bit such that the subsystem vendor ID
register and subsystem ID register is limited to read-only access. This approach saves the added cost of
implementing the serial electrically erasable programmable ROM (EEPROM).

protocol associated with PCI-to-PCI bridges, as also defined for

PCI Local Bus Specification, Revision 2.2

.

, and the issue is

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PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

loading subsystem identification (continued)

In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID
register must be loaded with a unique identifier via a serial EEPROM. The PCI121 1 loads the data from the serial
EEPROM after a reset of the primary bus. The SUSPEND
core, including the serial bus state machine (see

suspend mode

The PCI1211 provides a two-line serial bus host controller that can be used to interface to a serial EEPROM.
Refer to

serial bus interface

on page 30 for details on the two-wire serial bus controller and applications.

PC Card applications

This section describes the PC Card interfaces of the PCI1211. Discussions are provided for:

D

Card insertion/removal and recognition

D

P2C power-switch interface

D

Zoom video support

D

Speaker and audio applications

D

LED socket activity indicator

D

PC Card 16-distributed DMA support

D

PC Card controller programming model

D

CardBus socket registers

input gates the PCI reset from the entire PCI1211

, on page 39, for details on using SUSPEND).

PC Card insertion/removal and recognition

The 1997 PC Card Standard addresses the card-detection and recognition process through an interrogation
procedure that the socket must initiate on card insertion into a cold, unpowered socket. Through this
interrogation, card voltage requirements and interface (16-bit versus CardBus) are determined.

The scheme uses the CD1

, CD2, VS1, and VS2 signals (CCD1, CCD2, CVS1, and CVS2 for CardBus). The
configuration of these four terminals identifies the card type and voltage requirements of the PC Card interface.
The encoding scheme is defined in the 1995 PC Card Standard and is shown in Table 5.

Table 5. PC Card Card-Detect and Voltage-Sense Connections

CD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1 KEY INTERFACE VOLTAGE

Ground Ground Open Open 5 V 16-bit PC Card 5 V
Ground Ground Open Ground 5 V 16-bit PC Card 5 V and 3.3 V
Ground Ground Ground Ground 5 V 16-bit PC Card 5 V, 3.3 V, and X.X V
Ground Ground Open Ground LV 16-bit PC Card 3.3 V
Ground Connect to CVS1 Open Connect to CCD1 LV CardBus PC Card 3.3 V
Ground Ground Ground Ground LV 16-bit PC Card 3.3 V and X.X V

Connect to CVS2 Ground Connect to CCD2 Ground LV CardBus PC Card 3.3 V and X.X V
Connect to CVS1 Ground Ground Connect to CCD2 LV CardBus PC Card 3.3 V, X.X V, and Y.Y V

Ground Ground Ground Open LV 16-bit PC Card Y .Y V

Connect to CVS2 Ground Connect to CCD2 Open LV CardBus PC Card Y.Y V

Ground Connect to CVS2 Connect to CCD1 Open LV CardBus PC Card X.X V and Y.Y V

Connect to CVS1 Ground Open Connect to CCD2 LV CardBus PC Card Y.Y V

Ground Connect to CVS1 Ground Connect to CCD1 Reserved
Ground Connect to CVS2 Connect to CCD1 Ground Reserved

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

23

PCI1211 GGU/PGE
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P2C power-switch interface (TPS2211)

The PCI1211 provides a P
The VCCD

and VPPD terminals are used with the TI TPS2211 single slot PC Card power interface switch to
provide power switch support. Figure 2 shows the terminal assignments for the TPS2211. Figure 3 illustrates
a typical application, where the PCI1211 represents the PC Card controller.

2

C (PCMCIA peripheral control) interface for control of the PC Card power switch.

VCCD0
VCCD1

3.3V

3.3V
5V
5V
GND

OC

1
2
3
4
5
6
7
8

16
15
14
13
12

11

10

9

SHDN
VPPD0
VPPD1
AVCC
AVCC
AVCC
AVPP
12V

Figure 2. TPS2211 Terminal Assignments

The PCI121 1 also includes support for the Maxim 1602 single-channel CardBus and PCMCIA power-switching
network. Application of this power switch would be similar to the TPS2211.

Power Supply

12 V

5 V

3.3 V

Supervisor

PCI1211

(PCMCIA

Controller)

12V
5V

3.3V

SHDN
SHDN

VCCD0
VCCD1
VPPD0
VPPD1

TPS2211

AVPP

AVCC

V
V
V
V

PP1
PP2
CC
CC

PC Card

OC

Figure 3. TPS2211 Typical Application

zoom video support

The PCI1211 allows for the implementation of zoom video for PC Cards. Zoom video is supported by setting
the ZVENABLE bit in the card control register. Setting this bit puts PC Card-16 address lines A25–A4 of the PC
Card interface in the high-impedance state. These lines can then be used to transfer video and audio data
directly to the appropriate controller. Card address lines A3–A0 can still be used to access PC Card CIS registers
for PC Card configuration. Figure 4 illustrates a PCI1211 ZV implementation.

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

zoom video support (continued)

PCI1211 GGU/PGE

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

Audio

Codec

PCM
Audio
Input

Speakers

PC Card

19

PC Card
Interface

Video

Audio

4

CRT

Motherboard

PCI Bus

VGA

Controller

Zoom Video

Port

19 4

PCI1211

Figure 4. Zoom Video Implementation Using PCI1211

Not shown in Figure 4 is the multiplexing scheme used to route either a socket ZV source or an external ZV
source to the graphics controller. A typical external source might be provided from a high-speed serial bus like
IEEE1394. The PCI1211 provides ZVSTAT, ZVSEL0

signals on the multifunction terminals to switch external

bus drivers. Figure 5 shows an implementation for switching between two ZV streams using external logic.

PCI1211

ZVSTAT

ZVSEL0

Figure 5. Zoom Video Switching Application

The example shown in Figure 5 illustrates an implementation using standard 3-state bus drivers with active-low
output enables. ZVSEL0

is an active-low output indicating that the Socket ZV mode is enabled. ZVST AT is an
active-high output indicating the PCI121 1 socket is enabled for ZV mode. The implementation shown in Figure 5
can be used if PC Card ZV is prioritized over other sources.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SPKROUT and CAUDPWM usage

SPKROUT carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card is configured
for I/O mode, the BVD2 pin becomes SPKR
and is referred to as CAUDIO. SPKR
CAUDIO signal also can pass a single-amplitude binary waveform. The binary audio signals from the PC Card
socket is used in the PCI121 1 to produce SPKROUT . This output is enabled by the SPKROUTEN bit in the card
control register.

Older controllers support CAUDIO in binary or PWM mode but use the same pin (SPKROUT). Some audio chips
may not support both modes on one pin and may have a separate pin for binary and PWM. The PCI1211
implementation includes a signal for PWM, CAUDPWM, which can be routed to a MFUNC terminal. The
AUD2MUX bit located in the card control register is programmed to route a CardBus CAUDIO PWM terminal
to CAUDPWM. Refer to the

multifunction routing register

MFUNC terminals.
Figure 6 provides an illustration of a sample application using SPKROUT and CAUDPWM.

System

Core Logic

SPKROUT

PCI1211

CAUDPWM

. This terminal is also used in CardBus binary audio applications,

passes a TTL level digital audio signal to the PCI1211. The CardBus

description on page 61 for details on configuring the

BINARY_SPKR

Speaker

Subsystem

PWM_SPKR

Figure 6. Sample Application of SPKROUT and CAUDPWM

LED socket activity indicators

A socket activity LED indicates when a PC Card is being accessed. The LED_SKT signal can be routed to the
multifunction terminals. When configured for LED output, this terminal outputs an active high signal to indicate
socket activity. Refer to the

multifunction routing register

description on page 61 for details on configuring the

multifunction terminals.
The LED signal is active high and is driven for 64-ms durations. When the LED is not being driven high, it is driven

to a low state. Either of the two circuits shown in Figure 7 can be implemented to provide LED signaling, and
it is left for the board designer to implement the circuit that best fits the application.

The LED activity signal is valid when a card is inserted, powered, and not in reset. For PC Card 16, the LED
activity signal is pulsed when READY/IREQ
CFRAME

, CIRDY, or CREQ is active.

is low. For CardBus cards, the LED activity signal is pulsed if

26

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Reserved

Page

Reserved

Reserved

Reserved

Reserved

Reserved

LED socket activity indicators (continued)

PCI1211 GGU/PGE

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

Current Limiting

R ≈ 500 Ω

PCI1211

PCI1211

Application-

Specific Delay

Current Limiting

R ≈ 500 Ω

LED

LED

Figure 7. T wo Sample LED Circuits

As indicated, the LED signal is driven for 64 ms by a counter circuit. T o avoid the possibility of the LED appearing
to be stuck when the PCI clock is stopped, the LED signaling is cut-off when the SUSPEND
when the PCI clock is to be stopped during the CLKRUN

protocol, or when in the D2 or D1 power state.

signal is asserted,

If any additional socket activity occurs during this counter cycle, the counter is reset and the LED signal remains
driven. If socket activity is frequent (at least once every 64 ms), the LED signal remains driven.

PC Card16 Distributed DMA support

The PCI121 1 supports a distributed DMA slave engine for 16-bit PC Card DMA support. The distributed DMA
(DDMA) slave register set provides the programmability necessary for the slave DDMA engine. T able 6 shows
the DDMA register configuration.

Two critical PCI configuration header registers for DDMA are the socket DMA register 0 and the socket DMA
register 1. Distributed DMA is enabled through socket DMA register 0 and the contents of this register configure
the PC Card-16 terminal (SPKR

, IOIS16, or INPACK) which is used for the DMA request signal, DREQ. The
base address of the DDMA slave registers and the transfer size (bytes or words) are programmed through the
socket DMA register 1. Refer to the

PC Card controller programming model

on page 43 and the accompanying

register descriptions for details.

Table 6. Distributed DMA Registers

DMA

TYPE REGISTER NAME

R
W
R
W
R N/A
W Mode
R Multichannel
W Mask

Master clear

Current address 00

Base address
Current count 04

Base count

N/A Status 08

Request Command

N/A

BASE ADDRESS

OFFSET (HEX)

0C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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PCI1211 GGU/PGE
PC CARD CONTROLLERS

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PC Card16 Distributed DMA support (continued)

The DDMA registers contain control and status information consistent with the 8237 DMA controller; however,
the register locations are reordered and expanded in some cases. While the DDMA register definitions are
identical to those in the 8237 DMA controller of the same name, some register bits defined in the 8237 DMA
controller do not apply to distributed DMA in a PCI environment. In such cases, the PCI121 1 implements these
obsolete register bits as read-only , nonfunctional bits. The reserved registers shown in T able 6 are implemented
as read-only and return zeros when read. Writes to reserved registers have no effect.

The DDMA transfer is prefaced by several configuration steps that are specific to the PC Card and must be
completed after the PC Card is inserted and interrogated. These steps include setting the proper DREQ
assignment, setting the data transfer width, and mapping and enabling the DDMA register set. As discussed
above, this is done through socket DMA register 0
programmed similarly to an 8237 controller, and the PCI1211 awaits a DREQ
requesting a DMA transfer.

DMA writes transfer data from the PC Card to PCI memory addresses. The PCI121 1 accepts data 8 or 16 bits
at a time, depending on the programmed data width, and then requests access to the PCI bus by asserting its
REQ

signal. Once granted, the PCI bus and the bus returns to an idle state. The PCI121 1 initiates a PCI memory
write command to the current memory address and transfers the data in a single data phase. After terminating
the PCI cycle, the PCI1211 accepts the next byte(s) from the PC Card until the transfer count expires.

and socket DMA register 1. The DMA register set is then

assertion from the PC Card

signal

DMA reads transfer data from PCI memory addresses to the PC Card application. Upon the assertion of DREQ
the PCI121 1 asserts REQ
a PCI memory read operation to the current memory address and accepts 8 or 16 bits of data, depending on
the programmed data width. After terminating the PCI cycle, the data is passed on to the PC Card. After
terminating the PC Card cycle, the PCI121 1 requests access to the PCI bus again until the transfer count has
expired.

The PCI121 1 target interface acts normally during this procedure, and accepts I/O reads and writes to the DDMA
registers. While a DDMA transfer is in progress and the host resets the DMA channel, the PCI121 1 asserts TC
and ends the PC Card cycle(s). TC is indicated in the DDMA status register. At the PC Card interface, the
PCI1211 supports demand mode transfers. The PCI1211 asserts DACK during the transfer unless DREQ
deasserted before TC. TC is mapped to the OE
WE

PC Card terminal for DMA read operations. The DACK signal is mapped to the PC Card REG signal in all
transfers, and the DREQ
register 0.

PC Card-16 PC/PCI DMA

Some chipsets provide a way for legacy I/O devices to do DMA transfers on the PCI bus. In the PC/PCI DMA
protocol, the PCI121 1 acts as a PCI target device to certain DMA related I/O addresses. The PCI121 1 PCREQ
and PCGNT signals are provided as a point-to-point connection to a chipset supporting PC/PCI DMA. The
PCREQ

and PCGNT signals may be routed to the MFUNC2 and MFUNC5 terminals, respectively . Refer to the

multifunction routing register

Under the PC/PCI protocol, a PCI DMA slave device (such as the PCI1211) requests a DMA transfer on a
particular channel using a serialized protocol on PCREQ
and grants the channel through a serialized protocol on PCGNT
and memory cycles are then presented on the PCI bus which perform the DMA transfers similarly to legacy DMA
master devices.

to acquire the PCI bus. Once granted the bus and the bus is idle, the PCI121 1 initiates

PC Card terminal for DMA write operations, and is mapped to

terminal is routed to one of three options which is programmed through socket DMA

description on page 61 for details on configuring the multifunction terminals.

. The I/O DMA bus master arbitrates for the PCI bus,

when it is ready for the transfer. The I/O cycle

,

is

PC/PCI DMA is enabled for the PC Card-16 slot by setting bit 19 in the respective system control register . On
power-up this bit is reset and the card PC/PCI DMA is disabled. Bit 3 of the system control register is a global
enable for PC/PCI DMA, and is set at power-up and never cleared if the PC/PCI DMA mechanism is
implemented. The desired DMA channel for the PC Card-16 slot must be configured through bits 18–16 in the
system control register. The channels are configured as indicated in Table 7.

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DMA CHANNEL

CHANNEL TRANSFER DATA WIDTH

PCI1211 GGU/PGE

PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

Table 7. PC/PCI Channel Assignments

SYSTEM CONTROL REGISTER

BIT 18 BIT 17 BIT16

0 0 0 Channel 0 8-bit DMA transfers
0 0 1 Channel 1 8-bit DMA transfers
0 1 0 Channel 2 8-bit DMA transfers
0 1 1 Channel 3 8-bit DMA transfers
1 0 0 Channel 4 Not used
1 0 1 Channel 5 16-bit DMA transfers
1 1 0 Channel 6 16-bit DMA transfers
1 1 1 Channel 7 16-bit DMA transfers

As in distributed DMA, the PC Card terminal mapped to DREQ must be configured through socket DMA
register 0. The data transfer width is a function of channel number , and the DDMA slave registers are not used.
When a DREQ
addresses listed in Table 8 and performs actions dependent upon the address.

is received from a PC Card, and the channel has been granted, the PCI121 1 decodes the I/O

Table 8. I/O Addresses Used for PC/PCI DMA

DMA I/O ADDRESS DMA CYCLE TYPE TERMINAL COUNT PCI CYCLE TYPE

00h Normal 0 I/O read/write
04h Normal TC 1 I/O read/write
C0h Verify 0 I/O read
C4h Verify TC 1 I/O read

The PC/PCI DMA as a PC Card-16 DMA mechanism may not provide the performance levels of DDMA;
however, the design of a PCI target implementing PC/PCI DMA is considerably less complex. No bus master
state machine is required to support PC/PCI DMA since the DMA control is centralized in the chipset. This DMA
scheme is often referred to as centralized DMA for this reason.

CardBus socket registers

The PCI1211 contains all registers for compatibility with the latest PCI-to-PCMCIA CardBus bridge
specification. These registers exist as the CardBus socket registers, and are listed in Table 9.

Table 9. CardBus Socket Registers

REGISTER NAME OFFSET

Socket event 00h
Socket mask 04h
Socket present state 08h
Socket force event 0Ch
Socket control 10h
Reserved 14h
Reserved 18h
Reserved 1Ch

Socket power management 20h

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29

PCI1211 GGU/PGE
PC CARD CONTROLLERS

SCPS033A – OCTOBER 1998

serial bus interface

The PCI1211 provides a serial bus interface to accommodate loading subsystem identification and select
register defaults through a serial EEPROM. The PCI1211 serial bus interface is compatible with various I
SMBus components.

serial bus interface implementation

The PCI121 1 defaults to serial bus interface disabled. T o enable the serial interface, appropriate pullup resistors
must be implemented on the SDA and SCL signals, i.e., the MFUNC1 and MFUNC4 terminals. In addition,
pullup resistors must be implemented on VCCD0

and VCCD1. When the interface is detected, the SBDETECT

bit in the system control register is set. The SBDETECT bit is cleared by a write back of 1.
The PCI121 1 implements a two-pin serial interface with one clock signal (SCL) and one data signal (SDA). The

SCL signal is mapped to the MFUNC4 terminal and the SDA signal is mapped to the MFUNC1 terminal. The
PCI1211 drives SCL at nearly 100 kHz during data transfers, which is the maximum specified frequency for

VCCD0

VCCD1
MFUNC4
MFUNC1

2

C. Figure 8 illustrates an example application implementing the two-wire serial bus.

V

and

5 V

Serial

EEPROM

A2
A1
A0

CC

SCL
SDA

Pullup resistors are required
on the SCL and SDA signals.

Other Serial

Device

SCL

SDA

standard mode I

PCI1211

A weak (43 kW) pullup resistor
is implemented on VCCD0
VCCD1

terminals to enable the

serial EEPROM interface.

2

C and

Figure 8. Serial EEPROM Application

Some serial device applications may include PC Card power switches, ZV source switches, card ejectors, or
other devices that may enhance the user’s PC Card experience. The serial EEPROM device and PC Card power
switches are discussed in the sections that follow.

serial bus interface protocol

The SCL and SDA signals are bidirectional, open-drain signals and require pullup resistors as shown in
Figure 8. The PCI1211 supports up to 100 kb/s data transfer rate and is compatible with standard mode I
using seven-bit addressing.

All data transfers are initiated by the serial bus master. The beginning of a data transfer is indicated by a start
condition, which is signalled when the SDA line transitions to a low state while SCL is in the high state as
illustrated in Figure 9. The end of a requested data transfer is indicated by a stop condition, which is signalled
by a low-to-high transition of SDA while SCL is in the high state as shown in Figure 9. Data on SDA must remain
stable during the high state of the SCL signal as changes on the SDA signal during the high state of SCL is
interpreted as control signals, that is, a start or a stop condition.

2

C

30

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