PAL16L8AM, PAL16L8A-2M, PAL16R4AM, PAL16R4A-2M
PAL16R6AM, PAL16R6A-2M, PAL16R8AM, PAL16R8A-2M
STANDARD HIGH-SPEED PAL
SRPS016 – D2705, FEBRUARY 1984 – REVISED MARCH 1992
CIRCUITS
• Choice of Operating Speeds
High-Speed, A Devices . . . 25 MHz Min
Half-Power, A-2 Devices . . . 16 MHz Min
• Choice of Input/Output Configuration
• Package Options Include Both Ceramic DIP
and Chip Carrier in Addition to Ceramic
Flat Package
DEVICE
PAL16L8 10 2 0 6
PAL16R4 8 0 4 (3-state buffers) 4
PAL16R6 8 0 6 (3-state buffers) 2
PAL16R8 8 0 8 (3-state buffers) 0
I
INPUTS
description
These programmable array logic devices feature
high speed and a choice of either standard or
half-power devices. They combine Advanced
Low-Power Schottky technology with proven
titanium-tungsten fuses. These devices will
provide reliable, high-performance substitutes for
conventional TTL logic. Their easy
programmability allow for quick design of ”custom”
functions and typically results in a more compact
circuit board. In addition, chip carriers are
available for further reduction in board space.
The Half-Power versions offer a choice of
operating frequency, switching speeds, and
power dissipation. In many cases, these
Half-Power devices can result in significant power
reduction from an overall system level.
3-STATE
O OUTPUTS
REGISTERED
Q OUTPUTS
I/O
PORT
S
PAL16L8’
J OR W PACKAGE
(TOP VIEW)
I
1
I
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
GND
I
I
I
I
I
10
PAL16L8’
FK PACKAGE
(TOP VIEW)
I
I
3 2 1 20 19
4
5
6
7
8
910111213
I
GND
V
20
CC
O
19
I/O
18
I/O
17
I/O
16
15
I/O
14
I/O
13
I/O
12
O
11
I
CC
I
O
V
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I
O
I/O
The PAL16’ M series is characterized for
operation over the full military temperature range
of –55°C to 125°C.
PAL is a registered trademark of Advanced Micro Devices Inc.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1992, Texas Instruments Incorporated
1
PAL16R4AM, PAL16R4A-2M, PAL16R6AM, PAL16R6A-2M, PAL16R8AM, PAL16R8A-2M
STANDARD HIGH-SPEED PAL
SRPS016 – D2705, FEBRUARY 1984 – REVISED MARCH 1992
CIRCUITS
PAL16R4’
J OR W PACKAGE
(TOP VIEW)
CLK
1
I
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
GND
GND
10
PAL16R6’
J OR W PACKAGE
(TOP VIEW)
CLK
1
I
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
10
20
19
18
17
16
15
14
13
12
11
20
19
18
17
16
15
14
13
12
11
V
I/O
I/O
Q
Q
Q
Q
I/O
I/O
OE
V
I/O
Q
Q
Q
Q
Q
Q
I/O
OE
CC
CC
FK PACKAGE
3 2 1 20 19
I
4
I
5
I
6
I
7
I
8
910111213
FK PACKAGE
3 2 1 20 19
I
4
I
5
I
6
I
7
I
8
910111213
PAL16R4’
(TOP VIEW)
I
I
CLK
I
OE
GND
PAL16R6’
(TOP VIEW)
I
I
CLK
I
OE
GND
CC
V
I/O
CC
V
I/O
I/O
18
17
16
15
14
I/O
I/O
18
17
16
15
14
Q
I/O
Q
Q
Q
Q
Q
Q
Q
Q
Q
PAL16R8’
J OR W PACKAGE
(TOP VIEW)
CLK
1
I
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
GND
2
10
V
20
CC
Q
19
Q
18
Q
17
Q
16
15
Q
14
Q
13
Q
12
Q
11
OE
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
I
I
I
I
I
PAL16R8’
FK PACKAGE
(TOP VIEW)
I
I
CLK
3 2 1 20 19
4
5
6
7
8
910111213
I
OE
GND
CC
V
Q
Q
18
17
16
15
14
Q
Q
Q
Q
Q
Q
PAL16L8AM, PAL16L8A-2M, PAL16R4AM, PAL16R4A-2M
functional block diagrams (positive logic)
PAL16L8AM
PAL16L8A-2M
STANDARD HIGH-SPEED PAL
SRPS016 – D2705, FEBRUARY 1984 – REVISED MARCH 1992
CIRCUITS
OE
CLK
10 16
I
16 x
&
32 X 64
166
PAL16R4AM
PAL16R4A-2M
7
7
7
7
7
7
7
7
6
EN
≥1
O
O
I/O
I/O
I/O
I/O
I/O
I/O
EN 2
C1
denotes fused inputs
816
I
16 x
4
164
&
32 X 64
1D
I = 0
2
Q
Q
Q
Q
I/O
I/O
I/O
I/O
8
8
8
8
7
7
7
7
4
≥1
≥1
EN
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
PAL16R6AM, PAL16R6A-2M, PAL16R8AM, PAL16R8A-2M
STANDARD HIGH-SPEED PAL
SRPS016 – D2705, FEBRUARY 1984 – REVISED MARCH 1992
functional block diagrams (positive logic)
CIRCUITS
PAL16R6AM
PAL16R6A-2M
OE
CLK
816
I
16 x
6
162
&
32 X 64
PAL16R8AM
PAL16R8A-2M
EN 2
C1
1D
I = 0
2
Q
Q
Q
Q
Q
Q
I/O
I/O
8
8
8
8
8
8
7
7
2
≥1
≥1
EN
6
OE
CLK
denotes fused inputs
816
I
16 x
168
&
32 X 64
EN 2
C1
1D
I = 0
2
Q
Q
Q
Q
Q
Q
Q
Q
8
8
8
8
8
8
8
8
8
≥1
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1
I
First
Fuse
Numbers
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
I
0 4 8 12 16 20 24 28 31
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
Increment
PAL16L8AM, PAL16L8A-2M
STANDARD HIGH-SPEED PAL
SRPS016 – D2705, FEBRUARY 1984 – REVISED MARCH 1992
CIRCUITS
19
O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
I/O
12
O
11
I
Fuse number = First fuse number + Increment
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
PAL16R4AM, PAL16R4A-2M
STANDARD HIGH-SPEED PAL
SRPS016 – D2705, FEBRUARY 1984 – REVISED MARCH 1992
logic diagram (positive logic)
1
CLK
First
Fuse
Numbers
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
I
Fuse number = First fuse number + Increment
0 4812 16 20 24 28 31
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
CIRCUITS
Increment
I = 0
1D
I = 0
1D
I = 0
1D
I = 0
1D
C1
C1
C1
C1
19
18
17
16
15
14
13
12
11
I/O
I/O
Q
Q
Q
Q
I/O
I/O
OE
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1
CLK
First
Fuse
Numbers
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
I
Fuse number = First fuse number + Increment
0 4 8 12 16 20 24 28 31
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
Increment
PAL16R6AM, PAL16R6A-2M
STANDARD HIGH-SPEED PAL
SRPS016 – D2705, FEBRUARY 1984 – REVISED MARCH 1992
I = 0
1D
C1
I = 0
1D
C1
I = 0
1D
C1
I = 0
1D
C1
I = 0
1D
C1
I = 0
1D
C1
CIRCUITS
19
I/O
18
Q
17
Q
16
Q
15
Q
14
Q
13
Q
12
I/O
11
OE
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
PAL16R8AM, PAL16R8A-2M
STANDARD HIGH-SPEED PAL
SRPS016 – D2705, FEBRUARY 1984 – REVISED MARCH 1992
logic diagram (positive logic)
1
CLK
First
Fuse
Numbers
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
I
Fuse number = First fuse number + Increment
0 4 8 12 16 20 24 28 31
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
CIRCUITS
Increment
I = 0
1D
I = 0
1D
I = 0
1D
I = 0
1D
I = 0
1D
I = 0
1D
I = 0
1D
I = 0
1D
C1
C1
C1
C1
C1
C1
C1
C1
19
18
17
16
15
14
13
12
11
Q
Q
Q
Q
Q
Q
Q
Q
OE
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PAL16L8AM, PAL16L8A-2M, PAL16R4AM, PAL16R4A-2M
PAL16R6AM, PAL16R6A-2M, PAL16R8AM, PAL16R8A-2M
STANDARD HIGH-SPEED PAL
SRPS016 – D2705, FEBRUARY 1984 – REVISED MARCH 1992
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming T exas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
MIN NOM MAX UNIT
V
V
V
I
I
T
CC
IH
IL
OH
OL
A
Supply voltage 4.5 5 5.5 V
High-level input voltage 2 5.5 V
Low-level input voltage 0.8 V
High-level output current –2 mA
Low-level output current 12 mA
Operating free-air temperature –55 25 125 °C
CIRCUITS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
PAL16L8AM, PAL16R4AM, PAL16R6AM, PAL16R8AM
STANDARD HIGH-SPEED PAL
SRPS016 – D2705, FEBRUARY 1984 – REVISED MARCH 1992
electrical characteristics over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
V
OH
V
OL
I
OZH
I
OZL
I
I
I
IH
I
IL
I
OS
I
CC
Outputs 20
I/O ports 100
Outputs –20
I/O ports –100
I/O Ports 100
All others 25
OE input –0.2
All others –0.1
‡
timing requirements
VCC = 4.5 V, II = –18 mA –1.5 V
VCC = 4.5 V, IOH = –2 mA 2.4 3.2 V
VCC = 4.5 V, IOL = 12 mA 0.25 0.4 V
VCC = 5.5 V, VO = 2.7 V
VCC = 5.5 V, VO = 0.4 V
VCC = 5.5 V, VI = 5.5 V 0.2 mA
VCC = 5.5 V, VI = 2.7 V
VCC = 5.5 V, VI = 0.4 V
VCC = 5.5 V, VO = 0.5 V –30 –250 mA
VCC = 5.5 V, VI = 0, Outputs open 75 180 mA
CIRCUITS
µA
µA
µA
mA
MIN MAX UNIT
f
clock
t
w
t
su
t
h
NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, f
Clock Frequency 0 25 MHz
Pulse duration (see Note 2)
Setup time, input or feedback before CLK↑ 25 ns
Hold time, input or feedback after CLK↑ 0 ns
only for clock high or low, but not for both simultaneously.
Clock high 15
Clock low 20
. The minimum pulse durations specified are
clock
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
f
max
t
pd
t
pd
t
en
t
dis
t
en
t
dis
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set VO at 0.5 V to avoid
test equipment degradation.
FROM
(INPUT)
I, I/O O, I/O
CLK↑ Q R1 = 390 Ω, 10 20 ns
OE↓ Q R2 = 750 Ω, 15 25 ns
OE↑ Q See Figure 1 10 25 ns
I, I/O O, I/O 14 30 ns
I, I/O O, I/O 13 30 ns
TO
(OUTPUT)
TEST CONDITION MIN TYP†MAX UNIT
25 45 MHz
15 30 ns
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PAL16L8A-2M, PAL16R4A-2M, PAL16R6A-2M, PAL16R8A-2M
STANDARD HIGH-SPEED PAL
SRPS016 – D2705, FEBRUARY 1984 – REVISED MARCH 1992
electrical characteristics over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
V
OH
V
OL
I
OZH
I
OZL
I
I
I
IH
I
IL
I
OS
I
CC
Outputs 20
I/O ports 100
Outputs –20
I/O ports –100
I/O Ports 100
All others 25
OE input –0.2
All others –0.1
‡
timing requirements
VCC = 4.5 V, II = –18 mA –1.5 V
VCC = 4.5 V, IOH = –2 mA 2.4 3.2 V
VCC = 4.5 V, IOL = 12 mA 0.25 0.4 V
VCC = 5.5 V, VO = 2.7 V
VCC = 5.5 V, VO = 0.4 V
VCC = 5.5 V, VI = 5.5 V 0.2 mA
VCC = 5.5 V, VI = 2.7 V
VCC = 5.5 V, VI = 0.4 V
VCC = 5.5 V, VO = 0.5 V –30 –250 mA
VCC = 5.5 V, VI = 0, Outputs open 75 90 mA
CIRCUITS
µA
µA
µA
mA
MIN MAX UNIT
f
clock
t
w
t
su
t
h
NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, f
Clock Frequency 0 16 MHz
Pulse duration (see Note 2)
Setup time, input or feedback before CLK↑ 35 ns
Hold time, input or feedback after CLK↑ 0 ns
only for clock high or low, but not for both simultaneously.
Clock high 25
Clock low 25
. The minimum pulse durations specified are
clock
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
f
max
t
pd
t
pd
t
en
t
dis
t
en
t
dis
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set VO at 0.5 V to avoid
test equipment degradation.
FROM
(INPUT)
I, I/O O, I/O
CLK↑ Q R1 = 390 Ω, 11 25 ns
OE↓ Q R2 = 750 Ω, 20 25 ns
OE↑ Q See Figure 1 11 25 ns
I, I/O O, I/O 25 40 ns
I, I/O O, I/O 25 35 ns
TO
(OUTPUT)
TEST CONDITION MIN TYP†MAX UNIT
16 25 MHz
25 40 ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
PAL16L8AM, PAL16L8A-2M, PAL16R4AM, PAL16R4A-2M
PAL16R6AM, PAL16R6A-2M, PAL16R8AM, PAL16R8A-2M
STANDARD HIGH-SPEED PAL
SRPS016 – D2705, FEBRUARY 1984 – REVISED MARCH 1992
PARAMETER MEASUREMENT INFORMATION
CIRCUITS
From Output
Under Test
5 V
S1
R1
Test
Point
Timing
Input
t
su
Data
Input
Input
t
pd
In-Phase
Output
t
pd
Out-of-Phase
Output
(see Note D)
PROPAGATION DELAY TIMES
1.5 V
t
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
VOLTAGE WAVEFORMS
1.5 V
(see Note A)
h
t
pd
1.5 V
t
pd
C
L
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3 V
0
3 V
0
3 V
0
V
OH
V
OL
V
OH
V
OL
R2
High-Level
Pulse
Low-Level
Pulse
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
1.5 V 1.5 V
t
w
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.5 V 1.5 V
t
en
t
en
t
1.5 V
t
1.5 V
dis
dis
3 V
0
3 V
0
3 V
0
≈ 3.3 V
VOL + 0.5 V
V
OL
V
OH
VOH – 0.5 V
≈ 0 V
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for t
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR ≤ 10 MHz, tr and tf ≤ 2 ns, duty cycle = 50%
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
VOLTAGE WAVEFORMS
.
dis
Figure 1. Load Circuit and Voltage Waveforms
12 SRPS016
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICA TIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
Loading...