TEXAS INSTRUMENTS ONET4251PA Technical data

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1 Gbps to 4.25 Gbps Limiting Amplifier With LOS and RSSI

ONET4251PA

SLLS663A – SEPTEMBER 2005 – REVISED NOVEMBER 2005

FEATURES

• Polarity Select

• Multi-Rate Operation from 1 Gbps up to • Single 3.3-V Supply

4.25 Gbps

• Surface Mount Small Footprint 3-mm × 3-mm

• 89-mW Power Consumption 16-Pin QFN Package

• Input Offset Cancellation

• High Input Dynamic Range

• Output Disable

• CML Data Outputs

• Receive Signal Strength Indicator (RSSI)

APPLICATIONS

• Cable Driver and Receiver

• 1.0625 Gbps, 2.125 Gbps, and 4.25 Gbps Fibre

Channel Receivers

• Gigabit Ethernet Receivers

• Loss of Signal Detection

DESCRIPTION

The ONET4251PA is a versatile high-speed limiting amplifier for copper cable and fiber optic applications with data rates up to 4.25 Gbps.

This device provides a gain of about 50 dB, which ensures a full 800-mV input signal dynamic range.

The high input signal dynamic range ensures low jitter output signals even when overdriven with input signal swings as high as 1200 mV

p-p

The ONET4251PA comprises a loss of signal detection as well as a received signal strength indicator. The part is available in a small footprint 3-mm × 3-mm 16-pin QFN package. It requires a single 3.3-V supply. This power efficient limiting amplifier dissipates less than 89 mW typical. It is characterized for operation from

–40 ° C to 85 ° C.

differential output swing over its wide

p-p

BLOCK DIAGRAM

A simplified block diagram of the ONET4251PA is shown in Figure 1 . This compact 3.3 V, low power 4.25 Gbps limiting amplifier consists of a high-speed data path with offset

cancellation block, a loss of signal and RSSI detection block, and a bandgap voltage reference and bias current generation block.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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Input Buffer

DOUT+ DOUT−

DIN+ DIN−

Gain Stage

++ +

COC2 COC1

DISABLE LOS

VCC

GND

OUTPOL

Bandgap Voltage

Reference and

Bias Current

Generation

Gain Stage Gain Stage

Loss of Signal

and

RSSI Detection

Offset

Cancellation

−

RSSI

CML

Output

Buffer

Stage

− − − −

B0052-01

ONET4251PA

SLLS663A – SEPTEMBER 2005 – REVISED NOVEMBER 2005

Figure 1. Simplified Block Diagram of the ONET4251PA

HIGH SPEED DATA PATH

The high-speed data signal is applied to the data path by means of the input signal pins DIN+/DIN–. The data path consists of the input stage with 2 × 50- Ω on-chip line termination to VCC, three gain stages, which provide the required typical gain of about 50 dB, and a CML output stage. The amplified data output signal is available at the output pins DOUT+/DOUT–, which provide 2 × 50- Ω back-termination to VCC. The output stage also includes a data polarity switching function, which is controlled by the OUTPOL input, and a disable function, controlled by the signal applied to the DISABLE input pin.

An offset cancellation compensates for internal offset voltages and thus ensures proper operation even for very small input data signals.

The low frequency cutoff is typically as low as 50 kHz with the built-in filter capacitor. For applications which require even lower cutoff frequencies, an additional external filter capacitor may be

connected to the COC1/COC2 pins.

LOSS OF SIGNAL AND RSSI DETECTION

The output signal of the input buffer is monitored by the loss of signal and RSSI detection circuitry. In this block, a signal is generated that is linear proportional to the input amplitude over a wide input voltage range. This signal is available at the RSSI output pin.

Furthermore, this circuit block compares the input signal to a threshold which can be programmed by means of an external resistor connected to the TH pin. If the input signal falls below the specified threshold, a loss of signal is indicated at the LOS pin.

The relation between the LOS assert voltage V the TH pin can be approximated as given below:

(in mV

AST

) and the external resistor R

p-p

(in k Ω ) connected to

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

22.4 k



AST

mV

pp

 1



 560 

AST



22.4 mV

pp

RTHk  0.56

 1 mV

pp

GND

COC2

COC1

RSSI

1 2 3 4

VCC

DIN+

DIN−

VCC

RGT PACKAGE

(TOP VIEW)

12 11 10 9

VCC DOUT+ DOUT− OUTPOL

15 14 13

5 6 7 8

DISABLE

LOS

GND

P0019-01

ONET4251PA

SLLS663A – SEPTEMBER 2005 – REVISED NOVEMBER 2005

BANDGAP VOLTAGE AND BIAS GENERATION

The ONET4251PA limiting amplifier is supplied by a single 3.3-V ± 10% supply voltage connected to the VCC pins. This voltage is referred to ground (GND).

An on-chip bandgap voltage circuitry generates a supply voltage independent reference from which all other internally required voltages and bias currents are derived.

PACKAGE

For the ONET4251PA a small footprint 3-mm × 3-mm 16-pin QFN package, with a lead pitch of 0,5 mm is used. The pin out is shown in Figure 2 .

(1)

(2)

NO. NAME

1, 4, 12 VCC supply 3.3-V ± 10% supply voltage 2 DIN+ analog-in Non-inverted data input. On-chip 50- Ω terminated to VCC. 3 DIN- analog-in Inverted data input. On-chip 50- Ω terminated to VCC. 5 TH analog-in LOS threshold adjustment with resistor to GND. 6 DISABLE CMOS-in Disables CML output stage when set to high level. 7 LOS CMOS-out High level indicates that the input signal amplitude is below the programmed threshold level. 8, 16, EP GND supply Circuit ground. Exposed die pad (EP) must be grounded.

9 OUTPOL CMOS-in 10 DOUT- CML-out Inverted data output. On-chip 50- Ω back-terminated to VCC.

11 DOUT+ CML-out Non-inverted data output. On-chip 50- Ω back-terminated to VCC

TERMINAL

Figure 2. Pinout of ONET4251PA in a 3 mm x 3 mm 16-Pin QFN Package (Top View)

TERMINAL FUNCTIONS

TYPE DESCRIPTION

Output data signal polarity select (internally pulled high). Setting to a high level or leaving the pin open selects normal polarity. Low level selects inverted polarity.

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ONET4251PA

SLLS663A – SEPTEMBER 2005 – REVISED NOVEMBER 2005

TERMINAL FUNCTIONS (continued)

TERMINAL

NO. NAME

13 RSSI analog-out

14 COC1 analog and COC2 (pin 15).

15 COC2 analog and COC1 (pin 14).

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

, V

DIN+

DIN-

VTH, V V

DOUT–

COC,DIFF

DIN,DIFF

LOS

, I

DIN+

ESD ESD rating at all pins 2 kV (HBM) T

J(max)

STG

LEAD

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

, V

DISABLE

, V

RSSI

, I

DIN–

, V

LOS

, V

COC1

, I

DOUT+

DOUT–

TYPE DESCRIPTION

Analog output voltage proportional to the input data amplitude. Indicates the strength of the received signal (RSSI).

Offset cancellation filter capacitor terminal 1. Connect an additional filter capacitor between this pin To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15).

Offset cancellation filter capacitor terminal 2. Connect an additional filter capacitor between this pin To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15).

(1)

VALUE/UNIT

Supply voltage Voltage at DIN+, DIN–

, V

OUTPOL

COC2

, Voltage at TH, DISABLE, LOS, OUTPOL, DOUT+, DOUT-, RSSI, –0.3 V to 4 V

DOUT+

COC1, COC2

(2)

–0.3 V to 4 V

0.5 V to 4 V

Differential voltage between COC1 and COC2 ±1 V Differential voltage between DIN+ and DIN– ±2.5 V Current into LOS – 1 to 9 mA Continuous current at inputs and outputs –25 mA to 25 mA

Maximum junction temperature 125°C Storage temperature range –65 to 85°C Characterized free-air operating temperature range –40 to 85°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C

RECOMMENDED OPERATING CONDITIONS

Supply voltage 3.0 3.3 3.6 V Operating free-air temperature –40 85 ° C CMOS input high voltage 2.1 V CMOS input low voltage 0.6 V

MIN TYP MAX UNIT

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ONET4251PA

SLLS663A – SEPTEMBER 2005 – REVISED NOVEMBER 2005

DC ELECTRICAL CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VCC

RIN, R

RSSI

IN(MIN)

IN(MAX)

AC ELECTRICAL CHARACTERISTICS

over recommended operating conditions (unless otherwise noted), typical operating condition is at V

DJ Deterministic jitter K28.5 pattern at 2.125 Gbps 8 22 ps

RJ Random jitter Input = 50 mVpp 1 ps t

AST

DEA

LOS

DIS

Supply voltage 3 3.3 3.6 V Supply current DISABLE = low (excludes CML output current) 27 40 mA

Differential data output voltage swing mV

Data input/output resistance Single-ended 50 Ω

OUT

RSSI output voltage mV

RSSI Linearity 8 mV

DISABLE = high 0.25 10 DISABLE = low 600 760 1200

Input = 8 mV Input = 80 mV

p-p

≤ VIN≤ 80 mV

, R

≥ 10 k Ω 180

RSSI

, R

p-p

≥ 10 k Ω 1900

RSSI

p-p

± 3% Minimum data input voltage 50 mV Data input overload 1200 mV LOS high voltage I LOS low voltage I

= 30 µA 2.4 V

SOURCE

= 1 mA 0.4 V

SINK

= 3.3 V and TA= 25 ° C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

= open 50

Low frequency –3 dB bandwidth kHz

= 0.1 µF 0.8

Data rate 4.25 Gb/s Input referred noise 230 µV

K28.5 pattern at 4.25 Gbps 6 19

K28.5 pattern at 1.0625 Gbps 11 28

Output rise time 20% to 80% 35 70 ps Output fall time 20% to 80% 35 70 ps LOS hysteresis K28.5 pattern at 4.25 Gbps 2.5 4.5 dB LOS threshold adjustment resistor See LOS assert voltage R LOS deassert voltage R

(1)

= 4 k Ω K28.5 pattern at 4.25 Gbps 3 7 mV

= 4 k Ω K28.5 pattern at 4.25 Gbps 11 50 mV

4 k Ω

LOS assert/deassert time 2 100 µs Disable response time 20 ns

p-p

p-p p-p

RMS

p-p

RMS

p-p p-p

(1) For a given external resistor connected to the TH pin, the LOS assert voltage value may vary due to part-to-part variations. If high

precision is required, adjustment of this resistor for each device is mandatory.

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t − Time − 50 ps/Div

− Differential Output Voltage − 160 mV/Div

G005

t − Time − 50 ps/Div

− Differential Output Voltage − 160 mV/Div

G006

t − Time − 50 ps/Div

− Differential Output Voltage − 160 mV/Div

G007

f − Frequency − MHz

Small Signal Gain − dB

10 10k100 1k

G004

ONET4251PA

SLLS663A – SEPTEMBER 2005 – REVISED NOVEMBER 2005

Typical operating condition is at V

OUTPUT EYE-DIAGRAM AT 4.25 GBPS OUTPUT EYE-DIAGRAM AT 4.25 GBPS

AND MINIMUM INPUT VOLTAGE (50 mV

TYPICAL CHARACTERISTICS

= 3.3 V and TA= 25 ° C (unless otherwise noted).

) AND MAXIMUM INPUT VOLTAGE (1200 mV

p-p

)

p-p

OUTPUT EYE-DIAGRAM AT 4.25 GBPS AND 85 ° C FREQUENCY RESPONSE

Figure 3. Figure 4.

AND MINIMUM INPUT VOLTAGE (50 mV

Figure 5. Figure 6.

)

p-p

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t − Time − 100 ps/Div

− Differential Output Voltage − 160 mV/Div

G008

t − Time − 100 ps/Div

− Differential Output Voltage − 160 mV/Div

G009

t − Time − 200 ps/Div

− Differential Output Voltage − 160 mV/Div

G010

t − Time − 200 ps/Div

− Differential Output Voltage − 160 mV/Div

G011

Typical operating condition is at V

OUTPUT EYE-DIAGRAM AT 2.125 GBPS OUTPUT EYE-DIAGRAM AT 2.125 GBPS

AND MINIMUM INPUT VOLTAGE (50 mV

TYPICAL CHARACTERISTICS (continued)

= 3.3 V and TA= 25 ° C (unless otherwise noted).

) AND MAXIMUM INPUT VOLTAGE (1200 mV

p-p

ONET4251PA

SLLS663A – SEPTEMBER 2005 – REVISED NOVEMBER 2005

)

p-p

Figure 7. Figure 8.

OUTPUT EYE-DIAGRAM AT 1.0625 GBPS OUTPUT EYE-DIAGRAM AT 1.0625 GBPS

AND MINIMUM INPUT VOLTAGE (50 mV

) AND MAXIMUM INPUT VOLTAGE (1200 mV

p-p

Figure 9. Figure 10.

)

p-p

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RTH − Threshold Resistance − kΩ

0 1 2 3 4 5 6 7 8

LOS Deassert Voltage

LOS Assert Voltage

G012

LOS Assert/Deassert Voltage − mV

P-P

−60

−55

−50

−45

−40

−35

−30

−25

−20

−15

−10

−5

SDD11 − Differential Input Return Gain − dB

f − Frequency − MHz

G013

10 10k100 1k

−60

−55

−50

−45

−40

−35

−30

−25

−20

−15

−10

−5

SDD22 − Differential Input Return Gain − dB

f − Frequency − MHz

G014

10 10k100 1k

VID − Differential Input Voltage − mV

P-P

200

400

600

800

1000

1200

1400

1600

1800

2000

2200

2400

0 10 20 30 40 50 60 70 80 90 100

RSSI − Receive Signals Strength Indicator Voltage − mV

G015

ONET4251PA

SLLS663A – SEPTEMBER 2005 – REVISED NOVEMBER 2005

TYPICAL CHARACTERISTICS (continued)

Typical operating condition is at V

ASSERT/DEASSERT VOLTAGE DIFFERENTIAL INPUT RETURN GAIN

vs THRESHOLD RESISTANCE vs FREQUENCY

= 3.3 V and TA= 25 ° C (unless otherwise noted).

DIFFERENTIAL OUTPUT RETURN GAIN RSSI VOLTAGE

vs FREQUENCY vs INPUT AMPLITUDE

Figure 11. Figure 12.

Figure 13. Figure 14.

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VCC DIN+

DIN−

DISABLE

LOS

DOUT−

DOUT+

GND

DIN+ DIN−

DOUT−

DOUT+

GND

VCC

OUTPOL

VCC

RSSI

LOS

DISABLE

ONET4251PA

16-Pin QFN

COC2

COC1

OUTPOL

RSSI

Optional

S0072-01

Optional connection for squelch function

ONET4251PA

SLLS663A – SEPTEMBER 2005 – REVISED NOVEMBER 2005

APPLICATION INFORMATION

Figure 15 shows the ONET4251PA connected with an ac-coupled interface to the data signal source as well as

to the output load. Besides the ac-coupling capacitors C

external component is the LOS threshold setting resistor R an option, an external filter capacitor C

through C

may be used.

in the input and output data signal lines, the only required

. In addition, if a low cutoff frequency is required, as

Figure 15. Basic Application Circuit With AC Coupled I/Os

PACKAGE OPTION ADDENDUM

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4-Nov-2005

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

ONET4251PARGTR ACTIVE QFN RGT 16 3000 Green (RoHS &

no Sb/Br)

ONET4251PARGTRG4 ACTIVE QFN RGT 16 3000 Green (RoHS &

no Sb/Br)

ONET4251PARGTT ACTIVE QFN RGT 16 250 Green (RoHS &

no Sb/Br)

ONET4251PARGTTG4 ACTIVE QFN RGT 16 250 Green (RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-2-260C-1 YEAR

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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TEXAS INSTRUMENTS ONET4251PA Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual