TEXAS INSTRUMENTS MSP430xG461x Technical data
MSP430xG461x
V
V
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
D Low Supply-
oltage Range, 1.8Vto 3.6
D Ultralow-Power Consumption:
-- Active Mode: 400 μAat1MHz,2.2V
-- Standby Mode: 1.3 μA
-- Off Mode (RAM Retention): 0.22 μA
D Five Power-Saving Modes
D Wake-Up From Standby Mode in Less
Than 6 μs
D 16-Bit RISC Architecture, Extended
Memory, 125-ns Instruction Cycle Time
D Three Channel Internal DMA
D 12-Bit A/D Converter With Internal
Reference, Sample-and -Hold and Autoscan
Feature
D Three Configurable Operational Amplifiers
D Dual 12-Bit D/A Converters With
Synchronization
D 16-Bit Timer_A With Three
Capture/Compare Registers
D 16-Bit Timer_B With Seven
Capture/Compare-With-Shadow Registers
D On-Chip Comparator
D Supply Voltage Supervisor/Monitor With
Programmable Level Detection
D Serial Communication Interface (USART1),
Select Asynchronous UART or
Synchronous SPI by Software
D Universal Serial Communication Interface
-- Enhanced UART Supporting
Auto-Baudrate Detection
-- IrDA Encoder and Decoder
-- Synchronous SPI
TM
-- I 2 C
D Serial Onboard Programming,
Programmable Code Protection by Security
Fuse
D Brownout Detector
D Basic Timer With Real Time Clock Feature
D Integrated LCD Driver up to 160 Segments
With Regulated Charge Pump
D Family Members Include:
-- MSP430xG4616:
92KB+256B Flash or ROM Memory
4KB RAM
-- MSP430xG4617:
92KB+256B Flash or ROM Memory,
8KB RAM
-- MSP430xG4618:
116KB+256B Flash or ROM Memory,
8KB RAM
-- MSP430xG4619:
120KB+256B Flash or ROM Memory,
4KB RAM
D For Complete Module Descriptions, Refer
to the MSP430x4xx Family User’s Guide
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 6 μs.
The MSP430xG461x series are microcontroller configurations with two 16-bit timers, a high-performance 12-bit
A/D converter, dual 12-bit D/A converters, three configurable operational amplifiers, one universal serial
communication interface (USCI), one universal synchronous/asynchronous communication interface
(USART), DMA, 80 I/O pins, and a liquid crystal display (LCD) driver with regulated charge pump.
Typical applications for this device include portable medical applications and e-meter applications.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
T
A
-- 4 0 °Cto85°C
PLASTIC 100-PIN TQFP
AVAILABLE OPTIONS
PACKAGED DEVICES
(PZ)
MSP430FG4616IPZ MSP430FG4616IZQW
MSP430FG4617IPZ MSP430FG4617IZQW
MSP430FG4618IPZ MSP430FG4618IZQW
MSP430FG4619IPZ MSP430FG4619IZQW
MSP430CG4616IPZ MSP430CG4616IZQW
MSP430CG4617IPZ MSP430CG4617IZQW
MSP430CG4618IPZ MSP430CG4618IZQW
MSP430CG4619IPZ MSP430CG4619IZQW
PLASTIC 113-BALL BGA
(ZQW)
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
pin designation, MSP430xG461xIPZ
SS1
CCAVSS
P6.1/A1/OA0O
P6.2/A2/OA0I1
AV
96
97
98
30
29
28
DV
P6.3/A3/OA1O
P6.4/A4/OA1I0
P6.5/A5/OA2O
P6.6/A6/DAC0/OA2I0
P6.7/A7/DAC1/SVSIN
VeREF+/DAC0
VREF--/VeREF--
P5.1/S0/A12/DAC1
P5.0/S1/A13/OA1I1
P10.7/S2/A14/OA2I1
P10.6/S3/A15
CC1
VREF+
XIN
XOUT
P10.5/S4
P10.4/S5
P10.3/S6
P10.2/S7
P10.1/S8
P10.0/S9
P9.7/S10
P9.6/S11
P9.5/S12
P9.4/S13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100
26
DV
99
27
P6.0/A0/OA0I0
RST/NMI
TCK
TMS
92
93
94
95
MSP430xG4616IPZ
MSP430xG4617IPZ
MSP430xG4618IPZ
MSP430xG4619IPZ
34
33
32
31
XT2IN
TDI/TCLK
TDO/TDI
89
90
91
37
36
35
XT2OUT
88
38
P1.0/TA0
P1.1/TA0/MCLK
86
87
40
39
MIXED SIGNAL MICROCONTROLLER
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
84
42
83
43
P1.5/TACLK/ACLK
82
44
P1.2/TA1
85
41
MSP430xG461x
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
P1.7/CA1
P1.6/CA0
P2.0/TA2
79
80
81
47
46
45
P2.3/TB2
P2.1/TB0
P2.2/TB1
76
77
78
50
49
48
75
P2.4/UCA0TXD
74
P2.5/UCA0RXD
73
P2.6/CAOUT
72
P2.7/ADC12CLK/DMAE0
71
P3.0/UCB0STE
70
P3.1/UCB0SIMO/UCB0SDA
69
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK
68
P3.4/TB3
67
P3.5/TB4
66
P3.6/TB5
65
P3.7/TB6
64
P4.0/UTXD1
63
P4.1/URXD1
62
DV
61
60
59
58
57
56
55
54
53
52
51
SS2
DV
CC2
LCDCAP/R33
P5.7/R23
P5.6/LCDREF/R13
P5.5/R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P4.2/STE1/S39
P9,2/S15
P9.1/S16
P9.3/S14
P9.0/S17
P8.6/S19
P8.7/S18
P8.5/S20
P8.4/S21
P8.3/S22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
P8.0/S25
P8.1/S24
P8.2/S23
P7.7/S26
P7.6/S27
P7.5/S28
P7.4/S29
P7.3/UCA0CLK/S30
P7.2/UCA0SOMI/S31
P4.4/SOMI1/S37
P4.3/SIMO1/S38
P4.5/UCLK1/S36
P7.0/UCA0STE/S33
P4.6/UCA0TXD/S35
P4.7/UCA0RXD/S34
P7.1/UCA0SIMO/S32
3
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
pin designation, MSP430xG461xIZQW (top view)
A
B
C
D
E
F
G
H
J
K
L
M
12345 6789101112
NOTE: For terminal assignments, see the MSP430xG461x Terminal Functions table.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
XIN/
XT2IN
Oscillators
FLL+
8MH z
CPUX
incl. 16
Registers
Enhanced
Emulation
(FG only)
JTAG
Interface
XOUT/
XT2OUT
22
MCLK
ACLK
SMCLK
DVCC1/2 DVSS1/2
Flash(FG)
ROM(CG)
120kB
116k B
92kB
92kB
MAB
MDB
Brownout
Protection
SVS/ SVM
RST/NMI
RAM
4kB
8kB
8kB
4kB
Hardware
Multiplier
MPY,
MPYS,
MAC,
MACS
AVC C AVSS P1.x/P2.x
ADC12
12--Bit
12
Channels
Watchdog
WDT+
15/16--Bit
DAC12
12--Bit
2 Channels
Voltage out
Timer _A3
3CC
Registers
OA0, OA1,
OA2
3OpAmps
Timer_B7
7CC
Registers,
Shadow
Reg
Comparator
_A
Basic Timer
Real--Time
Clock
Ports P1/P2
2x8 I/O
Interrupt
capability
LCD_A
&
Segments
1, 2, 3 ,4 Mux
160
2x8
P3 .x/P4.x
P5 .x/P6.x
Ports
P3/P4
P5/P6
4x8 I/O
USCI_A0:
UART,
IrDA, SPI
USCI_B0:
SPI, I2C
4x8
P7.x/P8.x
P9.x/P 10.x
4x8/2x16
Ports
P7/ P8
P9/P10
4x8 / 2x16 I/O
USART1
UART, SPI
DMA
Controller
3 Channels
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
Terminal Functions
TERMINAL
NAME
DV
CC1
P6.3/A3/OA1O 2 B1 I/O General-purpose digital I/O / analog input a3—12-bit ADC / OA1 output
P6.4/A4/OA1I0 3
P6.5/A5/OA2O 4 C2 I/O General-purpose digital I/O / analog input a5—12-bit ADC / OA2 output
P6.6/A6/DAC0/OA2I0 5
P6.7/A7/DAC1/SVSIN 6 C3 I/O
V
REF+
XIN 8 D1 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT 9 E1 O Output terminal of crystal oscillator XT1
Ve
/DAC0 10 E2 I/O Input for an external reference voltage to the ADC / DAC12.0 output
REF+
V
/Ve
REF--
REF--
P5.1/S0/A12/DAC1 (see Note 1) 12 F1 I/O
P5.0/S1/A13/OA1I1 (see Note 1) 13 F2 I/O
P10.7/S2/A14/OA2I1 (see Note 1) 14 E5 I/O
P10.6/S3/A15 (see Note 1) 15 G1 I/O
P10.5/S4 16 G2 I/O General-purpose digital I/O / LCD segment output 4
P10.4/S5 17 F4 I/O General-purpose digital I/O / LCD segment output 5
P10.3/S6 18 H1 I/O General-purpose digital I/O / LCD segment output 6
P10.2/S7 19 H2 I/O General-purpose digital I/O / LCD segment output 7
P10.1/S8 20 F5 I/O General-purpose digital I/O / LCD segment output 8
P10.0/S9 21 J1 I/O General-purpose digital I/O / LCD segment output 9
P9.7/S10 22 J2 I/O General-purpose digital I/O / LCD segment output 10
P9.6/S11 23 G4 I/O General-purpose digital I/O / LCD segment output 11
P9.5/S12 24 K1 I/O General-purpose digital I/O / LCD segment output 12
P9.4/S13 25 L1 I/O General-purpose digital I/O / LCD segment output 13
P9.3/S14 26 M2 I/O General-purpose digital I/O / LCD segment output 14
P9.2/S15 27 K2 I/O General-purpose digital I/O / LCD segment output 15
P9.1/S16 28 L3 I/O General-purpose digital I/O / LCD segment output 16
P9.0/S17 29 M3 I/O General-purpose digital I/O / LCD segment output 17
P8.7/S18 30 H4 I/O General-purpose digital I/O / LCD segment output 18
P8.6/S19 31 L4 I/O General-purpose digital I/O / LCD segment output 19
P8.5/S20 32 M4 I/O General-purpose digital I/O / LCD segment output 20
P8.4/S21 33 G5 I/O General-purpose digital I/O / LCD segment output 21
P8.3/S22 34 L5 I/O General-purpose digital I/O / LCD segment output 22
NOTES: 1. Segments S0 through S3 are disabled when the LCD charge pump feature is enabled (LCDCPEN = 1) and cannot be used together
with the LCD charge pump. In addition, when using segments S0 through S3 with an external LCD voltage supply, V
NO.PZNO.
ZQW
1 A1 Digital supply voltage, positive terminal
7 D2 O Output of positive terminal of the reference voltage in the ADC
11 E4 I
I/O DESCRIPTION
I/O General-purpose digital I/O / analog input a4—12-bit ADC / OA1 input multiplexer
B2
C1
on +terminal and -- terminal
I/O General-purpose digital I/O / analog input a6—12-bit ADC / DAC12.0 output / OA2
input multiplexer on +terminal and --terminal
General-purpose digital I/O / analog input a7—12-bit ADC / DAC12.1 output /
analog input to brownout, supply voltage supervisor
Negative terminal for the ADC reference voltage for both sources, the internal
reference voltage, or an external applied reference voltage
General-purpose digital I/O / LCD segment output 0 / analog input a12 -- 12--bit
ADC / DAC12.1 output
General-purpose digital I/O / LCD segment output 1 / analog input a13 -- 12--bit
ADC/OA1 input multiplexer on +terminal and --terminal
General-purpose digital I/O / LCD segment output 2 / analog input a14 -- 12--bit
ADC/OA2 input multiplexer on +terminal and --terminal
General-purpose digital I/O / LCD segment output 3 / analog input a15 -- 12--bit
ADC
LCD
≤ AVCC.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
Terminal Functions (Continued)
TERMINAL
NAME
P8.2/S23 35 M5 I/O General-purpose digital I/O / LCD segment output 23
P8.1/S24 36 H5 I/O General-purpose digital I/O / LCD segment output 24
P8.0/S25 37 J5 I/O General-purpose digital I/O / LCD segment output 25
P7.7/S26 38 M6 I/O General-purpose digital I/O / LCD segment output 26
P7.6/S27 39 L6 I/O General-purpose digital I/O / LCD segment output 27
P7.5/S28 40 J6 I/O General-purpose digital I/O / LCD segment output 28
P7.4/S29 41 M7 I/O General-purpose digital I/O / LCD segment output 29
P7.3/UCA0CLK/S30 42 H6 I/O
P7.2/UCA0SOMI/S31 43 L7 I/O
P7.1/UCA0SIMO/S32 44 M8 I/O
P7.0/UCA0STE/S33 45 L8 I/O
P4.7/UCA0RXD/S34 46 J7 I/O
P4.6/UCA0TXD/S35 47 M9 I/O
P4.5/UCLK1/S36 48 L9 I/O
P4.4/SOMI1/S37 49 H7 I/O
P4.3/SIMO1/S38 50 M10 I/O
P4.2/STE1/S39 51 M11 I/O
COM0 52 L10 O COM0--3 are used for LCD backplanes.
P5.2/COM1 53 L12 I/O General-purpose digital I/O / common output, COM0--3 are used for LCD backplanes.
P5.3/COM2 54 J8 I/O General-purpose digital I/O / common output, COM0--3 are used for LCD backplanes.
P5.4/COM3 55 K12 I/O General-purpose digital I/O / common output, COM0--3 are used for LCD backplanes.
P5.5/R03 56 K11 I/O General-purpose digital I/O / Input port of lowest analog LCD level (V5)
P5.6/LCDREF/R13 57 J12 I/O
P5.7/R23 58 J11 I/O General-purpose digital I/O / Input port of second most positive analog LCD level (V2)
LCDCAP/R33 59 H11 I LCD capacitor connection / Input/output port of most positive analog LCD level (V1)
DV
CC2
DV
SS2
P4.1/URXD1 62 G1 1 I/O General-purpose digital I/O / receive data in—USART1/UART mode
P4.0/UTXD1 63 H9 I/O General-purpose digital I/O / transmit data out—USART1/UART mode
P3.7/TB6 64 F12 I/O
P3.6/TB5 65 F11 I/O
P3.5/TB4 66 G9 I/O
NO.PZNO.
ZQW
60 H12 Digital supply voltage, positive terminal
61 G12 Digital supply voltage, negative terminal
I/O DESCRIPTION
General-purpose digital I/O / external clock input -- USCI_A0/UART or SPI mode, clock
output -- USCI_A0/SPI mode / LCD segment 30
General-purpose digital I/O / slave out/master in of USCI_A0/SPI mode / LCD segment
output 31
General-purpose digital I/O / slave in/master out of USCI_A0/SPI mode / LCD segment
output 32
General-purpose digital I/O / slave transmit enable—USCI_A0/SPI mode / LCD segment
output 33
General-purpose digital I/O / receive data in -- USCI_A0/UART or IrDA mode / LCD
segment output 34
General-purpose digital I/O / transmit data out -- USCI_A0/UART or IrDA mode / LCD
segment output 35
General-purpose digital I/O / external clock input -- USART1/UART or SPI mode,
clock output -- USART1/SPI MODE / LCD segment output 36
General-purpose digital I/O / slave out/master in of USART1/SPI mode / LCD segment
output 37
General-purpose digital I/O / slave in/master out of USART1/SPI mode / LCD segment
output 38
General-purpose digital I/O / slave transmit enable—USART1/SPI mode / LCD segment
output 39
General-purpose digital I/O / External reference voltage input for regulated LCD voltage
/ Input port of third most positive analog LCD level (V4 or V3)
General-purpose digital I/O / Timer_B7 CCR6. Capture: CCI6A/CCI6B input, compare:
Out6 output
General-purpose digital I/O / Timer_B7 CCR5. Capture: CCI5A/CCI5B input, compare:
Out5 output
General-purpose digital I/O / Timer_B7 CCR4. Capture: CCI4A/CCI4B input, compare:
Out4 output
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
Terminal Functions (Continued)
TERMINAL
NAME
P3.4/TB3 67 E12 I/O
P3.3/UCB0CLK 68 E11 I/O
P3.2/UCB0SOMI/
UCB0SCL
P3.1/UCB0SIMO/
UCB0SDA
P3.0/UCB0STE 71 D11 I/O General-purpose digital I/O / slave transmit enable—USCI_B0/SPI mode
P2.7/ADC12CLK/
DMAE0
P2.6/CAOUT 73 C12 I/O General -purpose digital I/O / Comparator_A output
P2.5/UCA0RXD 74 C11 I/O General-purpose digital I/O / receive data in—USCI_A0/UART or IrDA mode
P2.4/UCA0TXD 75 B12 I/O General-purpose digital I/O / transmit data out—USCI_A0/UART or IrDA mode
P2.3/TB2 76 A11 I/O
P2.2/TB1 77 E8 I/O
P2.1/TB0 78 D8 I/O
P2.0/TA2 79 A10 I/O General-purpose digital I/O / Timer_A Capture: CCI2A input, compare: Out2 output
P1.7/CA1 80 B10 I/O General-purpose digital I/O / Comparator_A input
P1.6/CA0 81 A9 I/O General-purpose digital I/O / Comparator_A input
P1.5/TACLK/ACLK 82 B9 I/O
P1.4/TBCLK/SMCLK 83 B8 I/O
P1.3/TBOUTH/SVSOUT 84 A8 I/O
P1.2/TA1 85 D7 I/O General-purpose digital I/O / Timer_A, Capture: CCI1A input, compare: Out1 output
P1.1/TA0/MCLK 86 E7 I/O
P1.0/TA0 87 A7 I/O
XT2OUT 88 B7 O Output terminal of crystal oscillator XT2
XT2IN 89 B6 I Input port for crystal oscillator XT2. Only standard crystals can be connected.
TDO/TDI 90 A6 I/O Test data output port. TDO/TDI data output or programming data input terminal
TDI/TCLK 91 D6 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TMS 92 E6 I Test mode select. TMS is used as an input port for device programming and test.
TCK 93 A5 I Test clock. TCK is the clock input port for device programming and test.
RST/NMI 94 B5 I Reset input or nonmaskable interrupt input port
P6.0/A0/OA0I0 95 A4 I/O
P6.1/A1/OA0O 96 D5 I/O General-purpose digital I/O / analog input a1—12-bit ADC / OA0 output
P6.2/A2/OA0I1 97 B4 I/O
NO.PZNO.
ZQW
69 F9 I/O
70 D12 I/O
72 E9 I/O General-purpose digital I/O / conversion clock—12-bit ADC / DMA Channel 0 external trigger
I/O DESCRIPTION
General-purpose digital I/O / Timer_B7 CCR3. Capture: CCI3A/CCI3B input, compare: Out3
output
General-purpose digital I/O / external clock input—USCI_B0/UART or SPI mode, clock
output—USCI_B0/SPI mode
General-purpose digital I/O / slave out/master in of USCI_B0/SPI mode /I2C
clock—USCI_B0/I2C mode
General-purpose digital I/O / slave in/master out of USCI_B0/SPI mode, I2C
data—USCI_B0/I2C mode
General-purpose digital I/O / Timer_B7 CCR2. Capture: CCI2A/CCI2B input, compare: Out2
output
General-purpose digital I/O / Timer_B7 CCR1. Capture: CCI1A/CCI1B input, compare: Out1
output
General-purpose digital I/O / Timer_B7 CCR0. Capture: CCI0A/CCI0B input, compare: Out0
output
General-purpose digital I/O / Timer_A, clock signal TACLK input / ACLK output (divided by
1, 2, 4, or 8)
General-purpose digital I/O / input clock TBCLK—Timer_B7 / submain system clock SMCLK
output
General-purpose digital I/O / switch all PWM digital output ports to high
impedance—Timer_B7 TB0 to TB6 / SVS: output of SVS comparator
General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK output.
Note: TA0 is only an input on this pin / BSL receive
General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL
transmit
General-purpose digital I/O / analog input a0—12-bit ADC / OA0 input multiplexer on
+ terminal and -- terminal
General-purpose digital I/O / analog input a2—12-bit ADC / OA0 input multiplexer on
+ terminal and -- terminal
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
Terminal Functions (Continued)
TERMINAL
NAME
AV
SS
DV
(see Note 1) 99 B3 Digital supply voltage, negative terminal
SS1
AV
CC
NOTE 1: All unassigned ball locations on the ZQW package should be electrically tied to the ground supply. The shortest ground return path to
the device should be established via ball location B3.
NO.PZNO.
ZQW
98 A3
100 A2
I/O DESCRIPTION
Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator,comparator_A,
port 1
Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, comparator_A,
port 1; must not power up prior to DV
CC1
/DV
CC2
.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
The MSP430xG461x device family utilizes the
MSP430X CPU and is completely backwards
compatible with the MSP430 CPU. For a complete
description of the MSP430X CPU, refer to the
MSP430x4xx Family User’s Guide.
instruction set
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the
expanded address range. Each instruction can
operate on word and byte data. Table 1 shows
examples of the three types of instruction formats;
the address modes are listed in Table 2.
Program Counter
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
Table 1. Instruction Word Formats
Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 ------> R5
Single operands, destination only e.g., CALL R8 PC ---->(TOS), R8----> PC
Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE S D SYNTAX EXAMPLE OPERATION
Register F
Indexed F F MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)—> M(6+R6)
Symbolic (PC relative) F F MOV EDE,TONI M(EDE) —> M(TONI)
Absolute F F MOV&MEM,&TCDAT M(MEM) —> M(TCDAT)
Indirect F MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) —> M(Tab+R6)
Indirect
autoincrement
Immediate F MOV #X,TONI MOV #45,TONI #45 —> M(TONI)
NOTE: S = source D = destination
F
F MOV @Rn+,Rm MOV @R10+,R11
MOV Rs,Rd MOV R10,R11 R10 —> R11
M(R10) —> R11
R10 + 2—> R10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
operating modes
The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D Active mode (AM)
-- All clocks are active
D Low-power mode 0 (LPM0)
-- CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
FLL+ loop control remains active
D Low-power mode 1 (LPM1)
-- CPU is disabled
FLL+ loop control is disabled
ACLK and SMCLK remain active. MCLK is disabled
D Low-power mode 2 (LPM2)
-- CPU is disabled
MCLK, FLL+ loop control and DCOCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D Low-power mode 3 (LPM3)
-- CPU is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
D Low-power mode 4 (LPM4)
-- CPU is disabled
ACLK is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430xG461x
ReservedReserved(seeNote4
)
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
interrupt vector addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FFC0h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 3. Interrupt Sources, Flags, and Vectors of MSP430xG461x Configurations
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT
Power-Up
External Reset
Watchdog
Flash Memory
NMI
Oscillator Fault
Flash Memory Access Violation
Timer_B7 TBCCR0 CCIFG0 (see Note 2) Maskable 0FFFAh 29
Timer_B7
Comparator_A CAIFG Maskable 0FFF6h 27
Watchdog Timer+ WDTIFG Maskable 0FFF4h 26
USCI_A0/USCI_B0 Receive UCA0RXIFG, UCB0RXIFG (see Note 1) Maskable 0FFF2h 25
USCI_A0/USCI_B0 Transmit UCA0TXIFG, UCB0TXIFG (see Note 1) Maskable 0FFF0h 24
ADC12 ADC12IFG (see Notes 1 and 2) Maskable 0FFEEh 23
Timer_A3 TACCR0 CCIFG0 (see Note 2) Maskable 0FFECh 22
Timer_A3
I/O Port P1 (Eight Flags) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) Maskable 0FFE8h 20
USART1 Receive URXIFG1 Maskable 0FFE6h 19
USART1 Transmit UTXIFG1 Maskable 0FFE4h 18
I/O Port P2 (Eight Flags) P2IFG.0 to P2IFG.7 (see Notes 1 and 2) Maskable 0FFE2h 17
Basic Timer1/RTC BTIFG Maskable 0FFE0h 16
DMA DMA0IFG, DMA1IFG, DMA2IFG
DAC12 DAC12.0IFG, DAC12.1IFG (see Notes 1 and 2) Maskable 0FFDCh 14
Reserved Reserved (see Note 4)
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh).
(Non)maskable: the individual interrupt -enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
4. The interrupt vectors at addresses 0FFDAh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
5. Access and key violations, KEYV and ACCVIFG, only applicable to F devices.
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1, 2, and 5)
TBCCR1 CCIFG1 ... TBCCR6 CCIFG6,
TBIFG (see Notes 1 and 2)
TACCR1 CCIFG1 and TACCR2 CCIFG2,
TAIFG (see Notes 1 and 2)
WDTIFG
KEYV
(see Note 1 and 5)
(see Notes 1 and 2)
Reset 0FFFEh 31, highest
(Non)maskable
(Non)maskable
(Non)maskable
Maskable 0FFF8h 28
Maskable 0FFEAh 21
Maskable 0FFDEh 15
WORD
ADDRESS
0FFFCh 30
0FFDAh 13
... ...
0FFC0h 0, lowest
PRIORITY
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
special function registers (SFRs)
The MSP430 SFRs are located in the lowest address space and are organized as byte mode registers. SFRs
should be accessed with byte instructions.
interrupt enable 1 and 2
Address
0h ACCVIE NMIIE
WDTIE Watchdog-timer interrupt enable. Inactive if watchdog mode is selected.
OFIE Oscillator-fault-interrupt enable
NMIIE Nonmaskable-interrupt enable
ACCVIE Flash access violation interrupt enable
Address
01h
UCA0RXIE USCI_A0 receive-interrupt enable
UCA0TXIE USCI_A0 transmit-interrupt enable
UCB0RXIE USCI_B0 receive-interrupt enable
UCB0TXIE USCI_B0 transmit-interrupt enable
URXIE1 USART1 UART and SPI receive-interrupt enable
UTXIE1 USART1 UART and SPI transmit-interrupt enable
BTIE Basic timer interrupt enable
7654 0
rw–0
Active if watchdog timer is configured as a general-purpose timer.
7654 032 1
BTIE UTXIE1 URXIE1
rw–0
rw–0 rw–0
rw–0 rw–0 rw–0
32 1
UCB0TXIE UCB0RXIE
rw–0 rw–0
OFIE WDTIE
UCA0TXIE UCA0RXIE
rw–0 rw–0
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
interrupt flag register 1 and 2
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
Address
02h NMIIFG
WDTIFG: Set on watchdog timer overflow (in watchdog mode) or security key violation
OFIFG: Flag set on oscillator fault
NMIIFG: Set via RST
Address
03h
UCA0RXIFG USCI_A0 receive-interrupt flag
UCA0TXIFG USCI_A0 transmit-interrupt flag
UCB0RXIFG USCI_B0 receive-interrupt flag
UCB0TXIFG USCI_B0 transmit-interrupt flag
URXIFG0: USART1: UART and SPI receive flag
UTXIFG0: USART1: UART and SPI transmit flag
BTIFG: Basic timer flag
7654 0
rw–0 rw–1 rw–(0)
Reset on V
7654 032 1
BTIFG
rw–0
power-on or a reset condition at the RST/NMI pin in reset mode
CC
/NMI pin
UTXIFG1 URXIFG1
rw–1 rw–0
32 1
UCB0TXIFG UCB0RXIFG
rw–0 rw–0
module enable registers 1 and 2
Address
04h
7654 032 1
OFIFG WDTIFG
UCA0TXIFG UCA0RXIFG
rw–0 rw–0
Address
05h
URXE1: USART1: UART mode receive enable
UTXE1: USART1: UART mode transmit enable
USPIE1: USART1: SPI mode transmit and receive enable
Legend rw:
7654 0
rw-0,1:
rw-(0,1):
UTXE1
rw–0 rw–0
Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device
URXE1
USPIE1
32 1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
15
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
memory organization
MSP430FG4616 MSP430FG4617 MSP430FG4618 MSP430FG4619
Memory
Main: interrupt vector
Main: code memory
RAM (Total) Size 4KB
Extended Size 2KB
Mirrored Size 2KB
Information memory Size
Boot memory Size
RAM
(mirrored at
018FFh -- 01100h)
Peripherals 16 bit
Size
Flash
Flash
Flash
ROM
Size 2KB
8bit
8-bit SFR
018FFFh -- 002100h
92KB
0FFFFh -- 0FFC0h
020FFh -- 01100h
020FFh -- 01900h
018FFh -- 01100h
256 Byte
010FFh -- 01000h
1KB
0FFFh -- 0C00h
09FFh -- 0200h
01FFh -- 0100h
0FFh -- 010h
0Fh -- 00h
92KB
0FFFFh -- 0FFC0h
019FFFh -- 003100h
8KB
030FFh -- 01100h
6KB
030FFh -- 01900h
2KB
018FFh -- 01100h
256 Byte
010FFh -- 01000h
1KB
0FFFh -- 0C00h
2KB
09FFh -- 0200h
01FFh -- 0100h
0FFh -- 010h
0Fh -- 00h
116KB
0FFFFh -- 0FFC0h
01FFFFh -- 003100h
8KB
030FFh -- 01100h
6KB
030FFh -- 01900h
2KB
018FFh -- 01100h
256 Byte
010FFh -- 01000h
1KB
0FFFh -- 0C00h
2KB
09FFh -- 0200h
01FFh -- 0100h
0FFh -- 010h
0Fh -- 00h
120KB
0FFFFh -- 0FFC0h
01FFFFh -- 002100h
4KB
020FFh -- 01100h
2KB
020FFh -- 01900h
2KB
018FFh -- 01100h
256 Byte
010FFh -- 01000h
1KB
0FFFh -- 0C00h
2KB
09FFh -- 0200h
01FFh -- 0100h
0FFh -- 010h
0Fh -- 00h
MSP430CG4616 MSP430CG4617 MSP430CG4618 MSP430CG4619
Memory
Main: interrupt vector
Main: code memory
RAM (Total) Size 4KB
Extended Size 2KB
Mirrored Size 2KB
Information memory Size
Boot memory
(Optional on CG)
RAM
(mirrored at
018FFh -- 01100h)
Peripherals 16 bit
Size
ROM
ROM
ROM
Size
ROM
Size 2KB
8bit
8-bit SFR
018FFFh -- 002100h
92KB
0FFFFh -- 0FFC0h
020FFh -- 01100h
020FFh -- 01900h
018FFh -- 01100h
256 Byte
010FFh -- 01000h
1KB
0FFFh -- 0C00h
09FFh -- 0200h
01FFh -- 0100h
0FFh -- 010h
0Fh -- 00h
92KB
0FFFFh -- 0FFC0h
019FFFh -- 003100h
8KB
030FFh -- 01100h
6KB
030FFh -- 01900h
2KB
018FFh -- 01100h
256 Byte
010FFh -- 01000h
1KB
0FFFh -- 0C00h
2KB
09FFh -- 0200h
01FFh -- 0100h
0FFh -- 010h
0Fh -- 00h
116KB
0FFFFh -- 0FFC0h
01FFFFh -- 003100h
8KB
030FFh -- 01100h
6KB
030FFh -- 01900h
2KB
018FFh -- 01100h
256 Byte
010FFh -- 01000h
1KB
0FFFh -- 0C00h
2KB
09FFh -- 0200h
01FFh -- 0100h
0FFh -- 010h
0Fh -- 00h
120KB
0FFFFh -- 0FFC0h
01FFFFh -- 002100h
4KB
020FFh -- 01100h
2KB
020FFh -- 01900h
2KB
018FFh -- 01100h
256 Byte
010FFh -- 01000h
1KB
0FFFh -- 0C00h
2KB
09FFh -- 0200h
01FFh -- 0100h
0FFh -- 010h
0Fh -- 00h
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
bootstrap loader (BSL)
The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access
to the MSP430 memory via the BSL is protected by user-defined password. A bootstrap loader security key is
provided at address 0FFBEh to disable the BSL completely or to disable the erasure of the flash if an invalid
password is supplied. The BSL is optional for ROM-based devices. For complete description of the features of
the BSL and its implementation, see the application report Features of the MSP430 Bootstrap Loader, literature
number SLAA089.
BSLKEY DESCRIPTION
00000h Erasure of flash disabled if an invalid password is supplied
0AA55h BSL disabled
any other value BSL enabled
BSL FUNCTION PZ/ZQW PACKAGE PINS
Data Transmit 87/A7 -- P1.0
Data Receive 86/E7 -- P1.1
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A and B can be erased individually, or as a group with segments 0--n.
Segments A and B are also called information memory.
D New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
17
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s Guide.
DMA controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to
or from a peripheral.
oscillator and system clock
The clock system in the MSP430xG461x family of devices is supported by the FLL+ module, which includes
support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO), and a high
frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system
cost and low-power consumption. The FLL+ features digital frequency locked loop (FLL) hardware that, in
conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch
crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 μs. The
FLL+ module provides the following clock signals:
D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency c rystal
D Main clock (MCLK), the system clock used by the CPU
D Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules
D ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8
brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on
and power-off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, V
have ramped to V
reaches V
CC(min)
CC(min)
. If desired, the SVS circuit can be used to determine when VCCreaches V
at that time. The user must insure the default FLL+ settings are not changed until V
CC(min)
digital I/O
There are ten 8-bit I/O ports implemented—ports P1 through P10:
D All individual I/O bits are independently programmable.
D Any combination of input, output, and interrupt conditions is possible.
D Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
D Read/write access to port-control registers is supported by all instructions.
D Ports P7/P8 and P9/P10 can be accessed word-wise as ports PA and PB respectively.
CC
.
may not
CC
Basic Timer1 and Real-Time Clock
The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. Basic Timer1 is extended to provide an integrated real-time clock
(RTC). An internal calendar compensates for months with less than 31 days and includes leap-year correction.
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
LCD_A drive with regulated charge pump
The LCD_A driver generates the segment and common signals required to drive an LCD display. The LCD_A
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
The module can provide a LCD voltage independent of the supply voltage with its integrated charge pump.
Furthermore it is possible to control the level of the LCD voltage and, thus, contrast by software.
watchdog timer (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.
universal serial communication interface (USCI)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols like SPI (3 or 4 pin), I2C and asynchronous communication protocols like UART,
enhanced UART with automatic baudrate detection, and IrDA.
The USCI_A0 module provides support for SPI (3 or 4 pin), UART, enhanced UART and IrDA.
The USCI_B0 module provides support for SPI (3 or 4 pin) and I2C.
USART1
The hardware universal synchronous/asynchronous receive transmit (USART) peripheral module is used for
serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART
communication protocols, using double-buffered transmit and receive channels.
hardware multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs 16×16,
16×8, 8×16, and 8×8 bit operations. The module is capable of supporting signed and unsigned multiplication,
as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
19
MSP430xG461x
DeviceInput
ModuleInput
Modul
e
ModuleOutpu
t
A
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input Pin Number
PZ/ZQW
82/B9 - P1.5 TA C L K TA C L K
82/B9 - P1.5 TACLK INCLK
87/A7 - P1.0 TA0 CCI0A
86/E7 - P1.1 TA0 CCI0B
85/D7 - P1.2 TA1 CCI1A
79/A10 - P2.0 TA 2 CCI2A
Device Input Module Input Module Module Output
Signal
ACLK ACLK
SMCLK SMCLK
DV
SS
DV
CC
CAOUT (internal) CCI1B
DV
SS
DV
CC
ACLK (internal) CCI2B
DV
SS
DV
CC
Name
GND
V
CC
GND
V
CC
GND
V
CC
Block
Timer N
CCR0 TA0
CCR1 TA1
CCR2 TA2
Signal
Output Pin Number
PZ/ZQW
87/A7 - P1.0
85/D7 - P1.2
ADC12 (internal)
79/A10 - P2.0
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430xG461x
DeviceInput
ModuleInput
Modul
e
ModuleOutpu
t
A
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
timer_B7
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_B7 Signal Connections
Input Pin Number
PZ/ZQW
Device Input Module Input Module Module Output
Signal
83/B8 - P1.4 TBCLK TBCLK
ACLK ACLK
SMCLK SMCLK
83/B8 - P1.4 TBCLK INCLK
78/D8 - P2.1 TB0 CCI0A
78/D8 - P2.1 TB0 CCI0B
DV
SS
DV
CC
77/E8 - P2.2 TB1 CCI1A
77/E8 - P2.2 TB1 CCI1B
DV
SS
DV
CC
76/A11 - P2.3 TB2 CCI2A
76/A11 - P2.3 TB2 CCI2B
DV
SS
DV
CC
67/E12 - P3.4 TB3 CCI3A
67/E12 - P3.4 TB3 CCI3B
DV
SS
DV
CC
66/G9 - P3.5 TB4 CCI4A
66/G9 - P3.5 TB4 CCI4B
DV
SS
DV
CC
65/F11 - P3.6 TB5 CCI5A
65/F11 - P3.6 TB5 CCI5B
DV
SS
DV
CC
64/F12 - P3.7 TB6 CCI6A
ACLK (internal) CCI6B
DV
SS
DV
CC
Name
GND
V
CC
GND
V
CC
GND
V
CC
GND
V
CC
GND
V
CC
GND
V
CC
GND
V
CC
Block
Signal
Timer N
CCR0 TB0
CCR1 TB1
CCR2 TB2
CCR3 TB3
CCR4 TB4
CCR5 TB5
CCR6 TB6
Output Pin Number
PZ/ZQW
78/D8 - P2.1
ADC12 (internal)
77/E8 - P2.2
ADC12 (internal)
76/A11 - P2.3
67/E12 - P3.4
66/G9 - P3.5
65/F11 - P3.6
64/F12 - P3.7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
21
MSP430xG461x
p
p
Outpu
t
Outpu
t
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
comparator_A
The primary function of the comparator_A module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
ADC12
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator and a 16 word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without
any CPU intervention.
DAC12
The DAC12 module is a 12-bit, R-ladder, voltage output DAC. The DAC12 may be used in 8- or 12-bit mode,
and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may
be grouped together for synchronous operation.
OA
The MSP430xG461x has three configurable low-current general-purpose operational amplifiers. Each OA input
and output terminal is software-selectable and offer a flexible choice of connections for various applications.
The OA op amps primarily support front-end analog signal conditioning prior to analog-to-digital conversion.
Input Pin
Number
PZ
95 - P6.0 OA0I0 OA0I0
97 - P6.2 OA0I1 OA0I1
3- P6.4 OA1I0 OA1I0
13 - P5.0 OA1I1 OA1I1
5-P6.6 OA2I0 OA2I0
14 - P10.7 OA2I1 OA2I1
Device Input
Signal Name Block
DAC12_0OUT
(internal)
DAC12_1OUT
(internal)
DAC12_0OUT
(internal)
DAC12_1OUT
(internal)
DAC12_0OUT
(internal)
DAC12_1OUT
(internal)
Module Input
DAC12_0OUT
DAC12_1OUT
DAC12_0OUT
DAC12_1OUT
DAC12_0OUT
DAC12_1OUT
OA Signal Connections
Module
OA0 OA0OUT
OA1 OA1OUT
OA2 OA2OUT
Module
Out
ut
Signal
Device
Out
ut
Signal
OA0O 96 - P6.1
OA0O ADC12 (internal)
OA1O 2-P6.3
OA1O 13- P5.0
OA1O ADC12 (internal)
OA2O 4-P6.5
OA2O 14 - P10.7
OA2O ADC12 (internal)
Output Pin
Number
PZ
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map
_
_
Watchdog+ Watchdog timer control WDTCTL 0120h
Timer_B7
Timer_A3
Hardware
Multiplier
Flash
(FG devices only)
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
PERIPHERALS WITH W ORD ACCESS
Capture/compare register 6 TBCCR6 019Eh
Capture/compare register 5 TBCCR5 019Ch
Capture/compare register 4 TBCCR4 019Ah
Capture/compare register 3 TBCCR3 0198h
Capture/compare register 2 TBCCR2 0196h
Capture/compare register 1 TBCCR1 0194h
Capture/compare register 0 TBCCR0 0192h
Timer_B register TBR 0190h
Capture/compare control 6 TBCCTL6 018Eh
Capture/compare control 5 TBCCTL5 018Ch
Capture/compare control 4 TBCCTL4 018Ah
Capture/compare control 3 TBCCTL3 0188h
Capture/compare control 2 TBCCTL2 0186h
Capture/compare control 1 TBCCTL1 0184h
Capture/compare control 0 TBCCTL0 0182h
Timer_B control TBCTL 0180h
Timer_B interrupt vector TBIV 011Eh
Capture/compare register 2 TACCR2 0176h
Capture/compare register 1 TACCR1 0174h
Capture/compare register 0 TACCR0 0172h
Timer_A register TAR 0170h
Capture/compare control 2 TACCTL2 0166h
Capture/compare control 1 TACCTL1 0164h
Capture/compare control 0 TACCTL0 0162h
Timer_A control TAC T L 0160h
Timer_A interrupt vector TAI V 012Eh
Sum extend SUMEXT 013Eh
Result high word RESHI 013Ch
Result low word RESLO 013Ah
Second operand OP2 0138h
Multiply signed + accumulate/operand1 MACS 0136h
Multiply + accumulate/operand1 MAC 0134h
Multiply signed/operand1 MPYS 0132h
Multiply unsigned/operand1 MPY 0130h
Flash control 3 FCTL3 012Ch
Flash control 2 FCTL2 012Ah
Flash control 1 FCTL1 0128h
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
23
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
peripheral file map (continued)
PERIPHERALS WITH WORD ACCESS (CONTINUED)
DMA
DMA Channel 0
DMA Channel 1
DMA Channel 2
DMA module control 0 DMACTL0 0122h
DMA module control 1 DMACTL1 0124h
DMA interrupt vector DMAIV 0126h
DMA channel 0 control DMA0CTL 01D0h
DMA channel 0 source address DMA0SA 01D2h
DMA channel 0 destination address DMA0DA 01D6h
DMA channel 0 transfer size DMA0SZ 01DAh
DMA channel 1 control DMA1CTL 01DCh
DMA channel 1 source address DMA1SA 01DEh
DMA channel 1 destination address DMA1DA 01E2h
DMA channel 1 transfer size DMA1SZ 01E6h
DMA channel 2 control DMA2CTL 01E8h
DMA channel 2 source address DMA2SA 01EAh
DMA channel 2 destination address DMA2DA 01EEh
DMA channel 2 transfer size DMA2SZ 01F2h
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map (continued)
SeealsoPeripheral
s
y
PERIPHERALS WITH WORD ACCESS (CONTINUED)
ADC12
See also Peripherals
With Byte Access
DAC12
Port PA
Port PB
Conversion memory 15 ADC12MEM15 015Eh
Conversion memory 14 ADC12MEM14 015Ch
Conversion memory 13 ADC12MEM13 015Ah
Conversion memory 12 ADC12MEM12 0158h
Conversion memory 11 ADC12MEM11 0156h
Conversion memory 10 ADC12MEM10 0154h
Conversion memory 9 ADC12MEM9 0152h
Conversion memory 8 ADC12MEM8 0150h
Conversion memory 7 ADC12MEM7 014Eh
Conversion memory 6 ADC12MEM6 014Ch
Conversion memory 5 ADC12MEM5 014Ah
Conversion memory 4 ADC12MEM4 0148h
Conversion memory 3 ADC12MEM3 0146h
Conversion memory 2 ADC12MEM2 0144h
Conversion memory 1 ADC12MEM1 0142h
Conversion memory 0 ADC12MEM0 0140h
Interrupt-vector-word register ADC12IV 01A8h
Inerrupt-enable register ADC12IE 01A6h
Inerrupt-flag register ADC12IFG 01A4h
Control register 1 ADC12CTL1 01A2h
Control register 0 ADC12CTL0 01A0h
DAC12_1 data DAC12_1DAT 01CAh
DAC12_1 control DAC12_1CTL 01C2h
DAC12_0 data DAC12_0DAT 01C8h
DAC12_0 control DAC12_0CTL 01C0h
Port PA selection PASEL 03Eh
Port PA direction PAD I R 03Ch
Port PA output PA OUT 03Ah
Port PA input PAI N 038h
Port PB selection PBSEL 00Eh
Port PB direction PBDIR 00Ch
Port PB output PBOUT 00Ah
Port PB input PBIN 008h
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
25
MSP430xG461x
)
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS
OA2 Operational Amplifier 2 control register 1
Operational Amplifier 2 control register 0
OA1 Operational Amplifier 1 control register 1
Operational Amplifier 1 control register 0
OA0 Operational Amplifier 0 control register 1
Operational Amplifier 0 control register 0
LCD_A LCD Voltage Control 1
LCD Voltage Control 0
LCD Voltage Port Control 1
LCD Voltage Port Control 0
LCD memory 20
:
LCD memory 16
LCD memory 15
:
LCD memory 1
LCD control and mode
ADC12
(Memory control
registers require byte
access
USART1
ADC memory-control register 15 ADC12MCTL15 08Fh
ADC memory-control register 14 ADC12MCTL14 08Eh
ADC memory-control register 13 ADC12MCTL13 08Dh
ADC memory-control register 12 ADC12MCTL12 08Ch
ADC memory-control register 11 ADC12MCTL11 08Bh
ADC memory-control register 10 ADC12MCTL10 08Ah
ADC memory-control register 9 ADC12MCTL9 089h
ADC memory-control register 8 ADC12MCTL8 088h
ADC memory-control register 7 ADC12MCTL7 087h
ADC memory-control register 6 ADC12MCTL6 086h
ADC memory-control register 5 ADC12MCTL5 085h
ADC memory-control register 4 ADC12MCTL4 084h
ADC memory-control register 3 ADC12MCTL3 083h
ADC memory-control register 2 ADC12MCTL2 082h
ADC memory-control register 1 ADC12MCTL1 081h
ADC memory-control register 0 ADC12MCTL0 080h
Transmit buffer U1TXBUF 07Fh
Receive buffer U1RXBUF 07Eh
Baud rate U1BR1 07Dh
Baud rate U1BR0 07Ch
Modulation control U1MCTL 07Bh
Receive control U1RCTL 07Ah
Transmit control U1TCTL 079h
USART control U1CTL 078h
OA2CTL1
OA2CTL0
OA1CTL1
OA1CTL0
OA0CTL1
OA0CTL0
LCDAVCTL1
LCDAVCTL0
LCDAPCTL1
LCDAPCTL0
LCDM20
:
LCDM16
LCDM15
:
LCDM1
LCDCTL
0C5h
0C4h
0C3h
0C2h
0C1h
0C0h
0AFh
0AEh
0ADh
0ACh
0A4h
:
0A0h
09Fh
:
091h
090h
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map (continued)
p
_
(
)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
USCI
Comparator_A
BrownOUT, SVS SVS control register (Reset by brownout signal) SVSCTL 056h
FLL+Clock
RTC (Basic Timer 1)
USCI I2C Slave Address UCBI2CSA 011Ah
USCI I2C Own Address UCBI2COA 0118h
USCI Synchronous Transmit Buffer UCBTXBUF 06Fh
USCI Synchronous Receive Buffer UCBRXBUF 06Eh
USCI Synchronous Status UCBSTAT 06Dh
USCI I2C Interrupt Enable UCBI2CIE 06Ch
USCI Synchronous Bit Rate 1 UCBBR1 06Bh
USCI Synchronous Bit Rate 0 UCBBR0 06Ah
USCI Synchronous Control 1 UCBCTL1 069h
USCI Synchronous Control 0 UCBCTL0 068h
USCI Transmit Buffer UCATXBUF 067h
USCI Receive Buffer UCARXBUF 066h
USCI Status UCASTAT 065h
USCI Modulation Control UCAMCTL 064h
USCI Baud Rate 1 UCABR1 063h
USCI Baud Rate 0 UCABR0 062h
USCI Control 1 UCACTL1 061h
USCI Control 0 UCACTL0 060h
USCI IrDA Receive Control UCAIRRCTL 05Fh
USCI IrDA Transmit Control UCAIRTCTL 05Eh
USCI LIN Control UCAABCTL 05Dh
Comparator_A port disable CAPD 05Bh
Comparator_A control 2 CACTL2 05Ah
Comparator_A control 1 CACTL1 059h
FLL+ Control 1 FLL_CTL1 054h
FLL+ Control 0 FLL_CTL0 053h
System clock frequency control SCFQCTL 052h
System clock frequency integrator SCFI1 051h
System clock frequency integrator SCFI0 050h
Real Time Clock Year High Byte RTCYEARH 04Fh
Real Time Clock Year Low Byte RTCYEARL 04Eh
Real Time Clock Month RTCMON 04Dh
Real Time Clock Day of Month RTCDAY 04Ch
Basic Timer1 Counter 2 BTCNT2 047h
Basic Timer1 Counter 1 BTCNT1 046h
Real Time Counter 4
(Real Time Clock Day of Week)
Real Time Counter 3
(Real Time Clock Hour)
Real Time Counter 2
(Real Time Clock Minute)
Real Time Counter 1
(Real Time Clock Second)
Real Time Clock Control RTCCTL 041h
Basic Timer1 Control BTCTL 040h
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
RTCNT4
(RTCDOW)
RTCNT3
(RTCHOUR)
RTCNT2
(RTCMIN)
RTCNT1
(RTCSEC)
045h
044h
043h
042h
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
27
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
Port P10 Port P10 selection P10SEL 00Fh
Port P10 direction P10DIR 00Dh
Port P10 output P10OUT 00Bh
Port P10 input P10IN 009h
Port P9 Port P9 selection P9SEL 00Eh
Port P9 direction P9DIR 00Ch
Port P9 output P9OUT 00Ah
Port P9 input P9IN 008h
Port P8 Port P8 selection P8SEL 03Fh
Port P8 direction P8DIR 03Dh
Port P8 output P8OUT 03Bh
Port P8 input P8IN 039h
Port P7 Port P7 selection P7SEL 03Eh
Port P7 direction P7DIR 03Ch
Port P7 output P7OUT 03Ah
Port P7 input P7IN 038h
Port P6
Port P5
Port P4
Port P3
Port P2
Port P1
Port P6 selection P6SEL 037h
Port P6 direction P6DIR 036h
Port P6 output P6OUT 035h
Port P6 input P6IN 034h
Port P5 selection P5SEL 033h
Port P5 direction P5DIR 032h
Port P5 output P5OUT 031h
Port P5 input P5IN 030h
Port P4 selection P4SEL 01Fh
Port P4 direction P4DIR 01Eh
Port P4 output P4OUT 01Dh
Port P4 input P4IN 01Ch
Port P3 selection P3SEL 01Bh
Port P3 direction P3DIR 01Ah
Port P3 output P3OUT 019h
Port P3 input P3IN 018h
Port P2 selection P2SEL 02Eh
Port P2 interrupt enable P2IE 02Dh
Port P2 interrupt -edge select P2IES 02Ch
Port P2 interrupt flag P2IFG 02Bh
Port P2 direction P2DIR 02Ah
Port P2 output P2OUT 029h
Port P2 input P2IN 028h
Port P1 selection P1SEL 026h
Port P1 interrupt enable P1IE 025h
Port P1 interrupt -edge select P1IES 024h
Port P1 interrupt flag P1IFG 023h
Port P1 direction P1DIR 022h
Port P1 output P1OUT 021h
Port P1 input P1IN 020h
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map (continued)
p
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
Special functions
SFR module enable 2 ME2 005h
SFR module enable 1 ME1 004h
SFR interrupt flag 2 IFG2 003h
SFR interrupt flag 1 IFG1 002h
SFR interrupt enable 2 IE2 001h
SFR interrupt enable 1 IE1 000h
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
29
MSP430xG461x
(
2
)
kHz
f
(Sy
)
Processorfrequency(signalMCLK),
f
(System
)
MHz
MIXED SIGNAL MICROCONTROLLER
SLAS508G -- APRIL 2006 -- REVISED OCTOBER 2007
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Voltage range applied at VCCto V
Voltage range applied to any pin (see Note) --0.3 V to V
SS
†
--0.3 V to 4.1 V................................................
+0.3V...................................
CC
Diode current at any device terminal . ±2mA......................................................
Storage temperature range, T
: Unprogrammed device --55°C to 150°C...........................
stg
Programmed device --40°Cto85°C...............................
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to V
to the TDI/TCLK pin when blowing the JTAG fuse.
The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied
SS.
recommended operating conditions
MIN NOM MAX UNITS
Supply voltage during program execution (see Note 1),
V
(AVCC=DV
CC
Supply voltage during flash memory programming (see Note 1),
V
(AVCC=DV
CC
Supply voltage during program execution,
SVS enabled and PORON = 1 (see Note 1 and Note 2),
V
(AVCC=DV
CC
Supply voltage (see Note 1), VSS(AVSS=DV
Operating free-air temperature range, T
LFXT1 crystal frequency, f
seeNote
XT2 crystalfrequency,
Processor frequency (signal MCLK), f
NOTES: 1. It is recommended to power AVCCand DVCCfrom the s ame source. A maximum difference of 0.3 V between AVCCand DVCCcan
CC1/2=VCC
CC1/2=VCC
CC1/2=VCC
be tolerated during power up and operation.
2. The minimum operating s upply voltage is defined according to the trip point where POR is going active by decreasing the supply
voltage. POR is going inactive when the supply voltage is raised above the minimum supply voltage plus the hysteresis of the SVS
circuitry.
3. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
(XT2)
)
)
)
(LFXT1)
SS1/2=VSS
A
LF selected, XTS_FLL = 0 Watch crystal 32.768
XT1 selected, XTS_FLL = 1 Ceramic resonator 450 8000
XT1 selected, XTS_FLL = 1 Crystal 1000 8000
stem
) 0 0 V
MSP430xG461x 1.8 3.6 V
MSP430FG461x 2.7 3.6 V
MSP430xG461x 2 3.6 V
MSP430xG461x -- 4 0 85 °C
kHz
Ceramic resonator 450 8000
Crystal 1000 8000
VCC=1.8V DC 3.0
VCC=2.0V DC 4.6
VCC=3.6V DC 8.0
kHz
MHz
f
(MHz)
System
8.0 MHz
4.6 MHz
3.0 MHz
Supply voltage range,
MSP430xG461x, during
program execution
1.8 3.62.7 3
2.0
Supply Voltage -- V
Supply voltage range, MSP430FG461x,
during flash memory programming
Figure 1. Frequency vs Supply Voltage, Typical Characteristic
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Loading...