TEXAS INSTRUMENTS MSP430x31x Technical data

MSP430x31x

MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

D

Low Supply Voltage Range 2.5 V – 5.5 V

D

Ultra Low-Power Consumption

D

Low Operation Current, 400 µA at 1 MHz,
3V

D

Five Power Saving Modes: (Standby Mode:

1.3 µA, RAM Retention/Off Mode: 0.1 µA)

D

Wakeup From Standby Mode in 6 µs
Maximum

D

16-Bit RISC Architecture, 300 ns Instruction
Cycle Time

D

Single Common 32 kHz Crystal, Internal
System Clock up to 3.3 MHz

D

Integrated LCD Driver for up to 64 or 92
Segments

D

Slope A/D Converter With External
Components

D

Serial Onboard Programming

D

Program Code Protection by Security Fuse

D

Family Members Include:
MSP430C31 1S: 2k Byte ROM,128 Byte RAM
MSP430C312: 4k Byte ROM, 256 Byte RAM
MSP430C313: 8k Byte ROM, 256 Byte RAM
MSP430C314: 12k Byte ROM, 512 Byte RAM
MSP430C315: 16k Byte ROM, 512 Byte RAM
MSP430P313: 8k Byte OTP, 256 Byte RAM
MSP430P315: 16k Byte OTP, 512 Byte RAM
MSP430P315S: 16k Byte OTP, 512 ByteRAM

D

EPROM Version Available for Prototyping :

PMS430E313FZ†, PMS430E315FZ

D

Available in:
56-Pin Plastic Small-Outline Package
(SSOP),
48-Pin SSOP (MSP430C311S,
MSP430P315S),

TDO/TDI

TDI/VPP

TMS

TCK

/NMI

RST

XBUF

V

SS

V

CC

R23
R13

Xin

Xout/TCLK

P0.0

P0.1/RXD

P0.2/TXD

P0.3
P0.4
P0.5
P0.6

P0.7
TP0.0
TP0.1
TP0.2
TP0.3
TP0.4
TP0.5

CIN

NC

TDI/VPP

TMS

TCK

/NMI

RST

XBUF

V

SS

V

†

CC

R23
R13

Xin

Xout/TCLK

P0.1/RXD

P0.2/TXD

P0.3

P0.4

P0.5

P0.6

NC
TP0.0
TP0.1
TP0.2
TP0.3
TP0.5

CIN

DL PACKAGE

(56-PIN TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

DL PACKAGE

(48-PIN TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

68-Pin J-Leaded Ceramic Chip Carrier
(JLCC) Package (EPROM Only)

NC – No internal connection

description

The MSP430 is an ultralow-power mixed signal microcontroller family consisting of several devices that feature
different sets of modules targeted to various applications. The microcontroller is designed to be battery operated
for an extended application lifetime. With 16-bit RISC architecture, 16-bit integrated registers on the CPU, and
a constant generator, the MSP430 achieves maximum code efficiency. The digitally-controlled oscillator,
together with the frequency-locked-loop (FLL), provides a wakeup from a low-power mode to active mode in
less than 6 ms.

NC
COM3
COM2
COM1
COM0
S27/O27/CMPI
S26/O26
S23/O23
S22/O22
S18/O18
S17/O17
S16/O16
S15/O15
S14/O14
S13/O13
S12/O12
S11/O11
S10/O10
S9/O9
S8/O8
S7/O7
S6/O6
S5/O5
S4/O4
S3/O3
S2/O2
S1
S0

TDO/TDI
COM3
COM2
COM1
COM0
S27/O27/CMPI
NC
V

SS

NC
S16/O16
S15/O15
S14/O14
S13/O13
S12/O12
S11/O11
S10/O10
S9/O9
S8/O8
S7/O7
S6/O6
S5/O5
S4/O4
S3/O3
S2/O2

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

†

MSP430P313/E313 not recommended for new designs – replaced by MSP430P315/E315.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2000, Texas Instruments Incorporated

1

MSP430x31x

40°C to 85°C

†

25°C

MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

description (continued)

Typical applications include sensor systems that capture analog signals, converting them to digital values, and
then processes the data and displays them or transmits them to a host system. The timer/port module provides
single-slope A/D conversion capability for resistive sensors.

AVAILABLE OPTIONS

PACKAGED DEVICES

T

A

SSOP

48-Pin

(DL)

SSOP

56-Pin

(DL)

MSP430C312IDL
MSP430C313IDL

°

–

MSP430C311SIDL

°

MSP430P315SIDL

MSP430C314IDL
MSP430C315IDL

MSP430P313IDL

†

MSP430P315IDL

°

†

MSP430P313/E313 not recommended for new designs – replaced by MSP430P315/E315.

— —

JLCC

68-Pin

(FZ)

PMS430E313FZ

PMS430E315FZ

functional block diagram

MSP430C312,313,314,315 and MSP430P313†,315 and PMS430E313,315

VCCV

SS

256/512 B

RAM

Bus

Conv

Power-On-

Reset

MAB, 4 Bit

MCB

MDB, 8 Bit

Timer/Port

Applications:

A/D Conv.
Timer, O/P

5

8-Bit Timer/

Counter

Serial Protocol

Support

TDI/VPP
TDO/TDI

TMS

TCK

XIN Xout XBUF RST/NMI P0.0–7

4/8/12/16 kB

Oscillator

FLL

System Clock

CPU

Incl. 16 Reg.

ACLK
MCLK

MAB, 16 Bit

Test

JTAG

MDB, 16 Bit

ROM

8/16 kB

OPT or EPROM

C: ROM

P: OTP

E: EPROM

Watchdog

Timer

15/16 Bit

Basic

Timer1

CMPI

f

LCD

TXD

RXD

8

I/O Port

8 I/O’s, All With

Interr. Cap.

3 Int. Vectors

LCD

92 Segments

1, 2, 3, 4 MUX

Com0–3
S0–18,22,23,26/

O2–18,22,23,26
S27/O27/CMPI

2

TP0.0–4

TP0.5

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CIN

R13 R23

I/O

DESCRIPTION

MSP430x31x

MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

Terminal Functions

MSP430C312, MSP430C313†, MSP430C314, MSP430C315, MSP430P313†, MSP430P315

56-pin SSOP package

TERMINAL

NAME NO.

CIN 27 I Counter enable. CIN input enables counter (TPCNT1) (timer/port).
COM0–COM3 52–55 O Common output pins. COM0–COM3 are used for LCD back planes.
P0.0 13 I/O General-purpose digital I/O pin
P0.1/RXD 14 I/O General-purpose digital I/O pin, receive data input port – 8-bit (timer/counter)
P0.2/TXD 15 I/O General-purpose digital I/O pin, transmit data output port – 8-bit (timer/counter)
P0.3–P0.7 16–20 I/O Five general-purpose digital I/O pins, bit 3–7
R23 9 I Input of second positive analog LCD level (V2) (LCD)
R13 10 I Input of third positive analog LCD level (V3 of V4) (LCD)
RST/NMI 5 I Reset input or nonmaskable interrupt input
S0 29 O Segment line S0 (LCD)
S1 30 O Segment line S1 (LCD)
S2/O2–S5/O5 31–34 O Segment lines (S2 to S5) or digital output port O2 to O5, group 1 (LCD)
S6/O6–S9/O9 35–38 O Segment lines (S6 to S9) or digital output port O6 to O9, group 2 (LCD)
S10/O10–S13/O13 39–42 O Segment lines (S10 to S13) or digital output port O10 to O13, group 3 (LCD)
S14/O14–S17/O17 43–46 O Segment lines (S14 to S17) or digital output port O14 to O17, group 4 (LCD)
S18/O18 47 O Segment line (S18) or digital output port O18 , group 5 (LCD)
S22/O22–S23/O23 48,49 O Segment lines (S22 to S23) or digital output port O22 to O23, group 6 (LCD)
S26/O26 50 O Segment line (S26) or digital output port O26, group 7 (LCD)
S27/O27/CMPI 51 I/O Segment line (S27) or digital output port O27 group 7, can be used as a comparator input port CMPI

TCK 4 I Test clock. TCK is a clock input terminal for device programming and test.
TDI/VPP 2 I Test data input port. TDI/VPP is used as a data input terminal or an input for programming voltage.
TDO/TDI 1 I/O Test data output port. TDO/TDI is used as a data output terminal or as a data input during

TMS 3 I Test mode select. TMS is an input terminal for device programming and test.
TP0.0 21 O/Z General-purpose 3-state digital output port, bit 0 (timer/port)
TP0.1 22 O/Z General-purpose 3-state digital output port, bit 1 (timer/port)
TP0.2 23 O/Z General-purpose 3-state digital output port, bit 2 (timer/port)
TP0.3 24 O/Z General-purpose 3-state digital output port, bit 3( timer/port)
TP0.4 25 O/Z General-purpose 3-state digital output port, bit 4 (timer/port)
TP0.5 26 I/O/Z General-purpose 3-state digital I/O pin, bit 5 (timer/port)
V

CC

V

SS

XBUF 6 O Clock signal output of system clock (MCLK) or crystal clock (ACLK)
Xin 11 I Input terminal of crystal oscillator
Xout/TCLK 12 I/O Output terminal of crystal oscillator or test clock input

†

MSP430P313/E313 not recommended for new designs – replaced by MSP430P315/E315.

8 Supply voltage
7 Ground reference

(timer/port)

programming.

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3

MSP430x31x
MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

functional block diagram

MSP430C31 1S and MSP430P315S

XIN Xout XBUF RST/NMI

VCCV

SS

P0.1–6

TDI/VPP
TDO/TDI

TMS
TCK

Oscillator

FLL

System Clock

CPU

Incl. 16 Reg.

Test

JTAG

ACLK
MCLK

MAB, 16 Bit

MDB, 16 Bit

2 kB

ROM

16 kB

OTP
C: ROM
P: OTP

Watchdog

Timer

15/16 Bit

128/512B

RAM

Bus

Conv

TP0.5

Power-On-

Reset

MAB, 4 Bit

MCB

MDB, 8 Bit

Timer/Port

Applications:

A/D Conv.

Timer, O/P

4

TP0.0–3

8-bit Timer/

Serial Protocol

CIN

Counter

Support

CMPI

Basic

Timer1

f

LCD

TXD

RXD

6

I/O Port

6 I/O’s, All With

Interr. Cap.

2 Int. Vectors

LCD

64 Segments

1, 2, 3, 4 MUX

R13 R23

COM0–3
S2–16/O2–16
S27/O27/CMPI

4

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I/O

DESCRIPTION

MSP430x31x

MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

Terminal Functions

MSP430C311S, MSP430P315S

48-pin SSOP package

TERMINAL

NAME NO.

CIN 24 I Counter enable. CIN input enables counter (TPCNT1) (timer/port).
COM0–COM3 44–47 O Common output pins, COM0–COM3 are used for LCD back planes.
P0.1/RXD 12 I/O General-purpose digital I/O pin, receive data input port – 8-Bit (timer/counter)
P0.2/TXD 13 I/O General-purpose digital I/O pin, transmit data output port – 8-Bit (timer/counter)
P0.3 14 I/O General-purpose digital I/O pins, bit 3
P0.4 15 I/O General-purpose digital I/O pins, bit 4
P0.5 16 I/O General-purpose digital I/O pins, bit 5
P0.6 17 I/O General-purpose digital I/O pins, bit 6
R23 8 I Input of second positive analog LCD level (V2) (LCD)
R13 9 I Input of third positive analog LCD level (V3 of V4) (LCD)
RST/NMI 4 I Reset input or nonmaskable interrupt input
S2/O2–S5/O5 25–28 O Segment lines (S2 to S5) or digital output port O2 to O5, group 1 (LCD)
S6/O6–S9/O9 29–32 O Segment lines (S6 to S9) or digital output port O6 to O9, group 2 (LCD)
S10/O10–S13/O13 33–36 O Segment lines (S10 to S13) or digital output port O10 to O13, group 3 (LCD)
S14/O14–S16/O16 37–39 O Segment lines (S14 to S17) or digital output port O14 to O17, group 4 (LCD)
S27/O27/CMPI 43 I/O Segment line (S27) or digital output port O27 group 7, can be used as a comparator input port CMPI

TCK 3 I Test clock. TCK is a clock input terminal for device programming and test.
TDI/VPP 1 I Test data input port. TDI/VPP is used as a data input terminal or an input for programming voltage.
TDO/TDI 48 I/O Test data output port. TDO/TDI is used as a data output terminal or as a data input during

TMS 2 I Test mode select. TMS is an input terminal for device programming and test.
TP0.0 19 O/Z General-purpose 3-state digital output port, bit 0 (timer/port)
TP0.1 20 O/Z General-purpose 3-state digital output port, bit 1 (timer/port)
TP0.2 21 O/Z General-purpose 3-state digital output port, bit 2 (timer/port)
TP0.3 22 O/Z General-purpose 3-state digital output port, bit 3 (timer/port)
TP0.5 23 I/O/Z General-purpose 3-state digital I/O pin, bit 5 (timer/port)
V

CC

V

SS

XBUF 5 O Clock signal output of system clock (MCLK) or crystal clock (ACLK)
Xin 10 I Input terminal of crystal oscillator
Xout/TCLK 11 I/O Output terminal of crystal oscillator or test clock input

7 Supply voltage

6, 41 Ground references

(timer/port)

programming.

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5

MSP430x31x
MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

short-form description

processing unit

The processing unit is based on a consistent and orthogonal designed CPU and instruction set. This design
structure results in a RISC-like architecture, highly transparent to the application development and
distinguishable by the ease of programming. All operations other than program-flow instructions are
consequently performed as register operations in conjunction with seven addressing modes for source and four
modes for destination operand.

CPU

Program Counter

Sixteen registers located inside the CPU provide
reduced instruction execution time. This reduces

Stack Pointer

a register-register operation execution time to one
cycle of the processor frequency.

Four registers are reserved for special use as a

Status Register

Constant Generator

program counter, a stack pointer , a status register,
and a constant generator. The remaining ones are

General-Purpose Register

available as general-purpose registers.
Peripherals connected to the CPU using a data

General-Purpose Register

address and control bus can be handled easily
with all instructions for memory manipulation.

instruction set

The instruction set for this register-register

General-Purpose Register R14

General-Purpose Register

architecture provides a powerful and easy-to-use
assembly language. The instruction set consists of 51 instructions with three formats and seven addressing
modes. Table 1 provides a summation and example of the three types of instruction formats; the addressing
modes are listed in Table 2.

Table 1. Instruction Word Formats

Dual operands, source-destination e.g. ADD R4, R5 R4 + R5 → R5
Single operands, destination only e.g. CALL R8 PC → (TOS), R8 → PC

Relative jump, un-/conditional e.g. JNE Jump-on equal bit = 0

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R4

R5

R15

Each instruction that operates on word and byte data is identified by the suffix B.
Examples: Instructions for word operation Instructions for byte operation

MOV EDE,TONI MOV.B EDE,TONI
ADD #235h,&MEM ADD.B #35h,&MEM
PUSH R5 PUSH.B R5
SWPB R5 —

6

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MSP430x31x

MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

Table 2. Address Mode Descriptions

ADDRESS MODE s d SYNTAX EXAMPLE OPERATION

Register √ √ MOV Rs, Rd MOV R10, R11 R10 → R11
Indexed √ √ MOV X(Rn), Y(Rm) MOV 2(R5), 6(R6) M(2 + R5) → M(6 + R6)
Symbolic (PC relative) √ √ MOV EDE, TONI M(EDE) → M(TONI)
Absolute √ √ MOV &MEM, &TCDAT M(MEM) → M(TCDAT)
Indirect √ MOV @Rn, Y(Rm) MOV @R10, Tab(R6) M(R10) → M(Tab + R6)
Indirect autoincrement √ MOV @Rn+, RM MOV @R10+, R11 M(R10) →R11, R10 + 2 → R10
Immediate √ MOV #X, TONI MOV #45, TONI #45 → M(TONI)

NOTE: s = source d = destination

Computed branches (BR) and subroutine call (CALL) instructions use the same addressing modes as the other
instructions. These addressing modes provide
calls. The full use of this programming capability permits a program structure different from conventional 8- and
16-bit controllers. For example, numerous routines can easily be designed to deal with pointers and stacks
instead of using flag type programs for flow control.

operation modes and interrupts

indirect

addressing, ideally suited for computed branches and

The MSP430 operating modes support various advanced requirements for ultra low-power and ultra-low energy
consumption. This is achieved by the management of the operations during the different module operation
modes and CPU states. The requirements are fully supported during interrupt event handling. An interrupt event
awakens the system from each of the various operating modes and returns with the RETI instruction to the mode
that was selected before the interrupt event. The clocks used are ACLK and MCLK. ACLK is the crystal
frequency and MCLK , a multiple of ACLK, is used as the system clock.

The software can configure five operating modes:

D

Active mode (AM). The CPU is enabled with different combinations of active peripheral modules.

D

Low-power mode 0 (LPM0). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals
are active, and loop control for MCLK is active.

D

Low-power mode 1 (LPM1). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals
are active, and loop control for MCLK is inactive.

D

Low-power mode 2 (LPM2). The CPU is disabled, peripheral operation continues, ACLK signal is active,
and MCLK and loop control for MCLK are inactive.

D

Low-power mode 3 (LPM3). The CPU is disabled, peripheral operation continues, ACLK signal is active,
MCLK and loop control for MCLK are inactive, and the dc generator for the digital controlled oscillator (DCO)
(³MCLK generator) is switched off.

D

Low-power mode 4 (LPM4). The CPU is disabled, peripheral operation continues, ACLK signal is inactive
(crystal oscillator stopped), MCLK and loop control for MCLK are inactive, and the dc generator for the DCO
is switched off.

The special function registers (SFR) include module-enable bits that stop or enable the operation of the specific
peripheral module. All registers of the peripherals may be accessed if the operational function is stopped or
enabled. However, some peripheral current-saving functions are accessed through the state of local register
bits. An example is the enable/disable of the analog voltage generator in the LCD peripheral, which is turned
on or off using one register bit.

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7

MSP430x31x

P0.1IFG

Maskable

0FFF8h

12

MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

operation modes and interrupts (continued)

The most general bits that influence current consumption and support fast turn-on from low power operating
modes are located in the status register (SR). Four of these bits control the CPU and the system clock generator:
SCG1, SCG0, OscOff, and CPUOff.

15 9 8 7 0

Reserved For Future

Enhancements

rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0

interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the ROM with an address range of
0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction
sequence.

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY

Power-up, external reset, watchdog

NMI, oscillator fault
Dedicated I/O P0.0 P0.0IFG Maskable 0FFFAh 13

Dedicated I/O P0.1
8-Bit Timer/Counter

Watchdog Timer WDTIFG Maskable 0FFF4h 10

Timer/Port

Basic Timer1 BTIFG Maskable 0FFE2h 1
I/O Port 0.2–7

NOTES: 1. Multiple source flags

2. Timer/port interrupt flags are located in the timer/port registers

3. Non maskable: neither the individual nor the general interrupt enable bit will disable an interrupt event.

4. (Non) maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot.

V SCG1 SCG0 OscOff CPUOff GIE N Z C

WDTIFG (see Note 1)

NMIIFG (see Notes 1 and 3)

OFIFG (see Notes 1 and 4)

RC1FG, RC2FG, EN1FG

(see Note 2)

P0.27IFG (see Note 1)

Reset 0FFFEh 15, highest

Nonmaskable,

(Non)maskable

Maskable 0FFEAh 5

Maskable 0FFE0h 0, lowest

0FFFCh 14

0FFF6h 11

0FFF2h 9

0FFF0h 8
0FFEEh 7
0FFECh 6

0FFE8h 4
0FFE6h 3
0FFE4h 2

8

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MSP430x31x

MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

special function registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple software access
is provided with this arrangement.

interrupt enable 1 and 2

Address
0h

7654 0

WDTIE: Watchdog Timer enable signal
OFIE: Oscillator fault enable signal
P0IE.0: Dedicated I/O P0.0
P0IE.1: P0.1 or 8-Bit Timer/Counter, RXD

Address
01h BTIE

7654 0

321

P0IE.1 OFIE WDTIE

rw-0 rw-0 rw-0 rw-0

321

P0IE.0

TPIE

rw-0

TPIE: Timer/Port enable signal
BTIE: Basic Timer1 enable signal

interrupt flag register 1 and 2

Address
02h NMIIFG P0IFG.0

7654 0

rw-0 rw-1 rw-0

321

P0IFG.1 OFIFG WDTIFG

rw-0 rw-0

WDTIFG: Set on overflow or security key violation

OR

Reset on VCC power-on or reset condition at RST/NMI-pin
OFIFG: Flag set on oscillator fault
P0.0IFG: Dedicated I/O P0.0
P0.1IFG: P0.1 or 8-Bit Timer/Counter, RXD
NMIIFG: Signal at RST

Address
03h BTIFG

7654 0

rw

/NMI-pin

321

BTIFG: Basic Timer1 flag

module enable register 1 and 2

Address
04h

7654 0321

rw-0

Address
05h

Legend rw:

rw-0:

7654 0321

Bit can be read and written.
Bit can be read and written. It is reset by PUC
SFR bit is not present in device.

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9

MSP430x31x
MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

memory organization

FFFFh
FFE0h

FFDFh

F800h

027Fh
0200h
01FFh
0100h

00FFh
0010h
000Fh
0000h

FFFFh
FFE0h

FFDFh

E000h

MSP430C31 1S

Int. Vector

2 kB ROM

128B RAM

16b Per.

8b Per.

SFR

MSP430P313
PMS430E313

Int. Vector

8 kB OTP

or

EPROM

MSP430C312

FFFFh
FFE0h

FFDFh

†
†

FFFFh
FFE0h

FFDFh

C000h

F000h

02FFh
0200h

01FFh
0100h
00FFh
0010h
000Fh
0000h

Int. Vector

4 kB ROM

256B RAM

16b Per.

8b Per.

SFR

MSP430P315

MSP430P315S

PMS430E315

Int. Vector

16 kB

OTP

or

EPROM

FFFFh

FFE0h

FFDFh

E000h

02FFh

0200h

01FFh

0100h

00FFh

0010h

000Fh

0000h

MSP430C313

Int. Vector

8 kB ROM

256B RAM

16b Per.

8b Per.

SFR

FFFFh
FFE0h

FFDFh

D000h

03FFh

0200h

01FFh

0100h

00FFh

0010h
000Fh
0000h

MSP430C314

Int. Vector

12 kB ROM

512B RAM

16b Per.

8b Per.

SFR

FFFFh
FFE0h

FFDFh

C000h

03FFh

0200h

01FFh

0100h

00FFh

0010h

000Fh

0000h

MSP430C315

Int. Vector

16 kB ROM

512B RAM

16b Per.

8b Per.

SFR

03FFh

512B RAM

02FFh

01FFh

00FFh

000Fh

†

MSP430P313/E313 not recommended for new designs – replaced by MSP430P315/E315.

0200h

0100h

0010h

0000h

256B RAM

16b Per.

8b Per.

SFR

10

0200h

01FFh
0100h
00FFh
0010h
000Fh
0000h

16b Per.

8b Per.

SFR

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x31x

MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

peripherals

Peripherals connected to the CPU through a data, address, and control busses can be handled easily with
instructions for memory manipulation.

oscillator and system clock

Two clocks are used in the system: the system (master) clock (MCLK) and the auxiliary clock (ACLK). The MCLK
is a multiple of the ACLK. The ACLK runs with the crystal oscillator frequency . The special design of the oscillator
supports the feature of low current consumption and the use of a 32 768 Hz crystal. The crystal is connected
across two terminals without requiring any other external components.

The oscillator starts after applying VCC, due to a reset of the control bit (OscOff) in the status register (SR). It
can be stopped by setting the OscOff bit to a 1. The enabled clock signals ACLK, ACLK/2, ACLK/4, or MCLK
are accessible for use by external devices at output terminal XBUF.

The controller system clock has to operate with different requirements according to the application and system
conditions. Requirements include:

• High frequency in order to react quickly to system hardware requests or events

• Low frequency in order to minimize current consumption, EMI, etc.

• Stable frequency for timer applications e.g. real-time clock (RTC)

• Enable start-stop operation with a minimum delay

These requirements cannot all be met with fast frequency high-Q crystals or with RC-type low-Q oscillators. The
compromise selected for the MSP430 uses a low-crystal frequency , which is multiplied to achieve the desired
nominal operating range:

f

(system)

The crystal frequency multiplication is achieved with a frequency locked loop (FLL) technique. The factor N is
set to 31 after a power-up clear condition. The FLL technique, in combination with a digital controlled oscillator
(DCO), provides immediate start-up capability together with long-term crystal stability . The frequency variation
of the DCO with the FLL inactive is typically 330 ppm, which means that with a cycle time of 1 µs, the maximum
possible variation is 0.33 ns. For more precise timing, the FLL can be used. This forces longer cycle times if
the previous cycle time was shorter than the selected one. This switching of cycle times makes it possible to
meet the chosen system frequency over a long period of time.

The start-up operation of the system clock depends on the previous machine state. During a power-up clear
(PUC), the DCO is reset to its lowest possible frequency. The control logic starts operation immediately after
removal of the PUC condition. Correct operation of the FLL control logic requires the presence of a stable crystal
oscillator.

= (N+1) × f

(crystal)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

11

MSP430x31x
MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

peripherals (continued)

digital I/O

There is one eight-bit I/O port, Port0, that is implemented (MSP430C311S and MSP430P315S have six bits
available on external pins). Six control registers give maximum digital input/output flexibility to the application:

• All individual I/O bits are programmable independently.

• Any combination of input, output, and interrupt conditions is possible.

• Interrupt processing of external events is fully implemented for all eight bits of port P0.

• Provides read/write access to all registers with all instructions

The six registers are:

• Input register 8 bits contains information at the pins

• Output register 8 bits contains output information

• Direction register 8 bits controls direction

• Interrupt flags 6 bits indicates if interrupt(s) are pending

• Interrupt edge select 8 bits contains input signal change necessary for interrupt

• Interrupt enable 6 bits contains interrupt enable bits

All these registers contain eight bits except for the interrupt flag register and the interrupt enable register. The
two least significant bits (LSBs) of the interrupt flag and interrupt enable registers are located in the special
functions register (SFR). Three interrupt vectors are implemented, one for Port0.0, one for Port0.1, and one
commonly used for any interrupt event on Port0.2 to Port0.7. The Port0.1 and Port0.2 pin function is shared with
the 8-bit timer/counter.

LCD drive

Liquid crystal displays (LCDs) for static, 2-, 3-, and 4-MUX operations can be driven directly . The controller LCD
logic operation is defined by software using memory-bit manipulation. LCD memory is part of the LCD module
and not part of the data memory . Eight mode and control bits define the operation and current consumption of
the LCD drive. The information for the individual digits can be easily obtained using table programming
techniques combined with the correct addressing mode. The segment information is stored in LCD memory
using instructions for memory manipulation.

The drive capability is mainly defined by the external resistor divider that supports the analog levels for 2-, 3-,
and 4-MUX operation. Groups of the LCD segment lines can be selected for digital output signals. The
MSP430x31x has four common signals and 23 segment lines. The MSP430C311S and MSP430P315S have
four common lines and 16 segment lines.

Timer/Port

The Timer/Port module has two 8-bit counters, an input that triggers one counter , and six digital outputs in the
MSP430x31x (MSP430C311S, MSP430C315S have five digital outputs available on external pins) with
high-impedance state capability. Both counters have an independent clock-selector for selecting an external
signal or one of the internal clocks (ACLK or MCLK). One counter has an extended control capability to halt,
count continuously, or gate the counter by selecting one of two external signals. This gate signal sets the
interrupt flag, if an external signal is selected, and the gate stops the counter.

Both timers can be read from and written to by software. The two 8-bit counters can be cascaded to a 16-bit
counter. A common interrupt vector is implemented. The interrupt flag can be set from three events in the 8-bit
counter mode (gate signal, overflow from the counters) or from two events in the 16-bit counter mode (gate
signal, overflow from the MSB of the cascaded counter).

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

peripherals (continued)

slope A/D conversion

MSP430x31x

MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

Slope A/D conversion is accomplished with the timer/port module using external resistor(s) for reference (R
external resistor(s) to the measured (R
by software in such a way that the internal counter measures the time that is needed to charge or discharge
the capacitor. The reference resistor’s (R
unknown resistors (R
value (R
resistive sensor values that correspond to the physical data, for example temperature, when an NTC or PTC
resistor is used.

Basic Timer1

The Basic Timer1 (BT1) divides the frequency of MCLK or ACLK, as selected with the SSEL bit, to provide low
frequency control signals. This is done within the system by one central divider, the basic timer1, to support low
current applications. The BTCTL control register contains the flags which controls or selects the different
operational functions. When the supply voltage is applied or when a reset of the device (RST/NMI pin), a
watchdog overflow, or a watchdog security key violation occurs, all bits in the register hold undefined or
unchanged status. The user software usually configures the operational conditions on the BT1 during
initialization.

The Basic Timer1 has two 8 bit timers which can be cascaded to a 16 bit timer. Both timers can be read and
written by software. Two bits in the SFR address range handle the system control interaction according to the
function implemented in the Basic Timer1. These two bits are the Basic T imer1 interrupt flag (BTIFG) and the
basic timer interrupt enable (BTIE) bit.

Watchdog Timer

The primary function of the Watchdog Timer (WDT) module is to perform a controlled system restart after a
software problem has occurred. If the selected time interval expires, a system reset is generated. If this
watchdog function is not needed in an application, the module can work as an interval timer, which generates
an interrupt after the selected time interval.

) is the value of R

meas

) charge or discharge time is represented by N

meas

multiplied by the relative number of counts (N

ref

), and an external capacitor. The external components are driven

meas

) charge or discharge time is represented by N

ref

counts. The unknown resistor’s

meas

meas/Nref

). This value determines

counts. The

ref

ref

),

The Watchdog T imer counter (WDTCNT) is a 15/16-bit up-counter which is not directly accessible by software.
The WDTCNT is controlled using the Watchdog T imer control register (WDTCTL), which is a 16-bit read/write
register. W riting to WDTCTL, in both operating modes (watchdog or timer) is only possible by using the correct
password in the high-byte. The low-byte stores data written to the WDTCTL. The high-byte password is 05Ah.
If any value other than 05Ah is written to the high-byte of the WDTCTL, a system reset PUC is generated. When
the password is read its value is 069h. This minimizes accidental write operations to the WDTCTL register. In
addition to the Watchdog T imer control bits, there are two bits included in the WDTCTL which configure the NMI
pin.

8-Bit Timer/Counter

The 8-bit interval timer supports three major functions for the application:

• Serial communication or data exchange

• Pulse counting or pulse accumulation

• Timer

The 8-bit Timer/Counter peripheral includes the following major blocks: an 8-bit up-counter with
preload-register, an 8-bit control register, an input clock selector, an edge detection (e.g. start bit detection for
asynchronous protocols), and an input and output data latch, triggered by the carry-out-signal from the 8-bit
counter.

The 8-bit counter counts up with an input clock, which is selected by two control bits from the control register.
The four possible clock sources are MCLK, ACLK, the external signal from terminal P0.1, and the signal from
the logical AND of MCLK and terminal P0.1.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

13

MSP430x31x
MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

8-Bit Timer/Counter (continued)

Two counter inputs (load, enable) control the counter operation. The load input controls load operations. A
write-access to the counter results in loading the content of the preload-register into the counter. The software
writes or reads the preload-register with all instructions. The preload-register acts as a buffer and can be written
immediately after the load of the counter is completed. The enable input enables the count operation. When
the enable signal is set to high, the counter will count up each time a positive clock edge is applied to the clock
input of the counter.

Serial protocols, like UART protocol, need start-bit edge-detection to determine, at the receiver, the start of a
data transmission. When this function is activated, the counter starts counting after start-bit condition is
detected. The first signal level is sampled into the RXD input data-latch after completing the first timing interval,
which is programmed into the counter. T wo latches used for input and output data (RXD_FF and TXD_FF) are
clocked by the counter after the programmed timing interval has elapsed.

UART

The serial communication is realized by using software and the 8-bit timer/counter hardware. The hardware
supports the output of the serial data stream, bit-by-bit, with the timing determined by the counter. The
software/hardware interface connects the mixed signal controller to external devices, systems, or networks.

peripheral file map

PERIPHERALS WITH WORD ACCESS

Watchdog Watchdog Timer control WDTCTL 0120h

PERIPHERALS WITH BYTE ACCESS

EPROM EPROM control EPCTL 054h
Crystal buffer Crystal buffer control CBCTL 053h
System clock SCG frequency control

SCG frequency integrator
SCG frequency integrator

Timer /Port Timer/Port enable

Timer/Port data
Timer/Port counter2
Timer/Port counter1
Timer/Port control

8-Bit Timer/Counter 8-Bit Timer/Counter data

8-Bit Timer/Counter preload
8-Bit Timer/Counter control

Basic Timer1 Basic Timer/Counter2

Basic Timer/Counter1
Basic Timer control

LCD LCD memory 15

:
LCD memory1
LCD control & mode

Port P0 Port P0 interrupt enable

Port P0 interrupt edge select
Port P0 interrupt flag
Port P0 direction
Port P0 output
Port P0 input

Special function SFR interrupt flag2

SFR interrupt flag1
SFR interrupt enable2
SFR interrupt enable1

SCFQCTL
SCFI1
SCFI0

TPE
TPD
TPCNT2
TPCNT1
TPCTL

TCDAT
TCPLD
TCCTL

BTCNT2
BTCNT1
BTCTL

LCDM15

LCDM1
LCDCTL

P0IE
P0IES
P0IFG
P0DIR
P0OUT
P0IN

IFG2
IFG1
IE2
IE1

052h
051h
050h

04Fh
04Eh
04Dh
04Ch
04Bh

044h
043h
042h

047h
046h
040h

03Fh

031h
030h

015h
014h
013h
012h
011h
010h

003h
002h
001h
000h

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Suppl

oltage during programming, V

40

85

Processor frequency f

(signal MCLK) f

MH

V

V

V/5 V

V

MSP430x31x

MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

absolute maximum ratings

†

Voltage applied at VCC to VSS –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage applied to any pin (referenced to VSS) –0.3 V to VCC +0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Diode current at any device terminal ±2 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature, T
Storage temperature, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE: All voltages referenced to VSS.

(unprogrammed device) –55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

(programmed device) –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions

MIN NOM MAX UNIT

MSP430Cxxx 2.5 5.5

Supply voltage, V

pp

y v

Supply voltage, V

Operating free-air temperature range, T

XTAL frequency, f

Low-level input voltage, VIL (excluding Xin, Xout) V
High-level input voltage, VIH (excluding Xin, Xout)
Low-level input voltage, V
High-level input voltage, V

‡

MSP430P313/E313 not recommended for new designs – replaced by MSP430P315/E315.

CC

SS

(XTAL)

(system)

p

IL(Xin, Xout)

IH(Xin, Xout)

CC

A

system

MSP430P313‡, PMS430E313
MSP430P315, PMS430E315 2.7 5.5
MSP430P313 2.7 5.5 V
MSP430P315 4.5 5.5 V

MSP430C31x
MSP430P31x
PMS430E31x 25

VCC = 3 V DC 2.2
VCC = 5 V DC 3.3

= 3

CC

‡

2.7 5.5

0 V

–

32 768 Hz

SS

0.7×V

CC

V

SS

0.8×V

CC

VSS+0.8

V

CC

0.2×V

CC

V

CC

V

°C

z

f(MHz)

3.3

2.2

– Maximum Processor

Frequency – MHz

Minimum

(system)

f

NOTE: Minimum processor frequency is defined by system clock.

2.5

3 5 5.5

VCC – Supply Voltage – V

VCC (V)

Figure 1. Processor Frequency vs Supply Voltage, C Versions

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

15

MSP430x31x

C31xT

40°C

85°C

I

Active mode

P313

†

T

40°C

85°C

A

P315(S)

T

40°C

85°C

C31xT

40°C

85°C

I

Low-power mode, (LPM0,1)

P313

†

T

40°C

85°C

A

P315(S)

T

40°C

85°C

I

Low-power mode, (LPM2)

T

40°C

85°C

A

I

Low-power mode, (LPM3)

A

()

MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

f(MHz)

3.3

2.2

– Maximum Processor

(system)

f

NOTE: Minimum processor frequency is defined by system clock.

Figure 2. Processor Frequency vs Supply Voltage, P/E Versions

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

1.5

Frequency – MHz

Minimum

3 5 5.5

2.7
VCC – Supply Voltage – V

VCC (V)

supply current (into VCC) excluding external current (f

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

(AM)

(CPUOff)

(LPM2)

(LPM3)

I

(LPM4)

†

MSP430P313/E313 not recommended for new designs – replaced by MSP430P315/E315.

NOTE: All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. The current consumption in LPM2 and LPM3 are measured

with active basic timer (ACLK selected) and LCD module. (f

p

p

p

Low-power mode, (LPM4)

(system)

= –

A

= –

A

= –

A

= –

A

= –

A

= –

A

= –

A

TA = –40°C 1.5 2.4
TA = 25°C
TA = 85°C 1.6 2.8
TA = –40°C 5.2 7
TA = 25°C
TA = 85°C 4.8 5.4
TA = –40°C 0.1 0.8
TA = 25°C
TA = 85°C 0.4 1.3

= 1024 Hz, 4 mux)

LCD

°

°

°

°

°

°

°

+

+

+

+

+

+

+

= 1 MHz)

VCC = 3 V 400 500

°

VCC = 5 V 730 850
VCC = 3 V 2100 2700

°

VCC = 5 V 7000 8600
VCC = 3 V 490 550

°

VCC = 5 V 960 1050
VCC = 3 V 50 70

°

VCC = 5 V 100 130
VCC = 3 V 70 85

°

VCC = 5 V 150 170
VCC = 3 V 50 70

°

VCC = 5 V 100 130
VCC = 3 V 6 12

°

VCC = 5 V 13 25

VCC = 3 V

VCC = 5 V

VCC = 3 V/5 V

1.3 2

4.2 6

0.1 0.8

µ

µ

µ

µ

µA

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

V

Positive-going input threshold voltage

V

V

Negative-going input threshold voltage

V

V

Input hysteresis (V

V

)

V

V

V/5 V

V

VOHHigh-level output voltage

V

VOLLow-level out ut voltage

V

MSP430x31x

MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)

current consumption of active mode versus system frequency, C versions only

I

AM

= I

AM[1 MHz]

× f

system

[MHz]

current consumption of active mode versus supply voltage, C versions only

IAM = I

AM[3 V]

+ 200 µA/V × (VCC–3 V)

schmitt-trigger inputs port 0, Timer/Port, CIN, TP0.5

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

IT+

IT–

hys

p

p

p

IT+

–

IT–

VCC = 3 V 1.2 2.1
VCC = 5 V 2.3 3.4
VCC = 3 V 0.5 1.35
VCC = 5 V 1.4 2.3
VCC = 3 V 0.3 1
VCC = 5 V 0.6 1.4

standard inputs TCK, TMS, TDI, RST/NMI

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

V

Low-level input voltage

IL

V

High-level input voltage

IH

CC

= 3

V

0.7V

SS

CC

VSS+0.8

V

CC

outputs port 0, P0.x, Timer/Port, TP0.0 – 5, LCD: S2/O2 to S26/O26 XBUF:XBUF, JTAG:TDO

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

IOH = –1.2 mA, VCC = 3 V, See Note 5 VCC–0.4 V

p

p

NOTES: 5. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±9.6 mA to hold the maximum voltage

drop specified.

6. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±20 mA to hold the maximum voltage
drop specified.

IOH = –3.5 mA, VCC = 3 V, See Note 6 VCC–1 V
IOH = –1.5 mA, VCC = 5 V, See Note 5 VCC–0.4 V
IOH = –4.5 mA, VCC = 5 V, See Note 6 VCC–1 V
IOL = 1.2 mA, VCC = 3 V, See Note 5 V
IOL = 3.5 mA, VCC = 3 V, See Note 6 V
IOL = 1.5 mA, VCC = 5 V, See Note 5 V
IOL = 4.5 mA, VCC = 5 V, See Note 6 V

SS
SS
SS
SS

CC
CC
CC
CC

VSS+0.4

VSS+1

VSS+0.4

VSS+1

leakage current (see Note 7)

I

lkg(TP)

I

lkg(S27)

I

lkg(P0x)

NOTES: 7. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.

High-impedance leakage current, timer/port
High-impedance leakage current, S27 V

Leakage current, port 0

8. All timer/port pins TP0.0 to TP0.5 are Hi-Z. Pins CIN and TP .0 to TP0.5 are connected together during leakage current measurement.
In the leakage measurement the input CIN is included. The input voltage is VSS or VCC.

9. The port pin must be selected for input and there must be no optional pullup or pulldown resistor.

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

Timer/port:V
VCC = 3 V/5 V,

S27

Port P0: P0.x, 0 ≤×≤ 7,
(see Note 9)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TP0.x,

= VSS to VCC, VCC = 3 V/5 V ±50 nA

CIN = VSS, VCC,
(see Note 8)

VCC = 3 V/5 V,

±50 nA

±50 nA

17

MSP430x31x

yg

(system)

High level or low level time

t

Duty cycle of clock output frequenc

MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)

optional resistors, individually programmable with ROM code, P0.x, (see Note 10)

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

R

(opt1)

R

(opt2)

R

(opt3)

R

(opt4)

R

(opt5) Resistors, individually programmable with ROM code, all port pins,

R

(opt6)

R

(opt7)

R

(opt8)

R

(opt9)

R

(opt10)

NOTE 10: Optional resistors R

values applicable for pulldown and pullup

for pull-down or pull-up are not programmed in standard OTP/EPROM devices P/E313 (MSP430P313/E313

not recommended for new designs – replaced by MSP430P315/E315) and P/E315(s)

optx

inputs P0.x, CIN, TP.5; output XBUF

PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT

Port P0

t

(int)

f

(IN)

t

or t

(H)

t

or t

(H)

f

(XBUF)

(Xdc)

NOTES: 11. The external signal sets the interrupt flag every time t

External interrupt timing

Input frequency

(L)
(L)

Clock output frequency XBUF, CL = 20 pF 3 V/5 V f

p

to set the flag must be met independently from this timing constraint. T

12. The external interrupt signal cannot exceed the maximum inut frequency (f

External trigger signal for the
interrupt flag, (see Notes 11 and 12)

P0.x, CIN, TP.5

XBUF, CL = 20 pF,

f

= 1.1 MHz 3V/5V 40%

y

(MCLK)

f

= f

(XBUF)

f

= f

(XBUF)

is met. It may be set even with trigger signals shorter than t

int

crystal oscillator, Xin, Xout

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

C

(Xin)

C

(Xout)

Integrated capacitance at input VCC = 3 V/5 V 12 pF
Integrated capacitance at output VCC = 3 V/5 V 12 pF

(ACLK)
(ACLK/n)

VCC = 3 V/5 V 2.1 4.1 6.2 kΩ
VCC = 3 V/5 V 3.1 6.2 9.3 kΩ
VCC = 3 V/5 V 6 12 18 kΩ
VCC = 3 V/5 V 10 19 29 kΩ
VCC = 3 V/5 V 19 37 56 kΩ
VCC = 3 V/5 V 38 75 113 kΩ
VCC = 3 V/5 V 56 112 168 kΩ
VCC = 3 V/5 V 94 187 281 kΩ
VCC = 3 V/5 V 131 261 392 kΩ
VCC = 3 V/5 V 167 337 506 kΩ

3 V/5 V 1.5 cycle

3 V/5 V DC f

3 V 225 ns
5 V 150 ns

(system)

3V/5V 35% 60%
3V/5V 50% 65%

. The conditions

is defined in MCLK cycles.

int

).

(in)

int

MHz

MHz

18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

f

N

0110 0000 FN_4=FN_3=FN_2=0

f

MH

f

N

0100 0000 FN_4=FN_3=FN_2=0

f

N

00 0110 0000 FN_4=FN_3=0, FN_2=1

2xf

(NOM)

MHz

f

N

0100 0000 FN_4=FN_3=0, FN_2=1

f

N

0110 0000 FN_4=0, FN_3= 1, FN_2=X

3xf

(NOM)

MHz

f

N

0100 0000 FN_4= 0, FN_3=1, FN_2=X

f

N

0110 0000 FN_4 =1, FN_3=FN_2=X

4xf

(NOM)

MHz

f

N

0100 0000 FN_4=1, FN_3=FN_2=X

MSP430x31x

MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

electrical characteristics over recommended and operating free-air temperature range (unless
otherwise noted) (continued)

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

f

(NOM)

(NOM)

N

DCO

S f

DCO N

DCO3

DCO26

DCO3

DC26

DCO3

DCO26

DCO3

DCO26

= 1A0h FN_4=FN_3=FN_2=0 VCC = 3 V/5 V 1 MHz

DCO

DCO

DCO

DCO

DCO

DCO

DCO

DCO

DCO

f

MCLK
NDCO+1

= 00

= 11

=

= 11

= 00

= 11

= 00

= 11

= f

NOM
= S × f

FN_4=FN_3=FN_2=0 VCC = 3 V/5 V A0h 1A0h 340h

NDCO

VCC = 3 V 0.15 0.6
VCC = 5 V 0.18 0.62
VCC = 3 V 1.25 4.7
VCC = 5 V 1.45 5.5

VCC = 3 V 0.36 1.05
VCC = 5 V 0.39 1.2

VCC = 3 V 2.5 8.1
VCC = 5 V 3 9.9

VCC = 3 V 0.5 1.5
VCC = 5 V 0.6 1.8

VCC = 3 V 3.7 11
VCC = 5 V 4.5 13.8

VCC = 3 V 0.7 1.85
VCC = 5 V 0.8 2.4

VCC = 3 V 4.8 13.3
VCC = 5 V 6 17.7

VCC = 3 V/5 V 1.07 1.13

z

4xf

3xf

2xf

NOM

NOM

NOM

f

NOM

f

(DCO26)

f

(DCO3)

FN_2 = 0
FN_3 = 0
FN_4 = 0

f

(DCO26)

f

(DCO3)

FN_2 = 1
FN_3 = 0
FN_4 = 0

Figure 3

f

(DCO26)

f

(DCO3)

FN_2 = X
FN_3 = 1
FN_4 = 0

f

(DCO26)

f

(DCO3)

Legend

Tolerance at Tap 26

DCO Frequency
Adjusted by Bits
2∧9–2∧5 in SCFI1

Tolerance at Tap 3

FN_2 = X
FN_3 = X
FN_4 = 1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

19

MSP430x31x

Analog voltage

V

V

V/5 V

g

±20

nA

Output (SXX)

I

V

V/5 V

33

kΩ

I

Comparator (timer/port)

CPON

1

A

V

hys(

)

In ut hysteresis (com arator)

CPON

1

mV

()

V

V/5 V

MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

LCD

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

V

23

V

13

V

O(HLCD)

V

O(LLCD)

I

I(R13)

I

I(R23)

r

to S

o(R13)

r

to S

o(R23)

NOTE 13: I

(IRxx)

Output 1 (HLCD) I
Output 0 (LLCD) I
Input leakage

(see Note 13)

(XX)
(XX)

p

is measured with no load on the segment or common LCD I/O pins.

comparator (Timer/Port)

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

(com)

V

ref(com)

com

p

Internal reference voltage at (–) terminal CPON = 1 VCC = 3 V/5 V 0.230×V

p

Voltage at R23 VCC = 3 V/5 V

Voltage at R13 VCC = 3 V/5 V

<= 10 nA VCC–0.125 V

(HLCD)

<= 10 nA

(LLCD)

R13 = VCC/3
R23 = 2 VCC/3

= –3 µA,

(SXX)

p

p

=

=

= 3

CC

= 3

CC

VCC = 3 V 250 350
VCC = 5 V 450 600

VCC = 3 V 5 37
VCC = 5 V 10 42

V

SS

(VCC–VSS)×

2/3+V

(VCC–VSS) ×

1/3+V

0.25×V

CC

SS

SS

CC

CC

VSS+0.125

0.260×V

CC

V

V

µ

V

RAM

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

V

RAMh

NOTE 14: This parameter defines the minimum supply voltage when the data in the program memory RAM remains unchanged. No program

CPU halted (see Note 14) 1.8 V

execution should happen during this supply voltage condition.

PUC/POR

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

t

(POR_delay)

V

(POR)

V

(min)

t

(reset)

TA = –40°C 1.5 2.4 V

POR

PUC/POR Reset is accepted internally 2 µs

TA = 25°C
TA = 85°C

CC

= 3

150 250 µs

1.2 2.1 V

0.9 1.8 V
0 0.4 V

20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

f

6

()

f

6

MSP430x31x

MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

V

VCC

V

(POR)

No POR

2.1

POR

t

V

(min)

POR

Figure 4. Power-On Reset (POR) vs Supply Voltage

3

2.4

2.5

2

1.5

V POR [V]

1

0.5

0

–40 –20 0 20 40 60 80

wakeup from LPM3

t

(LPM3)

Delay time

1.8

1.5

1.2

25°C

Temperature [°C]

Figure 5. V

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

vs Temperature

(POR)

= 1 MHz

= 2 MHz

f = 3 MHz VCC = 5 V 6

VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V

0.9

µs

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

21

MSP430x31x

f

TCK frequenc

MH

JTAG/Test

()

V
(see

8)

(see Note 18)

EPROM (E)

MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

JT AG, program memory

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

(TCK)

R

(TEST)

V

(FB)

JTAG/Fuse (see Note 16)

I

(FB)

t

(FB)

(PP)

I

(PP)

t

(pps)

t

(ppf)

P

n

t

(erase)

NOTES: 15. The TMS and TCK pullup resistors are implemented in all ROM(C) and EPROM(E) versions.

P313, E313 Programming voltage, applied to TDI/VPP 11 11.5 13 V
P315(S), E315 Programming voltage, applied to TDI/VPP 12 12.5 13 V

EPROM (E) and OTP(P) –
versions only

Note 1

16. Once the JTAG fuse is blown no further access to the MSP430 JTAG/test feature is possible.

17. The voltage supply to blow the JTAG fuse is applied to TDI/VPP pin when fuse blowing is desired.

18. Refer to the Recommended Operating Conditions for the correct VCC during programing.

Pullup resistors on TMS, TCK, TDI
(see Note 15)

Fuse blow voltage, C versions (see Note 15) VCC = 3 V/ 5 V 5.5 6
Fuse blow voltage, E/P versions

(see Note 17)
Supply current on TDI/VPP to blow fuse 100 mA
Time to blow the fuse 1 ms

Current from programming voltage source 70 mA
Programming time, single pulse 5 ms
Programming time, fast algorithm 100 µs
Pulses for successful programming 4 100 Pulses
Erase time wave length 2537 Å at 15 Ws/cm

(UV lamp of 12 mW/ cm2)
Write/erase cycles 1000 cycles
Data retention TJ < 55°C 10 years

y

VCC = 3 V DC 5
VCC = 5 V DC 10

VCC = 3 V/ 5 V 25 60 90 kΩ

VCC = 3 V/ 5 V 11 12

2

30 min

z

V

22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x31x

MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

TYPICAL CHARACTERISTICS

JTAG fuse check mode

MSP430 devices that have the fuse on the TDI/VPP terminal have a fuse check mode that tests the continuity
of the fuse the first time the JT AG port is accessed after a power-on reset (POR). When activated, a fuse check
current, ITF, of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TDI/VPP pin to ground if the fuse is not burned.
Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.

Activation of the fuse check mode occurs with the first negative edge on the TMS pin, after power up, or if the
TMS is being held low after power-up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.

Time TMS Goes Low After POR

TMS

I

TF

I

TDI

Figure 6. Fuse Check Mode Current, MSP430P/E313,P/E315,C31x

Care must be taken to avoid accidentally activating the fuse check mode, including guarding against EMI/ESD
spikes that could cause signal edges on the TMS pin.

Configuration of TMS, TCK, TDI/VPP and TDO/TDI pins in applications.

C3xx P/E3xx

TDI Open 68k, pulldown
TDO Open 68k, pulldown
TMS Open Open
TCK Open Open

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

23

MSP430x31x
MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

TYPICAL CHARACTERISTICS

DIGITAL CONTROLLED OSCILLATOR FREQUENCY

vs

OPERATING FREE-AIR TEMPERATURE

1.8

1.5

C

°

1.2

(DCO@ 25 )

0.9

/f

(DCO)

f

0.6

0.3

0
–40 –20 0 20 40 9060 80

T – Operating Free-Air Temperature – °C

Figure 7

DIGITAL CONTROLLED OSCILLATOR FREQUENCY

vs

SUPPLY VOLTAGE

1.2

1

0.8

(DCO@ 3 V)

0.6

/f

(DCO)

f

0.4

0.2

0

02

VCC – Supply Voltage – V

46

Figure 8

24

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

typical input/output schematics

MSP430x31x

MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

TYPICAL CHARACTERISTICS

V

CC

(see Note A)

(see Note B)

(see Note B)

(see Note A)

GND

CMOS INPUT (RST/NMI)

V

CC

(see Note A)

(see Note B)

(see Note B)

(see Note A)

V

CC

(see Note A)

(see Note B)

(see Note B)

(see Note A)

GND

CMOS SCHMITT-TRIGGER INPUT (CIN)

GND

I/O WITH SCHMITT-TRIGGER INPUT (P0.x,
TP0.5)

V

CC

60 k TYP

MSP430C31x: TMS, TCK
MSP430P/E31x: TMS, TCK

NOTES: A. Optional selection of pull-up or pull-down resistors with ROM (masked) versions.

B. Fuses for the optional pull-up and pull-down resistors can only be programmed at the factory.

CMOS 3-STATE OUTPUT
(TP0.0–4, XBUF)

TDO_Internal

TDO_Control

TDI_Control

TDI_Internal

MSP430C31x: TDO/TDI
MSP430P/E31x: TDO/TDI

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

25

MSP430x31x
MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

TYPICAL CHARACTERISTICS

typical input/output schematics

VC
VD

Control COM0–3

VA

VB

Segment control

VA

VB

Segment control

LCDCTL (LCDM5,6,7)

Data (LCD RAM bits 0–3

or bits 4–7)

LCD OUTPUT (COM0–4, Sn, Sn/On)

NOTE: The signals VA, VB, VC, and VD come from the LCD module analog voltage generator.

COM0–3

S0, S1

S2/O2–Sn/On

VPP_ Internal

TDI_ Internal

TDI/VPP

JTAG
Fuse

TDO/TDI_Control

TDO/TDI

JTAG Fuse

TMS

NOTES: A. During programming activity and when blowing the JTAG enable fuse, the TDI/VPP terminal is used to apply the correct voltage

source. The TDO/TDI terminal is used to apply the test input data for JTAG circuitry.

B. The TDI/VPP terminal of the ’P31x and ’E31x does not have an internal pullup resistor. An external pulldown resistor is

recommended to avoid a floating node, which could increase the current consumption of the device.

C. The TDO/TDI terminal is in a high-impedance state after POR. The ’P31x and ’E31x need a pullup or a pulldown resistor to avoid

floating a node, which could increase the current consumption of the device.

Blow

Control

TDO_ Internal

From/To JTAG_CBT_SIG_REG

Figure 9. MSP430P313/E313/P315(S)/E315: TDI/VPP, TDO/TDI

26

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x31x

MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

MECHANICAL DATA

DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

48-PIN SHOWN

0.025 (0,635)

48

1

0.110 (2,79) MAX

0.012 (0,305)

0.008 (0,203)
25

0.299 (7,59)

0.291 (7,39)

24

A

0.008 (0,20) MIN

0.005 (0,13)

0.420 (10,67)

0.395 (10,03)

Seating Plane

0.004 (0,10)

M

0.006 (0,15) NOM

Gage Plane

0.010 (0,25)

0°–8°

0.040 (1,02)

0.020 (0,51)

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118

0.380
(9,65)

0.370
(9,40)

4828

0.630

(16,00)

0.620

(15,75)

56

0.730

(18,54)

0.720

(18,29)

4040048/D 08/97

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

27

MSP430x31x
MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

PMS430E313†, PMS430E315 (FZ package)

FZ PACKAGE

(TOP VIEW)

NC

10

NC

11

V

12

CC

R23

13

R13

14

Xin

15

Xout/TCLK

P0.0

P0.1/RXD

P0.2/TXD

P0.3
P0.4
P0.5
P0.6
P0.7

TP0.0

NC – No internal connection

NC

16
17
18
19
20
21
22
23
24
25
26

27

SS

NC

NC

XBUF

RST/NMI

TCK

TP0.3

TP0.4

TMS

TP0.5

V

87 65493

30

NC

28 29

NC

31 32 33 34

TP0.1

TP0.2

COM3

TDI/VPP

TDO/TDI

168672

35 36 37 38 39

S0

S1

Cin

COM1

COM2

66 65

S2/O2

S3/O3

S27/O27/CMPI

S26/O26NCNC

COM0

64 63 62 61

40 41 42 43

NC

S5/O5

S6/O6

S4/O4

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

NC

NC
S23/O23
S22/O22
S18/O18
S17/O17
S16/O16
S15/O15
S14/O14
S13/O13
S12/O12
S11/O11
S10/O10
S9/O9
S8/O8
S7/O7
NC
NC

†

MSP430P313/E313 not recommended for new designs – replaced by MSP430P315/E315.

28

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430x31x

MIXED SIGNAL MICROCONTROLLERS

SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000

MECHANICAL DATA

FZ (S-CQCC-J**) J-LEADED CERAMIC CHIP CARRIER

28 LEAD SHOWN

0.040 (1,02)  45°

5

A B

11

12

A

B

1426

18

0.180 (4,57)

0.155 (3,94)

0.140 (3,55)

0.120 (3,05)

25

0.032 (0,81)

0.026 (0,66)

19

0.025 (0,64) R TYP

Seating Plane

0.050 (1,27)

C

(at Seating

Plane)

0.020 (0,51)

0.014 (0,36)

0.040 (1,02) MIN

0.120 (3,05)

0.090 (2,29)

NO. OFJEDEC

OUTLINE

MO-087AA

MO-087AB

MO-087AC

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.

PINS**

28

44

52

68MO-087AD

MIN MAX

0.485

(12,32) (12,57)

A

0.495

BC

0.430

MAXMIN

0.455

(11,56)(10,92)

MIN MAX

0.410

(10,41) (10,92)

0.430

0.6300.6100.630 0.6550.6950.685

(16,00)(15,49)(16,00) (16,64)(17,65)(17,40)

0.7400.6800.730 0.7650.7950.785

(18,79)(17,28)(18,54) (19,43)(20,19)(19,94)

0.9300.9100.930 0.9550.9950.985

(23,62)(23,11)(23,62) (24,26)(25,27)(25,02)

4040219/B 03/95

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

29

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