TEXAS INSTRUMENTS MSP430x241x Technical data
MSP430x241x, MSP430x261x
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
D Low Supply-Voltage Range, 1.8 V to 3.6 V
D Ultralow-Power Consumption:
-- Active Mode: 365 μAat1MHz,2.2V
-- Standby Mode (VLO): 0.5 μA
-- Off Mode (RAM Retention): 0.1 μA
D Wake-Up From Standby Mode in Less
Than 1 μs
D 16-Bit RISC Architecture,
62.5-nsInstruction Cycle Time
D Three-Channel Internal DMA
D 12-Bit Analog-to-Digital (A/D) Converter
With Internal Reference, Sample-and-Hold,
and Autoscan Feature
D Dual 12-Bit Digital-to-Analog (D/A)
Converters With Synchronization
D 16-Bit Timer_A With Three
Capture/Compare Registers
D 16-Bit Timer_B With Seven
Capture/Compare-With-Shadow Registers
D On-Chip Comparator
D Four Universal Serial Communication
Interfaces (USCIs)
-- USCI_A0 and USCI_A1
-- Enhanced UART Supporting
Auto-Baudrate Detection
-- IrDA Encoder and Decoder
-- Synchronous SPI
-- USCI_B0 and USCI_B1
2
Ct
-- I
-- Synchronous SPI
description
D Supply Voltage Supervisor/Monitor With
Programmable Level Detection
D Brownout Detector
D Bootstrap Loader
D Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
D Family Members Include:
-- MSP430F2416:
92KB+256B Flash Memory, 4KB RAM
-- MSP430F2417:
92KB+256B Flash Memory, 8KB RAM
-- MSP430F2418:
116KB+256B Flash Memory, 8KB RAM
-- MSP430F2419:
120KB+256B Flash Memory, 4KB RAM
-- MSP430F2616:
92KB+256B Flash Memory, 4KB RAM
-- MSP430F2617:
92KB+256B Flash Memory, 8KB RAM
-- MSP430F2618:
116KB+256B Flash Memory, 8KB RAM
-- MSP430F2619:
120KB+256B Flash Memory, 4KB RAM
D Availablein80-PinQuadFlatPack(QFP)
and 64-Pin QFP (See Available Options)
D For Complete Module Descriptions, See the
MSP430x2xx Family User’s Guide,
Literature Number SLAU144
†
The MSP430F241x devices are identical to the MSP430F261x
devices, with the exception that the DAC12 modules and the DMA
controller are not implemented.
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes is optimized to achieve extended battery life in por table measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The calibrated digitally controlled oscillator (DCO) allows wake-up from low-power modes to active
mode in less than 1 μs.
The MSP430F261x/241x series are microcontroller configurations with two built-in 16-bit timers, a fast 12-bit
A/D converter, a comparator, dual 12-bit D/A converters, four universal serial communication interface (USCI)
modules, DMA, and up to 64 I/O pins. The MSP430F241x devices are identical to the MSP430F261x devices,
with the exception that the DAC12 and the DMA modules are not implemented.
Typical applications include sensor systems, industrial control applications, hand-held meters, etc.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I2C is a registered trademark of Philips Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright © 2007, Texas Instruments Incorporated
1
MSP430x241x, MSP430x261x
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
T
A
-- 4 0 °C to 105°C
PLASTIC 80-PIN LQFP (PN) PLASTIC 64-PIN LQFP (PM)
MSP430F2416TPN
MSP430F2417TPN
MSP430F2418TPN
MSP430F2419TPN
MSP430F2616TPN
MSP430F2617TPN
MSP430F2618TPN
MSP430F2619TPN
AVAILABLE OPTIONS
PACKAGED DEVICES
MSP430F2416TPM
MSP430F2417TPM
MSP430F2418TPM
MSP430F2419TPM
MSP430F2616TPM
MSP430F2617TPM
MSP430F2618TPM
MSP430F2619TPM
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
pin designation, MSP430F241x, 80-pin package
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
SS1
AVSSP6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
AVCCDV
TDI/TCLK
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
TDO/TDI
P8.7/XT2IN
P8.5
P8.6/XT2OUT
P8.2
P8.3
P8.4
P7.7
P8.0
P8.1
DV
CC1
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7/SVSIN
V
REF+
XIN
XOUT
Ve
REF+
V
/Ve
REF-
REF-
P1.0/TACLK/CAOUT
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
P1.5/TA0
P1.6/TA1
P1.7/TA2
P2.0/ACLK/CA2
78 77 76 75 74 73 72 71 70 69 68 67 66 65
80 79
1
2
3
4
5
6
7
8
9
10
11
12
80-pin
PN PACKAGE
(TOP VIEW)
13
14
15
16
17
18
19
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
/CA5
OSC
P2.7/TA0/CA7
P2.5/R
P2.6/ADC12CLK/CA6
P3.0/UCB0STE/UCA0CLK
P3.3/UCB0CLK/UCA0STE
P3.2/UCB0SOMI/UCB0SCL
P3.1/UCB0SIMO/UCB0SDA
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/CA0/TA1
P2.4/CA1/TA2
P3.6/UCA1TXD/UCA1SIMO
P3.7/UCA1RXD/UCA1SOMI
64
37
P4.0/TB0
63 62 61
38 39 40
P4.1/TB1
P4.2/TB2
P4.3/TB3
60
P7.6
59
P7.5
58
P7.4
57
P7.3
56
P7.2
55
P7.1
54
P7.0
53
DV
SS2
52
DV
CC2
51
P5.7/TBOUTH/SVSOUT
50
P5.6/ACLK
49
P5.5/SMCLK
48
P5.4/MCLK
47
P5.3/UCB1CLK/UCA1STE
46
P5.2/UCB1SOMI/UCB1SCL
45
P5.1/UCB1SIMO/UCB1SDA
44
P5.0/UCB1STE/UCA1CLK
43
P4.7/TBCLK
42
P4.6/TB6
P4.5/TB5
41
P4.4/TB4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
MSP430x241x, MSP430x261x
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
pin designation, MSP430F241x, 64-pin package
SS1
AVSSP6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
64-pin
(TOP VIEW)
DV
CC1
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7/SVSIN
V
REF+
XIN
XOUT
Ve
REF+
V
/Ve
REF-
REF-
P1.0/TACLK/CAOUT
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
AVCCDV
64 63
62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
3
4
5
6
7
8
9
PM PACKAGE
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
P5.5/SMCLK
P5.7/TBOUTH/SVSOUT
P5.6/ACLK
48
P5.4/MCLK
47
P5.3/UC B1CLK/UCA1 STE
46
P5.2/UCB1SOMI/UCB1SCL
45
P5.1/UC B1SIMO/UCB 1 SDA
44
P5.0/UC B1STE/UCA1 CLK
43
P4.7/TBCLK
42
P4.6/TB6
41
P4.5/TB5
40
P4.4/TB4
39
P4.3/TB3
38
P4.2/TB2
37
P4.1/TB1
36
P4.0/TB0
35
P3.7/UC A1RXD/UCA1SOMI
34
P3.6/UC A1TXD/UCA1 SIMO
33
P3.5/UC A0RXD/UCA0SOMI
/CA5
P2.3/CA0/TA1
P2.4/CA1/TA2
OSC
P2.7/TA0/CA7
P2.5/R
P2.6/ADC12CLK/CA6
P3.0/UCB0STE/UCA0CLK
P3.3/UCB0CLK/UCA0STE
P3.2/UCB0SOMI/UCB0SCL
P3.1/UCB0SIMO/UCB0SDA
P3.4/UCA0TXD/UCA0SIMO
P1.5/TA0
P1.6/TA1
P1.7/TA2
P2.0/ACLK/CA2
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
pin designation, MSP430F261x, 80-pin package
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
SS1
AVSSP6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
AVCCDV
TDI/TCLK
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
TDO/TDI
P8.5
P8.6/XT2OUT
P8.7/XT2IN
P8.2
P8.3
P8.4
P7.7
P8.0
P8.1
DV
CC1
P6.3/A3
P6.4/A4
P6.5/A5/DAC1
P6.6/A6/DAC0
P6.7/A7/DAC1/SVSIN
V
REF+
XIN
XOUT
Ve
/DAC0
REF+
V
/Ve
REF-
REF-
P1.0/TACLK/CAOUT
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
P1.5/TA0
P1.6/TA1
P1.7/TA2
P2.0/ACLK/CA2
80 79
78 77 76 75 74 73 72 71 70 69 68 67 66 65
1
2
3
4
5
6
7
8
9
10
11
12
80-pin
PN PACKAGE
(TOP VIEW)
13
14
15
16
17
18
19
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
/CA5
OSC
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.7/TA0/CA7
P2.5/R
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P3.0/UCB0STE/UCA0CLK
P2.6/ADC12CLK/DMAE0/CA6
P3.3/UCB0CLK/UCA0STE
P3.2/UCB0SOMI/UCB0SCL
P3.1/UCB0SIMO/UCB0SDA
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/UCA1TXD/UCA1SIMO
P3.7/UCA1RXD/UCA1SOMI
64
37
P4.0/TB0
63 62 61
38 39 40
P4.1/TB1
P4.2/TB2
60
P7.6
59
P7.5
58
P7.4
57
P7.3
56
P7.2
55
P7.1
54
P7.0
53
DV
SS2
52
DV
CC2
51
P5.7/TBOUTH/SVSOUT
50
P5.6/ACLK
49
P5.5/SMCLK
48
P5.4/MCLK
47
P5.3/UCB1CLK/UCA1STE
46
P5.2/UCB1SOMI/UCB1SCL
45
P5.1/UCB1SIMO/UCB1SDA
44
P5.0/UCB1STE/UCA1CLK
43
P4.7/TBCLK
42
P4.6/TB6
P4.5/TB5
41
P4.3/TB3
P4.4/TB4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
MSP430x241x, MSP430x261x
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
pin designation, MSP430F261x, 64-pin package
SS1
AVSSP6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
64-pin
(TOP VIEW)
DV
CC1
P6.3/A3
P6.4/A4
P6.5/A5/DAC1
P6.6/A6/DAC0
P6.7/A7/DAC1/SVSIN
V
REF+
XIN
XOUT
Ve
/DAC0
REF+
V
/Ve
REF-
REF-
P1.0/TACLK/CAOUT
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
AVCCDV
64 63
62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PM PACKA GE
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
P5.5/SMCLK
P5.7/TBOUTH/SVSOUT
P5.6/ACLK
48
P5.4/MCLK
47
P5.3/UCB1CLK/UCA1STE
46
P5.2/UCB1SOMI/UCB1SCL
45
P5.1/UCB1SIMO/UCB1SDA
44
P5.0/UCB1STE/UCA1CLK
43
P4.7/TBCLK
42
P4.6/TB6
41
P4.5/TB5
40
P4.4/TB4
39
P4.3/TB3
38
P4.2/TB2
37
P4.1/TB1
36
P4.0/TB0
35
P3.7/UCA1RXD/UCA1SOMI
34
P3.6/UCA1TXD/UCA1SIMO
33
P3.5/UCA0RXD/UCA0SOMI
/CA5
P1.5/TA0
P1.6/TA1
P1.7/TA2
P2.0/ACLK/CA2
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
OSC
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.7/TA0/CA7
P2.5/R
P3.0/UCB0STE/UCA0CLK
P2.6/ADC12CLK/DMAE0/CA6
P3.3/UCB0CLK/UCA0STE
P3.2/UCB0SOMI/UCB0SCL
P3.1/UCB0SIMO/UCB0SDA
P3.4/UCA0TXD/UCA0SIMO
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram, MSP430F241x, 80-pin package
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
XIN/
XT2IN
Oscillators
Basic Clock
System+
16MHz
CPU
1MB
incl. 16
Registers
Emulation
JTAG
Interface
XOUT/
XT2OUT
22
MCLK
ACLK
SMCLK
DVCC1/2 DVSS1/2
Flash
120kB
116kB
92kB
92kB
MAB
MDB
Brownout
Protection
SVS,
SVM
RST/NMI
RAM
4kB
8kB
8kB
4kB
Hardware
Multiplier
MPY,
MPYS,
MAC,
MACS
AVCC AVSS P1.x/P2.x
ADC12
12-Bit
8
Channels
Watchdog
WDT+
15-Bit
Ports
P1/P2
2x8 I/O
Interrupt
capability
Timer_A3
3 CC
Registers
2x8
P3.x/P4.x
P5.x/P6.x
4x8
Ports
P3/P4
P5/P6
4x8 I/O
Timer_B7
7 CC
Registers,
Shadow
Reg
P7.x/P8.x
Ports
P7/P8
2x8/1x16
I/O
Comp_A+
8
Channels
2x8/
1x16
USCI A0
UART/
LIN,
IrDA, SPI
USCI B0
SPI, I2C
USCI A1
UART/
LIN,
IrDA, SPI
USCI B1
SPI, I2C
functional block diagram, MSP430F241x, 64-pin package
XOUT/
XIN/
XT2IN
Oscillators
Basic Clock
System+
16MHz
CPU
1MB
incl. 16
Registers
Emulation
JTAG
Interface
XT2OUT
22
ACLK
SMCLK
MCLK
DVCC DVSS
Flash
120kB
116kB
92kB
92kB
MAB
MDB
Brownout
Protection
SVS,
SVM
RAM
4kB
8kB
8kB
4kB
Hardware
Multiplier
MPY,
MPYS,
MAC,
MACS
AVCC AVSS P1.x/P2.x
ADC12
12-Bit
8
Channels
Watchdog
WDT+
15-Bit
Ports
P1/P2
2x8 I/O
Interrupt
capability
Timer_A3
3 CC
Registers
2x8
P3.x/P4.x
P5.x/P6.x
4x8
Ports
P3/P4
P5/P6
4x8 I/O
Timer_B7
7 CC
Registers,
Shadow
Reg
Comp_A+
8
Channels
USCI A0
UART/
LIN,
IrDA, SPI
USCI B0
SPI, I2C
USCI A1
UART/
LIN,
IrDA, SPI
USCI B1
SPI, I2C
RST/NMI
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
MSP430x241x, MSP430x261x
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
functional block diagram, MSP430F261x, 80-pin package
XIN/
XT2IN
Oscillators
Basic Clock
System+
16MHz
CPU
1MB
incl. 16
Registers
Emulation
JTAG
Interface
XOUT/
XT2OUT
22
MCLK
ACLK
SMCLK
DVCC1/2 DVSS1/2
Flash
120kB
116kB
92kB
92kB
56kB
MAB
MDB
Brownout
Protection
SVS,
SVM
RST/NMI
RAM
4kB
8kB
8kB
4kB
4kB
Hardware
Multiplier
MPY,
MPYS,
MAC,
MACS
AVCC AVSS P1.x/P2.x
ADC12
12-Bit
8
Channels
DMA
Controller
3
Channels
DAC12
12-Bit
2
Channels
Voltage
Out
Watchdog
WDT+
15-Bit
Ports
P1/P2
2x8 I/O
Interrupt
capability
Timer_A3
3 CC
Registers
2x8
P3.x/P4.x
P5.x/P6.x
4x8
Ports
P3/P4
P5/P6
4x8 I/O
Timer_B7
7 CC
Registers,
Shadow
Reg
P7.x/P8.x
Ports
P7/P8
2x8/1x16
I/O
Comp_A+
8
Channels
2x8/
1x16
USCI A0
UART/
LIN,
IrDA, SPI
USCI B0
SPI, I2C
USCI A1
UART/
LIN,
IrDA, SPI
USCI B1
SPI, I2C
functional block diagram, MSP430F261x, 64-pin package
XIN/
XT2IN
Oscillators
Basic Clock
System+
16MHz
CPU
1MB
incl. 16
Registers
Emulation
JTAG
Interface
XOUT/
XT2OUT
22
ACLK
SMCLK
MCLK
DVCC DVSS
Flash
120kB
116kB
92kB
92kB
56kB
MAB
MDB
Brownout
Protection
SVS,
SVM
RAM
4kB
8kB
8kB
4kB
4kB
Hardware
Multiplier
MPY,
MPYS,
MAC,
MACS
AVCC AVSS P1.x/P2.x
ADC12
12-Bit
8
Channels
DMA
Controller
3
Channels
DAC12
12-Bit
2
Channels
Voltage
Out
Watchdog
WDT+
15-Bit
Ports
P1/P2
2x8 I/O
Interrupt
capability
Timer_A3
3 CC
Registers
2x8
P3.x/P4.x
P5.x/P6.x
4x8
Ports
P3/P4
P5/P6
4x8 I/O
Timer_B7
7 CC
Registers,
Shadow
Reg
Comp_A+
8
Channels
USCI A0
UART/
LIN,
IrDA, SPI
USCI B0
SPI, I2C
USCI A1
UART/
LIN,
IrDA, SPI
USCI B1
SPI, I2C
8
RST/NMI
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
I/ODESCRIPTIO
N
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Terminal Functions
TERMINAL
NO.
NAME
AV
CC
AV
SS
DV
CC1
DV
SS1
DV
CC2
DV
SS2
P1.0/TACLK/
CAOUT
P1.1/TA0 13 13 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit
P1.2/TA1 14 14 I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output
P1.3/TA2 15 15 I/O General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output
P1.4/SMCLK 16 16 I/O General-purpose digital I/O pin/SMCLK signal output
P1.5/TA0 17 17 I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output
P1.6/TA1 18 18 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output
P1.7/TA2 19 19 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output
P2.0/ACLK/CA2 20 20 I/O General-purpose digital I/O pin/ACLK output/Comparator_A input
P2.1/TAINCLK/
CA3
P2.2/CAOUT/
TA0 / C A 4
P2.3/CA0/TA1 23 23 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/Comparator_A input
P2.4/CA1/TA2 24 24 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/Comparator_A input
P2.5/Rosc/CA5 25 25 I/O
P2.6/ADC12CLK/
DMAE0†/CA6
P2.7/TA0/CA7 27 27 I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output/Comparator_A input
P3.0/UCB0STE/
UCA0CLK
P3.1/UCB0SIMO/
UCB0SDA
P3.2/UCB0SOMI/
UCB0SCL
P3.3/UCB0CLK/
UCA0STE
P3.4/UCA0TXD/
UCA0SIMO
P3.5/UCA0RXD/
UCA0SOMI
P3.6/UCA1TXD/
UCA1SIMO
P3.7/UCA1RXD/
UCA1SOMI
†
MSP430F261x devices only
64
PIN80PIN
64 80 Analog supply voltage, positive terminal. Supplies only the analog portion of ADC12 and DAC12.
62 78 Analog supply voltage, negative terminal. Supplies only the analog portion of ADC12 and DAC12.
1 1 Digital supply voltage, positive terminal. Supplies all digital parts.
63 79 Digital supply voltage, negative terminal. Supplies all digital parts.
52 Digital supply voltage, positive terminal. Supplies all digital parts.
53 Digital supply voltage, negative terminal. Supplies all digital parts.
12 12 I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input/Comparator_A output
21 21 I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK
22 22 I/O
26 26 I/O
28 28 I/O General-purpose digital I/O pin/USCI B0 slave transmit enable/USCI A0 clock input/output
29 29 I/O General-purpose digital I/O pin/USCI B0 slave in/master out in SPI mode, SDA I2C data in I2Cmode
30 30 I/O General-purpose digital I/O pin/USCI B0 slave out/master in in SPI mode, SCL I2C clock in I2Cmode
31 31 I/O General-purpose digital I/O/USCI B0 clock input/output, USCI A0 slave transmit enable
32 32 I/O
33 33 I/O
34 34 I/O
35 35 I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0B input/Comparator_A output/BSL
receive/Comparator_A input
General-purpose digital I/O pin/input for external resistor defining the DCO nominal
frequency/Comparator_A input
General-purpose digital I/O pin/conversion clock – 12 -bit ADC/DMA channel 0 external
trigger/Comparator_A input
General-purpose digital I/O pin/USCIA transmit data output in UART mode, slave data in/master out
in SPI mode
General-purpose digital I/O pin/USCI A0 receive data input in UART mode, slave data out/master
in in SPI mode
General-purpose digital I/O pin/USCI A1 transmit data output in UART mode, slave data in/master
out in SPI mode
General-purpose digital I/O pin/USCIA1 receive data input in UART mode, slave data out/master
in in SPI mode
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
MSP430x241x, MSP430x261x
I/ODESCRIPTIO
N
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Terminal Functions (Continued)
TERMINAL
NO.
NAME
P4.0/TB0 36 36 I/O General-purpose digital I/O pin/Timer_B, capture: CCI0A/B input, compare: Out0 output
P4.1/TB1 37 37 I/O General-purpose digital I/O pin/Timer_B, capture: CCI1A/B input, compare: Out1 output
P4.2/TB2 38 38 I/O General-purpose digital I/O pin/Timer_B, capture: CCI2A/B input, compare: Out2 output
P4.3/TB3 39 39 I/O General-purpose digital I/O pin/Timer_B, capture: CCI3A/B input, compare: Out3 output
P4.4/TB4 40 40 I/O General-purpose digital I/O pin/Timer_B, capture: CCI4A/B input, compare: Out4 output
P4.5/TB5 41 41 I/O General-purpose digital I/O pin/Timer_B, capture: CCI5A/B input, compare: Out5 output
P4.6/TB6 42 42 I/O General-purpose digital I/O pin/Timer_B, capture: CCI6A input, compare: Out6 output
P4.7/TBCLK 43 43 I/O General-purpose digital I/O pin/Timer_B, clock signal TBCLK input
P5.0/UCB1STE/
UCA1CLK
P5.1/UCB1SIMO/
UCB1SDA
P5.2/UCB1SOMI/
UCB1SCL
P5.3/UCB1CLK/
UCA1STE
P5.4/MCLK 48 48 I/O General-purpose digital I/O pin/main system clock MCLK output
P5.5/SMCLK 49 49 I/O General-purpose digital I/O pin/submain system clock SMCLK output
P5.6/ACLK 50 50 I/O General-purpose digital I/O pin/auxiliary clock ACLK output
P5.7/TBOUTH/
SVSOUT
P6.0/A0 59 75 I/O General-purpose digital I/O pin/analog input A0 – 12-bit ADC
P6.1/A1 60 76 I/O General-purpose digital I/O pin/analog input A1 – 12-bit ADC
P6.2/A2 61 77 I/O General-purpose digital I/O pin/analog input A2 – 12-bit ADC
P6.3/A3 2 2 I/O General-purpose digital I/O pin/analog input A3 – 12-bit ADC
P6.4/A4 3 3 I/O General-purpose digital I/O pin/analog input A4 – 12-bit ADC
P6.5/A5/DAC1
P6.6/A6/DAC0
P6.7/A7/DAC1†/
SVSIN
P7.0 54 I/O General-purpose digital I/O pin
P7.1 55 I/O General-purpose digital I/O pin
P7.2 56 I/O General-purpose digital I/O pin
P7.3 57 I/O General-purpose digital I/O pin
P7.4 58 I/O General-purpose digital I/O pin
P7.5 59 I/O General-purpose digital I/O pin
P7.6 60 I/O General-purpose digital I/O pin
P7.7 61 I/O General-purpose digital I/O pin
P8.0 62 I/O General-purpose digital I/O pin
P8.1 63 I/O General-purpose digital I/O pin
P8.2 64 I/O General-purpose digital I/O pin
P8.3 65 I/O General-purpose digital I/O pin
†
MSP430F261x devices only
64
PIN80PIN
44 44 I/O General-purpose digital I/O pin/USCI B1 slave transmit enable/USCI A1 clock input/output
45 45 I/O General-purpose digital I/O pin/USCI B1slave in/master out in SPI mode, SDA I2C data in I2C mode
46 46 I/O General-purpose digital I/O pin/USCI B1slave out/master in in SPI mode, SCL I2C clock in I2C mode
47 47 I/O General-purpose digital I/O/USCI B1 clock input/output, USCI A1 slave transmit enable
51 51 I/O
†
4 4 I/O General-purpose digital I/O pin/analog input A5 – 12-bit ADC/DAC12.1 output
†
5 5 I/O General-purpose digital I/O pin/analog input A6 – 12-bit ADC/DAC12.0 output
6 6 I/O General-purpose digital I/O pin/analog input a7 – 12-bit ADC/DAC12.1 output/SVS input
General-purpose digital I/O pin/switch all PWM digital output ports to high impedance -- Timer_B
TB0 to TB6/SVS comparator output
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
I/ODESCRIPTIO
N
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Terminal Functions (Continued)
TERMINAL
NO.
NAME
P8.4 66 I/O General-purpose digital I/O pin
P8.5 67 I/O General-purpose digital I/O pin
P8.6/XT2OUT 68 O General-purpose digital I/O pin/Output terminal of crystal oscillator XT2
P8.7/XT2IN 69 I
XT2OUT 52 O Output terminal of crystal oscillator XT2
XT2IN 53 I Input port for crystal oscillator XT2
RST/NMI 58 74 I Reset input, nonmaskable interrupt input port, or bootstrap loader start (in flash devices).
TCK 57 73 I Test clock (JTAG). TCK is the clock input port for device programming test and bootstrap loader start.
TDI/TCLK 55 71 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TDO/TDI 54 70 I/O Test data output port. TDO/TDI data output or programming data input terminal.
TMS 56 72 I Test mode select. TMS is used as an input port for device programming and test.
Ve
/DAC0
REF+
V
REF+
V
/Ve
REF--
REF--
XIN 8 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT 9 9 O Output port for crystal oscillator XT1. Standard or watch crystals can be connected.
†
MSP430F261x devices only
64
PIN80PIN
General-purpose digital I/O pin/Input port for crystal oscillator XT2. Only standard crystals can be
connected.
†
10 10 I Input for an external reference voltage/DAC12.0 output
7 7 O Output of positive terminal of the reference voltage in the ADC12
11 11 I
Negative terminal for the reference voltage for both sources, the internal reference voltage, or an
external applied reference voltage
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
MSP430x241x, MSP430x261x
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator, respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
Program Counter
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
Table 1. Instruction Word Formats
Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 ------> R5
Single operands, destination only e.g., CALL R8 PC ---->(TOS), R8----> PC
Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE S D SYNTAX EXAMPLE OPERATION
Register D
Indexed D D MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)-- --> M(6+R6)
Symbolic (PC relative) D D MOV EDE,TONI M(EDE) ----> M(TONI)
Absolute D D MOV &MEM,&TCDAT M(MEM) -- --> M(TCDAT)
Indirect D MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) -- --> M(Tab+R6)
Indirect
autoincrement
Immediate D MOV #X,TONI MOV #45,TONI #45 -- --> M(TONI)
NOTE: S = source D = destination
D
D MOV @Rn+,Rm MOV @R10+,R11
MOV Rs,Rd MOV R10,R11 R10 ----> R11
M(R10) -- --> R11
R10 + 2----> R10
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D Active mode (AM)
-- All clocks are active.
D Low-power mode 0 (LPM0)
-- CPU is disabled.
ACLK and SMCLK remain active. MCLK is disabled.
D Low-power mode 1 (LPM1)
-- CPU is disabled.
ACLK and SMCLK remain active. MCLK is disabled.
DCO’s dc-generator is disabled if DCO not used in active mode.
D Low-power mode 2 (LPM2)
-- CPU is disabled.
MCLK and SMCLK are disabled.
DCO’s dc-generator remains enabled.
ACLK remains active.
D Low-power mode 3 (LPM3)
-- CPU is disabled.
MCLK and SMCLK are disabled.
DCO’s dc-generator is disabled.
ACLK remains active.
D Low-power mode 4 (LPM4)
-- CPU is disabled.
ACLK is disabled.
MCLK and SMCLK are disabled.
DCO’s dc-generator is disabled.
Crystal oscillator is stopped.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
MSP430x241x, MSP430x261x
0x0FFDAto1
3to0
Reserved(seeNotes7and8)Reserved
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0x0FFFF to 0x0FFC0.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. If the reset
vector (0x0FFFE) contains 0xFFFF (e.g., flash is not programmed), the CPU enters LPM4 after power-up.
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
Power-up
External Reset
Watchdog
Flash Key Violation
PC out of range (see Note 1)
NMI
Oscillator Fault
Flash memory access violation
Timer_B7
Timer_B7
Comparator_A+ CAIFG Maskable 0x0FFF6 27
Watchdog timer+ WDTIFG Maskable 0x0FFF4 26
Timer_A3 TACCR0 CCIFG (see Note 3) Maskable 0x0FFF2 25
Timer_A3
USCI_A0/USCI_B0 receive
USCI_B0 I2C status
USCI_A0/USCI_B0 transmit
USCI_B0 I2C receive/transmit
ADC12 ADC12IFG (see Notes 2 and 3) Maskable 0x0FFEA 21
I/O port P2 (eight flags) P2IFG.0 to P2IFG.7 (see Notes 2 and 3) Maskable 0x0FFE6 19
I/O port P1 (eight flags) P1IFG.0 to P1IFG.7 (see Notes 2 and 3) Maskable 0x0FFE4 18
USCI_A0/USCI_B1 receive
USCI_B1 I2C status
USCI_A1/USCI_B1 transmit
USCI_B1 I2C receive/transmit
DMA
DAC12
NOTES: 1. A reset is executed if the CPU tries to fetch instructions from within the module register memory address range (0x00000 to 0x001FF)
or from within unused address ranges.
2. Multiple source flags.
3. Interrupt flags are located in the module.
4. In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
5. In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
6. (Non)maskable: The individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot.
7. The address 0x0FFBE is used as bootstrap loader security key (BSLSKEY).
A 0x0AA55 at this location disables the BSL completely.
A zero disables the erasure of the flash if an invalid password is supplied.
8. The interrupt vectors at addresses 0x0FFDA to 0x0FFC0 are not used in this device and can be used for regular program code if
necessary.
ACCVIFG (see Notes 2 and 6)
TBCCR1 to TBCCR6 CCIFGs, TBIFG
TAIFG (see Notes 2 and 3)
UCA0RXIFG, UCB0RXIFG
UCA0TXIFG, UCB0TXIFG
UCA1RXIFG, UCB1RXIFG
UCA1TXIFG, UCB1TXIFG
DMA0IFG, DMA1IFG, DMA2IFG
DAC12_0IFG, DAC12_1IFG
PORIFG
WDTIFG
RSTIFG
KEYV (see Note 2)
NMIIFG
OFIFG
TBCCR0 CCIFG
(see Note 3)
(see Notes 2 and 3)
TACCR1 CCIFG
TACCR2 CCIFG
(see Notes 2 and 4)
(see Note 2 and 4)
(see Notes 2 and 4)
(see Notes 2 and 5)
(see Notes 2 and 3)
(see Notes 2 and 3)
Reset 0x0FFFE 31, highest
(Non)maskable
(Non)maskable
(Non)maskable
Maskable 0x0FFFA 29
Maskable 0x0FFF8 28
Maskable 0x0FFF0 24
Maskable 0x0FFEE 23
Maskable 0x0FFEC 22
Maskable 0x0FFE2 17
Maskable 0x0FFE0 16
Maskable 0x0FFDE 15
Maskable 0x0FFDC 14
0x0FFFC 30
0x0FFE8 20
0x0FFC0 lowest
,
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
special function registers
Most interrupt enable bits are collected in the lowest address space. Special-function register bits not allocated
to a functional purpose are not physically present in the device. This arrangement provides simple software
access.
interrupt enable 1 and 2
Address76543210
00h
WDTIE Watchdog timer interrupt enable. Inactive if watchdog mode is selected.
Active if watchdog timer is configured as general-purpose timer.
OFIE Oscillator-fault-interrupt enable
NMIIE Nonmaskable-interrupt enable
ACCVIE Flash memory access violation interrupt enable
ACCVIE NMIIE OFIE WDTIE
rw--0 rw--0 rw--0 rw--0
Interrupt Enable Register 1
Address76543210
01h
UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE
rw--0 rw--0 rw--0 rw--0
Interrupt Enable Register 2
UCA0RXIE USCI_A0 receive-interrupt enable
UCA0TXIE USCI_A0 transmit-interrupt enable
UCB0RXIE USCI_B0 receive-interrupt enable
UCB0TXIE USCI_B0 transmit-interrupt enable
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
15
MSP430x241x, MSP430x261x
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
interrupt flag register 1 and 2
Address76543210
02h
Interrupt Flag Register 1
WDTIFG Set on watchdog timer overflow or security key violation
Reset on V
power-on or a reset condition at the RST/NMI pin in reset mode
CC
OFIFG Flag set on oscillator fault7
PORIFG Power--on interrupt flag. Set on V
RSTIFG External reset interrupt flag. Set on a reset condition at RST
on V
NMIIFG Set via RST
Address76543210
03h
power up.
CC
/NMI pin
NMIIFG RSTIFG PORIFG OFIFG WDTIFG
rw--0 rw--(0) rw--(1) rw--1 rw --(0)
power up.
CC
UCB0TX
IFG
rw--1 rw--0 rw--1 rw--0
/NMI pin in reset mode. Reset
UCB0RX
IFG
UCA0TX
IFG
UCA0RX
IFG
Interrupt Flag Register 2
UCA0RXIFG USCI_A0 receive-interrupt flag
UCA0TXIFG USCI_A0 transmit-interrupt flag
UCB0RXIFG USCI_B0 receive-interrupt flag
UCB0TXIFG USCI_B0 transmit-interrupt flag
Legend rw: Bit can be read and written.
rw-0,1: B it can be read and w ritten. It is R eset or Set by PU C.
rw-(0,1) B it can be read and w ritten. It is R eset or Set by PO R.
SFR bit is not present in device.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
memory organization
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Memory
Main: interrupt vector
Main: code memory
RAM (total)
Extended
Mirrored
Information memory Size
Boot memory Size
RAM (mirrored at
0x18FF to 0x01100)
Peripherals 16-bit
Memory
Main: interrupt vector
Main: code memory
RAM (total)
Extended
Mirrored
Information memory Size
Boot memory Size
RAM (mirrored at
0x18FF to 0x01100)
Peripherals 16-bit
Size
Flash
Flash
Size
Size
Size
Flash
ROM
Size 2KB
8-bit
8-bit SFR
Size
Flash
Flash
Size
Size
Size
Flash
ROM
Size 2KB
8-bit
8-bit SFR
MSP430F2416
MSP430F2616
92KB
0x0FFFF -- 0x0FFC0
0x18FFF -- 0x02100
4kB
0x020FF -- 0x01100
2kB
0x020FF -- 0x01900
2kB
0x018FF -- 0x01100
256 Byte
0x010FF -- 0x01000
1KB
0x00FFF -- 0x00C00
0x009FF -- 0x00200
0x001FF -- 0x00100
0x000FF -- 0x00010
0x0000F -- 0x00000
MSP430F2618
MSP430F2418
116KB
0x0FFFF -- 0x0FFC0
0x1FFFF -- 0x03100
8kB
0x030FF -- 0x01100
6kB
0x030FF -- 0x01900
2kB
0x018FF -- 0x01100
256 Byte
0x010FF -- 0x01000
1KB
0x00FFF -- 0x00C00
0x009FF -- 0x00200
0x001FF -- 0x00100
0x000FF -- 0x00010
0x0000F -- 0x00000
MSP430F2417
MSP430F2617
92KB
0x0FFFF -- 0x0FFC0
0x19FFF -- 0x03100
8kB
0x030FF -- 0x01100
6kB
0x030FF -- 0x01900
2kB
0x018FF -- 0x01100
256 Byte
0x010FF -- 0x01000
1KB
0x00FFF -- 0x00C00
2KB
0x009FF -- 0x00200
0x001FF -- 0x00100
0x000FF -- 0x00010
0x0000F -- 0x00000
MSP430F2619
MSP430F2419
120KB
0x0FFFF -- 0x0FFC0
0x1FFFF -- 0x02100
4kB
0x020FF -- 0x01100
2kB
0x020FF -- 0x01900
2kB
0x018FF -- 0x01100
256 Byte
0x010FF -- 0x01000
1KB
0x00FFF -- 0x00C00
2KB
0x009FF -- 0x00200
0x001FF -- 0x00100
0x000FF -- 0x00010
0x0000F -- 0x00000
bootstrap loader (BSL)
The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access
to the MSP430 memory via the BSL is protected by a user-defined password. For complete description of the
features of the BSL and its implementation, see the application report Features of the MSP430 Bootstrap
Loader, literature number SLAA089.
BSL Function PM, RTD Package Pins
Data Transmit 13 - P1.1
Data Receive 22 - P2.2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
17
MSP430x241x, MSP430x261x
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and four segments of information memory (A to D) of 64
bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A to D can be erased individually, or as a group with segments 0 to n.
Segments A to D are also called information memory.
D Segment A contains calibration data. After reset, segment A is protected against programming or erasing.
It can be unlocked, but care should be taken not to erase this segment if the calibration data is required.
D Flash content integrity check with marginal read modes
peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User’s Guide, literature number
SLAU144.
DMA controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to
or from a peripheral.
oscillator and system clock
The clock system in the MSP430x241x and MSP43x261x family of devices is supported by the basic clock
module that includes support for a 32768-Hz watch crystal oscillator, an internal very low power, low frequency
oscillator,an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock
module is designed to meet the requirements of both low system cost and low-power consumption. The internal
DCO provides a fast turn-on clock source and stabilizes in less than 1 μs. The basic clock module provides the
following clock signals:
D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high frequency crystal, or a very
low-power LF oscillator
D Main clock (MCLK), the system clock used by the CPU
D Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules
The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
calibration data stored in information memory segment A
Calibration data is stored for the DCO and for the ADC12. It is organized in a tag-length-value (TLV) structure.
TAGS USED BY THE ADC CALIBRATION TAGS
NAME ADDRESS VALU E DESCRIPTION
TAG_DCO_30 0x10F6 0x01 DCO frequency calibration at VCC = 3 V and TA=25°C at calibration
TAG_ADC12_1 0x10DA 0x10 ADC12_1 calibration tag
TAG_EMPTY -- 0xFE Identifier for empty memory areas
LABELS USED BY THE ADC CALIBRATION TAGS
LABEL CONDITION AT CALIBRATION / DESCRIPTION SIZE ADDRESS OFFSET
CAL_ADC_25T85 INCHx = 0x1010; REF2_5 = 1, TA=85°C word 0x000E
CAL_ADC_25T30 INCHx = 0x1010; REF2_5 = 1, TA=30°C word 0x000C
CAL_ADC_25VREF_FACTOR REF2_5 = 1, TA=30°C word 0x000A
CAL_ADC_15T85 INCHx = 0x1010; REF2_5 = 0, TA=85°C word 0x0008
CAL_ADC_15T30 INCHx = 0x1010; REF2_5 = 0, TA=30°C word 0x0006
CAL_ADC_15VREF_FACTOR REF2_5 = 0, TA=30°C word 0x0004
CAL_ADC_OFFSET External V
CAL_ADC_GAIN_FACTOR External V
CAL_BC1_1MHz -- byte 0x0007
CAL_DCO_1MHz -- byte 0x0006
CAL_BC1_8MHz -- byte 0x0005
CAL_DCO_8MHz -- byte 0x0004
CAL_BC1_12MHz -- byte 0x0003
CAL_DCO_12MHz -- byte 0x0002
CAL_BC1_16MHz -- byte 0x0001
CAL_DCO_16MHz -- byte 0x0000
REF
REF
=1.5V,f
=1.5V,f
ADC12CLK
ADC12CLK
=5MHz word 0x0002
=5MHz word 0x0000
brownout, supply voltage supervisor (SVS)
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The SVS circuitry detects if the supply voltage drops below a user selectable level and supports
both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the
device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, V
have ramped to V
reaches V
V
CC
CC(min)
CC(min)
at that time. The user must ensure that the default DCO settings are not changed until
. If desired, the SVS circuit can be used to determine when VCCreaches V
may not
CC
CC(min)
.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
19
MSP430x241x, MSP430x261x
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
digital I/O
There are up to eight 8-bit I/O ports implemented—ports P1 through P8:
D All individual I/O bits are independently programmable.
D Any combination of input, output, and interrupt conditions is possible.
D Edge-selectable interrupt input capability for all eight bits of ports P1 and P2.
D Read/write access to port-control registers is supported by all instructions.
D Each I/O has an individually programmable pullup/pulldown r esistor.
D Ports P7/P8 can be accessed word wise.
watchdog timer+ (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.
hardware multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs 16×16,
16×8, 8×16, and 8×8 bit operations. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
universal serial communication interface (USCI)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3 pin or 4 pin) or I
UART, enhanced UART with automatic baudrate detection (LIN), and IrDA.
The USCI A module provides support for SPI (3 pin or 4 pin), UART, enhanced UART, and IrDA.
The USCI B module provides support for SPI (3 pin or 4 pin) and I
2
C, and asynchronous combination protocols such as
2
C.
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
A
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_A3 SIGNAL CONNECTIONS
INPUT PIN
NUMBER
12 - P1.0 TACLK TACL K
21 - P2.1 TAINCLK INCLK
13 - P1.1 TA 0 CCI0A
22 - P2.2 TA 0 CCI0B
14 - P1.2 TA 1 CCI1A
15 - P1.3 TA 2 CCI2A
DEVICE INPUT
SIGNAL
ACLK ACLK
SMCLK SMCLK
DV
SS
DV
CC
CAOUT (internal) CCI1B
DV
SS
DV
CC
ACLK (internal) CCI2B
DV
SS
DV
CC
MODULE INPUT
NAME
GND
V
CC
GND
V
CC
GND
V
CC
MODULE
BLOCK
Timer N
CCR0 TA0
CCR1
CCR2 TA2
MODULE OUTPUT
SIGNAL
TA1
OUTPUT PIN NUMBER
13 - P1.1
17 - P1.5
27 - P2.7
14 - P1.2
18 - P1.6
23 - P2.3
ADC12 (internal)
DAC12_0 (internal)
DAC12_1 (internal)
15 - P1.3
19 - P1.7
24 - P2.4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
21
MSP430x241x, MSP430x261x
A
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
timer_B7
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_B3/B7 SIGNAL CONNECTIONS
INPUT PIN
NUMBER
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
43 - P4.7 TBCLK TBCLK
ACLK ACLK
SMCLK SMCLK
43 - P4.7 TBCLK INCLK
36 - P4.0 TB0 CCI0A
36 - P4.0 TB0 CCI0B
DV
DV
SS
CC
GND
V
CC
37 - P4.1 TB1 CCI1A
37 - P4.1 TB1 CCI1B
DV
DV
SS
CC
GND
V
CC
38 - P4.2 TB2 CCI2A
38 - P4.2 TB2 CCI2B
DV
DV
SS
CC
GND
V
CC
39 - P4.3 TB3 CCI3A
39 - P4.3 TB3 CCI3B
DV
DV
SS
CC
GND
V
CC
40 - P4.4 TB4 CCI4A
40 - P4.4 TB4 CCI4B
DV
DV
SS
CC
GND
V
CC
41 - P4.5 TB5 CCI5A
41 - P4.5 TB5 CCI5B
DV
DV
SS
CC
GND
V
CC
42 - P4.6 TB6 CCI6A
ACLK (internal) CCI6B
DV
DV
SS
CC
GND
V
CC
†
MODULE
BLOCK
MODULE OUTPUT
SIGNAL
Timer N
CCR0 TB0
CCR1 TB1
CCR2 TB2
CCR3 TB3
CCR4 TB4
CCR5 TB5
CCR6 TB6
OUTPUT PIN NUMBER
36 - P4.0
ADC12 (internal)
37 - P4.1
ADC12 (internal)
38 - P4.2
DAC_0(internal)
DAC_1(internal)
39 - P4.3
40 - P4.4
41 - P4.5
42 - P4.6
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
comparator_A+
The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
ADC12
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without
any CPU intervention.
DAC12
The DAC12 module is a 12-bit, R-ladder, voltage output DAC. The DAC12 may be used in 8-bit or 12-bit mode
and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may
be grouped together for synchronous operation.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
23
MSP430x241x, MSP430x261x
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
peripheral file map
†
DMA
†
DAC12
ADC12
†
MSP430F261x devices only
DMA channel 2 transfer size DMA2SZ 0x01F2
DMA channel 2 destination address DMA2DA 0x01EE
DMA channel 2 source address DMA2SA 0x01EA
DMA channel 2 control DMA2CTL 0x01E8
DMA channel 1 transfer size DMA1SZ 0x01E6
DMA channel 1 destination address DMA1DA 0x01E2
DMA channel 1 source address DMA1SA 0x01DE
DMA channel 1 control DMA1CTL 0x01DC
DMA channel 0 transfer size DMA0SZ 0x01DA
DMA channel 0 destination address DMA0DA 0x01D6
DMA channel 0 source address DMA0SA 0x01D2
DMA channel 0 control DMA0CTL 0x01D0
DMA module interrupt vector word DMAIV 0x0126
DMA module control 1 DMACTL1 0x0124
DMA module control 0 DMACTL0 0x0122
DAC12_1 data DAC12_1DAT 0x01CA
DAC12_1 control DAC12_1CTL 0x01C2
DAC12_0 data DAC12_0DAT 0x01C8
DAC12_0 control DAC12_0CTL 0x01C0
Interrupt-vector-word register ADC12IV 0x01A8
Inerrupt-enable register ADC12IE 0x01A6
Inerrupt-flag register ADC12IFG 0x01A4
Control register 1 ADC12CTL1 0x01A2
Control register 0 ADC12CTL0 0x01A0
Conversion memory 15 ADC12MEM15 0x015E
Conversion memory 14 ADC12MEM14 0x015C
Conversion memory 13 ADC12MEM13 0x015A
Conversion memory 12 ADC12MEM12 0x0158
Conversion memory 11 ADC12MEM11 0x0156
Conversion memory 10 ADC12MEM10 0x0154
Conversion memory 9 ADC12MEM9 0x0152
Conversion memory 8 ADC12MEM8 0x0150
Conversion memory 7 ADC12MEM7 0x014E
Conversion memory 6 ADC12MEM6 0x014C
Conversion memory 5 ADC12MEM5 0x014A
Conversion memory 4 ADC12MEM4 0x0148
Conversion memory 3 ADC12MEM3 0x0146
Conversion memory 2 ADC12MEM2 0x0144
Conversion memory 1 ADC12MEM1 0x0142
Conversion memory 0 ADC12MEM0 0x0140
PERIPHERAL FILE MAP
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ADC12
_
_
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
(continued)
Timer_B7
Timer_A3
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
PERIPHERAL FILE MAP (CONTINUED)
ADC memory-control register15 ADC12MCTL15 0x008F
ADC memory-control register14 ADC12MCTL14 0x008E
ADC memory-control register13 ADC12MCTL13 0x008D
ADC memory-control register12 ADC12MCTL12 0x008C
ADC memory-control register11 ADC12MCTL11 0x008B
ADC memory-control register10 ADC12MCTL10 0x008A
ADC memory-control register9 ADC12MCTL9 0x0089
ADC memory-control register8 ADC12MCTL8 0x0088
ADC memory-control register7 ADC12MCTL7 0x0087
ADC memory-control register6 ADC12MCTL6 0x0086
ADC memory-control register5 ADC12MCTL5 0x0085
ADC memory-control register4 ADC12MCTL4 0x0084
ADC memory-control register3 ADC12MCTL3 0x0083
ADC memory-control register2 ADC12MCTL2 0x0082
ADC memory-control register1 ADC12MCTL1 0x0081
ADC memory-control register0 ADC12MCTL0 0x0080
Capture/compare register 6 TBCCR6 0x019E
Capture/compare register 5 TBCCR5 0x019C
Capture/compare register 4 TBCCR4 0x019A
Capture/compare register 3 TBCCR3 0x0198
Capture/compare register 2 TBCCR2 0x0196
Capture/compare register 1 TBCCR1 0x0194
Capture/compare register 0 TBCCR0 0x0192
Timer_B register TBR 0x0190
Capture/compare control 6 TBCCTL6 0x018E
Capture/compare control 5 TBCCTL5 0x018C
Capture/compare control 4 TBCCTL4 0x018A
Capture/compare control 3 TBCCTL3 0x0188
Capture/compare control 2 TBCCTL2 0x0186
Capture/compare control 1 TBCCTL1 0x0184
Capture/compare control 0 TBCCTL0 0x0182
Timer_B control TBCTL 0x0180
Timer_B interrupt vector TBIV 0x011E
Capture/compare register 2 TACCR2 0x0176
Capture/compare register 1 TACCR1 0x0174
Capture/compare register 0 TACCR0 0x0172
Timer_A register TAR 0x0170
Reserved 0x016E
Reserved 0x016C
Reserved 0x016A
Reserved 0x0168
Capture/compare control 2 TACCTL2 0x0166
Capture/compare control 1 TACCTL1 0x0164
Capture/compare control 0 TACCTL0 0x0162
Timer_A control TAC T L 0x0160
Timer_A interrupt vector TAIV 0x012E
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
25
MSP430x241x, MSP430x261x
/
/
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
PERIPHERAL FILE MAP (CONTINUED)
Hardware
Multiplier
Flash
Watchdog Watchdog Timer control WDTCTL 0x0120
USCI A0/B0
USCI A1/B1
Sum extend SUMEXT 0x013E
Result high word RESHI 0x013C
Result low word RESLO 0x013A
Second operand OP2 0x0138
Multiply signed +accumulate/operand1 MACS 0x0136
Multiply+accumulate/operand1 MAC 0x0134
Multiply signed/operand1 MPYS 0x0132
Multiply unsigned/operand1 MPY 0x0130
Flash control 4 FCTL4 0x01BE
Flash control 3 FCTL3 0x012C
Flash control 2 FCTL2 0x012A
Flash control 1 FCTL1 0x0128
USCI A0 auto baud rate control UCA0ABCTL 0x005D
USCI A0 transmit buffer UCA0TXBUF 0x0067
USCI A0 receive buffer UCA0RXBUF 0x0066
USCI A0 status UCA0STAT 0x0065
USCI A0 modulation control UCA0MCTL 0x0064
USCI A0 baud rate control 1 UCA0BR1 0x0063
USCI A0 baud rate control 0 UCA0BR0 0x0062
USCI A0 control 1 UCA0CTL1 0x0061
USCI A0 control 0 UCA0CTL0 0x0060
USCI A0 IrDA receive control UCA0IRRCTL 0x005F
USCI A0 IrDA transmit control UCA0IRTCLT 0x005E
USCI B0 transmit buffer UCB0TXBUF 0x006F
USCI B0 receive buffer UCB0RXBUF 0x006E
USCI B0 status UCB0STAT 0x006D
USCI B0 I2C Interrupt enable UCB0CIE 0x006C
USCI B0 baud rate control 1 UCB0BR1 0x006B
USCI B0 baud rate control 0 UCB0BR0 0x006A
USCI B0 control 1 UCB0CTL1 0x0069
USCI B0 control 0 UCB0CTL0 0x0068
USCI B0 I2C slave address UCB0SA 0x011A
USCI B0 I2C own address UCB0OA 0x0118
USCI A1 auto baud rate control UCA1ABCTL 0x00CD
USCI A1 transmit buffer UCA1TXBUF 0x00D7
USCI A1 receive buffer UCA1RXBUF 0x00D6
USCI A1 status UCA1STAT 0x00D5
USCI A1 modulation control UCA1MCTL 0x00D4
USCI A1 baud rate control 1 UCA1BR1 0x00D3
USCI A1 baud rate control 0 UCA1BR0 0x00D2
USCI A1 control 1 UCA1CTL1 0x00D1
USCI A1 control 0 UCA1CTL0 0x00D0
USCI A1 IrDA receive control UCA1IRRCTL 0x00CF
USCI A1 IrDA transmit control UCA1IRTCLT 0x00CE
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
/
p
_
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
PERIPHERAL FILE MAP (CONTINUED)
USCI A1/B1
(continued)
Comparator_A+
Basic Clock
Brownout, SVS SVS control register (reset by brownout signal) SVSCTL 0x0055
†
Port PA
†
Port P8
†
Port P7
Port P6
Port P5
†
80-pin devices only
USCI B1 transmit buffer UCB1TXBUF 0x00DF
USCI B1 receive buffer UCB1RXBUF 0x00DE
USCI B1 status UCB1STAT 0x00DD
USCI B1 I2C Interrupt enable UCB1CIE 0x00DC
USCI B1 baud rate control 1 UCB1BR1 0x00DB
USCI B1 baud rate control 0 UCB1BR0 0x00DA
USCI B1 control 1 UCB1CTL1 0x00D9
USCI B1 control 0 UCB1CTL0 0x00D8
USCI B1 I2C slave address UCB1SA 0x017E
USCI B1 I2C own address UCB1OA 0x017C
USCI A1/B1 interrupt enable UC1IE 0x0006
USCI A1/B1 interrupt flag UC1IFG 0x0007
Comparator_A port disable CAPD 0x005B
Comparator_A control2 CACTL2 0x005A
Comparator_A control1 CACTL1 0x0059
Basic clock system control3 BCSCTL3 0x0053
Basic clock system control2 BCSCTL2 0x0058
Basic clock system control1 BCSCTL1 0x0057
DCO clock frequency control DCOCTL 0x0056
Port PA resistor enable PAREN 0x0014
Port PA selection PASEL 0x003E
Port PA direction PAD I R 0x003C
Port PA output PAO U T 0x003A
Port PA input PAI N 0x0038
Port P8 resistor enable P8REN 0x0015
Port P8 selection P8SEL 0x003F
Port P8 direction P8DIR 0x003D
Port P8 output P8OUT 0x003B
Port P8 input P8IN 0x0039
Port P7 resistor enable P7REN 0x0014
Port P7 selection P7SEL 0x003E
Port P7 direction P7DIR 0x003C
Port P7 output P7OUT 0x003A
Port P7 input P7IN 0x0038
Port P6 resistor enable P6REN 0x0013
Port P6 selection P6SEL 0x0037
Port P6 direction P6DIR 0x0036
Port P6 output P6OUT 0x0035
Port P6 input P6IN 0x0034
Port P5 resistor enable P5REN 0x0012
Port P5 selection P5SEL 0x0033
Port P5 direction P5DIR 0x0032
Port P5 output P5OUT 0x0031
Port P5 input P5IN 0x0030
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
27
MSP430x241x, MSP430x261x
p
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
PERIPHERAL FILE MAP (CONTINUED)
Port P4
Port P3
Port P2
Port P1
Special Functions
Port P4 selection P4SEL 0x001F
Port P4 resistor enable P4REN 0x0011
Port P4 direction P4DIR 0x001E
Port P4 output P4OUT 0x001D
Port P4 input P4IN 0x001C
Port P3 resistor enable P3REN 0x0010
Port P3 selection P3SEL 0x001B
Port P3 direction P3DIR 0x001A
Port P3 output P3OUT 0x0019
Port P3 input P3IN 0x0018
Port P2 resistor enable P2REN 0x002F
Port P2 selection P2SEL 0x002E
Port P2 interrupt enable P2IE 0x002D
Port P2 interrupt -edge select P2IES 0x002C
Port P2 interrupt flag P2IFG 0x002B
Port P2 direction P2DIR 0x002A
Port P2 output P2OUT 0x0029
Port P2 input P2IN 0x0028
Port P1 resistor enable P1REN 0x0027
Port P1 selection P1SEL 0x0026
Port P1 interrupt enable P1IE 0x0025
Port P1 interrupt -edge select P1IES 0x0024
Port P1 interrupt flag P1IFG 0x0023
Port P1 direction P1DIR 0x0022
Port P1 output P1OUT 0x0021
Port P1 input P1IN 0x0020
SFR interrupt flag2 IFG2 0x0003
SFR interrupt flag1 IFG1 0x0002
SFR interrupt enable2 IE2 0x0001
SFR interrupt enable1 IE1 0x0000
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
absolute maximum ratings (see Note 1)
Voltage applied at VCCto V
SS
Voltage applied to any pin (see Note 2) --0.3 V to V
Diode current at any device terminal . ±2mA......................................................
Storage temperature: Unprogrammed device (see Note 3) --55°C to 150°C..........................
Programmed device (see Note 3) --40°C to 105°C.............................
NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Expos ure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
2. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The v oltage
is applied to the TDI/TCLK pin when blowing the JTAG fuse.
3. Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification, with
peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
recommended operating conditions
PARAMETER MIN MAX UNIT
Supply voltage during program execution, V
Supply voltage during flash memory programming, V
Supply voltage, V
Operatingfree-air temperature, T
Processor frequency f
(see Notes 2 and 3 and Figure 1)
NOTES: 1. It is recommended to power AVCCand DVCCfrom the s ame source. A maximum difference of 0.3 V between AVCCand DVCCcan
2. The MSP430 CPU is clocked directly with MCLK.
3. Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
SS
A
SYSYTEM
be tolerated during power-up.
Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency.
(maximum MCLK frequency)
CC
CC
AVCC=DVCC=VCC(see Note 1) 1.8 3.6 V
AVCC=DVCC=VCC(see Note 1) 2.2 3.6 V
AVSS=DVSS=V
I version -- 4 0 85
T v ersion -- 4 0 105
VCC=1.8V,
Duty cycle = 50% ± 10%
VCC=2.7V,
Duty cycle = 50% ± 10%
VCC≥ 3.3 V,
Duty cycle = 50% ± 10%
SS
--0.3 V to 4.1 V......................................................
+0.3V.......................................
CC
0.0 0.0 V
dc 4.15
dc 12
dc 16
MHz
°C
16 MHz
12 MHz
7.5 MHz
System Frequency -- MHz
4.15 MHz
1.8 V 2.2 V 2.7 V 3.3 V 3.6 V
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCCof 2.2 V.
Supply Voltage -- V
Legend:
Supply voltage range
during flash memory
programming
Supply voltage range
during program execution
Figure 1. Operating Area
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
29
MSP430x241x, MSP430x261x
A
(
AM)
f
3
2,768
H
V
Activemode(AM
)
A
A
_
V
A
(
AM)
f
3
2,768
H
V
Activemode(AM
)
A
A
_
V
f
,
A
(
AM)
f
A
CLK
=32,768Hz/8=4,096Hz
g
V
Activemode(AM
)
Programexecutesinflas
h
ADIVMxDIVSxDIVAx11,
V
A
(
AM)
f
f
V
Activemode(AM
)
Programexecutesinflas
h
A
V
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
active mode supply current into VCCexcluding external current (see Notes 1 and 2)
PARAMETER TEST CONDITIONS T
f
DCO=fMCLK=fSMCLK
=
ACLK
I
AM, 1MHz
I
AM, 1MHz
I
AM, 4kHz
I
AM,100kHz
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
ctive mode
current (1 MHz)
ctive mode
current (1 MHz)
ctive mode
current (4 kHz)
ctive mode
current (100 kHz)
2. The currents are characterized with a micro crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
Program executes from flash,
BCSCTL1 = C
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
f
DCO=fMCLK=fSMCLK
=
ACLK
Program executes in RAM,
BCSCTL1 = C
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
f
MCLK=fSMCLK
=32,768 Hz/8=4,096 Hz
f
=0Hz,
DCO
Pro
ram executes inflash,
SELMx = 11, SELS = 1,
DIVMx = DIVSx = DIVAx = 11,
CPUOFF = 0, SCG0 = 1, SCG1 = 0,
OSCOFF = 0
f
MCLK=fSMCLK=fDCO(0, 0)
=0Hz,
ACLK
Program executes in
RSELx = 0, DCOx = 0,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 1
=1MHz,
z,
LBC1_1MHZ,
=1MHz,
z,
LBC1_1MHZ,
=
,
lash,
,
,
≈ 100 kHz,
-- 4 0 _Cto85_C
105_C
-- 4 0 _Cto85_C
105_C
-- 4 0 _Cto85_C
105_C
-- 4 0 _Cto85_C
105_C
-- 4 0 _Cto85_C
105_C
-- 4 0 _Cto85_C
105_C
-- 4 0 _Cto85_C
105_C
-- 4 0 _Cto85_C
105_C
A
VCC MIN TYP MAX UNIT
2.2
3
2.2
3
2.2
3
2.2
3
365 395
375 420
515 560
525 595
330 370
340 390
460 495
470 520
2.1 9
15 31
3 11
19 32
67 86
80 99
84 107
99 128
μ
μ
μ
μ
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Loading...