The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 1μs.
The MSP430x20xx series is an ultralow-power mixed signal microcontroller with a built-in 16-bit timer, and ten
I/O pins. In addition the MSP430x20x1 has a versatile analog comparator. The MSP430x20x2 and
MSP430x20x3 have built-in communication capability using synchronous protocols (SPI or I2C), and a 10-bit
A/D converter (MSP430x20x2) or a 16-bit sigma-delta A/D converter (MSP430x20x3).
Typicalapplicationsinclude sensor systems that capture analog signals,convert them to digital values, and then
process the data for display or for transmission to a host system. Stand alone RF sensor front end is another
area of application.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
ADC10 conversion clock output
ADC10 analog input A3
Input for negative external reference voltage/negative internal reference
voltage output
SMCLK signal output
ADC10 analog input A4
Input for positive external reference voltage/positive internal reference
voltage output
JTAG test clock, input terminal for device programming and test
Timer_A, compare: Out0 output
ADC10 analog input A5
USI: external clock input in SPI or I2C mode; clock output in SPI mode
JTAG test mode select, input terminal for device programming and test
Timer_A, capture: CCI1B input, compare: Out1 output
ADC10 analog input A6
USI: Data output in SPI mode; I2C clock in I2C mode
JTAG test data input or test clock input during programming and test
ADC10 analog input A7
USI: Data input in SPI mode; I2C data in I2C mode
JTAGtestdataoutputterminalortestdata input during programming and
test
General-purpose digital I/O pin
Timer_A, compare: Out1 output
General-purpose digital I/O pin
Spy-Bi-Wire test data input/output during programming and test
connected to TEST.
Spy-Bi-Wire test clock input during programming and test
DESCRIPTION
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
DESCRIPTION
DESCRIPTION
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Terminal Functions, MSP430x20x2 (Continued)
TERMINAL
NAME
DV
CC
AV
CC
DV
SS
AV
SS
QFN PadNAPackage
TERMINAL
NAME
P1.0/TACLK/ACLK/A0+21I/OGeneral-purpose digital I/O pin
P1.1/TA0/A0--/A4+32I/OGeneral-purpose digital I/O pin
P1.2/TA1/A1+/A4--43I/OGeneral-purpose digital I/O pin
P1.3/VREF/A1--54I/OGeneral-purpose digital I/O pin
P1.4/SMCLK/A2+/TCK65I/OGeneral-purpose digital I/O pin
P1.5/TA0/A2--/SCLK/TMS76I/OGeneral-purpose digital I/O pin
P1.6/TA1/A3+/SDO/SCL/TDI/TCLK87I/OGeneral-purpose digital I/O pin
P1.7/A3--/SDI/SDA/TDO/TDI
†
TDO or TDI is selected via JTAG instruction.
†
PW, or NRSA
NO.NO.
NA16Digital supply voltage
NA15Analog supply voltage
NA14Digital ground reference
NA13Analog ground reference
Pad
I/O
NAQFN package pad connection to VSSrecommended.
Terminal Functions, MSP430x20x3
PW, or NRSA
NO.NO.
98I/OGeneral-purpose digital I/O pin
I/O
Timer_A, clock signal TACLK input
ACLK signal ouput
SD16_A positive analog input A0
Timer_A, capture: CCI0A input, compare: Out0 output
SD16_A negative analog input A0
SD16_A positive analog input A4
Timer_A, capture: CCI1A input, compare: Out1 output
SD16_A positive analog input A1
SD16_A negative analog input A4
Input for an external reference voltage/internal reference voltage output
(can be used as mid-voltage)
SD16_A negative analog input A1
SMCLK signal output
SD16_A positive analog input A2
JTAG test clock, input terminal for device programming and test
Timer_A, compare: Out0 output
SD16_A negative analog input A2
USI: external clock input in SPI or I2C mode; clock output in SPI mode
JTAG test mode select, input terminal for device programming and test
Timer_A, capture: CCI1B input, compare: Out1 output
SD16_A positive analog input A3
USI: Data output in SPI mode; I2C clock in I2C mode
JTAG test data input or test clock input during programming and test
SD16_A negative analog input A3
USI: Data input in SPI mode; I2C data in I2C mode
JTAGtestdataoutputterminalortestdata input during programming and
test
DESCRIPTION
DESCRIPTION
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
MSP430x20x1, MSP430x20x2, MSP430x20x3
DESCRIPTION
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Terminal Functions, MSP430x20x3 (Continued)
TERMINAL
NAME
XIN/P2.6/TA11312I/OInput terminal of crystal oscillator
XOUT/P2.71211I/OOutput terminal of crystal oscillator
RST/NMI/SBWTDIO109IReset or nonmaskable interrupt input
TEST/SBWTCK1110ISelects test mode for JTAG pins on Port1. The device protection fuse is
V
CC
V
SS
DV
CC
AV
CC
DV
SS
AV
SS
QFN PadNAPackage
NOTE: If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection
to this pad after reset.
PW, or NRSA
NO.NO.
1NASupply voltage
14NAGround reference
NA16Digital supply voltage
NA15Analog supply voltage
NA14Digital ground reference
NA13Analog ground reference
Pad
I/O
General-purpose digital I/O pin
Timer_A, compare: Out1 output
General-purpose digital I/O pin
Spy-Bi-Wire test data input/output during programming and test
connected to TEST.
Spy-Bi-Wire test clock input during programming and test
NAQFN package pad connection to VSSrecommended.
DESCRIPTION
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
short-form description
CPU
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
areperformedasregisteroperationsin
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
andconstantgeneratorrespectively.The
remainingregistersaregeneral-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
operating modes
The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, s ervice the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
DActive mode AM;
--All clocks are active
DLow-power mode 0 (LPM0);
--CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
DLow-power mode 1 (LPM1);
--CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
DCO’s dc-generator is disabled if DCO not used in active mode
DLow-power mode 2 (LPM2);
--CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
DLow-power mode 3 (LPM3);
--CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
DLow-power mode 4 (LPM4);
--CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh--0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed) the CPU will
go into LPM4 immediately after power-up.
NOTES: 1. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h--01FFh) or from
within unused address ranges.
2. Multiple source flags
3. Interrupt flags are located in the module
4. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
5. The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
TAIFG (see Notes 2 and 3)
SD16CCTL0 SD16OVIFG,
PORIFG
RSTIFG
WDTIFG
KEYV
(see Note 2)
NMIIFG
OFIFG
ACCVIFG
(see Notes 2 and 4)
TACCR1 CCIFG.
ADC10IFG (see Note 3)
SD16CCTL0 SD16IFG
(see Notes 2 and 3)
USIIFG, USISTTIFG
(see Notes 2 and 3)
P2IFG.6toP2IFG.7
(see Notes 2 and 3)
P1IFG.0toP1IFG.7
(see Notes 2 and 3)
Reset0FFFEh31, highest
(non)-maskable,
(non)-maskable,
(non)-maskable
maskable0FFF0h24
maskable
maskable
maskable0FFE8h20
maskable0FFE6h19
maskable0FFE4h18
0FFFCh30
0FFFAh29
0FFF8h28
0FFEEh23
0FFECh22
0FFEAh21
0FFE2h17
0FFE0h16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
interrupt enable 1 and 2
Address
0h
76540
NMIIEACCVIE
rw-0rw-0rw-0
32 1
OFIEWDTIE
rw-0
WDTIE:WatchdogTimer interrupt enable. Inactive if watchdog mode is selected. Active if WatchdogTimer
is configured in interval timer mode.
OFIE:Oscillator fault enable
NMIIE:(Non)maskable interrupt enable
ACCVIE:Flash access violation interrupt enable
Address
01h
7654032 1
interrupt flag register 1 and 2
Address
02hNMIIFG
76540
rw-0rw-1rw-(0)
32 1
RSTIFG
rw-(0)
PORIFG
rw-(1)
OFIFGWDTIFG
WDTIFG:Set on Watchdog Timer overflow (in watchdog mode) or security key violation.
Reset on V
power-up or a reset condition at RST/NMI pin in reset mode.
CC
OFIFG:Flag set on oscillator fault
RSTIFG:External reset interrupt flag. Set on a reset condition at RST
/NMI pin in reset mode. Reset on V
power-up
PORIFG:Power-On Reset interrupt flag. Set on V
NMIIFG:Set via RST
/NMI-pin
power-up.
CC
CC
14
Address
03h
Legendrw:
rw-0,1:
rw-(0,1):
7654032 1
Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
memory organization
MSP430F200xMSP430F201x
Memory
Main: interrupt vector
Main: code memory
Information memorySize
RAMSize128 Byte
Peripherals16-bit
flash memory
The flash memory can be programmed via the Spy-Bi-Wire/JTAG port, or in-system by the CPU. The CPU can
perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
DFlash memory has n segments of main memory and four segments of information memory (A to D) of 64
bytes each. Each segment in main memory is 512 bytes in size.
Size
Flash
Flash
Flash
8-bit
8-bit SFR
1KB Flash
0FFFFh--0FFC0h
0FFFFh--0FC00h
256 Byte
010FFh -- 01000h
027Fh -- 0200h
01FFh -- 0100h
0FFh -- 010h
0Fh -- 00h
2KB Flash
0FFFFh--0FFC0h
0FFFFh--0F800h
256 Byte
010FFh -- 01000h
128 Byte
027Fh -- 0200h
01FFh -- 0100h
0FFh -- 010h
0Fh -- 00h
DSegments 0 to n may be erased in one step, or each segment may be individually erased.
DSegments A to D can be erased individually, or as a group with segments 0 --n.
Segments A to D are also called information memory.
DSegment A contains calibration data. After reset segment A is protected against programming and erasing.
It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data
is required.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
15
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, refer to the MSP430x2xx Family User’s Guide.
oscillator and system clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very-low-power low-frequency oscillator and an internal digitally-controlled oscillator
(DCO). The basic clock module is designed to meet the requirements of both low system cost and low power
consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 μs. The basic
clock module provides the following clock signals:
DAuxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.
DMain clock (MCLK), the system clock used by the CPU.
DSub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
DCO Calibration Data (provided from factory in flash info memory segment A)
DCO FrequencyCalibration RegisterSizeAddress
1MHz
8MHz
12 MHz
16 MHz
CALBC1_1MHZbyte
CALDCO_1MHZbyte
CALBC1_8MHZbyte
CALDCO_8MHZbyte
CALBC1_12MHZbyte
CALDCO_12MHZbyte
CALBC1_16MHZbyte
CALDCO_16MHZbyte
010FFh
010FEh
010FDh
010FCh
010FBh
010FAh
010F9h
010F8h
brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off.
digital I/O
There is one 8-bit I/O port implemented—port P1—and two bits of I/O port P2:
DAll individual I/O bits are independently programmable.
DAny combination of input, output, and interrupt condition is possible.
DEdge-selectable interrupt input capability for all the eight bits of port P1 and the two bits of port P2.
DRead/write access to port-control registers is supported by all instructions.
DEach I/O has an individually programmable pull-up/pull-down resistor.
WDT+ watchdog timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be disabled or configured as an interval timer and can
generate interrupts at selected time intervals.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
A
A
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
timer_A2
Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities.
Interrupts may be generated from the c ounter on overflow conditions and from each of the capture/compare
registers.
Timer_A2 Signal Connections (MSP43020x1 only)
Input
Pin Number
PW, NRSAPW, NRSA
2-P1.01-P1.0TACLKTAC L K
2-P1.01-P1.0TACLKINCLK
3-P1.12-P1.1TA0CCI0A
4-P1.23-P1.2TA1CCI1A
Device
Input Signal
ACLKACLK
SMCLKSMCLK
ACLK (internal)CCI0B
V
SS
V
CC
CAOUT (internal)CCI1B
V
SS
V
CC
Module
Input Name
GND
V
CC
GND
V
CC
Module
Block
TimerN
CCR0TA0
CCR1TA1
Module
Output Signal
Output
Pin Number
3-P1.12-P1.1
7-P1.56-P1.5
4-P1.23-P1.2
8-P1.67-P1.6
13 - P2.612 - P2.6
Timer_A2 Signal Connections (MSP430F20x2, MSP430F20x3)
Input
Pin Number
PW, NRSAPW, NRSA
2-P1.01-P1.0TACLKTAC L K
2-P1.01-P1.0TACLKINCLK
3-P1.12-P1.1TA0CCI0A
7-P1.56-P1.5ACLK (internal)CCI0B
4-P1.23-P1.2TA1CCI1A
8-P1.67-P1.6TA1CCI1B
Device
Input Signal
ACLKACLK
SMCLKSMCLK
V
SS
V
CC
V
SS
V
CC
Module
Input Name
GND
V
CC
GND
V
CC
Module
Block
TimerN
CCR0TA0
CCR1TA1
Module
Output Signal
Output
Pin Number
3-P1.12-P1.1
7-P1.56-P1.5
4-P1.23-P1.2
8-P1.67-P1.6
13 - P2.612 - P2.6
comparator_A+ (MSP430x20x1 only)
The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
17
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
USI (MSP430x20x2 and MSP430x20x3 only)
The universal serial interface (USI) module is used for serial data communication and provides the basic
hardware for synchronous communication protocols like SPI and I2C.
ADC10 (MSP430x20x2 only)
The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion
result handling, allowing ADC samples to be converted and stored without any CPU intervention.
SD16_A (MSP430x20x3 only)
The SD16_A module supports 16-bit analog-to-digital conversions. The module implements a 16-bit
sigma-delta core and reference generator. In addition to external analog inputs, internal V
temperature sensors are also available.
CC
sense and
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map
ADC10 (MSP430x20x2 only)ADC control 0
SD16_A (MSP430x20x3 only) General Control
Timer_ACapture/compare register
Flash MemoryFlash control 3
Watchdog Timer+Watchdog/timer controlWDTCTL0120h
ADC10 (MSP430x20x2 only)Analog enableADC10AE04Ah
SD16_A (MSP430x20x3 only) Channel 0 Input Control
USI
(MSP430x20x2 and
MSP430x20x3 only)
Comparator_A+
(MSP430x20x1 only)
Basic Clock System+Basic clock system control 3
Port P2Port P2 resistor enable
Port P1Port P1 resistor enable
Special FunctionSFR interrupt flag 2
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
PERIPHERALS WITH WORD ACCESS
ADC control 1
ADC memory
Channel 0 Control
Interrupt vector word register
Channel 0 conversion memory
Capture/compare register
Timer_A register
Capture/compare control
Capture/compare control
Timer_A control
Timer_A interrupt vector
Flash control 2
Flash control 1
PERIPHERALS WITH BYTE ACCESS
Analog Enable
USI control 0
USI control 1
USI clock control
USI bit counter
USI shift register
Comparator_A+ port disable
Comparator_A+ control 2
Comparator_A+ control 1
Basic clock system control 2
Basic clock system control 1
DCO clock frequency control
Port P2 selection
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt flag
Port P2 direction
Port P2 output
Port P2 input
Port P1 selection
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt flag
Port P1 direction
Port P1 output
Port P1 input
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
absolute maximum ratings
Voltage applied at VCCto V
Voltage applied to any pin (see Note 2)--0.3 V to V
†
SS
--0.3 V to 4.1 V......................................................
+0.3 V........................................
CC
Diode current at any device terminal±2mA.......................................................
Storage temperature, T
Storage temperature, T
NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
2. All voltages referenced to V
is applied to the TEST pin when blowing the JTAG fuse.
3. Higher temperature may be applied during board soldering process according to the current JEDEC J--STD--020 specification with
peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
(unprogrammed device, see Note 3)--55°C to 150°C........................
stg
(programmed device, see Note 3)--40°Cto85°C...........................
stg
. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage
SS
recommended operating conditions
MINNOMMAX UNITS
Supply voltage during program execution, V
Supply voltage during program/erase flash memory, V
Supply voltage, V
Operatingfree-air temperature range, T
Processor frequency f
NOTES: 1. The MSP430 CPU is clocked directly with MCLK.
SS
(Maximum MCLK frequency)
SYSTEM
Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency.
2. Modules might have a different maximum input clock specification. Refer to the specification of the respective module in this data
sheet.
CC
CC
A
I Version-- 4 085°C
T Version-- 4 0105°C
VCC=1.8V,
Duty Cycle = 50% ±10%
VCC=2.7V,
Duty Cycle = 50% ±10%
VCC≥ 3.3 V,
Duty Cycle = 50% ±10%
1.83.6V
2.23.6V
0V
dc6
dc12
dc16
MHz
16 MHz
12 MHz
6MHz
System Frequency -- MHz
1.8 V2.2 V2.7 V3.3 V 3.6 V
Supply Voltage --V
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum V
Legend:
Supply voltage range,
during flash memory
programming
Supply voltage range,
during program execution
Figure 1. Save Operating Area
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CC
of 2.2 V.
MSP430x20x1, MSP430x20x2, MSP430x20x3
A
(
AM)
Activemode(AM
)
A
A
A
(
AM)
Activemode(AM
)
A
A
f
,
A
(
AM)
f
A
CLK
=32,768Hz/8=4,096Hz
g
Activemode(AM
)
Programexecutesinflas
h
ADIVMxDIVSxDIVAx11,
A
(
AM)
f
f
Activemode(AM
)
Programexecutesinflas
h
A
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
active mode supply current (into VCC) excluding external current (see Notes 1 and 2)
I
AM, 1MHz
I
AM, 1MHz
I
AM, 4kHz
I
AM,100kHz
PARAMETERTEST CONDITIONST
ctive mode
current (1MHz)
f
DCO=fMCLK=fSMCLK
f
= 32,768Hz,
ACLK
Program executes in flash,
BCSCTL1 = C
DCOCTL = CALDCO_1MHZ,
=1MHz,
LBC1_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
ctive mode
current (1MHz)
f
DCO=fMCLK=fSMCLK
f
= 32,768Hz,
ACLK
Program executes in RAM,
BCSCTL1 = C
DCOCTL = CALDCO_1MHZ,
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
2. The currents are characterized with a Micro Crystal CC4V--T1A SMD crystal with a load capacitance of 9 pF.
The internal and external load capacitance is chosen to closely match the required 9pF.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
21
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- active mode supply current (into VCC)
5.0
f
=16MHz
=12MHz
DCO
f
DCO
=1MHz
4.0
3.0
f
DCO
2.0
Active Mode Current -- mA
1.0
0.0
1.52.02.53.03.54.0
f
=8MHz
DCO
VCC-- Supply Voltage -- V
Figure 2. Active mode current vs VCC,TA=25°C
4.0
3.0
2.0
Active Mode Current -- mA
1.0
0.0
0.04.08.012.016.0
VCC=3V
TA=85°C
TA=25°C
VCC=2.2V
f
-- DCO Frequency -- MHz
DCO
TA=85°C
TA=25°C
Figure 3. Active mode current vs DCO frequency
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
A
A
f
A
CLK
f
ACL
K
=0H
z
A
f
1MH
V
A
A
_
V
V
A
L
(
f
f
f
0MH
f
3(LPM3)curren
t
f
ACL
K
=32,768Hz
V
A
V
A
L
(
)
f
f
f
0MH
f
f
(
VLO)
3curren
t,(LPM3
)
f
ACL
K
frominternalLFoscillator(VLO)
V
A
f
f
f
0MH
f
f
ACL
K
=0H
z
V
/
AseeNote5
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
low power mode supply currents (into VCC) excluding external current (see Notes 1 and 2)
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
2. The currents are characterized with a Micro Crystal CC4V--T1A SMD crystal with a load capacitance of 9 pF.
The internal and external load capacitance is chosen to closely match the required 9pF.
3. Current for brownout and WDT clocked by SMCLK included.
4. Current for brownout and WDT clocked by ACLK included.
5. Current for brownout included.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
23
MSP430x20x1, MSP430x20x2, MSP430x20x3
V
IT+
l
t
V
V
I
T
l
t
V
Inputvoltagehysteresis(
V
I
T
V
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Schmitt-trigger inputs -- Ports P1 and P2
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
V
IT+
Positive-going input threshold
vo
age
2.2 V1.001.65
3V1.352.25
0.250.55V
0.450.75V
V
IT--
--
Negative-going input threshold
vo
age
2.2 V0.551.20
3V0.751.65
V
hys
R
Pull
C
I
Input voltagehysteresis(V
V
)
IT--
Pull-up/pull-down resistor
Input CapacitanceVIN=VSSor V
--
+
For pullup: VIN=VSS;
For pulldown: V
IN=VCC
CC
2.2 V0.21.0
3V0.31.0
203550kΩ
inputs -- Ports P1 and P2
PARAMETERTEST CONDITIONSVCCMINTYPMAX UNIT
Port P1, P2: P1.x to P2.x, External
t
(int)
External interrupt timing
trigger pulse width to set interrupt
2.2 V/3 V20ns
flag, (see Note 1)
NOTES: 1. An external signal sets the interrupt flag every time the minimum interrupt puls width t
shorter than t
(int)
.
is met. It may be set even with trigger signals
(int)
leakage current -- Ports P1 and P2
PARAMETERTEST CONDITIONSVCCMINTYPMAX UNIT
I
lkg(Px.x)
NOTES: 1. The leakage current is measured with VSSor VCCapplied to the corresponding pin(s), unless otherwise noted.
High-impedance leakage currentsee Notes 1 and 22.2 V/3 V±50nA
2. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pull-up/pull-down resistor is
disabled.
5pF
CC
CC
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
Highleveloutput
V
Lowleveloutpu
t
V
y
f
Portoutputfrequency
P
1.4/SMCLK,CL=20pF,RL=1kOh
m
/
A
f
P
2.0/ACL
K,P
1.4/SMCLK,CL=20pF
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
outputs -- Ports P1 and P2
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
I
V
OH
High-level output
voltage
I
I
I
I
V
OL
Low-level output
voltage
I
I
I
NOTES: 1. The maximum total current, I
OHmax
voltage drop specified.
2. The maximum total current, I
OHmax
voltage drop specified.
output frequency -- Ports P1 and P2
PARAMETERTEST CONDITIONSVCCMINTYPMAX UNIT
Px.y
Port_CLK
Port outputfrequenc
(with load)
Clock outputfrequency
NOTES: 1. A resistive divider with 2 times 0.5 kΩ between VCCand VSSis used as load. The output is connected to the center tap of the divider.
2. The output voltage reaches at least 10% and 90% V
P1.4/SMCLK, C
(see Note 1 and 2)
P2.0
(see Note 2)
= --1.5 mA (see Notes 1)2.2 VVCC--0.25V
(OHmax)
=--6mA(seeNotes2)2.2 VVCC-- 0 . 6V
(OHmax)
= --1.5 mA (see Notes 1)3VVCC--0.25V
(OHmax)
=--6mA(seeNotes2)3VVCC-- 0 . 6V
(OHmax)
= 1.5 mA (see Notes 1)2.2 VV
(OLmax)
=6mA(seeNotes2)2.2 VV
(OLmax)
= 1.5 mA (see Notes 1)3VV
(OLmax)
=6mA(seeNotes2)3VV
(OLmax)
and I
and I
, for all outputs combined, should not exceed ±12 mA to hold the maximum
OLmax
, for all outputs combined, should not exceed ±48 mA to hold the maximum
OLmax
=20pF, R
=1kOhm
2.2 V10MHz
SS
SS
SS
SS
3V12MHz
CLK, P1.4/SMCLK, C
=20pF
2.2 V12MHz
3V16MHz
at the specified toggle frequency.
CC
CC
CC
CC
CC
VSS+0.25
VSS+0.6
VSS+0.25
VSS+0.6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
25
MSP430x20x1, MSP430x20x2, MSP430x20x3
A
A
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- outputs
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
30.0
VCC=2.2V
P1.7
5.0
0.0
0.00.51.01.52.02.5
VOL-- Low-Level Output Voltage -- V
I-- Typical Low-Level Output Current -- m
25.0
20.0
15.0
10.0
OL
Figure 4
TA=25°C
TA=85°C
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50.0
VCC=3V
P1.7
40.0
30.0
20.0
10.0
OL
I-- Typical Low-Level Output Current -- mA
0.0
0.00.51.01.52.02.53.03.5
VOL-- Low-Level Output Voltage -- V
Figure 5
TA=25°C
TA=85°C
TYPICAL HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
0.0
VCC=2.2V
P1.7
-- 5 . 0
--10.0
--15.0
TA=85°C
--20.0
OH
I-- Typical High-Level Output Current -- m
--25.0
TA=25°C
0.00.51.01.52.02.5
VOH-- High-Level Output Voltage -- V
Figure 6
NOTE: One output loaded at a time.
vs
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0.0
VCC=3V
P1.7
--10.0
--20.0
--30.0
TA=85°C
--40.0
OH
I-- Typical High-Level Output Current -- mA
--50.0
TA=25°C
0.00.51.01.52.02.53.03.5
VOH-- High-Level Output Voltage -- V
Figure 7
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
POR/brownout reset (BOR) (see Notes 1 and 2)
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
V
CC(start)
V
(B_IT--)
V
hys(B_IT--)
t
d(BOR)
t
(reset)
NOTES: 1. The current consumption of the brownout module i s already included in the ICCcurrent consumption data. The voltage level V
(see Figure 8)dVCC/dt ≤ 3V/s0.7 × V
(B_IT--)
(see Figure 8 through Figure 10)dVCC/dt ≤ 3V/s1.71V
(see Figure 8)dVCC/dt ≤ 3V/s70130210mV
(see Figure 8)2000μs
Pulse length needed at RST/NMI pin
to accepted reset internally
+V
hys(B_IT--)
is ≤ 1.8V.
2. During power up, the CPU begins code execution following a period of t
DCO settings must not be changed until V
CC
≥ V
CC(min)
, where V
CC(min)
d(BOR)
is the minimum supply voltage for the desired
2.2 V/3 V2μs
after VCC=V
(B_IT--)+Vhys(B_IT--)
operating frequency.
V
CC
V
hys(B_IT--)
V
(B_IT--)
. The default
V
CC(start)
V
(B_IT--)
1
0
t
d(BOR)
Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
27
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Osc. fault frequency threshold,
LF mode (see Note 3)
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Measured with logic level input frequency but also applies to operation with crystals.
3. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag.
Frequencies in between might set the flag.
4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
XTS = 0, LFXT1Sx = 0 or 11.8 V -- 3.6 V32,768Hz
XTS = 0, LFXT1Sx = 31.8 V -- 3.6 V10,00032,76850,000Hz
XTS = 0, LFXT1Sx = 0;
f
LFXT1,LF
C
XTS = 0, LFXT1Sx = 0;
f
LFXT1,LF
C
XTS = 0, XCAPx = 01pF
XTS = 0, XCAPx = 15.5pF
XTS = 0, XCAPx = 28.5pF
XTS = 0, XCAPx = 311pF
XTS = 0, Measured at
P1.4/ACLK,
f
LFXT1,LF
XTS = 0, LFXT1Sx = 3
(see Note 2)
L,eff
L,eff
=6pF
=12pF
= 32,768 kHz,
= 32,768 kHz,
= 32,768 Hz
500kΩ
200kΩ
2.2 V/3 V305070%
2.2 V/3 V1010,000Hz
-- Keep as short of a trace as possible between the device and the crystal.
-- Design a good ground plane around the oscillator pins.
-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
-- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
-- Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
-- If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
-- Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
internal very low power, low frequency oscillator (VLO)
PARAMETERTEST CONDITIONST
VLO
df
/dT
VLO
df
/dV
VLO
NOTES: 1. Calculated using the box method:
34
VLOfrequency
VLO frequency
temperature drift
VLO frequency supply
CC
voltage drift
I Version: (MAX(--40...85_C) -- MIN(--40...85_C))/MIN(--40...85_C)/(85_C--(--40_C))
T Version: (MAX(--40...105_C) -- MIN(--40...105_C))/MIN(--40...105_C)/(105_C--(--40_C))
2. Calculated using the box method: (MAX(1.8...3.6V) -- MIN(1.8...3.6V))/MIN(1.8...3.6V)/(3.6V -- 1.8V)
(see Note 1)
(see Note 2)25°C1.8V -- 3.6V4%/V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
A
-40--85°C2.2 V/3 V41220
105°C2.2 V/3 V22
I: -40--85°C
T: -40--105°C
VCCMINTYPMAX UNIT
kHz
2.2 V/3 V0.5%/°C
MSP430x20x1, MSP430x20x2, MSP430x20x3
f
_
A
x
f
A
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Timer_A
PARAMETERTEST CONDITIONSVCCMINTYPMAX UNIT
Internal: SMCLK, ACLK;
E
ternal: TACLK, INCLK;
Duty Cycle = 50% ±10%
TA
t
TA, cap
Timer
Timer_A, capture timingTA 0, TA12.2 V/3 V20ns
clockfrequency
USI, Universal Serial Interface (MSP430x20x2, MSP430x20x3 only)
typical characteristics -- USI low-level output voltage on SDA and SCL (MSP430x20x2, MSP430x20x3 only)
2.2 V10
3V16
2.2 V10
3V16
2.2 V/3 VV
SS
VSS+0.4V
MHz
MHz
5.0
VCC=2.2V
4.0
3.0
2.0
1.0
OL
I-- Low-Level Output Current -- m
0.0
0.00.20.40.60.81.0
VOL-- Low-Level Output Voltage -- V
TA=25°C
TA=85°C
Figure 14. USI Low-Level Output Voltage vs.
Output Current
5.0
VCC=3V
4.0
3.0
2.0
1.0
OL
I-- Low-Level Output Current -- mA
0.0
0.00.20.40.60.81.0
VOL-- Low-Level Output Voltage -- V
TA=25°C
TA=85°C
Figure 15. USI Low-Level Output Voltage vs.
Output Current
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
35
MSP430x20x1, MSP430x20x2, MSP430x20x3
A
A
/CA
A
V
f
Withoutfilter:CAF=0
Responsetim
e
f
Withfilter:CAF=
1
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
MSP430x20x1 electrical characteristics over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted)
Comparator_A+ (see Note 1, MSP430x20x1 only)
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
I
(DD)
CAON=1, CARSEL=0, CAREF=0
CAON=1, CARSEL=0,
I
(Refladder/RefDiode)
CAREF=1/2/3,
no load at P1.0/CA0 and P1.1/CA1
V
(IC)
V
(Ref025)
V
(Ref050)
Common-mode input
voltage
Voltage @ 0.25 VCCnode
V
CC
Voltage @ 0.5VCCnode
V
CC
CAON=12.2 V/3 V0VCC-- 1V
PCA0=1, CARSEL=1, CAREF=1,
no load at P1.0/CA0 and P1.1/CA1
PCA0=1, CARSEL=1, CAREF=2,
no load at P1.0/CA0 and P1.1/CA1
PCA0=1, CARSEL=1, CAREF=3,
V
(RefVT)
V
(offset)
V
hys
(see Figure 19 and Figure 20)
no load at P1.0
T
=85°C
0 and P1.1/CA1,
Offset voltageSeeNote22.2 V/3 V-- 3 030mV
Input hysteresisCAON=12.2 V/3 V00.71.4mV
TA=25°C, Overdrive 10 mV,
Without
ilter: CAF=0
(see Note 3, Figure 16 and
t
(response)
Response time
(low--high and high--low)
Figure 17)
=25°C, Overdrive 10 mV,
T
A
With
ilter: CAF=1
(see Note 3, Figure 16 and
Figure 17)
NOTES: 1. The leakage current for the Comparator_A+ terminals is identical to I
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements.
The two successive measurements are then summed together.
3. Response time measured at P1.3/CAOUT.
lkg(Px.x)
2.2 V2540
3V4560
2.2 V3050
3V4571
2.2 V/3 V0.230.240.25
2.2 V/3 V0.470.480.5
2.2 V390480540
3V400490550
2.2 V80165300
3V70120240
2.2 V1.41.92.8
3V0.91.52.2
specification.
μ
μ
m
ns
μs
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
MSP430x20x1 electrical characteristics over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted) (continued)
V
0V
CC
0
1
CAON
CAF
Low Pass Filter
V+
V--
+
_
0
1
τ≈2.0 μs
Figure 16. Block Diagram of Comparator_A+ Module
V
CAOUT
V--
400 mV
V+
Overdrive
t
(response)
Figure 17. Overdrive Definition
To I n t e rnal
Modules
0
1
CAOUT
Set CAIFG
Flag
CASHORT
CA1CA0
1
+
V
IN
--
Comparator_A+
CASHORT = 1
Figure 18. Comparator_A+ Short Resistance Test Condition
I
OUT
=10μA
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
37
MSP430x20x1, MSP430x20x2, MSP430x20x3
(
)
(
)
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
MSP430x20x1 electrical characteristics over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted) (continued)
MSP430x20x2 electrical characteristics over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted) (continued)
10-bit ADC, power supply and input range conditions (see Note 1, MSP430x20x2 only)
V
CC
V
Ax
I
ADC10
PARAMETERTEST CONDITIONST
Analog supply voltage
range
Analog input voltage range
(see Note 2)
DC10 su
current
(see Note 3)
VSS=0V2.23.6V
All Ax terminals.
Analog inputs selected in
ADC10AE register.
f
ADC10CLK
=5.0MHz
ADC10ON = 1, REFON = 0
DC10SHT0 = 1,
ADC10SHT1 = 0, ADC10DIV
A
I: -40--85°C
T: -40--105°C
=0
I
REF+
I
REFB,0
I
REFB,1
Reference supply current,
reference bu
er disabled
(see Note 4)
Reference buffer supply
current withADC10SR=0
(see Note 4)
Reference buffer supply
current withADC10SR=1
(see Note 4)
NOTES: 1. The leakage current is defined in the leakage current table with Px.x/Ax parameter.
2. The analog input voltage range must be within the selected reference voltage range V
3. The internal reference supply current is not included in current consumption parameter I
4. The internal reference current is supplied via terminal V
. Consumption is independent of the ADC10ON control bit, unless a
CC
conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
VCCMINTYPMAXUNIT
0V
CC
2.2 V0.521.05
m
3V0.61.2
2.2 V/3 V
mA
0.250.4
3V
mA
27pF
2.2 V/3 V2000Ω
to V
R+
for valid conversion results.
R--
.
ADC10
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
39
MSP430x20x1, MSP430x20x2, MSP430x20x3
V
C
C,REF
+
l
t
V
A
x
V
V
f
f
REF2_5V=0
Settlingtimeofreferencebuffer
V
REF2_5V=1
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
MSP430x20x2 electrical characteristics over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted) (continued)
10-bit ADC, built-in voltage reference (MSP430x20x2 only)
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
I
≤ 1mA, REF2_5V=02.2
V
CC,REF+
V
REF+
I
LD,VREF+
C
VREF+
TC
REF+
t
REFON
t
REFBURST
Positive built-in reference analog
supplyvo
age range
Positive built-in reference voltage
Maximum V
V
load regulation
REF+
V
load regulation response time
REF+
Max. capacitance at pin V
REF+
load current
REF+
(see Note 1)
Temperature coefficient
Settling time of internal reference
voltage (see Note 2)
Settlingtime ofreference bu
er
(see Note 2)
NOTES: 1. The capacitance applied to the internal buffer operational amplifier, if switched to terminal P2.4/TA2/A4/V
must be limited; the reference buffer may become unstable otherwise.
2. The condition is that the error in a conversion started after t
VREF+
I
≤ 0.5mA, REF2_5V=12.8
VREF+
I
≤ 1mA, REF2_5V=12.9
VREF+
I
VREF+
I
VREF+
≤ I
≤ I
max, REF2_5V = 02.2 V/3 V1.411.51.59V
VREF+
max, REF2_5V = 13V2.352.52.65V
VREF+
2.2 V±0.5
I
= 500 μA +/-- 100 μA
VREF+
Analog input voltage V
≈ 0.75 V;
Ax
2.2 V/3 V±2LSB
REF2_5V = 0
I
= 500 μA ± 100 μA
VREF+
Analog input voltage V
≈ 1.25 V;
Ax
REF2_5V = 1
I
=
VREF+
100μA→900μA,
≈ 0.5
V
Ax
REF+
Error of conversion
result ≤ 1LSB
I
≤±1mA,
VREF+
REFON = 1, REFOUT = 1
I
= const. with
VREF+
0mA≤ I
I
VREF+
≤ 1mA
VREF+
= 0.5 mA, REF2_5V=0
REFON = 0 → 1
I
=0.5mA,
VREF+
REF2 5
=0,
,
REFON = 1,
REFBURST = 1
=0.5mA,
I
VREF+
REF2 5
=1,
,
REFON = 1,
REFBURST = 1
ADC10SR = 03V400
ADC10SR = 13V2000
2.2 V/3 V100pF
2.2 V/3 V±100 ppm/°C
3.6 V30
ADC10SR = 02.2 V1
ADC10SR = 12.2 V2.5
ADC10SR = 03V2
ADC10SR = 13V4.5
REFON
or t
is less than ±0.5 LSB.
RefBuf
V
3V±1
m
3V±2LSB
ns
μs
μs
REF+/VeREF+
(REFOUT=1),
40
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
Positiveexternalreferenceinpu
t
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
MSP430x20x2 electrical characteristics over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted) (continued)
10-bit ADC, external reference (see Note 1, MSP430x20x2 only)
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
V
eREF+>VeREF--
V
eREF+
Positive external reference input
voltage range (see Note 2)
SREF1 = 1, SREF0 = 0
V
eREF--
≤ V
eREF+
≤ VCC-- 0.15V
SREF1=1,SREF0=1(seeNote3)
V
eREF--
Negative external reference input
voltage range (see Note 4)
V
eREF+>VeREF--
Differential external reference input
∆V
eREF
I
VeREF+
I
VeREF --
voltage range
∆V
eREF=VeREF+
-- V
eREF--
Static input current into V
Static input current into V
eREF+
eREF--
V
eREF+>VeREF--
0V ≤ V
eREF+
(see Note 5)1.4V
≤ VCC,
SREF1 = 1, SREF0 = 0
0V ≤V
≤ VCC-- 0.15V ≤ 3V
eREF+
SREF1=1,SREF0=1(seeNote3)
0V ≤ V
eREF--
≤ V
CC
2.2 V/3 V±1μA
2.2 V/3 V0μA
2.2 V/3 V±1μA
NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI,isalso
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
3. Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer
supply current I
. The current consumption can be limited to the sample and conversion period with REBURST = 1.
REFB
4. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
5. The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied
with reduced accuracy requirements.
1.4V
CC
1.43.0V
01.2V
CC
V
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
41
MSP430x20x1, MSP430x20x2, MSP430x20x3
perf
f
f
A
performanceof
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
MSP430x20x2 electrical characteristics over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted) (continued)
10-bit ADC, timing parameters (MSP430x20x2 only)
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
For specified
ADC10CLK
DC10 input clockfrequency
ormance o
ADC10 linearity
parameters
f
ADC10OSC
ADC10 built-in oscillator frequency
ADC10DIVx=0, ADC10SSELx = 0
f
ADC10CLK=fADC10OSC
ADC10 built-in oscillator,
ADC10SSELx = 0
f
t
CONVERT
Conversion time
ADC10CLK=fADC10OSC
f
ADC10CLK
from ACLK, MCLK or
SMCLK: ADC10SSELx ≠ 0
t
ADC10ON
Turn on settling time of the ADC(see Note 1)100ns
NOTES: 1. The condition is that the error in a conversion started after t
settled.
ADC10SR = 02.2 V/3 V0.456.3
ADC10SR = 12.2 V/3 V0.451.5
2.2 V/3 V3.76.3MHz
2.2 V/3 V2.063.51μs
ADC10DIV×
1/f
ADC10ON
is less than ±0.5 LSB. The reference and input signal are already
MSP430x20x2 electrical characteristics over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted) (continued)
10-bit ADC, temperature sensor and built-in V
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
I
SENSOR
TC
SENSOR
V
Offset,Sensor
V
Sensor
Temperature sensor su
current (see Note 1)
Sensor offset voltage
Sensor output voltage
(see Note 3)
Sample time required if
t
Sensor(sample)
I
VMID
V
MID
channel 10 is selected (see
Note 4)
Current into divider at channel
11 (see Note 5)
VCCdivider at channel 11
Sample time required if
t
VMID(sample)
channel 11 is selected (see
Note 6)
NOTES: 1. The sensor current I
is high). When REFON = 1, I
sensor input (INCH = 0Ah).
2. The following formula can be used to calculate the temperature sensor output voltage:
V
Sensor,typ
V
Sensor,typ
=TC
=TC
Sensor
Sensor
3. Values are not based on calculations using TC
4. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time t
5. No additional current is needed. The V
6. The on-time t
VMID(on)
is consumed if (ADC10ON = 1 and REFON = 1), or (ADC10ON=1 and INCH=0Ah and sample signal
SENSOR
SENSOR
( 273 + T [°C] ) + V
T[°C] + V
is included in the sampling time t
REFON = 0, INCHx=0Ah,
T
=25_C
A
ADC10ON = 1, INCHx = 0Ah
(see Note 2)
ADC10ON = 1, INCHx = 0Ah
(see Note 2)
Temperature sensor voltage
at T
= 105°C (T Version only)
A
Temperature sensor voltage
at T
=85°C
A
Temperature sensor voltage
at T
=25°C
A
Temperature sensor voltage
at T
=0°C
A
ADC10ON = 1, INCHx = 0Ah,
Error of conversion result ≤ 1LSB
DC10ON = 1, INCHx=0Bh,
DC10ON = 1, INCHx=0Bh,
V
is ≈0.5 x V
MID
DC10ON = 1, INCHx=0Bh,
Error of conversion result ≤ 1LSB
is included in I
Offset,sensor
Sensor(TA
=0°C) [mV]
is used during sampling.
MID
(MSP430x20x2 only)
MID
,
CC
. When REFON = 0, I
REF+
[mV] or
or V
Sensor
Offset,sensor
VMID(sample)
; no additional on time is needed.
2.2 V40120
3V60160
2.2 V/3 V3.443.553.66 mV/°C
2.2 V/3 V126513651465mV
2.2 V/3 V119512951395
2.2 V/3 V98510851185
2.2 V/3 V8959951095
2.2 V/3 V30μs
2.2 VNA
3VNA
,
2.2 V1.061.11.14
3V1.461.51.54
,
2.2 V1400
3V1220
applies during conversion of the temperature
SENSOR
but on measurements.
μ
--100100mV
mV
μ
ns
SENSOR(on)
.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
43
MSP430x20x1, MSP430x20x2, MSP430x20x3
f
V
A
A
p
ply
SD16OSR=256
Analogsupplycurrent
f
V
ASD16OS
R=256GA
f
f
Differentialfullscaleinputvoltage
f
V(seeNote1)
Inputimpedanc
e
f
f
f
DifferentialInputimpedanc
e
f
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
MSP430x20x3 electrical characteristics over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted)
SD16_A, power supply and recommended operating conditions (MSP430x20x3 only)
AV
I
SD16
f
SD16
f
SD16
PARAMETERTEST CONDITIONST
Analog supply voltage range
CC
nalogsu
including internal reference
SD16 input clock frequency
SD16 input clock frequency
current
AVCC=DVCC=V
CC
AVSS=DVSS=VSS=0V
GAIN: 1,2
SD16LP = 0,
SD16
=1MHz,
GAIN: 4,8,16
=
GAIN: 32
SD16LP = 1,
=0.5MHz,
SD16
=
GAIN: 1
IN: 32
SD16LP = 0
(Low power mode disabled)
SD16LP = 1
(Low power mode enabled)
A
-40--85°C7301050
105°C1170
-40--85°C
105°C
-40--85°C11601700
105°C1850
-40--85°C7201030
105°C
-40--85°C
105°C1300
VCCMINTYPMAXUNIT
2.53.6V
3
3
8101150
1300
1160
8101150
μ
μ
3V0.0311.1MHz
3V0.030.5MHz
SD16_A, input range (MSP430x20x3 only)
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
Di
V
ID,FSR
erentialfull scale input voltage
range (see Note 1)
Differential input voltage range
V
ID
Z
I
Z
ID
V
I
V
IC
or specified performance
Input impedance
(one input pin to AVSS)
Di
erential Input impedance
(IN+ to IN--)
Absolute input voltage range
Common-mode input voltage
range
NOTES: 1. The analog input range depends on the reference voltage applied to V
is defined by V
V
or V
FSR+
FSR--
FSR+
.
=+(V
/2)/GAIN and V
REF
Bipolar Mode, SD16UNI = 0
Unipolar Mode, SD16UNI = 1
SD16GAINx=1±500
SD16GAINx=2±250
SD16REFON=1
SD16GAINx=4±125
SD16GAINx=8±62
SD16GAINx=16±31
SD16GAINx=32±15
SD16
SD16
FSR--
=1MHz
=1MHz
=--(V
SD16GAINx=13V200
SD16GAINx=323V75
SD16GAINx=13V300400
SD16GAINx=323V100150
/2)/GAIN. The analog input range should not exceed 80% of
REF
REF
.IfV
-- ( V
/2)/
REF
GAIN
0
AV
SS
-0.1V
AV
SS
-0.1V
is sourced externally, the full-scale range
REF
+(V
+(V
REF
GAIN
REF
GAIN
AV
AV
/2)/
/2)/
CC
CC
mV
mV
m
kΩ
kΩ
V
V
44
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
V
SignaltoNoise+DistortionRatio
V
SignaltoNoise+DistortionRatio
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
MSP430x20x3 electrical characteristics over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted) (continued)
SD16GAINx = 1,
Signal Amplitude: V
Signal Frequency: f
= 500mV,
IN
= 100Hz
IN
3V80818283
SD16GAINx = 2,
Signal Amplitude: V
Signal Frequency: f
= 250mV,
IN
= 100Hz
IN
3V74757677
SD16GAINx = 4,
Signal Amplitude: V
Signal Frequency: f
= 125mV,
IN
= 100Hz
IN
3V69707172
SD16GAINx = 8,
Signal Amplitude: V
Signal Frequency: f
= 62mV,
IN
= 100Hz
IN
3V63646768
SD16GAINx = 16,
Signal Amplitude: V
Signal Frequency: f
= 31mV,
IN
= 100Hz
IN
3V58596364
SD16GAINx = 32,
Signal Amplitude: V
Signal Frequency: f
= 15mV,
IN
= 100Hz
IN
3V52535758
UNIT
dB
UNIT
dB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
45
MSP430x20x1, MSP430x20x2, MSP430x20x3
f
f
f
f
p
p
/
OffsetErrorTemperatur
e
ppm
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
MSP430x20x3 electrical characteristics over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted) (continued)
typical characteristics -- SD16_A SINAD performance over OSR (MSP430x20x3 only)
90.0
85.0
80.0
75.0
70.0
SINAD -- dB
65.0
60.0
55.0
10.00100.001000.00
Figure 22. SINAD performance over OSR, f
SD16_A, performance (f
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
G
dG/dTGain Temperature DriftSD16GAINx = 1 (see Note 1)3V15ppm/_C
E
OS
dE
dT
OS
CMRRCommon-Mode Rejection Ratio
DC PSRDC Power Supply Rejection
AC PSRRAC Power Supply Rejection Ratio
NOTES: 1. Calculated using the box method: (MAX(--40...85_C) -- MIN(--40...85_C)) / MIN(--40...85_C) / (85_C--(--40_C))
Nominal Gain
O
set Error
O
set Error Temperature
Coefficient
2. Calculated using the ADC output code and the box method:
(MAX-code(2.5...3.6V) -- MIN-code(2.5...3.6V)) / MIN-code(2.5...3.6V) / (3.6V -- 2.5V)
MSP430x20x3 electrical characteristics over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted) (continued)
SD16_A, built-in voltage reference (MSP430x20x3 only)
PARAMETERTEST CONDITIONST
V
I
REF
REF
Internal reference voltage
Reference supply current
TCTemperature coefficient
C
REF
I
LOAD
t
ON
DC PSR
V
load capacitance
REF
V
maximum load current
REF(I)
Turn on time
DC Power Supply Rejection
∆V
/∆V
REF
CC
NOTES: 1. There is no capacitance required on V
voltage noise.
A
SD16REFON = 1,
SD16VMIDON = 0
SD16REFON = 1,
SD16VMIDON = 0
-40--85°C3V190280
,
105°C3V295
SD16REFON = 1,
SD16VMIDON = 0
SD16REFON = 1,
SD16VMIDON = 0
(see Note 1)
SD16REFON = 1;
SD16VMIDON = 0
SD16REFON = 0 → 1;
SD16VMIDON = 0;
C
= 100nF
REF
SD16REFON = 1;
SD16VMIDON = 0;
V
= 2.5V - 3.6V
CC
. However, a capacitance of at least 100nF is recommended to reduce any reference
MSP430x20x3 electrical characteristics over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted) (continued)
SD16_A, temperature sensor (MSP430x20x3 only)
PARAMETERTEST CONDITIONSVCCMINTYPMAXUNIT
TC
Sensor
V
Offset,Sensor
V
Sensor
NOTES: 1. The following formula can be used to calculate the temperature sensor output voltage:
Sensor temperature coefficient1.181.321.46mV/K
Sensor offset voltage--100100mV
Temperature sensor voltage
at T
A
Sensor output voltage
(see Note 2)
Temperature sensor voltage
at T
A
Temperature sensor voltage
at T
A
V
Sensor,typ
V
Sensor,typ
=TC
=TC
( 273 + T [°C] ) + V
Sensor
T[°C] + V
Sensor
Sensor(TA
Offset,sensor
=0°C) [mV]
2. Values are not based on calculations using TC
=85°C
=25°C
=0°C
Sensor
[mV] or
or V
Offset,sensor
but on measurements.
3V435475515
3V355395435
3V320360400
mV
48
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Flash Memory
PARAMETERTEST CONDITIONSVCCMINTYPMAX UNIT
V
CC(PGM/
ERASE)
f
FTG
I
PGM
I
ERASE
t
CPT
t
CMErase
t
Retention
t
Word
t
Block, 0
t
Block, 1-63
t
Block, End
t
Mass Erase
t
Seg Erase
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
RAM
V
(RAMh)
NOTE 1: This parameter defines the m inimum supply voltage VCCwhen the data in RAM remains unchanged. No program execution should
Program and Erase supply voltage2.23.6V
Flash Timing Generator frequency257476kHz
Supply current from VCCduring program2.2 V/3.6 V15mA
Supply current from VCCduring erase2.2 V/3.6 V17mA
Cumulative program time (see Note 1)2.2 V/3.6 V10ms
Cumulative mass erase time2.2 V/3.6 V20ms
Program/Erase endurance10
4
10
5
Data retention durationTJ=25°C100years
Word or byte program time30
Block program time for 1stbyte or word25
Block program time for each additional byte or word
Block program end-sequence wait time
seeNote2
18
6
Mass erase time10593
Segment erase time4819
methods: individual word/byte write and block write modes.
2. These values are hardwired into the Flash Controller’s state machine (t
FTG
=1/f
FTG
).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
RAM retention supply voltage (see Note 1)CPU halted1.6V
happen during this supply voltage condition.
cycles
t
FTG
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
49
MSP430x20x1, MSP430x20x2, MSP430x20x3
f
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
JTAG and Spy-Bi-Wire Interface
PARAMETER
f
SBW
t
SBW,Low
t
SBW,En
t
SBW,Ret
TCK
R
Internal
NOTES: 1. Tools accessing the Spy-Bi-Wire interface need to wait for the maximum t
Spy-Bi-Wire input frequency2.2 V / 3 V020MHz
Spy-Bi-Wire low clock pulse length2.2 V / 3 V0.02515us
Spy-Bi-Wire enable time
(TEST high to acceptance of first clock edge, see
Note 1)
Spy-Bi-Wire return to normal operation time2.2 V/ 3 V15100us
TCK inputfrequency -- 4-wire JTAG(seeNote2)
Internal pull-down resistance on TEST2.2 V/ 3 V256090kΩ
before applying the first SBWTCK clock edge.
2. f
may be restricted to meet the timing requirements of the module selected.
TCK
JTAG Fuse (see Note 1)
PARAMETER
V
CC(FB)
V
FB
I
FB
t
FB
NOTES: 1. Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible and JTAG is switched
Supply voltage during fuse-blow conditionTA=25°C2.5V
Voltage level on TEST for fuse-blow67V
Supply current into TEST during fuse blow100mA
Time to blow fuse1ms
to bypass mode.
TEST
CONDITIONS
TEST
CONDITIONS
VCCMINTYPMAXUNIT
2.2 V/ 3 V1us
2.2 V05MHz
3V010MHz
time after pulling the TEST/SBWTCK pin high
SBW,En
VCCMINTYPMAXUNIT
50
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION, MSP430x20x1
X
///
/
/
/
/
/
/
Port P1 (P1.0 to P1.3) pin functions, MSP430x20x1
PIN NAME (P1.X)
P1.0/TACLK/ACLK/0
CA0
P1.1/TA0/CA11
P1.2/TA1/CA22
P1.3/CAOUT/CA33
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the CAPD.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying
analog signals. Selecting the CAx input pin to the comparator multiplexer with the P2CAx bits automatically disables the input buffer
for that pin, regardless of the state of the associated CAPD.x bit.
P1.0† Input/Output0/100
Timer_A2.TACLK/INCLK010
ACLK110
CA0(seeNote3)XX1
P1.1† Input/Output0/100
Timer_A2.CCI0A010
Timer_A2.TA0110
CA1(seeNote3)XX1
P1.2† Input/Output0/100
Timer_A2.CCI1A010
Timer_A2.TA1110
CA2(seeNote3)XX1
P1.3† Input/Output0/100
N/A010
CAOUT110
CA3(seeNote3)XX1
FUNCTION
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
CONTROL BITS / SIGNALS
P1DIR.xP1SEL.xCAPD.x
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
51
MSP430x20x1, MSP430x20x2, MSP430x20x3
O
R
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.0 to P1.3) pin schematics, MSP430x20x1
3. Setting the CAPD.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying
analog signals. Selecting the CAx input pin to the comparator multiplexer with the P2CAx bits automatically disables the input buffer
for that pin, regardless of the state of the associated CAPD.x bit.
4. In JTAG mode the internal pull-up/down resistors are disabled.
5. Function controlled by JTAG
P1.4† Input/Output0/1000
N/A0100
SMCLK1100
CA4(seeNote3)XX10
TCK(seeNote4)XXX1
P1.5† Input/Output0/1000
N/A0100
Timer_A2.TA01100
CA5(seeNote3)XX10
TMS(seeNote4)XXX1
P1.6† Input/Output0/1000
N/A0100
Timer_A2.TA11100
CA6(seeNote3)XX10
TDI(seeNote4)XXX1
P1.7† Input/Output0/1000
N/A0100
CAOUT1100
CA7(seeNote3)XX10
TDO/TDI (see Notes 4, 5)XXX1
FUNCTION
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
CONTROL BITS / SIGNALS
P1DIR.xP1SEL.xCAPD.xJTAG Mode
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
53
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.4 to P1.6) pin schematics, MSP430x20x1
3. XIN is used as digital clock input if the bits LFXT1Sx in register BCSCTL3 are set to 11.
P2.6 Input/Output0/10
XIN† (see Note 3)01
Timer_A2.TA111
FUNCTION
CONTROL BITS / SIGNALS
P2DIR.xP2SEL.x
56
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P2 (P2.7) pin schematics, MSP430x20x1
X
/
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
LFXT1 off
LFXT1CLK
P2SEL.6
P2REN.7
P2DIR.7
P2OUT.7
Module X OUT
P2SEL.7
P2IN.7
BCSCTL3.LFXT1Sx = 11
0
1
0
1
0
1
EN
From P2.6/XIN
Direction
0: Input
1: Output
LFXT1 Oscillator
DVSS
DVCC
Bus
Keeper
EN
0
1
P2.6/XIN/TA1
Pad Logic
1
P2.7/XOUT
Module X IN
P2IRQ.7
P2IE.7
P2IFG.7
P2SEL.7
P2IES.7
D
EN
Q
Set
Interrupt
Edge
Select
Port P2 (P2.7) pin functions, MSP430x20x1
PIN NAME (P2.X)
P2.7/XOUT7
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. If the pin P2.7/XOUT is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection
to this pin after reset.
P2.7 Input/Output0/10
DVSS01
XOUT†(seeNote3)11
FUNCTION
CONTROL BITS / SIGNALS
P2DIR.xP2SEL.x
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
57
MSP430x20x1, MSP430x20x2, MSP430x20x3
X
///
/
/
/
/
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
APPLICATION INFORMATION, MSP430x20x2
Port P1 (P1.0 to P1.2) pin functions, MSP430x20x2
PIN NAME (P1.X)
P1.0/TACLK/ACLK/A00
P1.1/TA0/A11
P1.2/TA1/A22
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the ADC10AE.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when
applying analog signals.
P1.0† Input/Output0/100N/A
Timer_A2.TACLK/INCLK010N/A
ACLK110N/A
A0 (see Note 3)XX10
P1.1† Input/Output0/100N/A
Timer_A2.CCI0A010N/A
Timer_A2.TA0110N/A
A1 (see Note 3)XX11
P1.2† Input/Output0/100N/A
Timer_A2.CCI1A010N/A
Timer_A2.TA1110N/A
A2 (see Note 3)XX12
FUNCTION
CONTROL BITS / SIGNALS
P1DIR.xP1SEL.xADC10AE.xINCHx
58
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P1 (P1.0 to P1.2) pin schematics, MSP430x20x2
To A DC 1 0
INCHx = x
ADC10AE.x
P1REN.x
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Pad Logic
P1DIR.x
P1OUT.x
Module X OUT
P1SEL.x
P1IN.x
Module X IN
P1IRQ.x
0
1
0
1
P1IE.x
P1IFG.x
P1SEL.x
P1IES.x
EN
DVSS
DVCC
Direction
0: Input
1: Output
Bus
Keeper
EN
D
EN
Q
Set
Interrupt
Edge
Select
0
1
1
P1.0/TACLK/ACLK/A0
P1.1/TA0/A1
P1.2/TA1/A2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
59
MSP430x20x1, MSP430x20x2, MSP430x20x3
X
/
/
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.3) pin schematics, MSP430x20x2
SREF2
To A DC 1 0 V
A3
INCHx = 3
ADC10AE.3
P1REN.3
P1DIR.3
P1OUT.3
Module X OUT
P1SEL.3
P1IN.3
R--
VSS
0
1
DVSS
DVCC
0
1
0
1
EN
Direction
0: Input
1: Output
Bus
Keeper
EN
0
1
Pad Logic
1
P1.3/ADC10CLK/
A3/VREF--/VeREF--
Module X IN
P1IRQ.3
P1IE.3
P1IFG.3
P1SEL.3
P1IES.3
D
EN
Q
Set
Interrupt
Edge
Select
Port P1 (P1.0 to P1.3) pin functions, MSP430x20x2
PIN NAME (P1.X)
P1.3/ADC10CLK/3
A3/VREF--/VeREF--
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the ADC10AE.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when
applying analog signals.
4. An applied voltage is used as negative reference if bit SREF3 in register ADC10CTL0 is set.
P1.3† Input/Output0/100N/A
N/A010N/A
ADC10CLK110N/A
A3 (see Note 3)XX13
VREF--/VeREF-- (see Notes 3, 4)XX1N/A
FUNCTION
CONTROL BITS / SIGNALS
P1DIR.xP1SEL.xADC10AE.xINCHx
60
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P1 (P1.4 to P1.7) pin functions, MSP430x20x2
///
/
///
/
/////
///
/
PIN NAME (P1.X)
P1.4/SMCLK/A4/4
VREF+/VeREF+/
TCK
P1.5/TA0/SCLK/A5/5
TMS
P1.6/TA1/SDO/SCL/A6/6
TDI
P1.7/SDI/SDA/A7/7
TDO/TDI
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the ADC10AE.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when
applying analog signals.
4. The reference voltage is output if bit REFOUT in register ADC10CTL0 is set. An applied voltage is used as positive reference if
bits SREF0/1 in register ADC10CTL0 are set to 10 or 11.
5. In JTAG mode the internal pull-up/down resistors are disabled.
6. Function controlled by JTAG
XFUNCTION
P1.4† Input/Output0/100N/A0
N/A010N/A0
SMCLK110N/A0
A4 (see Note 3)XX
VREF+/VeREF+
(see Notes 3, 4)
TCK(seeNote5)XXXX1
P1.5† Input/Output0/10X0N/A0
N/A01X0N/A0
Timer_A2.TA011X0N/A0
SCLKXX10N/A0
A5 (see Note 3)XXX150
TMS(seeNote5)XXXXX1
P1.6† Input/Output0/10X0N/A0
Timer_A2.CCI1B01X0N/A0
Timer_A2.TA111X0N/A0
SDO (SPI) / SCL (I2C)XX10N/A0
A6 (see Note 3)XXX160
TDI(seeNote5)XXXXX1
P1.7† Input/Output0/10X0N/A0
N/A01X0N/A0
DVSS11X0N/A0
SDI (SPI) / SDA (I2C)XX10N/A0
A7 (see Note 3)XXX170
TDO/TDI (see Notes 5,
6)
P1DIR.xP1SEL.xUSIP.xADC10AE.xINCHx
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
CONTROL BITS / SIGNALS
JTAG
Mode
N/A
XX
XXXXX1
140
1N/A0
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
61
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.4) pin schematics, MSP430x20x2
To /from ADC10
positive reference
A4
INCHx = 4
ADC10AE.4
P1REN.4
P1DIR.4
P1OUT.4
Module X OUT
P1SEL.4
Pad Logic
DVSS
DVCC
0
1
0
1
EN
Direction
0: Input
1: Output
Bus
Keeper
EN
0
1
1
P1.4/SMCLK/A4/VREF+/VeREF+/TCK
Module X IN
P1IRQ.4
To JTA G
From JTAG
P1IE.4
P1IFG.4
P1SEL.4
P1IES.4
D
EN
Q
Set
Interrupt
Edge
Select
62
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P1 (P1.5) pin schematics, MSP430x20x2
A5
INCHx = 5
ADC10AE.5
P1REN.5
P1SEL.5
USIPE5
P1DIR.5
USI Module Direction
0
1
Direction
0: Input
1: Output
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Pad Logic
DVSS
DVCC
0
1
1
P1OUT.5
Module X OUT
P1IN.5
Module X IN
P1IRQ.5
To JTA G
From JTAG
0
1
P1IE.5
P1IFG.5
P1SEL.5
P1IES.5
P1.5/TA0/SCLK/A5/TMS
Bus
Keeper
EN
EN
D
EN
Q
Set
Interrupt
Edge
Select
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
63
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.6) pin schematics, MSP430x20x2
A6
INCHx = 6
ADC10AE.6
P1REN.6
P1SEL.6
USIPE6
P1DIR.6
USI Module Direction
0
1
Direction
0: Input
1: Output
DVSS
DVCC
0
1
Pad Logic
1
P1OUT.6
Module X OUT
USI Module Output
(I2C Mode)
P1IN.6
Module X IN
P1IRQ.6
To JTA G
From JTAG
0
1
P1IE.6
P1IFG.6
P1SEL.6
P1IES.6
P1.6/TA1/SDO/SCL/A6/TDI
Bus
Keeper
EN
EN
D
EN
Q
Set
Interrupt
Edge
Select
64
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P1 (P1.7) pin schematics, MSP430x20x2
A7
INCHx = 7
ADC10AE.7
P1REN.7
P1SEL.7
USIPE7
P1DIR.7
USI Module Direction
0
1
Direction
0: Input
1: Output
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Pad Logic
DVSS
DVCC
0
1
1
P1OUT.7
Module X OUT
USI Module Output
(I2C Mode)
P1IN.7
Module X IN
P1IRQ.7
To JTA G
From JTAG
From JTAG
0
1
P1IE.7
P1IFG.7
P1SEL.7
P1IES.7
P1.7/SDI/SDA/A7/TDO/TDI
Bus
Keeper
EN
EN
D
EN
Q
Set
Interrupt
Edge
Select
From JTAG (TDO)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
65
MSP430x20x1, MSP430x20x2, MSP430x20x3
X
/
/
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P2 (P2.6) pin schematics, MSP430x20x2
LFXT1 off
LFXT1CLK
P2SEL.7
P2REN.6
P2DIR.6
P2OUT.6
Module X OUT
P2SEL.6
P2IN.6
BCSCTL3.LFXT1Sx = 11
0
1
0
1
0
1
EN
Direction
0: Input
1: Output
LFXT1 Oscillator
DVSS
DVCC
Bus
Keeper
EN
0
1
P2.7/XOUT
Pad Logic
1
P2.6/XIN/TA1
Module X IN
P2IRQ.6
P2IE.6
P2IFG.6
P2SEL.6
P2IES.6
D
EN
Q
Set
Interrupt
Edge
Select
Port P2 (P2.6) pin functions, MSP430x20x2
PIN NAME (P2.X)
P2.6/XIN/TA16
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. XIN is used as digital clock input if the bits LFXT1Sx in register BCSCTL3 are set to 11.
P2.6 Input/Output0/10
XIN† (see Note 3)01
Timer_A2.TA111
FUNCTION
CONTROL BITS / SIGNALS
P2DIR.xP2SEL.x
66
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P2 (P2.7) pin schematics, MSP430x20x2
X
/
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
LFXT1 off
LFXT1CLK
P2SEL.6
P2REN.7
P2DIR.7
P2OUT.7
Module X OUT
P2SEL.7
P2IN.7
BCSCTL3.LFXT1Sx = 11
0
1
0
1
0
1
EN
From P2.6/XIN
Direction
0: Input
1: Output
LFXT1 Oscillator
DVSS
DVCC
Bus
Keeper
EN
0
1
P2.6/XIN/TA1
Pad Logic
1
P2.7/XOUT
Module X IN
P2IRQ.7
P2IE.7
P2IFG.7
P2SEL.7
P2IES.7
D
EN
Q
Set
Interrupt
Edge
Select
Port P2 (P2.7) pin functions, MSP430x20x2
PIN NAME (P2.X)
P2.7/XOUT7
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. If the pin P2.7/XOUT is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection
to this pin after reset.
P2.7 Input/Output0/10
DVSS01
XOUT†(seeNote3)11
FUNCTION
CONTROL BITS / SIGNALS
P2DIR.xP2SEL.x
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
67
MSP430x20x1, MSP430x20x2, MSP430x20x3
X
///
///
///
/
/
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
APPLICATION INFORMATION, MSP430x20x3
Port P1 (P1.0 to P1.3) pin functions, MSP430x20x3
PIN NAME (P1.X)
P1.0/TACLK/ACLK/A0+ 0
P1.1/TA0/A0--/A4+1
P1.2/TA1/A1+/A4--2
P1.3/VREF/A1--3
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the SD16AE.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when
applying analog signals.
4. With SD16AE.x = 0 the negative inputs are connected to VSS if the corresponding input is selected.
P1.0† Input/Output0/100N/A
Timer_A2.TACLK/INCLK010N/A
ACLK110N/A
A0+(seeNote3)XX10
P1.1† Input/Output0/100N/A
Timer_A2.CCI0A010N/A
Timer_A2.TA0110N/A
A0-- (see Notes 3, 4)XX10
A4+(seeNote3)XX14
P1.2† Input/Output0/100N/A
Timer_A2.CCI1A010N/A
Timer_A2.TA1110N/A
A1+(seeNote3)XX11
A4-- (see Notes 3, 4)XX14
P1.3† Input/Output0/100N/A
VREFX10N/A
A1-- (see Notes 3, 4)XX11
FUNCTION
CONTROL BITS / SIGNALS
P1DIR.xP1SEL.xSD16AE.xINCHx
68
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P1 (P1.0) pin schematics, MSP430x20x3
=0
INCH
A0+
.0
16AE
SD
P1
.0
REN
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Pad Logic
P1
DIR
P1OUT.0
Module X OUT
P1SEL.0
P1IN.0
Module X IN
P1
IRQ
DVSS
DVCC
.0
0
1
0
1
EN
D
P1IE.0
.0
P1
IFG
P1SEL.0
P1
.0
IES
.0
Direction
0: Input
1: Output
Bus
Keeper
EN
EN
Q
Set
Interrupt
Edge
Select
0
1
1
P1.0/
TAC L K/ACLK
/A0+
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
69
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.1) pin schematics, MSP430x20x3
=4
INCH
A4+
=0
INCH
0
AV
SS
SD
P1
16
REN
AE
A0--
1
.1
.1
Pad Logic
P1
DIR
P1OUT.1
Module X OUT
P1SEL.1
P1IN.1
Module X IN
P1
IRQ
DVSS
DVCC
.1
0
1
0
1
EN
D
P1IE.1
.1
P1
IFG
P1SEL.1
P1
.1
IES
.1
Direction
0: Input
1: Output
Bus
Keeper
EN
EN
Q
Set
Interrupt
Edge
Select
0
1
1
P1.1/TA0/A0--/A4+
70
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P1 (P1.2) pin schematics, MSP430x20x3
=1
INCH
A1+
=4
INCH
0
AV
SS
SD
P1
16
REN
AE
A4--
.2
.2
1
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Pad Logic
P1
DIR
P1OUT.2
Module X OUT
P1SEL.2
P1IN.2
Module X IN
P1
IRQ
DVSS
DVCC
.2
0
1
0
1
EN
D
P1IE.2
.2
P1
IFG
P1SEL.2
P1
.2
IES
.2
Direction
0: Input
1: Output
Bus
Keeper
EN
EN
Q
Set
Interrupt
Edge
Select
0
1
1
P1.2/TA1/A1+/A4--
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
71
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.3) pin schematics, MSP430x20x3
V
REF
=1
INCH
0
AV
SS
SD
P1
16
REN
AE
A1--
1
.3
.3
Pad Logic
P1
DIR
P1OUT.3
P1SEL.3
P1IN.3
P1
IRQ
DVSS
DVCC
.3
0
1
0
1
P1IE.3
.3
P1
P1SEL.3
P1
IES
.3
IFG
Direction
0: Input
1: Output
.3
Bus
Keeper
EN
EN
Q
Set
Interrupt
Edge
Select
0
1
1
P1.3/VREF/A1--
72
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P1 (P1.4 to P1.7) pin functions, MSP430x20x3
///
///
/
/////
///
/
PIN NAME (P1.X)
P1.4/SMCLK/A2+/4
TCK
P1.5/TA0/SCLK/A2--/5
TMS
P1.6/TA1/SDO/SCL/A3+/ 6
TDI
P1.7/SDI/SDA/A3--/7
TDO/TDI
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the SD16AE.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when
applying analog signals.
4. With SD16AE.x = 0 the negative inputs are connected to VSS if the corresponding input is selected.
5. In JTAG mode the internal pull-up/down resistors are disabled.
6. Function controlled by JTAG
XFUNCTION
P1.4† Input/Output0/10N/A0N/A0
N/A01N/A0N/A0
SMCLK11N/A0N/A0
A2+(seeNote3)XXN/A120
TCK(seeNote5)XXN/AXX1
P1.5† Input/Output0/10X0N/A0
N/A01X0N/A0
Timer_A2.TA011X0N/A0
SCLKXX10N/A0
A2-- (see Notes 3, 4)XXX120
TMS(seeNote5)XXXXX1
P1.6† Input/Output0/10X0N/A0
Timer_A2.CCI1B01X0N/A0
Timer_A2.TA111X0N/A0
SDO (SPI) / SCL (I2C)XX10N/A0
A3+(seeNote3)XXX130
TDI(seeNote5)XXXXX1
P1.7† Input/Output0/10X0N/A0
N/A01X0N/A0
DVSS11X0N/A0
SDI (SPI) / SDA (I2C)XX10N/A0
A3-- (see Notes 3, 4)XXX130
TDO/TDI (see Notes 5, 6)XXXXX1
P1DIR.xP1SEL.xUSIP.xSD16AE.xINCHx
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
CONTROL BITS / SIGNALS
JTAG
Mode
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
73
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.4) pin schematics, MSP430x20x3
=2
INCH
A2+
.4
AE
16
SD
P1
.4
REN
Pad Logic
P1
DIR
P1OUT.4
Module X OUT
P1SEL.4
P1IN.4
Module X IN
P1
IRQ
To JTA G
DVSS
DVCC
.4
0
1
0
1
EN
D
P1IE.4
.4
P1
IFG
P1SEL.4
P1
.4
IES
.4
Direction
0: Input
1: Output
Bus
Keeper
EN
EN
Q
Set
Interrupt
Edge
Select
0
1
1
P1.4/
SMCLK
/A2+/
TCK
From JTAG
74
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P1 (P1.5) pin schematics, MSP430x20x3
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
=2
INCH
A2--
16AE
SD
P1
REN
P1SEL.5
USIPE
P1
DIR
USI Module Direction
P1OUT.5
Module X OUT
P1IN.5
Module X IN
Pad Logic
0
AV
SS
1
.5
.5
5
.5
0
1
0
1
EN
Direction
0: Input
1: Output
D
DVSS
DVCC
Bus
Keeper
EN
0
1
1
P1.5/TA0/
SCLK
/A2--/
TMS
P1
IRQ
To JTA G
From JTAG
P1IE.5
.5
P1
IFG
P1SEL.5
P1
.5
IES
.5
EN
Q
Set
Interrupt
Edge
Select
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
75
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P1 (P1.6) pin schematics, MSP430x20x3
=3
INCH
A3+
AE
16
SD
P1
REN
P1SEL.6
USIPE
P1
DIR
USI Module Direction
P1OUT.6
Module X OUT
USI Module Output
2
(I
C Mode
P1IN.6
Pad Logic
.6
.6
6
.6
0
1
0
1
)
EN
Direction
0: Input
1: Output
DVSS
DVCC
Bus
Keeper
EN
0
1
1
P1.6/TA1/
/SCL/A3+/TDI
SDO
Module X IN
P1
IRQ
To JTA G
From JTAG
D
P1IE.6
.6
P1
IFG
P1SEL.6
P1
.6
IES
.6
EN
Q
Set
Interrupt
Edge
Select
76
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P1 (P1.7) pin schematics, MSP430x20x3
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
=3
INCH
A3--
16AE
SD
P1
REN
P1SEL.x
USIPE
P1
DIR
USI Module Direction
P1OUT.x
Module X OUT
USI Module Output
2
(I
C Mode
P1IN.x
Pad Logic
0
AV
SS
1
.x
.x
7
.x
0
1
0
1
)
EN
Direction
0: Input
1: Output
DVSS
DVCC
Bus
Keeper
EN
0
1
1
P1.7/SDI/
SDA
/A3--/
TDO
/TDI
Module X IN
P1
To JTA G
From JTAG
From JTAG
From JTAG (
IRQ
TDO
D
P1IE.x
.x
P1
IFG
P1SEL.x
P1
.x
IES
)
.x
EN
Q
Set
Interrupt
Edge
Select
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
77
MSP430x20x1, MSP430x20x2, MSP430x20x3
X
/
/
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Port P2 (P2.6) pin schematics, MSP430x20x3
LFXT1 off
LFXT1CLK
P2SEL.7
P2REN.6
P2DIR.6
P2OUT.6
Module X OUT
P2SEL.6
P2IN.6
BCSCTL3.LFXT1Sx = 11
0
1
0
1
0
1
EN
Direction
0: Input
1: Output
LFXT1 Oscillator
DVSS
DVCC
Bus
Keeper
EN
0
1
P2.7/XOUT
Pad Logic
1
P2.6/XIN/TA1
Module X IN
P2IRQ.6
P2IE.6
P2IFG.6
P2SEL.6
P2IES.6
D
EN
Q
Set
Interrupt
Edge
Select
Port P2 (P2.6) pin functions, MSP430x20x3
PIN NAME (P2.X)
P2.6/XIN/TA16
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. XIN is used as digital clock input if the bits LFXT1Sx in register BCSCTL3 are set to 11.
P2.6 Input/Output0/10
XIN† (see Note 3)01
Timer_A2.TA111
FUNCTION
CONTROL BITS / SIGNALS
P2DIR.xP2SEL.x
78
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P2 (P2.7) pin schematics, MSP430x20x3
X
/
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
LFXT1 off
LFXT1CLK
P2SEL.6
P2REN.7
P2DIR.7
P2OUT.7
Module X OUT
P2SEL.7
P2IN.7
BCSCTL3.LFXT1Sx = 11
0
1
0
1
0
1
EN
From P2.6/XIN
Direction
0: Input
1: Output
LFXT1 Oscillator
DVSS
DVCC
Bus
Keeper
EN
0
1
P2.6/XIN/TA1
Pad Logic
1
P2.7/XOUT
Module X IN
P2IRQ.7
P2IE.7
P2IFG.7
P2SEL.7
P2IES.7
D
EN
Q
Set
Interrupt
Edge
Select
Port P2 (P2.7) pin functions, MSP430x20x3
PIN NAME (P2.X)
P2.7/XOUT7
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. If the pin P2.7/XOUT is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection
to this pin after reset.
P2.7 Input/Output0/10
DVSS01
XOUT†(seeNote3)11
FUNCTION
CONTROL BITS / SIGNALS
P2DIR.xP2SEL.x
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
79
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Data Sheet Revision History
Literature
Number
SLAS491Preliminary PRODUCT PREVIEW data sheet release
SLAS491AProduction data sheet release for MSP430x20x3I.
SLAS491BProduction data sheet release for MSP430x20x3T, MSP430x20x1I and MSP430x20x1T.
SLAS491CProduction data sheet release for MSP430x20x2I and MSP430x20x2T.
SLAS491DChanged f
Updated specification and added characterization graphs.
105°C characterization results added.
SD16_A SINAD characterization results for MSP430x20x3RSA package added.
Updated SD16_A Power Supply Rejection specification.
DCO Calibration Register names: lower case “z” changed to upper case “Z”.
V
hys(B_IT--)
MIN and MAX percentages for “calibrated DCO frequencies -- tolerance over supply voltage VCC” corrected from 2.5% to
3.0% to match the specified frequency ranges.
MAX specification increased from 180mV to 210mV.
ACLK
to0HzinI
test conditions on page 23.
LPM4
Summary
80
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
PACKAGING INFORMATION
Orderable DeviceStatus
MSP430F2001INACTIVEPDIPN1425Pb-Free
MSP430F2001IPWACTIVETSSOPPW1490Green (RoHS &
MSP430F2001IPWRACTIVETSSOPPW142000 Green (RoHS &
MSP430F2001IRSARACTIVEQFNRSA163000 Green (RoHS &
MSP430F2001IRSATACTIVEQFNRSA16250 Green (RoHS &
MSP430F2001TNACTIVEPDIPN1425Pb-Free
MSP430F2001TPWACTIVETSSOPPW1490Green (RoHS &
MSP430F2001TPWRACTIVETSSOPPW142000 Green (RoHS &
MSP430F2001TRSARACTIVEQFNRSA163000 Green (RoHS &
MSP430F2001TRSATACTIVEQFNRSA16250 Green (RoHS &
MSP430F2002INACTIVEPDIPN1425Pb-Free
MSP430F2002IPWACTIVETSSOPPW1490Green (RoHS &
MSP430F2002IPWRACTIVETSSOPPW142000 Green (RoHS &
MSP430F2002IRSARACTIVEQFNRSA163000 Green (RoHS &
MSP430F2002IRSATACTIVEQFNRSA16250 Green (RoHS &
MSP430F2002TNACTIVEPDIPN1425Pb-Free
MSP430F2002TPWACTIVETSSOPPW1490Green (RoHS &
MSP430F2002TPWRACTIVETSSOPPW142000 Green (RoHS &
MSP430F2002TRSARACTIVEQFNRSA163000 Green (RoHS &
MSP430F2002TRSATACTIVEQFNRSA16250 Green (RoHS &
MSP430F2003INACTIVEPDIPN1425Pb-Free
MSP430F2003IPWACTIVETSSOPPW1490Green (RoHS &
MSP430F2003IPWRACTIVETSSOPPW142000 Green (RoHS &
MSP430F2003IRSARACTIVEQFNRSA163000 Green (RoHS &
MSP430F2003IRSATACTIVEQFNRSA16250 Green (RoHS &
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(RoHS)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
(RoHS)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
(RoHS)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
(RoHS)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
(RoHS)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
11-Jun-2007
(3)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable DeviceStatus
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
MSP430F2003TNACTIVEPDIPN1425Pb-Free
(RoHS)
MSP430F2003TPWACTIVETSSOPPW1490Green (RoHS &
no Sb/Br)
MSP430F2003TPWRACTIVETSSOPPW142000 Green (RoHS &
no Sb/Br)
MSP430F2003TRSARACTIVEQFNRSA163000 Green (RoHS &
no Sb/Br)
MSP430F2003TRSATACTIVEQFNRSA16250 Green (RoHS &
no Sb/Br)
MSP430F2011INACTIVEPDIPN1425Pb-Free
(RoHS)
MSP430F2011IPWACTIVETSSOPPW1490Green (RoHS &
no Sb/Br)
MSP430F2011IPWRACTIVETSSOPPW142000 Green (RoHS &
no Sb/Br)
MSP430F2011IRSARACTIVEQFNRSA163000 Green (RoHS &
no Sb/Br)
MSP430F2011IRSATACTIVEQFNRSA16250 Green (RoHS &
no Sb/Br)
MSP430F2011TNACTIVEPDIPN1425Pb-Free
(RoHS)
MSP430F2011TPWACTIVETSSOPPW1490Green (RoHS &
no Sb/Br)
MSP430F2011TPWRACTIVETSSOPPW142000 Green (RoHS &
no Sb/Br)
MSP430F2011TRSARACTIVEQFNRSA163000 Green (RoHS &
no Sb/Br)
MSP430F2011TRSATACTIVEQFNRSA16250 Green (RoHS &
no Sb/Br)
MSP430F2012INACTIVEPDIPN1425Pb-Free
(RoHS)
MSP430F2012IPWACTIVETSSOPPW1490Green (RoHS &
no Sb/Br)
MSP430F2012IPWRACTIVETSSOPPW142000 Green (RoHS &
no Sb/Br)
MSP430F2012IRSARACTIVEQFNRSA163000 Green (RoHS &
no Sb/Br)
MSP430F2012IRSATACTIVEQFNRSA16250 Green (RoHS &
no Sb/Br)
MSP430F2012TNACTIVEPDIPN1425Pb-Free
(RoHS)
MSP430F2012TPWACTIVETSSOPPW1490Green (RoHS &
no Sb/Br)
MSP430F2012TPWRACTIVETSSOPPW142000 Green (RoHS &
no Sb/Br)
MSP430F2012TRSARACTIVEQFNRSA163000 Green (RoHS &
no Sb/Br)
MSP430F2012TRSATACTIVEQFNRSA16250 Green (RoHS &
no Sb/Br)
MSP430F2013INACTIVEPDIPN1425Pb-Free
(RoHS)
11-Jun-2007
Lead/Ball Finish MSL Peak Temp
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-1-260C-UNLIM
(3)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable DeviceStatus
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
MSP430F2013IPWACTIVETSSOPPW1490Green (RoHS &
Lead/Ball Finish MSL Peak Temp
CU NIPDAULevel-1-260C-UNLIM
11-Jun-2007
(3)
no Sb/Br)
MSP430F2013IPWRACTIVETSSOPPW142000 Green (RoHS &
CU NIPDAULevel-1-260C-UNLIM
no Sb/Br)
MSP430F2013IRSARACTIVEQFNRSA163000 Green (RoHS &
CU NIPDAULevel-2-260C-1 YEAR
no Sb/Br)
MSP430F2013IRSATACTIVEQFNRSA16250 Green (RoHS &
CU NIPDAULevel-2-260C-1 YEAR
no Sb/Br)
MSP430F2013TNACTIVEPDIPN1425Pb-Free
CU NIPDAULevel-1-260C-UNLIM
(RoHS)
MSP430F2013TPWACTIVETSSOPPW1490Green (RoHS &
CU NIPDAULevel-1-260C-UNLIM
no Sb/Br)
MSP430F2013TPWRACTIVETSSOPPW142000 Green (RoHS &
CU NIPDAULevel-1-260C-UNLIM
no Sb/Br)
MSP430F2013TRSARACTIVEQFNRSA163000 Green (RoHS &
CU NIPDAULevel-2-260C-1 YEAR
no Sb/Br)
MSP430F2013TRSATACTIVEQFNRSA16250 Green (RoHS &
CU NIPDAULevel-2-260C-1 YEAR
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 3
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
1,20 MAX
14
0,30
0,19
8
4,50
4,30
PINS **
7
Seating Plane
0,15
0,05
8
1
A
DIM
6,60
6,20
14
0,10
M
0,10
0,15 NOM
0°–8°
2016
Gage Plane
24
0,25
0,75
0,50
28
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153