TEXAS INSTRUMENTS MSP430x20x1 Technical data
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
D Low Supply Voltage Range 1.8 V to 3.6 V
D Ultralow Power Consumption
-- Active Mode: 220 μAat1MHz,2.2V
-- Standby Mode: 0.5 μA
-- Off Mode (RAM Retention): 0.1 μA
D Five Power-Saving Modes
D Ultrafast Wake-Up From Standby Mode in
Less Than 1 μs
D 16-Bit RISC Architecture, 62.5 ns
Instruction Cycle Time
D Basic Clock Module Configurations:
-- Internal Frequencies up to 16 MHz With
Four Calibrated Frequencies to ±1%
-- Internal Very Low Power LF Oscillator
-- 32-kHz Crystal
-- External Digital Clock Source
D 16-Bit Timer_A With Two Capture/Compare
Registers
D On-Chip Comparator for Analog Signal
Compare Function or Slope A/D
(MSP430x20x1 only)
D 10-Bit 200-ksps A/D Converter With Internal
Reference, Sample-and-Hold, and Autoscan
(MSP430x20x2 only)
D 16-Bit Sigma-Delta A/D Converter With
Differential PGA Inputs and Internal
Reference (MSP430x20x3 only)
D Universal Serial Interface (USI) Supporting
SPI and I2C
(MSP430x20x2 and MSP430x20x3 only)
D Brownout Detector
D Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by
Security Fuse
D On-Chip Emulation Logic With Spy-Bi-Wire
Interface
D Family Members Include:
MSP430F2001: 1KB + 256B Flash Memory
128B RAM
MSP430F2011: 2KB + 256B Flash Memory
128B RAM
MSP430F2002: 1KB + 256B Flash Memory
128B RAM
MSP430F2012: 2KB + 256B Flash Memory
128B RAM
MSP430F2003: 1KB + 256B Flash Memory
128B RAM
MSP430F2013: 2KB + 256B Flash Memory
128B RAM
D Available in a 14-Pin Plastic Small-Outline
Thin Package (TSSOP), 14-Pin Plastic Dual
Inline Package (PDIP), and 16-Pin QFN
D For Complete Module Descriptions, See the
MSP430x2xx Family User’s Guide
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 1μs.
The MSP430x20xx series is an ultralow-power mixed signal microcontroller with a built-in 16-bit timer, and ten
I/O pins. In addition the MSP430x20x1 has a versatile analog comparator. The MSP430x20x2 and
MSP430x20x3 have built-in communication capability using synchronous protocols (SPI or I2C), and a 10-bit
A/D converter (MSP430x20x2) or a 16-bit sigma-delta A/D converter (MSP430x20x3).
Typicalapplicationsinclude sensor systems that capture analog signals,convert them to digital values, and then
process the data for display or for transmission to a host system. Stand alone RF sensor front end is another
area of application.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright © 2007 Texas Instruments Incorporated
1
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
AVAILABLE OPTIONS
T
A
-- 4 0 °Cto85°C
-- 4 0 °C to 105°C
device pinout, MSP430x20x1
PW or N PACKAGE
V
CC
P1.0/TACLK/ACLK/CA0
P1.1/TA0/CA1
P1.2/TA1/CA2
P1.3/CAOUT/CA3
P1.4/SMCLK/CA4/TCK
P1.5/TA0/CA5/TMS
(TOP VIEW)
1
2
3
4
5
6
7
PLASTIC
14-PIN TSSOP
(PW)
MSP430F2001IPW
MSP430F2011IPW
MSP430F2002IPW
MSP430F2012IPW
MSP430F2003IPW
MSP430F2013IPW
MSP430F2001TPW
MSP430F2011TPW
MSP430F2002TPW
MSP430F2012TPW
MSP430F2003TPW
MSP430F2013TPW
14
V
13
12
11
10
9
8
SS
XIN/P2.6/TA1
XOUT/P2.7
TEST/SBWTCK
RST
/NMI/SBWTDIO
P1.7/CAOUT/CA7/TDO/TDI
P1.6/TA1/CA6/TDI/TCLK
PACKAGED DEVICES
PLASTIC
14-PIN DIP
(N)
MSP430F2001IN
MSP430F2011IN
MSP430F2002IN
MSP430F2012IN
MSP430F2003IN
MSP430F2013IN
MSP430F2001TN
MSP430F2011TN
MSP430F2002TN
MSP430F2012TN
MSP430F2003TN
MSP430F2013TN
PLASTIC
16-PIN QFN
(RSA)
MSP430F2001IRSA
MSP430F2011IRSA
MSP430F2002IRSA
MSP430F2012IRSA
MSP430F2003IRSA
MSP430F2013IRSA
MSP430F2001TRSA
MSP430F2011TRSA
MSP430F2002TRSA
MSP430F2012TRSA
MSP430F2003TRSA
MSP430F2013TRSA
P1.0/TACLK/ACLK/CA0
P1.1/TA0/CA1
P1.2/TA1/CA2
P1.3/CAOUT/CA3
NOTE: See port schematics section for detailed I/O information.
RSA PACKAGE
(TOP VIEW)
CCVSS
V
NC
15
1
2
3
4
67
P1.5/TA0/CA5/TMS
P1.4/SMCLK/CA4/TCK
NC
14
12
11
10
9
P1.6/TA1/CA6/TDI/TCLK
P1.7/CAOUT/CA7/TDO/TDI
XIN/P2.6/TA1
XOUT/P2.7
TEST/SBWTCK
RST
/NMI/SBWTDIO
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
device pinout, MSP430x20x2
V
P1.0/TACLK/ACLK/A0
P1.1/TA0/A1
P1.2/TA1/A2
P1.3/ADC10CLK/A3/VREF--/VeREF--
P1.4/SMCLK/A4/VREF+/VeREF+/TCK
P1.5/TA0/A5/SCLK/TMS
PW or N PACKAGE
(TOP VIEW)
1
CC
2
3
4
5
6
7
P1.3/ADC10CLK/A3/VREF--/VeREF--
14
13
12
11
10
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
V
SS
XIN/P2.6/TA1
XOUT/P2.7
TEST/SBWTCK
RST
/NMI/SBWTDIO
9
P1.7/A7/SDI/SDA/TDO/TDI
8
P1.6/TA1/A6/SDO/SCL/TDI/TCLK
P1.0/TACLK/ACLK/A0
P1.1/TA0/A1
P1.2/TA1/A2
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
RSA PACKAGE
(TOP VIEW)
SS
DVCCDV
15
1
2
3
4
CC
AV
67
14
SS
AV
XIN/P2.6/TA1
12
XOUT/P2.7
11
10
TEST/SBWTCK
RST
9
/NMI/SBWTDIO
NOTE: See port schematics section for detailed I/O information.
P1.5/TA0/A5/SCLK/TMS
P1.7/A7/SDI/SDA/TDO/TDI
P1.6/TA1/A6/SDO/SCL/TDI/TCLK
P1.4/SMCLK/A4/VREF+/VeREF+/TCK
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
device pinout, MSP430x20x3
PW or N PACKAGE
(TOP VIEW)
V
CC
P1.0/TACLK/ACLK/A0+
P1.1/TA0/A0--/A4+
P1.2/TA1/A1+/A4--
P1.3/VREF/A1--
P1.4/SMCLK/A2+/TCK
P1.5/TA0/A2--/SCLK/TMS
1
2
3
4
5
6
7
14
13
12
11
10
V
SS
XIN/P2.6/TA1
XOUT/P2.7
TEST/SBWTCK
RST
/NMI/SBWTDIO
9
P1.7/A3--/SDI/SDA/TDO/TDI
8
P1.6/TA1/A3+/SDO/SCL/TDI/TCLK
P1.0/TACLK/ACLK/A0+
P1.1/TA0/A0--/A4+
P1.2/TA1/A1+/A4--
P1.3/VREF/A1--
RSA PACKAGE
(TOP VIEW)
SS
CC
DVCCDV
AV
15
1
2
3
4
14
67
SS
AV
XIN/P2.6/TA1
12
XOUT/P2.7
11
10
TEST/SBWTCK
RST
9
/NMI/SBWTDIO
NOTE: See port schematics section for detailed I/O information.
P1.4/SMCLK/A2+/TCK
P1.5/TA0/A2--/SCLK/TMS
P1.7/A3--/SDI/SDA/TDO/TDI
P1.6/TA1/A3+/SDO/SCL/TDI/TCLK
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram, MSP430x20x1
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
VCC VSS
System+
16MHz
CPU
incl. 16
Registers
Emulation
(2BP)
JTAG
Interface
XOUT
MCLK
ACLK
SMCLK
MAB
MDB
Flash
2kB
1kB
Brownout
Protection
RST/NMI
XIN
Basic Clock
Spy--Bi Wire
NOTE: See port schematics section for detailed I/O information.
functional block diagram, MSP430x20x2
VCC VSS
System+
16MHz
CPU
incl. 16
Registers
XOUT
MCLK
ACLK
SMCLK
MAB
MDB
Flash
2kB
1kB
XIN
Basic Clock
RAM
128B
128B
RAM
128B
128B
Comparator
_A+
8 channel
input mux
Watchdog
WDT+
15/16--Bit
ADC10
10--bit
8 Channels
Autoscan
DTC
P1.x & JTAG
8 2
Port P1
8I/O
Interrupt
capability,
pull--up/down
resistors
Timer_A2
2CC
Registers
P1.x & JTAG
8 2
Port P1
8I/O
Interrupt
capability,
pull--up/down
resistors
P2.x &
XIN/XOUT
Port P2
2I/O
Interrupt
capability,
pull--up/down
resistors
P2.x &
XIN/XOUT
Port P2
2I/O
Interrupt
capability,
pull--up/down
resistors
Emulation
(2BP)
JTAG
Interface
Spy--Bi Wire
Brownout
Protection
RST/NMI
NOTE: See port schematics section for detailed I/O information.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Watchdog
WDT+
15/16--Bit
Timer_A2
2CC
Registers
USI
Universal
Serial
Interface
SPI, I2C
5
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
functional block diagram, MSP430x20x3
VCC VSS
System+
16MHz
CPU
incl. 16
Registers
Emulation
(2BP)
JTAG
Interface
XOUT
MCLK
ACLK
SMCLK
MAB
MDB
Flash
2kB
1kB
Brownout
Protection
RST/NMI
RAM
128B
128B
XIN
Basic Clock
Spy--Bi Wire
NOTE: See port schematics section for detailed I/O information.
SD16_A
16--bit
Sigma-Delta A/D
Converter
Watchdog
WDT+
15/16--Bit
P1.x & JTAG
8 2
Port P1
8I/O
Interrupt
capability,
pull--up/down
resistors
Timer_A2
2CC
Registers
P2.x &
XIN/XOUT
Port P2
2I/O
Interrupt
capability,
pull--up/down
resistors
USI
Universal
Serial
Interface
SPI, I2C
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
DESCRIPTION
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Terminal Functions, MSP430x20x1
TERMINAL
NAME
P1.0/TACLK/ACLK/CA0 2 1 I/O General-purpose digital I/O pin
P1.1/TA0/CA1 3 2 I/O General-purpose digital I/O pin
P1.2/TA1/CA2 4 3 I/O General-purpose digital I/O pin
P1.3/CAOUT/CA3 5 4 I/O General-purpose digital I/O pin
P1.4/SMCLK/C4/TCK 6 5 I/O General-purpose digital I/O pin
P1.5/TA0/CA5/TMS 7 6 I/O General-purpose digital I/O pin
P1.6/TA1/CA6/TDI/TCLK 8 7 I/O General-purpose digital I/O pin
P1.7/CAOUT/CA7/TDO/TDI
XIN/P2.6/TA1 13 12 I/O Input terminal of crystal oscillator
XOUT/P2.7 12 11 I/O Output terminal of crystal oscillator
RST/NMI/SBWTDIO 10 9 I Reset or nonmaskable interrupt input
TEST/SBWTCK 11 10 I Selects test mode for JTAG pins on Port1. The device protection fuse is
V
CC
V
SS
NC NA 13, 15 Not connected
QFN Pad NA Package
†
TDO or TDI is selected via JTAG instruction.
NOTE: If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection
to this pad after reset.
†
PW or N RSA
NO. NO.
9 8 I/O General-purpose digital I/O pin
1 16 Supply voltage
14 14 Ground reference
Pad
I/O
Timer_A, clock signal TACLK input
ACLK signal ouput
Comparator_A+, CA0 input
Timer_A, capture: CCI0A input, compare: Out0 output
Comparator_A+, CA1 input
Timer_A, capture: CCI1A input, compare: Out1 output
Comparator_A+, CA2 input
Comparator_A+, output / CA3 input
SMCLK signal output
Comparator_A+, CA4 input
JTAG test clock, input terminal for device programming and test
Timer_A, compare: Out0 output
Comparator_A+, CA5 input
JTAG test mode select, input terminal for device programming and test
Timer_A, compare: Out1 output
Comparator_A+, CA6 input
JTAG test data input or test clock input during programming and test
Comparator_A+, output / CA7 input
JTAGtestdataoutputterminalortestdata input during programming and
test
General-purpose digital I/O pin
Timer_A, compare: Out1 output
General-purpose digital I/O pin
Spy-Bi-Wire test data input/output during programming and test
connected to TEST.
Spy-Bi-Wire test clock input during programming and test
NA QFN package pad connection to VSSrecommended.
DESCRIPTION
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
MSP430x20x1, MSP430x20x2, MSP430x20x3
DESCRIPTION
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Terminal Functions, MSP430x20x2
TERMINAL
NAME
P1.0/TACLK/ACLK/A0 2 1 I/O General-purpose digital I/O pin
P1.1/TA0/A1 3 2 I/O General-purpose digital I/O pin
P1.2/TA1/A2 4 3 I/O General-purpose digital I/O pin
P1.3/ADC10CLK/
A3/VREF--/VeREF--
P1.4/SMCLK/A4/VREF+/VeREF+/
TCK
P1.5/TA0/A5/SCLK/TMS 7 6 I/O General-purpose digital I/O pin
P1.6/TA1/A6/SDO/SCL/TDI/TCLK 8 7 I/O General-purpose digital I/O pin
P1.7/A7/SDI/SDA/TDO/TDI
XIN/P2.6/TA1 13 12 I/O Input terminal of crystal oscillator
XOUT/P2.7 12 11 I/O Output terminal of crystal oscillator
RST/NMI/SBWTDIO 10 9 I Reset or nonmaskable interrupt input
TEST/SBWTCK 11 10 I Selects test mode for JTAG pins on Port1. The device protection fuse is
V
CC
V
SS
†
TDO or TDI is selected via JTAG instruction.
NOTE: If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection
to this pad after reset.
†
PW, or N RSA
NO. NO.
5 4 I/O General-purpose digital I/O pin
6 5 I/O General-purpose digital I/O pin
9 8 I/O General-purpose digital I/O pin
1 NA Supply voltage
14 NA Ground reference
I/O
Timer_A, clock signal TACLK input
ACLK signal ouput
ADC10 analog input A0
Timer_A, capture: CCI0A input, compare: Out0 output
ADC10 analog input A1
Timer_A, capture: CCI1A input, compare: Out1 output
ADC10 analog input A2
ADC10 conversion clock output
ADC10 analog input A3
Input for negative external reference voltage/negative internal reference
voltage output
SMCLK signal output
ADC10 analog input A4
Input for positive external reference voltage/positive internal reference
voltage output
JTAG test clock, input terminal for device programming and test
Timer_A, compare: Out0 output
ADC10 analog input A5
USI: external clock input in SPI or I2C mode; clock output in SPI mode
JTAG test mode select, input terminal for device programming and test
Timer_A, capture: CCI1B input, compare: Out1 output
ADC10 analog input A6
USI: Data output in SPI mode; I2C clock in I2C mode
JTAG test data input or test clock input during programming and test
ADC10 analog input A7
USI: Data input in SPI mode; I2C data in I2C mode
JTAGtestdataoutputterminalortestdata input during programming and
test
General-purpose digital I/O pin
Timer_A, compare: Out1 output
General-purpose digital I/O pin
Spy-Bi-Wire test data input/output during programming and test
connected to TEST.
Spy-Bi-Wire test clock input during programming and test
DESCRIPTION
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
DESCRIPTION
DESCRIPTION
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Terminal Functions, MSP430x20x2 (Continued)
TERMINAL
NAME
DV
CC
AV
CC
DV
SS
AV
SS
QFN Pad NA Package
TERMINAL
NAME
P1.0/TACLK/ACLK/A0+ 2 1 I/O General-purpose digital I/O pin
P1.1/TA0/A0--/A4+ 3 2 I/O General-purpose digital I/O pin
P1.2/TA1/A1+/A4-- 4 3 I/O General-purpose digital I/O pin
P1.3/VREF/A1-- 5 4 I/O General-purpose digital I/O pin
P1.4/SMCLK/A2+/TCK 6 5 I/O General-purpose digital I/O pin
P1.5/TA0/A2--/SCLK/TMS 7 6 I/O General-purpose digital I/O pin
P1.6/TA1/A3+/SDO/SCL/TDI/TCLK 8 7 I/O General-purpose digital I/O pin
P1.7/A3--/SDI/SDA/TDO/TDI
†
TDO or TDI is selected via JTAG instruction.
†
PW, or N RSA
NO. NO.
NA 16 Digital supply voltage
NA 15 Analog supply voltage
NA 14 Digital ground reference
NA 13 Analog ground reference
Pad
I/O
NA QFN package pad connection to VSSrecommended.
Terminal Functions, MSP430x20x3
PW, or N RSA
NO. NO.
9 8 I/O General-purpose digital I/O pin
I/O
Timer_A, clock signal TACLK input
ACLK signal ouput
SD16_A positive analog input A0
Timer_A, capture: CCI0A input, compare: Out0 output
SD16_A negative analog input A0
SD16_A positive analog input A4
Timer_A, capture: CCI1A input, compare: Out1 output
SD16_A positive analog input A1
SD16_A negative analog input A4
Input for an external reference voltage/internal reference voltage output
(can be used as mid-voltage)
SD16_A negative analog input A1
SMCLK signal output
SD16_A positive analog input A2
JTAG test clock, input terminal for device programming and test
Timer_A, compare: Out0 output
SD16_A negative analog input A2
USI: external clock input in SPI or I2C mode; clock output in SPI mode
JTAG test mode select, input terminal for device programming and test
Timer_A, capture: CCI1B input, compare: Out1 output
SD16_A positive analog input A3
USI: Data output in SPI mode; I2C clock in I2C mode
JTAG test data input or test clock input during programming and test
SD16_A negative analog input A3
USI: Data input in SPI mode; I2C data in I2C mode
JTAGtestdataoutputterminalortestdata input during programming and
test
DESCRIPTION
DESCRIPTION
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
MSP430x20x1, MSP430x20x2, MSP430x20x3
DESCRIPTION
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
Terminal Functions, MSP430x20x3 (Continued)
TERMINAL
NAME
XIN/P2.6/TA1 13 12 I/O Input terminal of crystal oscillator
XOUT/P2.7 12 11 I/O Output terminal of crystal oscillator
RST/NMI/SBWTDIO 10 9 I Reset or nonmaskable interrupt input
TEST/SBWTCK 11 10 I Selects test mode for JTAG pins on Port1. The device protection fuse is
V
CC
V
SS
DV
CC
AV
CC
DV
SS
AV
SS
QFN Pad NA Package
NOTE: If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection
to this pad after reset.
PW, or N RSA
NO. NO.
1 NA Supply voltage
14 NA Ground reference
NA 16 Digital supply voltage
NA 15 Analog supply voltage
NA 14 Digital ground reference
NA 13 Analog ground reference
Pad
I/O
General-purpose digital I/O pin
Timer_A, compare: Out1 output
General-purpose digital I/O pin
Spy-Bi-Wire test data input/output during programming and test
connected to TEST.
Spy-Bi-Wire test clock input during programming and test
NA QFN package pad connection to VSSrecommended.
DESCRIPTION
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
short-form description
CPU
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
Program Counter
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
Table 1. Instruction Word Formats
Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 ------> R5
Single operands, destination only e.g., CALL R8 PC -- -->(TOS), R8----> PC
Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE S D SYNTAX EXAMPLE OPERATION
Register F
Indexed F F MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)----> M(6+R6)
Symbolic (PC relative) F F MOV EDE,TONI M(EDE) ----> M(TONI)
Absolute F F MOV &MEM,&TCDAT M(MEM) ----> M(TCDAT)
Indirect F MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) ----> M(Tab+R6)
Indirect
autoincrement
Immediate F MOV #X,TONI MOV #45,TONI #45 ----> M(TONI)
NOTE: S = source D = destination
F
F MOV @Rn+,Rm MOV @R10+,R11
MOV Rs,Rd MOV R10,R11 R10 ----> R11
M(R10) ----> R11
R10 + 2----> R10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
operating modes
The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, s ervice the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D Active mode AM;
-- All clocks are active
D Low-power mode 0 (LPM0);
-- CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
D Low-power mode 1 (LPM1);
-- CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
DCO’s dc-generator is disabled if DCO not used in active mode
D Low-power mode 2 (LPM2);
-- CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D Low-power mode 3 (LPM3);
-- CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
D Low-power mode 4 (LPM4);
-- CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh--0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed) the CPU will
go into LPM4 immediately after power-up.
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
Power-up
External reset
Watchdog Timer+
Flash key violation
PC out-of-range (see Note 1)
NMI
Oscillator fault
Flash memory access violation
Comparator_A+ (MSP430x20x1 only) CAIFG(seeNote3) maskable 0FFF6h 27
Watchdog Timer+ WDTIFG maskable 0FFF4h 26
Timer_A2 TACCR0 CCIFG (see Note 3) maskable 0FFF2h 25
Timer_A2
ADC10 (MSP430x20x2 only)
SD16_A (MSP430x20x3 only)
USI
(MSP430x20x2, MSP430x20x3 only)
I/O Port P2
(two flags)
I/O Port P1
(eight flags)
(see Note 5) 0FFDEh ... 0FFC0h 15 ... 0, lowest
NOTES: 1. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h--01FFh) or from
within unused address ranges.
2. Multiple source flags
3. Interrupt flags are located in the module
4. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
5. The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
TAIFG (see Notes 2 and 3)
SD16CCTL0 SD16OVIFG,
PORIFG
RSTIFG
WDTIFG
KEYV
(see Note 2)
NMIIFG
OFIFG
ACCVIFG
(see Notes 2 and 4)
TACCR1 CCIFG.
ADC10IFG (see Note 3)
SD16CCTL0 SD16IFG
(see Notes 2 and 3)
USIIFG, USISTTIFG
(see Notes 2 and 3)
P2IFG.6toP2IFG.7
(see Notes 2 and 3)
P1IFG.0toP1IFG.7
(see Notes 2 and 3)
Reset 0FFFEh 31, highest
(non)-maskable,
(non)-maskable,
(non)-maskable
maskable 0FFF0h 24
maskable
maskable
maskable 0FFE8h 20
maskable 0FFE6h 19
maskable 0FFE4h 18
0FFFCh 30
0FFFAh 29
0FFF8h 28
0FFEEh 23
0FFECh 22
0FFEAh 21
0FFE2h 17
0FFE0h 16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
interrupt enable 1 and 2
Address
0h
7654 0
NMIIEACCVIE
rw-0 rw-0 rw-0
32 1
OFIE WDTIE
rw-0
WDTIE: WatchdogTimer interrupt enable. Inactive if watchdog mode is selected. Active if WatchdogTimer
is configured in interval timer mode.
OFIE: Oscillator fault enable
NMIIE: (Non)maskable interrupt enable
ACCVIE: Flash access violation interrupt enable
Address
01h
7654 032 1
interrupt flag register 1 and 2
Address
02h NMIIFG
7654 0
rw-0 rw-1 rw-(0)
32 1
RSTIFG
rw-(0)
PORIFG
rw-(1)
OFIFG WDTIFG
WDTIFG: Set on Watchdog Timer overflow (in watchdog mode) or security key violation.
Reset on V
power-up or a reset condition at RST/NMI pin in reset mode.
CC
OFIFG: Flag set on oscillator fault
RSTIFG: External reset interrupt flag. Set on a reset condition at RST
/NMI pin in reset mode. Reset on V
power-up
PORIFG: Power-On Reset interrupt flag. Set on V
NMIIFG: Set via RST
/NMI-pin
power-up.
CC
CC
14
Address
03h
Legend rw:
rw-0,1:
rw-(0,1):
7654 032 1
Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
memory organization
MSP430F200x MSP430F201x
Memory
Main: interrupt vector
Main: code memory
Information memory Size
RAM Size 128 Byte
Peripherals 16-bit
flash memory
The flash memory can be programmed via the Spy-Bi-Wire/JTAG port, or in-system by the CPU. The CPU can
perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and four segments of information memory (A to D) of 64
bytes each. Each segment in main memory is 512 bytes in size.
Size
Flash
Flash
Flash
8-bit
8-bit SFR
1KB Flash
0FFFFh--0FFC0h
0FFFFh--0FC00h
256 Byte
010FFh -- 01000h
027Fh -- 0200h
01FFh -- 0100h
0FFh -- 010h
0Fh -- 00h
2KB Flash
0FFFFh--0FFC0h
0FFFFh--0F800h
256 Byte
010FFh -- 01000h
128 Byte
027Fh -- 0200h
01FFh -- 0100h
0FFh -- 010h
0Fh -- 00h
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A to D can be erased individually, or as a group with segments 0 --n.
Segments A to D are also called information memory.
D Segment A contains calibration data. After reset segment A is protected against programming and erasing.
It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data
is required.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
15
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, refer to the MSP430x2xx Family User’s Guide.
oscillator and system clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very-low-power low-frequency oscillator and an internal digitally-controlled oscillator
(DCO). The basic clock module is designed to meet the requirements of both low system cost and low power
consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 μs. The basic
clock module provides the following clock signals:
D Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.
D Main clock (MCLK), the system clock used by the CPU.
D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
DCO Calibration Data (provided from factory in flash info memory segment A)
DCO Frequency Calibration Register Size Address
1MHz
8MHz
12 MHz
16 MHz
CALBC1_1MHZ byte
CALDCO_1MHZ byte
CALBC1_8MHZ byte
CALDCO_8MHZ byte
CALBC1_12MHZ byte
CALDCO_12MHZ byte
CALBC1_16MHZ byte
CALDCO_16MHZ byte
010FFh
010FEh
010FDh
010FCh
010FBh
010FAh
010F9h
010F8h
brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off.
digital I/O
There is one 8-bit I/O port implemented—port P1—and two bits of I/O port P2:
D All individual I/O bits are independently programmable.
D Any combination of input, output, and interrupt condition is possible.
D Edge-selectable interrupt input capability for all the eight bits of port P1 and the two bits of port P2.
D Read/write access to port-control registers is supported by all instructions.
D Each I/O has an individually programmable pull-up/pull-down resistor.
WDT+ watchdog timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be disabled or configured as an interval timer and can
generate interrupts at selected time intervals.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
A
A
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
timer_A2
Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities.
Interrupts may be generated from the c ounter on overflow conditions and from each of the capture/compare
registers.
Timer_A2 Signal Connections (MSP43020x1 only)
Input
Pin Number
PW, N RSA PW, N RSA
2-P1.0 1-P1.0 TACLK TAC L K
2-P1.0 1-P1.0 TACLK INCLK
3-P1.1 2-P1.1 TA0 CCI0A
4-P1.2 3-P1.2 TA1 CCI1A
Device
Input Signal
ACLK ACLK
SMCLK SMCLK
ACLK (internal) CCI0B
V
SS
V
CC
CAOUT (internal) CCI1B
V
SS
V
CC
Module
Input Name
GND
V
CC
GND
V
CC
Module
Block
Timer N
CCR0 TA0
CCR1 TA1
Module
Output Signal
Output
Pin Number
3-P1.1 2-P1.1
7-P1.5 6-P1.5
4-P1.2 3-P1.2
8-P1.6 7-P1.6
13 - P2.6 12 - P2.6
Timer_A2 Signal Connections (MSP430F20x2, MSP430F20x3)
Input
Pin Number
PW, N RSA PW, N RSA
2-P1.0 1-P1.0 TACLK TAC L K
2-P1.0 1-P1.0 TACLK INCLK
3-P1.1 2-P1.1 TA0 CCI0A
7-P1.5 6-P1.5 ACLK (internal) CCI0B
4-P1.2 3-P1.2 TA1 CCI1A
8-P1.6 7-P1.6 TA1 CCI1B
Device
Input Signal
ACLK ACLK
SMCLK SMCLK
V
SS
V
CC
V
SS
V
CC
Module
Input Name
GND
V
CC
GND
V
CC
Module
Block
Timer N
CCR0 TA0
CCR1 TA1
Module
Output Signal
Output
Pin Number
3-P1.1 2-P1.1
7-P1.5 6-P1.5
4-P1.2 3-P1.2
8-P1.6 7-P1.6
13 - P2.6 12 - P2.6
comparator_A+ (MSP430x20x1 only)
The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
17
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
USI (MSP430x20x2 and MSP430x20x3 only)
The universal serial interface (USI) module is used for serial data communication and provides the basic
hardware for synchronous communication protocols like SPI and I2C.
ADC10 (MSP430x20x2 only)
The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion
result handling, allowing ADC samples to be converted and stored without any CPU intervention.
SD16_A (MSP430x20x3 only)
The SD16_A module supports 16-bit analog-to-digital conversions. The module implements a 16-bit
sigma-delta core and reference generator. In addition to external analog inputs, internal V
temperature sensors are also available.
CC
sense and
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map
ADC10 (MSP430x20x2 only) ADC control 0
SD16_A (MSP430x20x3 only) General Control
Timer_A Capture/compare register
Flash Memory Flash control 3
Watchdog Timer+ Watchdog/timer control WDTCTL 0120h
ADC10 (MSP430x20x2 only) Analog enable ADC10AE 04Ah
SD16_A (MSP430x20x3 only) Channel 0 Input Control
USI
(MSP430x20x2 and
MSP430x20x3 only)
Comparator_A+
(MSP430x20x1 only)
Basic Clock System+ Basic clock system control 3
Port P2 Port P2 resistor enable
Port P1 Port P1 resistor enable
Special Function SFR interrupt flag 2
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
PERIPHERALS WITH WORD ACCESS
ADC control 1
ADC memory
Channel 0 Control
Interrupt vector word register
Channel 0 conversion memory
Capture/compare register
Timer_A register
Capture/compare control
Capture/compare control
Timer_A control
Timer_A interrupt vector
Flash control 2
Flash control 1
PERIPHERALS WITH BYTE ACCESS
Analog Enable
USI control 0
USI control 1
USI clock control
USI bit counter
USI shift register
Comparator_A+ port disable
Comparator_A+ control 2
Comparator_A+ control 1
Basic clock system control 2
Basic clock system control 1
DCO clock frequency control
Port P2 selection
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt flag
Port P2 direction
Port P2 output
Port P2 input
Port P1 selection
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt flag
Port P1 direction
Port P1 output
Port P1 input
SFR interrupt flag 1
SFR interrupt enable 2
SFR interrupt enable 1
ADC10CTL0
ADC10CTL0
ADC10MEM
SD16CTL
SD16CCTL0
SD16IV
SD16MEM0
TACCR1
TACCR0
TAR
TACCTL1
TACCTL0
TAC T L
TAI V
FCTL3
FCTL2
FCTL1
SD16INCTL0
SD16AE
USICTL0
USICTL1
USICKCTL
USICNT
USISR
CAPD
CACTL2
CACTL1
BCSCTL3
BCSCTL2
BCSCTL1
DCOCTL
P2REN
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
P1REN
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
IFG2
IFG1
IE2
IE1
01B0h
01B2h
01B4h
0100h
0102h
0110h
0112h
0174h
0172h
0170h
0164h
0162h
0160h
012Eh
012Ch
012Ah
0128h
0B0h
0B7h
078h
079h
07Ah
07Bh
07Ch
05Bh
05Ah
059h
053h
058h
057h
056h
02Fh
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
027h
026h
025h
024h
023h
022h
021h
020h
003h
002h
001h
000h
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
19
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
absolute maximum ratings
Voltage applied at VCCto V
Voltage applied to any pin (see Note 2) --0.3 V to V
†
SS
--0.3 V to 4.1 V......................................................
+0.3 V........................................
CC
Diode current at any device terminal ±2mA.......................................................
Storage temperature, T
Storage temperature, T
NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
2. All voltages referenced to V
is applied to the TEST pin when blowing the JTAG fuse.
3. Higher temperature may be applied during board soldering process according to the current JEDEC J--STD--020 specification with
peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
(unprogrammed device, see Note 3) --55°C to 150°C........................
stg
(programmed device, see Note 3) --40°Cto85°C...........................
stg
. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage
SS
recommended operating conditions
MIN NOM MAX UNITS
Supply voltage during program execution, V
Supply voltage during program/erase flash memory, V
Supply voltage, V
Operatingfree-air temperature range, T
Processor frequency f
NOTES: 1. The MSP430 CPU is clocked directly with MCLK.
SS
(Maximum MCLK frequency)
SYSTEM
Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency.
2. Modules might have a different maximum input clock specification. Refer to the specification of the respective module in this data
sheet.
CC
CC
A
I Version -- 4 0 85 °C
T Version -- 4 0 105 °C
VCC=1.8V,
Duty Cycle = 50% ±10%
VCC=2.7V,
Duty Cycle = 50% ±10%
VCC≥ 3.3 V,
Duty Cycle = 50% ±10%
1.8 3.6 V
2.2 3.6 V
0 V
dc 6
dc 12
dc 16
MHz
16 MHz
12 MHz
6MHz
System Frequency -- MHz
1.8 V 2.2 V 2.7 V 3.3 V 3.6 V
Supply Voltage --V
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum V
Legend:
Supply voltage range,
during flash memory
programming
Supply voltage range,
during program execution
Figure 1. Save Operating Area
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CC
of 2.2 V.
MSP430x20x1, MSP430x20x2, MSP430x20x3
A
(
AM)
Activemode(AM
)
A
A
A
(
AM)
Activemode(AM
)
A
A
f
,
A
(
AM)
f
A
CLK
=32,768Hz/8=4,096Hz
g
Activemode(AM
)
Programexecutesinflas
h
ADIVMxDIVSxDIVAx11,
A
(
AM)
f
f
Activemode(AM
)
Programexecutesinflas
h
A
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
active mode supply current (into VCC) excluding external current (see Notes 1 and 2)
I
AM, 1MHz
I
AM, 1MHz
I
AM, 4kHz
I
AM,100kHz
PARAMETER TEST CONDITIONS T
ctive mode
current (1MHz)
f
DCO=fMCLK=fSMCLK
f
= 32,768Hz,
ACLK
Program executes in flash,
BCSCTL1 = C
DCOCTL = CALDCO_1MHZ,
=1MHz,
LBC1_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
ctive mode
current (1MHz)
f
DCO=fMCLK=fSMCLK
f
= 32,768Hz,
ACLK
Program executes in RAM,
BCSCTL1 = C
DCOCTL = CALDCO_1MHZ,
=1MHz,
LBC1_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
ctive mode
current (4kHz)
ctive mode
current (100kHz)
f
MCLK=fSMCLK
=32,768Hz/8=4,096Hz
f
=0Hz,
DCO
Pro
ram executes inflash,
SELMx = 11, SELS = 1,
DIVMx = DIVSx = DIVAx = 11,
CPUOFF = 0, SCG0 = 1, SCG1 = 0,
OSCOFF = 0
f
MCLK=fSMCLK=fDCO(0, 0)
=0Hz,
ACLK
Program executes in
RSELx = 0, DCOx = 0,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 1
=
,
,
-40--85°C 2.2 V 1.2 3
105°C 2.2 V 6
-40--85°C 3V 1.6 4
105°C 3V 7
lash,
≈ 100kHz,
,
-40--85°C 2.2 V 37 50
105°C 2.2 V 60
-40--85°C 3V 40 55
105°C 3V 65
A
VCC MIN TYP MAX UNIT
2.2 V 220 270
μ
3V 300 370
2.2 V 190
μ
3V 260
μ
μ
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
2. The currents are characterized with a Micro Crystal CC4V--T1A SMD crystal with a load capacitance of 9 pF.
The internal and external load capacitance is chosen to closely match the required 9pF.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
21
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- active mode supply current (into VCC)
5.0
f
=16MHz
=12MHz
DCO
f
DCO
=1MHz
4.0
3.0
f
DCO
2.0
Active Mode Current -- mA
1.0
0.0
1.5 2.0 2.5 3.0 3.5 4.0
f
=8MHz
DCO
VCC-- Supply Voltage -- V
Figure 2. Active mode current vs VCC,TA=25°C
4.0
3.0
2.0
Active Mode Current -- mA
1.0
0.0
0.0 4.0 8.0 12.0 16.0
VCC=3V
TA=85°C
TA=25°C
VCC=2.2V
f
-- DCO Frequency -- MHz
DCO
TA=85°C
TA=25°C
Figure 3. Active mode current vs DCO frequency
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
A
A
f
A
CLK
f
ACL
K
=0H
z
A
f
1MH
V
A
A
_
V
V
A
L
(
f
f
f
0MH
f
3(LPM3)curren
t
f
ACL
K
=32,768Hz
V
A
V
A
L
(
)
f
f
f
0MH
f
f
(
VLO)
3curren
t,(LPM3
)
f
ACL
K
frominternalLFoscillator(VLO)
V
A
f
f
f
0MH
f
f
ACL
K
=0H
z
V
/
AseeNote5
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
low power mode supply currents (into VCC) excluding external current (see Notes 1 and 2)
I
LPM0, 1MHz
I
LPM0, 100kHz
I
LPM2
I
LPM3,LFXT1
I
LPM3,VLO
I
LPM4
PARAMETER TEST CONDITIONS T
f
=0MHz,
MCLK
Low-power mode
0 (LPM0) current,
seeNote3
f
SMCLK=fDCO
f
= 32,768 Hz,
ACLK
BCSCTL1 = C
DCOCTL = CALDCO_1MHZ,
=1MHz,
LBC1_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
f
=0MHz,
MCLK
Low-power mode
0 (LPM0) current,
seeNote3
f
SMCLK=fDCO(0, 0)
=0Hz,
RSELx = 0, DCOx = 0,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
≈ 100 kHz,
,
OSCOFF = 1
Low-power mode
2 (LPM2) current,
seeNote4
f
MCLK=fSMCLK
=
DCO
f
= 32,768 Hz,
ACLK
BCSCTL1 = C
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
=0MHz,
z,
LBC1_1MHZ,
-40--85°C
105°C
-40--85°C
105°C
-40°C 0.7 1.2
25°C
ow-power mode
3
LPM3)current,
seeNote4
=
DCO
,
=
MCLK
= 32,768 Hz,
SMCLK
,
=
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
z,
85°C
105°C 3 6
-40°C 0.9 1.2
25°C
85°C
105°C 3 7
-40°C 0.4 0.7
25°C
ow-power mode
3 current,
LPM3
seeNote4
=
DCO
MCLK
=
SMCLK
=
z,
rom internal LF oscillator
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
85°C
105°C 2 5
,
,
-40°C 0.5 0.9
25°C
85°C
105°C 2.5 6
-40°C 0.1 0.5
25°C
85°C
105°C 2 4
Low-power mode
4 (LPM4) current,
seeNote5
=
DCO
MCLK
=0Hz,
=
,
SMCLK
=
z,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
A
VCC MIN TYP MAX UNIT
2.2 V 65 80
3V 85 100
2.2 V 37 48
3V 41 52
22 29
2.2
31
25 32
3
34
0.7 1.0
1.4 2.3
0.9 1.2
1.6 2.8
0.5 0.7
1.0 1.6
0.6 0.9
1.3 1.8
0.1 0.5
0.8 1.5
2.2
2.2
3
2.2
3
3V
μ
μ
μ
μ
μ
μ
μ
μ
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
2. The currents are characterized with a Micro Crystal CC4V--T1A SMD crystal with a load capacitance of 9 pF.
The internal and external load capacitance is chosen to closely match the required 9pF.
3. Current for brownout and WDT clocked by SMCLK included.
4. Current for brownout and WDT clocked by ACLK included.
5. Current for brownout included.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
23
MSP430x20x1, MSP430x20x2, MSP430x20x3
V
IT+
l
t
V
V
I
T
l
t
V
Inputvoltagehysteresis(
V
I
T
V
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Schmitt-trigger inputs -- Ports P1 and P2
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
V
IT+
Positive-going input threshold
vo
age
2.2 V 1.00 1.65
3V 1.35 2.25
0.25 0.55 V
0.45 0.75 V
V
IT--
--
Negative-going input threshold
vo
age
2.2 V 0.55 1.20
3V 0.75 1.65
V
hys
R
Pull
C
I
Input voltagehysteresis(V
V
)
IT--
Pull-up/pull-down resistor
Input Capacitance VIN=VSSor V
--
+
For pullup: VIN=VSS;
For pulldown: V
IN=VCC
CC
2.2 V 0.2 1.0
3V 0.3 1.0
20 35 50 kΩ
inputs -- Ports P1 and P2
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Port P1, P2: P1.x to P2.x, External
t
(int)
External interrupt timing
trigger pulse width to set interrupt
2.2 V/3 V 20 ns
flag, (see Note 1)
NOTES: 1. An external signal sets the interrupt flag every time the minimum interrupt puls width t
shorter than t
(int)
.
is met. It may be set even with trigger signals
(int)
leakage current -- Ports P1 and P2
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
I
lkg(Px.x)
NOTES: 1. The leakage current is measured with VSSor VCCapplied to the corresponding pin(s), unless otherwise noted.
High-impedance leakage current see Notes 1 and 2 2.2 V/3 V ±50 nA
2. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pull-up/pull-down resistor is
disabled.
5 pF
CC
CC
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
Highleveloutput
V
Lowleveloutpu
t
V
y
f
Portoutputfrequency
P
1.4/SMCLK,CL=20pF,RL=1kOh
m
/
A
f
P
2.0/ACL
K,P
1.4/SMCLK,CL=20pF
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
outputs -- Ports P1 and P2
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
I
V
OH
High-level output
voltage
I
I
I
I
V
OL
Low-level output
voltage
I
I
I
NOTES: 1. The maximum total current, I
OHmax
voltage drop specified.
2. The maximum total current, I
OHmax
voltage drop specified.
output frequency -- Ports P1 and P2
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Px.y
Port_CLK
Port outputfrequenc
(with load)
Clock outputfrequency
NOTES: 1. A resistive divider with 2 times 0.5 kΩ between VCCand VSSis used as load. The output is connected to the center tap of the divider.
2. The output voltage reaches at least 10% and 90% V
P1.4/SMCLK, C
(see Note 1 and 2)
P2.0
(see Note 2)
= --1.5 mA (see Notes 1) 2.2 V VCC--0.25 V
(OHmax)
=--6mA(seeNotes2) 2.2 V VCC-- 0 . 6 V
(OHmax)
= --1.5 mA (see Notes 1) 3V VCC--0.25 V
(OHmax)
=--6mA(seeNotes2) 3V VCC-- 0 . 6 V
(OHmax)
= 1.5 mA (see Notes 1) 2.2 V V
(OLmax)
=6mA(seeNotes2) 2.2 V V
(OLmax)
= 1.5 mA (see Notes 1) 3V V
(OLmax)
=6mA(seeNotes2) 3V V
(OLmax)
and I
and I
, for all outputs combined, should not exceed ±12 mA to hold the maximum
OLmax
, for all outputs combined, should not exceed ±48 mA to hold the maximum
OLmax
=20pF, R
=1kOhm
2.2 V 10 MHz
SS
SS
SS
SS
3V 12 MHz
CLK, P1.4/SMCLK, C
=20pF
2.2 V 12 MHz
3V 16 MHz
at the specified toggle frequency.
CC
CC
CC
CC
CC
VSS+0.25
VSS+0.6
VSS+0.25
VSS+0.6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
25
MSP430x20x1, MSP430x20x2, MSP430x20x3
A
A
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- outputs
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
30.0
VCC=2.2V
P1.7
5.0
0.0
0.0 0.5 1.0 1.5 2.0 2.5
VOL-- Low-Level Output Voltage -- V
I -- Typical Low-Level Output Current -- m
25.0
20.0
15.0
10.0
OL
Figure 4
TA=25°C
TA=85°C
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50.0
VCC=3V
P1.7
40.0
30.0
20.0
10.0
OL
I -- Typical Low-Level Output Current -- mA
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VOL-- Low-Level Output Voltage -- V
Figure 5
TA=25°C
TA=85°C
TYPICAL HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
0.0
VCC=2.2V
P1.7
-- 5 . 0
--10.0
--15.0
TA=85°C
--20.0
OH
I -- Typical High-Level Output Current -- m
--25.0
TA=25°C
0.0 0.5 1.0 1.5 2.0 2.5
VOH-- High-Level Output Voltage -- V
Figure 6
NOTE: One output loaded at a time.
vs
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0.0
VCC=3V
P1.7
--10.0
--20.0
--30.0
TA=85°C
--40.0
OH
I -- Typical High-Level Output Current -- mA
--50.0
TA=25°C
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VOH-- High-Level Output Voltage -- V
Figure 7
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x20x1, MSP430x20x2, MSP430x20x3
MIXED SIGNAL MICROCONTROLLER
SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
POR/brownout reset (BOR) (see Notes 1 and 2)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
V
CC(start)
V
(B_IT--)
V
hys(B_IT--)
t
d(BOR)
t
(reset)
NOTES: 1. The current consumption of the brownout module i s already included in the ICCcurrent consumption data. The voltage level V
(see Figure 8) dVCC/dt ≤ 3V/s 0.7 × V
(B_IT--)
(see Figure 8 through Figure 10) dVCC/dt ≤ 3V/s 1.71 V
(see Figure 8) dVCC/dt ≤ 3V/s 70 130 210 mV
(see Figure 8) 2000 μs
Pulse length needed at RST/NMI pin
to accepted reset internally
+V
hys(B_IT--)
is ≤ 1.8V.
2. During power up, the CPU begins code execution following a period of t
DCO settings must not be changed until V
CC
≥ V
CC(min)
, where V
CC(min)
d(BOR)
is the minimum supply voltage for the desired
2.2 V/3 V 2 μs
after VCC=V
(B_IT--)+Vhys(B_IT--)
operating frequency.
V
CC
V
hys(B_IT--)
V
(B_IT--)
. The default
V
CC(start)
V
(B_IT--)
1
0
t
d(BOR)
Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
27
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