Texas Instruments MSP430P337IPJM, MSP-EVK430X330, MSP-EVK430B330 Datasheet
MSP430x33x
MIXED SIGNAL MICROCONTROLLERS
SLAS163 – FEBRUARY 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Low Supply Voltage Range 2.5 V – 5.5 V
D
Low Operation Current, 400 mA at 1 MHz,
3 V
D
Ultra-Low Power Consumption (Standby
Mode Down to 0.1 µA)
D
Five Power-Saving Modes
D
Wake Up from Standby Mode in 6 µS
D
16-Bit RISC Architecture, 300 ns Instruction
Cycle Time
D
Single Common 32 kHz Crystal, Internal
System Clock up to 3.8 MHz
D
Integrated LCD Driver for up to 120
Segments
D
Integrated Hardware Multiplier Performs
Signed, Unsigned, and MAC Operations for
Operands Up to 16 X 16 Bits
D
Serial Communication Interface (USART),
Select Asynchronous UART or
Synchronous SPI by Software
D
Slope A/D Converter Using External
Components
D
16-Bit Timer With Five Capture/Compare
Registers
D
Programmable Code Protection by Security
Fuse
D
Family Members Include:
MSP430C336 – 24 KB ROM, 1 KB RAM
MSP430C337 – 32 KB ROM, 1 KB RAM
MSP430P337 – 32 KB OTP, 1 KB RAM
D
EPROM Version Available for Prototyping:
PMS430E337
D
Serial On-Board Programming
D
Available in 100 Pin Quad Flat-Pack (QFP)
Package, 100 Pin Ceramic Quad Flat-Pack
(CFP) package (EPROM Version)
description
The T exas Instruments MSP430 series is a ultra low-power microcontroller family consisting of several devices
which features different sets of modules targeted to various applications. The controller is designed to be battery
operated for an extended application lifetime. With the 16-bit RISC architecture, 16 integrated registers on the
CPU, and the constant generator, the MSP430 achieves maximum code efficiency. The digital-controlled
oscillator, together with the frequency lock loop (FLL), provides a fast wake up from a low-power mode to an
active mode in less than 6 ms. The MSP430x33x series micro-controllers have built in hardware multiplication
and communication capability using asynchronous (UART) and synchronous protocols.
Typical applications of the MSP430 family include electronic gas, water, and electric meters and other sensor
systems that capture analog signals, converts them to digital values, processes, displays, or transmits them to
a host system.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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24
25
81
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50
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46
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44
43
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40
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38
37
36
35
34
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32
31
NC
S22/O22
S21/O21
S19/O19
S17/O17
S16/O16
S15/O15
S14/O14
S13/O13
S12/O12
S11/O11
S10/O10
S9/O9
S7/07
S8/O8
S4/O4
S3/O3
S2/O2
S1
S0
COM0
TP0.0
TP0.1
TP0.2
TP0.3
TP0.4
TP0.5
P0.0
P0.2/TXD
P0.3
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.6
P1.7
Xin
Xout/TCLK
RST/NMI
TCK
TMS
TDI/VPP
TDO/TDI
R13
S27/O27
S26/O26
S25/O25
S24/O24
S23/O23
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.3/TA0
P3.4/TA1
P3.6/TA3
P3.7/TA4
P4.0
P4.1
P4.2/STE
P4.4/SOMI
P4.5/UCLK
V
SS3
P4.3/SIMO
PJM or HFD PACKAGE
(TOP VIEW)
CIN
S29/O29/CMPI
R33
R23
S20/O20
S5/O5
P3.5/TA2
P0.1/RXD
P1.5
26
27
28
29
30
55
54
53
52
51
P2.1
P2.2
NC
COM1
COM2
COM3
P4.7/URXD
S28/O28
XBUF
V
CC1
P0.4
P2.0
V
SS2
V
CC2
P3.2/TACLK
P4.6/UTXD
S18/O18
S6/O6
SS1
V
R03
NC – No internal connection
Copyright 1998, Texas Instruments Incorporated
MSP430x33x
MIXED SIGNAL MICROCONTROLLER
SLAS163 – FEBRUARY 1998
Template Release Date: 7–11–94
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
PLASTIC
QFP
(PJM)
CERAMIC
QFP
(HFD)
°
°
MSP430C336IPJM
–
40°C to 85°C
MSP430C337IPJM
MSP430P337IPJM
—
°
25°C
—
PMS430E337HFD
functional block diagram
Oscillator
FLL
System Clock
ACLK
MCLK
24/32 kB ROM
32 kB OPT or
1024B
RAM
SRAM
Power-on-
Reset
I/O Port
1x8 Digital
I/O’s
I/O Port
2x8 I/O’s All
Interr. Cap.
8 8
2 Int. Vectors
I/O Port
1x8 Digital
I/O’s
I/O Port
8 I/O’s, All With
Interr. Cap.
3 Int. Vectors
CPU
Incl. 16 Reg.
Test
JTAG
Bus
Conv
USART
UART or
8 Bit Timer/Port
Applications
Timer, O/P
Basic
LCD
120 Segments
1, 2, 3, 4 MUX
SPI Function
Timer/Counter
Timer1
MPY
Watchdog TimerA
MPYS
timer
MAC
16x16 Bit
8x8 Bit
15/16 Bit
16 Bit
PWM
MAB, 16 Bit
MDB, 16 Bit
MAB, 4 Bit
MDB, 8 Bit
MCB
TACLK
TA0–4
UTXD
URXD
UCLK
STE
SIMO
SOMI
TXD RXD
6
LCD
f
CMPI
TP0.0–0.5
CIN
XIN XOut XBUF
V
CC1VCC2VSS1VSS2
RST/NMI P4.0 P4.7 P2.x P1.x P3.0 P3.7 P0.0 P0.7
Com0–3
S0–28/O2–28
S29/O29/CMPI
R03
R13
R23
R33
TDI
TDO
TMS
TCK
USART TimerA RXD,
TXD
A/D Conv.
EPROM
C: ROM
P: OTP
E: EPROM
Multiplier
MSP430x33x
MIXED SIGNAL MICROCONTROLLERS
SLAS163 – FEBRUARY 1998
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
CIN 2 I Input port. CIN is used as an enable for counter TPCNT1 – timer/port
COM0–3 56–53 O Common outputs. COMM0-3 are used for LCD backplanes – LCD
P0.0 9 I/O General purpose digital I/O
P0.1/RXD 10 I/O General purpose digital I/O, receive digital Input port – 8-bit timer/counter
P0.2/TXD 11 I/O General purpose digital I/O, transmit data output port – 8-bit timer/counter
P0.3–P0.7 12–16 I/O Five general purpose digital I/Os, bit 3-7
P1.0–P1.7 17–24 I/O Eight general purpose digital I/Os, bit 0-7
P2.0–P2.7 25–27,
31–35
I/O Eight general purpose digital I/Os, bit 0-7
P3.0, P3.1 36,37 I/O Two general purpose digital I/Os, bit 0 and bit 1
P3.2/TACLK 38 I/O General purpose digital I/O, clock input – timer A
P3.3/TA0 39 I/O General purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR0
P3.4/TA1 40 I/O General purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR1
P3.5/TA2 41 I/O General purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR2
P3.6/TA3 42 I/O General purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR3
P3.7/TA4 43 I/O General purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR4
P4.0 44 I/O General purpose digital I/O, bit 0
P4.1 45 I/O General purpose digital I/O, bit 1
P4.2/STE 46 I/O General purpose digital I/O, slave transmit enable – USART/SPI mode
P4.3/SIMO 47 I/O General purpose digital I/O, slave in/master out – USART/SPI mode
P4.4/SOMI 48 I/O General purpose digital I/O, master in/slave out – USART/SPI mode
P4.5/UCLK 49 I/O General purpose digital I/O, external clock input – USART
P4.6/UTXD 50 I/O General purpose digital I/O, transmit data out – USART/UART mode
P4.7/URXD 51 I/O General purpose digital I/O, receive data in – USART/UART mode
R03 88 I Input port of fourth positive (lowest) analog LCD level (V5) – LCD
R13 89 I Input port of third most positive analog LCD level (V3 of V4) – LCD
R23 90 I Input port of second most positive analog LCD level (V2) – LCD
R33 91 O Output of most positive analog LCD level (V1) – LCD
RST/NMI 96 I Reset input or non-maskable interrupt input port
S0 57 O Segment line S0 – LCD
S1 58 O Segment line S1 – LCD
S2/O2–S5/O5 59–62 O Segment lines S2 to S5 or digital output ports, O2-O5, group 1 – LCD
S6/O6–S9/O9 63–66 O Segment lines S6 to S9 or digital output ports O6-O9, group 2 – LCD
S10/O10–S13/O13 67–70 O Segment lines S10 to S13 or digital output ports O10-O13, group 3 – LCD
S14/O14–S17/O17 71–74 O Segment lines S14 to S17 or digital output ports O14-O17, group 4 – LCD
S18/O18–S21/O21 75–78 O Segment lines S18 to S21 or digital output ports O18-O21, group 5 – LCD
S22/O22–S25/O25 79, 81–83 O Segment line S22 to S25 or digital output ports O22-O25, group 6 – LCD
S26/O26–S29/O29/CMPI 84–87 O Segment line S26 to S29 or digital output ports O26-O29, group 7 – LCD. Segment line S29
can be used as comparator input port CMPI – timer/port
TCK 95 I Test clock. TCK is the clock input port for device programming and test
TDI/VPP 93 I Test data input. TDI/VPP is used as a data input port or input for programming voltage
MSP430x33x
MIXED SIGNAL MICROCONTROLLERS
SLAS163 – FEBRUARY 1998
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
TMS 94 I Test mode select. TMS is used as an input port for device programming and test
TDO/TDI 92 I/O Test data output port. TDO/TDI data output or programming data input terminal
TP0.0 3 O General purpose 3–state digital output port, bit 0 – timer/port
TP0.1 4 O General purpose 3–state digital output port, bit 1 – timer/port
TP0.2 5 O General purpose 3–state digital output port, bit 2 – timer/port
TP0.3 6 O General purpose 3–state digital output port, bit 3 – timer/port
TP0.4 7 O General purpose 3–state digital output port, bit 4 – timer/port
TP0.5 8 I/O General purpose 3–state digital input/output port, bit 5 – timer/port
VCC1 1 Positive supply voltage
VCC2 29 Positive supply voltage
VSS1 100 Ground reference
VSS2 28 Ground reference
VSS3 52 Ground reference
XBUF 97 O System clock (MCLK) or crystal clock (ACLK) output
Xin 99 I Input port for crystal oscillator
Xout/TCLK 98 I/O Output terminal of crystal oscillator or test clock input
short-form description
processing unit
The processing unit is based on a consistent and orthogonal designed CPU and instruction set. This design
structure results in a RISC-like architecture, highly transparent to the application development and is
distinguished due to ease of programming. All operations, other than program-flow instructions consequently
are performed as register operations in conjunction with seven addressing modes for source and four modes
for destination operand.
cpu registers
Sixteen registers are located inside the CPU,
providing reduced instruction execution time. This
reduces a register-register operation execution
time to one cycle of the processor frequency.
Four of the registers are reserved for special use
as a program counter, a stack pointer, a status
register and a constant generator. The remaining
registers are available as general purpose
registers.
Peripherals are connected to the CPU using a
data address and control bus and can be handled
easily with all instructions for memory manipulation.
Program Counter
General Purpose Register
PC/R0
Stack Pointer
SP/R1
Status Register
SR/CG1/R2
Constant Generator
CG2/R3
R4
General Purpose Register
R5
General Purpose Register R14
General Purpose Register
R15
MSP430x33x
MIXED SIGNAL MICROCONTROLLERS
SLAS163 – FEBRUARY 1998
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
instruction set
The instruction set for this register-register architecture provides a powerful and easy-to-use assembly
language. The instruction set consists of 52 instructions, with three formats and seven addressing modes.
T able 1 provides a summation and example of the three types of instruction formats; the addressing modes are
listed in Table 2.
Table 1. Instruction Word Formats
Dual operands, source–destination e.g. ADD R4,R5 R4 + R5 → R5
Single operands, destination only e.g. CALL R8 PC → (TOS), SR → (TOS), R8→ PC
Relative jump, un–/conditional e.g. JNE Jump-on equal bit = 0
Instructions that can operate on both word and byte data are differentiated by the suffix ’.B’ when a byte
operation is required.
Examples: Instructions for word operation: Instructions for byte operation:
MOV ede,toni MOV.B ede,toni
ADD #235h,&MEM ADD.B #35h,&MEM
PUSH R5 PUSH.B R5
SWPB R5 –––
Table 2. Address Mode Descriptions
ADDRESS MODE S D SYNTAX EXAMPLE OPERATION
register √ √ MOV Rs,Rd MOV R10,R11 R10 → R11
indexed √ √ MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) → M(6+R6)
symbolic (PC relative) √ √ MOV EDE,TONI M(EDE) → M(TONI)
absolute √ √ MOV &MEM,&TCDAT M(MEM) → M(TCDAT)
indirect √ MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) → M(Tab+R6)
indirect autoincrement √ MOV @Rn+,Rm MOV @R10+,R11 M(R10) → R11
R10 + 2
→ R10
immediate √ MOV #X,T ONI MOV #45,TONI #45 → M(TONI)
NOTE 1: S = source, D = destination.
Computed branches (BR) and subroutine calls (CALL) instructions use the same addressing modes as the other
instructions. These addressing modes provide
indirect
addressing, ideally suited for computed branches and
calls. The full use of this programming capability permits a program structure different from conventional 8- and
16-bit controllers. For example, numerous routines can easily be designed to deal with pointers and stacks
instead of using Flag type programs for flow control.
MSP430x33x
MIXED SIGNAL MICROCONTROLLERS
SLAS163 – FEBRUARY 1998
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operation modes and interrupts
The MSP430 operating modes support various advanced requirements for ultra-low power and ultra-low energy
consumption. This is achieved by the intelligent management of the operations during the different module
operation modes and CPU states. The requirements are fully supported during interrupt event handling. An
interrupt event awakens the system from each of the various operating modes and returns with the RETI
instruction to the mode that was selected before the interrupt event. The clocks used are ACLK and MCLK.
ACLK is the crystal frequency and MCLK is a multiple of ACLK and is used as the system clock.
The following five operating modes are supported:
D
Active mode (AM). The CPU is enabled with different combinations of active peripheral modules.
D
Low power mode 0 (LPM0). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals
are active, and loop control for MCLK is active.
D
Low power mode 1 (LPM1). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals
are active, and loop control for MCLK is inactive.
D
Low power mode 2 (LMP2). The CPU is disabled, peripheral operation continues, ACLK signal is active,
and MCLK and loop control for MCLK are inactive.
D
Low power mode 3 (LMP3). The CPU is disabled, peripheral operation continues, ACLK signal is active,
MCLK and loop control for MCLK are inactive, and the dc generator for the digital controlled oscillator (DCO)
(³MCLK generator) is switched off.
D
Low power mode 4 (LMP4). The CPU is disabled, peripheral operation continues, ACLK signal is inactive
(crystal oscillator stopped), MCLK and loop control for MCLK are inactive, and the dc generator for the DCO
is switched off.
The special function registers (SFR) include module-enable bits that stop or enable the operation of the specific
peripheral module. All registers of the peripherals may be accessed if the operational function is stopped or
enabled. However, some peripheral current-saving functions are accessed through the state of local register
bits. An example is the enable/disable of the analog voltage generator in the LCD peripheral which is turned
on or off using one register bit.
The most general bits that influence current consumption and support fast turn-on from low power operating
modes are located in the status register (SR). Four of these bits control the CPU and the system clock generator:
SCG1, SCG0, OscOff, and CPUOff.
Reserved For Future
Enhancements
15 9 8 7 0
V SCG1 SCG0 OscOff CPUOff GIE N Z C
rw-0
interrupts
Software determines the activation of interrupts through the monitoring of hardware set interrupt flag status bits,
the control of specific interrupt enable bits in SRs, the establishment of interrupt vectors, and the programming
of interrupt handlers. The interrupt vectors and the power-up starting address are located in ROM address
locations 0FFFFh through 0FFE0h. Each vector contains the 16-bit address of the appropriate interrupt handler
instruction sequence. Table 3 provides a summation of interrupt functions and addresses.
MSP430x33x
MIXED SIGNAL MICROCONTROLLERS
SLAS163 – FEBRUARY 1998
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Table 3. Interrupt Functions and Addresses
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
Power-up, external reset, Watchdog WDTIFG Reset 0FFFEh 15, highest
NMI,
Oscillator fault
NMIIFG (see Note 2)
OFIFG (see Note 2)
non-maskable
(non)-maskable
0FFFCh 14
Dedicated I/O P0IFG.0 maskable 0FFFAh 13
Dedicated I/O P0IFG.1 maskable 0FFF8h 12
maskable 0FFF6h 11
Watchdog timer WDTIFG maskable 0FFF4h 10
Timer_A CCIFG0 (see Note 3) maskable 0FFF2h 9
Timer_A TAIFG (see Note 3) maskable 0FFF0h 8
UART Receive URXIFG maskable 0FFEEh 7
UART Transmit UTXIFG maskable 0FFECh 6
0FFEAh 5
Timer/Port See Note 3 maskable 0FFE8h 4
I/O Port P2 P2IFG.07 (see Note 2) maskable 0FFE6h 3
I/O Port P1 P1IFG.07 (see Note 2) maskable 0FFE4h 2
Basic Timer BTIFG maskable 0FFE2h 1
I/O Port P0 P0IFG.27 (see Note 2) maskable 0FFE0h 0, lowest
NOTES: 2. Multiple source flags
3. Interrupt flags are located in the module
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple SW access is
provided with this arrangement.
interrupt enable 1 and 2
7654 0
P0IE.1 OFIE WDTIE
321
P0IE.0
rw-0 rw-0 rw-0 rw-0
Address
0h
WDTIE: Watchdog timer interrupt enable signal
OFIE: Oscillator fault interrupt enable signal
P0IE.0: Dedicated I/O P0.0 interrupt enable signal
P0IE.1: P0.1 or 8-bit timer/counter, RXD interrupt enable signal
7654 0
TPIE UTXIE URXIE
rw-0
321
rw-0 rw-0 rw-0
Address
01h BTIE
URXIE: USART receive interrupt enable signal
UTXIE: USART transmit interrupt enable signal
TPIE: Timer/Port interrupt enable signal
BTIE: Basic Timer interrupt enable signal
MSP430x33x
MIXED SIGNAL MICROCONTROLLERS
SLAS163 – FEBRUARY 1998
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
interrupt flag registers 1 and 2
7654 0
P0IFG.1 OFIFG WDTIFG
321
rw-0 rw-1 rw-0
Address
02h NMIIFG P0IFG.0
rw-0 rw-0
WDTIFG: Set on overflow or security key violation
or
Reset on VCC1 power-on or reset condition at ’RST/NMI-pin
OFIFG: Flag set on oscillator fault
P0.0IFG: Dedicated I/O P0.0
P0.1IFG: P0.1 or 8-bit timer/counter, RXD
NMIIFG: Signal at ’RST/NMI-pin
7654 0
UTXIFG URXIFG
rw
321
rw-1 rw-0
Address
03h BTIFG
URXIFG: USART receive flag
UTXIFG: USART transmit flag
BTIFG: Basic Timer flag
module enable registers 1 and 2
7654 0321
Address
04h
7654 0
UTXE URXE
321
rw-0 rw-0
Address
05h
UTXE: USART transmit enable
URXE: USART receive enable
MSP430x33x
MIXED SIGNAL MICROCONTROLLERS
SLAS163 – FEBRUARY 1998
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
module enable registers 1 and 2 (continued)
Legend rw:
rw-0:
Bit can be read and written
Bit can be read and written. It is reset by PUC
SFR bit not present in device
ROM memory organization
Int. Vector
24 kB ROM
1024B RAM
16b Per.
8b Per.
SFR
FFFFh
FFE0h
FFDFh
A000h
05FFh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
MSP430C336
Int. Vector
32 kB ROM
1024B RAM
16b Per.
8b Per.
SFR
FFFFh
FFE0h
FFDFh
8000h
05FFh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
MSP430C337
Int. Vector
32 kB OTP
or
EPROM
1024B RAM
16b Per.
8b Per.
SFR
FFFFh
FFE0h
FFDFh
8000h
05FFh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
MSP430P337
PMS430E337
peripherals
Peripherals are connected to the CPU through a data, address, and control bus and can be handled easily with
instructions for memory manipulation.
oscillator and system clock
Two clocks are used in the system, the system (master) clock (MCLK) and the auxiliary clock (ACLK). The MCLK
is a multiple of the ACLK. The ACLK runs with the crystal oscillator frequency. The special design of the oscillator
supports the feature of low current consumption and the use of a 32 768 Hz crystal. The crystal is connected
across two terminals without any other external components being required.
The oscillator starts after applying VCC, due to a reset of the control bit (OscOff) in the status register (SR). It
can be stopped by setting the OscOff bit to a 1. The enabled clock signals ACLK, ACLK/2, ACLK/4, OR MCLK
are accessible for use by external devices at output terminal XBUF .
The controller system clocks have to deal with different requirements according to the application and system
condition. Requirements include:
D
High frequency in order to react quickly to system hardware requests or events
D
Low frequency in order to minimize current consumption, EMI, etc.
D
Stable frequency for timer applications e.g. real time clock (RTC)
D
Enable start-stop operation with minimum delay to operation function.
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