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MSP430F5517
User Manual
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Texas Instruments MSP430F5528, MSP430F5524, MSP430F5526, MSP430F5527, MSP430F5522 User Manual

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Reference Design
MSP430F5529,MSP430F5528,MSP430F5527,MSP430F5526 MSP430F5525,MSP430F5524,MSP430F5522,MSP430F5521
MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
MSP430F552x, MSP430F551x Mixed-Signal Microcontrollers
1 Device Overview
1.1 Features
1
• Low Supply Voltage Range:
3.6 V Down to 1.8 V
• Ultra-Low Power Consumption – Active Mode (AM):
• All System Clocks Active: – 290 µA/MHz at 8 MHz, 3.0 V, Flash
Program Execution (Typical)
– 150 µA/MHz at 8 MHz, 3.0 V, RAM
Program Execution (Typical)
– Standby Mode (LPM3):
• Real-Time Clock (RTC) With Crystal, Watchdog, and Supply Supervisor Operational, Full RAM Retention, Fast Wake up:
– 1.9 µA at 2.2 V, 2.1 µA at 3.0 V (Typical)
• Low-Power Oscillator (VLO), General­Purpose Counter, Watchdog, and Supply Supervisor Operational, Full RAM Retention, Fast Wake up:
– 1.4 µA at 3.0 V (Typical)
– Off Mode (LPM4):
• Full RAM Retention, Supply Supervisor Operational, Fast Wake up:
– 1.1 µA at 3.0 V (Typical)
– Shutdown Mode (LPM4.5):
• 0.18 µA at 3.0 V (Typical)
• Wake up From Standby Mode in 3.5 µs (Typical)
• 16-Bit RISC Architecture, Extended Memory, up to 25-MHz System Clock
• Flexible Power Management System – Fully Integrated LDO With Programmable
Regulated Core Supply Voltage
– Supply Voltage Supervision, Monitoring, and
Brownout
• Unified Clock System – FLL Control Loop for Frequency Stabilization – Low-Power Low-Frequency Internal Clock
Source (VLO)
SLAS590M –MARCH 2009–REVISED NOVEMBER 2015
– Low-Frequency Trimmed Internal Reference
Source (REFO) – 32-kHz Watch Crystals (XT1) – High-Frequency Crystals up to 32 MHz (XT2)
• 16-Bit Timer TA0, Timer_A With Five Capture/Compare Registers
• 16-Bit Timer TA1, Timer_A With Three Capture/Compare Registers
• 16-Bit Timer TA2, Timer_A With Three Capture/Compare Registers
• 16-Bit Timer TB0, Timer_B With Seven Capture/Compare Shadow Registers
• Two Universal Serial Communication Interfaces – USCI_A0 and USCI_A1 Each Support:
• Enhanced UART Supports Automatic Baud­Rate Detection
• IrDA Encoder and Decoder
• Synchronous SPI
– USCI_B0 and USCI_B1 Each Support:
• I2C
• Synchronous SPI
• Full-Speed Universal Serial Bus (USB) – Integrated USB-PHY – Integrated 3.3-V and 1.8-V USB Power System – Integrated USB-PLL – Eight Input and Eight Output Endpoints
• 12-Bit Analog-to-Digital Converter (ADC) (MSP430F552x Only) With Internal Reference, Sample-and-Hold, and Autoscan Feature
• Comparator
• Hardware Multiplier Supports 32-Bit Operations
• Serial Onboard Programming, No External Programming Voltage Needed
• Three-Channel Internal DMA
• Basic Timer With RTC Feature
• Section 3 Summarizes Available Family Members
• For Complete Module Descriptions, See the
MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208)
1.2 Applications
• Analog and Digital Sensor Systems • Connection to USB Hosts
• Data Loggers
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430F5529,MSP430F5528,MSP430F5527,MSP430F5526 MSP430F5525,MSP430F5524,MSP430F5522,MSP430F5521 MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
SLAS590M –MARCH 2009–REVISED NOVEMBER 2015
1.3 Description
The TI MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring peripheral sets targeted for a variety of applications. The architecture, combined with extensive low-power modes, is optimized to achieve extended battery life in portable measurement applications. The microcontroller features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows the devices to wake up from low-power modes to active mode in 3.5 µs (typical).
The MSP430F5529, MSP430F5527, MSP430F5525, and MSP430F5521 microcontrollers have integrated USB and PHY supporting USB 2.0, four 16-bit timers, a high-performance 12-bit analog-to-digital converter (ADC), two universal serial communication interfaces (USCI), a hardware multiplier, DMA, a real-time clock (RTC) module with alarm capabilities, and 63 I/O pins. The MSP430F5528, MSP430F5526, MSP430F5524, and MSP430F5522 microcontrollers include all of these peripherals but have 47 I/O pins.
The MSP430F5519, MSP430F5517, and MSP430F5515 microcontrollers have integrated USB and PHY supporting USB 2.0, four 16-bit timers, two universal serial communication interfaces (USCI), a hardware multiplier, DMA, an RTC module with alarm capabilities, and 63 I/O pins. The MSP430F5514 and MSP430FF5513 microcontrollers include all of these peripherals but have 47 I/O pins.
Typical applications include analog and digital sensor systems, data loggers, and others that require connectivity to various USB hosts.
www.ti.com
Device Information
PART NUMBER PACKAGE BODY SIZE
MSP430F5529PN LQFP (80) 12 mm × 12 mm MSP430F5528RGC VQFN (64) 9 mm× 9 mm MSP430F5528YFF DSBGA (64) 3.5 mm × 3.5 mm MSP430F5528ZQE MicroStar Junior™ BGA (80) 5 mm × 5 mm
(1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 8,
or see the TI website at www.ti.com.
(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 8.
(1)
(2)
2 Device Overview Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524
MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513
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Unified
Clock
System
128KB
96KB 64KB 32KB
Flash
8KB+2KB 6KB+2KB 4KB+2KB
RAM
MCLK
ACLK
SMCLK
I/OPorts
P1/P2
2×8I/Os
Interrupt
&Wakeup
PA
1×16I/Os
CPUXV2
and
Working
Registers
EEM
(L:8+2)
XIN
XOUT
JTAG/
Interface
SBW
PA PB PC
DMA
3Channel
XT2IN
XT OUT2
Power
Management
LDO SVM/ Brownout
SVS
SYS
Watchdog
PortMap
Control
(P4)
I/OPorts
P3/P4 1×5I/Os 1
PB
1×13I/Os
×8I/Os
I/OPorts
P5/P6
1×6I/Os
PC
1×14I/Os
1×8I/Os
Full-speed
USB
USB-PHY USB-LDO USB-PLL
MPY32
TA0
Timer_A
5CC
Registers
TA1
Timer_A
3CC
Registers
TB0
Timer_B
7CC
Registers
RTC_A
CRC16
USCI0,1
USCI_Ax:
UART,
IrDA,SPI
USCI_Bx:
SPI,I2C
ADC12_A
200KSPS
12Channels (10ext/2int)
Autoscan
12Bit
DVCC DVSS AVCC AVSS
P1.x P2.x
P3.x
P4.x
P5.x P6.x
DP,DM,PUR
RST/NMI
TA2
Timer_A
3CC
Registers
REF
VCORE
MAB
MDB
COMP_B
8Channels
Unified
Clock
System
128KB
96KB 64KB 32KB
Flash
8KB+2KB 6KB+2KB 4KB+2KB
RAM
MCLK
ACLK
SMCLK
I/OPorts
P1/P2
2×8I/Os
Interrupt
&Wakeup
PA
1×16I/Os
CPUXV2
and
Working
Registers
EEM
(L:8+2)
XIN
XOUT
JTAG/
Interface
SBW
PA PB PC PD
DMA
3Channel
XT2IN
XT OUT2
Power
Management
LDO SVM/ Brownout
SVS
SYS
Watchdog
PortMap
Control
(P4)
I/OPorts
P3/P4
2×8I/Os
PB
1×16I/Os
I/OPorts
P5/P6
2×8I/Os
PC
1×16I/Os
I/OPorts
P7/P8 1×8I/Os 1
PD
1×11I/Os
×3I/Os
Full-speed
USB
USB-PHY USB-LDO USB-PLL
MPY32
TA0
Timer_A
5CC
Registers
TA1
Timer_A
3CC
Registers
TB0
Timer_B
7CC
Registers
RTC_A
CRC16
USCI0,1
USCI_Ax:
UART,
IrDA,SPI
USCI_Bx:
SPI,I2C
ADC12_A
200KSPS
16Channels (14ext/2int)
Autoscan
12Bit
DVCC DVSS AVCC AVSS
P1.x P2.x
P3.x
P4.x
P5.x P6.x
DP,DM,PUR
RST/NMI
TA2
Timer_A
3CC
Registers
REF
VCORE
MAB
MDB
P7.x P8.x
COMP_B
12Channels
MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
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1.4 Functional Block Diagrams
Figure 1-1 shows the functional block diagram for the MSP430F5529, MSP430F5527, MSP430F5525, and
MSP430F5521 devices in the PN package.
MSP430F5529,MSP430F5528,MSP430F5527,MSP430F5526 MSP430F5525,MSP430F5524,MSP430F5522,MSP430F5521
SLAS590M –MARCH 2009–REVISED NOVEMBER 2015
Figure 1-1. Functional Block Diagram – MSP430F5529IPN, MSP430F5527IPN, MSP430F5525IPN,
MSP430F5521IPN
Figure 1-2 shows the functional block diagram for the MSP430F5528, MSP430F5526, MSP430F5524, and
MSP430F5522 devices in the RGC and ZQE packages and for the MSP430F5528, MSP430F5526, and MSP430F5524 devices in the YFF package.
MSP430F5528IRGC, MSP430F5526IRGC, MSP430F5524IRGC, MSP430F5522IRGC
MSP430F5528IZQE, MSP430F5526IZQE, MSP430F5524IZQE, MSP430F5522IZQE
MSP430F5528IYFF, MSP430F5526IYFF, MSP430F5524IYFF
Copyright © 2009–2015, Texas Instruments Incorporated Device Overview 3
Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524
MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513
Figure 1-2. Functional Block Diagram –
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Unified
Clock
System
64KB 32KB
Flash
4KB+2KB
RAM
MCLK
ACLK
SMCLK
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
PA
1×16 I/Os
CPUXV2
and
Working
Registers
EEM
(L: 8+2)
XIN
XOUT
JTAG/
SBW
Interface
PA PB PC
DMA
3 Channel
XT2IN
XT2OUT
Power
Management
LDO SVM/SVS Brownout
SYS
Watchdog
Port Map
Control
(P4)
I/O Ports
P3/P4 1×5 I/Os 1
PB
1×13 I/Os
×8 I/Os
I/O Ports
P5/P6
1×6 I/Os
PC
1×14 I/Os
1×8 I/Os
Full-speed
USB
USB-PHY USB-LDO USB-PLL
MPY32
TA0
Timer_A
5 CC
Registers
TA1
Timer_A
3 CC
Registers
TB0
Timer_B
7 CC
Registers
RTC_A
CRC16
USCI0,1
USCI_Ax:
UART,
IrDA, SPI
USCI_Bx:
SPI, I2C
DVCC DVSS AVCC AVSS
P1.x P2.x
P3.x
P4.x
P5.x P6.x
DP,DM,PUR
RST/NMI
TA2
Timer_A
3 CC
Registers
COMP_B
8 Channels
VCORE
MAB
MDB
REF
Unified
Clock
System
128KB
96KB 64KB
Flash
4KB+2KB
RAM
MCLK
ACLK
SMCLK
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
PA
1×16 I/Os
CPUXV2
and
Working
Registers
EEM
(L: 8+2)
XIN
XOUT
JTAG/
SBW
Interface
PA PB PC PD
DMA
3 Channel
XT2IN
XT2OUT
Power
Management
LDO SVM/SVS Brownout
SYS
Watchdog
Port Map
Control
(P4)
I/O Ports
P3/P4
2×8 I/Os
PB
1×16 I/Os
I/O Ports
P5/P6
2×8 I/Os
PC
1×16 I/Os
I/O Ports
P7/P8 1×8 I/Os 1
PD
1×11 I/Os
×3 I/Os
Full-speed
USB
USB-PHY USB-LDO USB-PLL
MPY32
TA0
Timer_A
5 CC
Registers
TA1
Timer_A
3 CC
Registers
TB0
Timer_B
7 CC
Registers
RTC_A
CRC16
USCI0,1
USCI_Ax:
UART,
IrDA, SPI
USCI_Bx:
SPI, I2C
DVCC DVSS AVCC AVSS
P1.x P2.x
P3.x
P4.x
P5.x P6.x
DP,DM,PUR
RST/NMI
TA2
Timer_A
3 CC
Registers
COMP_B
12 Channels
VCORE
MAB
MDB
P7.x P8.x
REF
MSP430F5529,MSP430F5528,MSP430F5527,MSP430F5526 MSP430F5525,MSP430F5524,MSP430F5522,MSP430F5521 MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
SLAS590M –MARCH 2009–REVISED NOVEMBER 2015
Figure 1-3 shows the functional block diagram for the MSP430F5519, MSP430F5517, and MSP430F5515
devices in the PN package.
www.ti.com
Figure 1-3. Functional Block Diagram – MSP430F5519IPN, MSP430F5517IPN, MSP430F5515IPN
Figure 1-4 shows the functional block diagram for the MSP430F5514 and MSP430F5513 devices in the
RGC and ZQE packages.
Figure 1-4. Functional Block Diagram – MSP430F5514IRGC, MSP430F5513IRGC, MSP430F5514IZQE,
MSP430F5513IZQE
4 Device Overview Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524
MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513
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MSP430F5529,MSP430F5528,MSP430F5527,MSP430F5526 MSP430F5525,MSP430F5524,MSP430F5522,MSP430F5521
MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
www.ti.com
SLAS590M –MARCH 2009–REVISED NOVEMBER 2015
Table of Contents
1 Device Overview ......................................... 1 5.24 PMM, SVS Low Side................................ 33
1.1 Features .............................................. 1 5.25 PMM, SVM Low Side ............................... 33
1.2 Applications........................................... 1
1.3 Description............................................ 2
1.4 Functional Block Diagrams ........................... 3
2 Revision History ......................................... 6
3 Device Comparison ..................................... 7
4 Terminal Configuration and Functions.............. 8
4.1 Pin Diagrams......................................... 8
4.2 Signal Descriptions.................................. 14
5 Specifications........................................... 19
5.1 Absolute Maximum Ratings ........................ 19
5.2 ESD Ratings ........................................ 19
5.3 Recommended Operating Conditions............... 19
5.4 Active Mode Supply Current Into VCCExcluding
External Current..................................... 21
5.5 Low-Power Mode Supply Currents (Into VCC)
Excluding External Current.......................... 22
5.6 Thermal Characteristics............................. 23
5.7 Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to
P8.2, PJ.0 to PJ.3, RST/NMI)....................... 24
5.8 Inputs – Ports P1 and P2
(P1.0 to P1.7, P2.0 to P2.7)......................... 24
5.9 Leakage Current – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to
P8.2, PJ.0 to PJ.3, RST/NMI)....................... 24
5.10 Outputs – General-Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7)
(P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to 5.49 JTAG and Spy-Bi-Wire Interface.................... 49
P8.2, PJ.0 to PJ.3) .................................. 24
5.11 Outputs – General-Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to
P8.2, PJ.0 to PJ.3) .................................. 25
5.12 Output Frequency – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to
P8.2, PJ.0 to PJ.3) .................................. 25
5.13 Typical Characteristics – Outputs, Reduced Drive
Strength (PxDS.y = 0)............................... 26
5.14 Typical Characteristics – Outputs, Full Drive
Strength (PxDS.y = 1)............................... 27
5.15 Crystal Oscillator, XT1, Low-Frequency Mode ..... 28
5.16 Crystal Oscillator, XT2 .............................. 29
5.17 Internal Very-Low-Power Low-Frequency Oscillator
(VLO)................................................ 30
5.18 Internal Reference, Low-Frequency Oscillator
(REFO) .............................................. 30
5.19 DCO Frequency..................................... 31
5.20 PMM, Brown-Out Reset (BOR) ..................... 32
5.21 PMM, Core Voltage ................................. 32
5.22 PMM, SVS High Side ............................... 32
5.23 PMM, SVM High Side............................... 33
5.26 Wake-up Times From Low-Power Modes and
Reset ................................................ 34
5.27 Timer_A ............................................. 34
5.28 Timer_B ............................................. 34
5.29 USCI (UART Mode) Clock Frequency .............. 35
5.30 USCI (UART Mode) ................................. 35
5.31 USCI (SPI Master Mode) Clock Frequency......... 35
5.32 USCI (SPI Master Mode)............................ 35
5.33 USCI (SPI Slave Mode)............................. 37
5.34 USCI (I
5.35 12-Bit ADC, Power Supply and Input Range
5.36 12-Bit ADC, Timing Parameters .................... 40
5.37 12-Bit ADC, Linearity Parameters Using an External
5.38 12-Bit ADC, Linearity Parameters Using the Internal
5.39 12-Bit ADC, Temperature Sensor and Built-In V
5.40 REF, External Reference ........................... 43
5.41 REF, Built-In Reference............................. 43
5.42 Comparator_B....................................... 45
5.43 Ports PU.0 and PU.1................................ 45
5.44 USB Output Ports DP and DM...................... 47
5.45 USB Input Ports DP and DM........................ 47
5.46 USB-PWR (USB Power System) ................... 48
5.47 USB-PLL (USB Phase Locked Loop) ............... 48
5.48 Flash Memory....................................... 49
2
C Mode).................................... 39
Conditions ........................................... 40
Reference Voltage or AVCC as Reference Voltage 41
Reference Voltage .................................. 41
42
MID
6 Detailed Description................................... 50
6.1 CPU (Link to User's Guide) ......................... 50
6.2 Operating Modes.................................... 51
6.3 Interrupt Vector Addresses.......................... 52
6.4 Memory Organization ............................... 53
6.5 Bootstrap Loader (BSL) ............................. 54
6.6 JTAG Operation ..................................... 55
6.7 Flash Memory (Link to User's Guide)............... 56
6.8 RAM (Link to User's Guide)......................... 56
6.9 Peripherals .......................................... 56
6.10 Input/Output Schematics ............................ 81
6.11 Device Descriptors (TLV) .......................... 103
7 Device and Documentation Support.............. 109
7.1 Device Support..................................... 109
7.2 Documentation Support............................ 112
7.3 Related Links ...................................... 113
7.4 Community Resources............................. 113
7.5 Trademarks ........................................ 113
7.6 Electrostatic Discharge Caution ................... 113
7.7 Glossary............................................ 113
8 Mechanical, Packaging, and Orderable
Information............................................. 114
Copyright © 2009–2015, Texas Instruments Incorporated Table of Contents 5
Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524
MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513
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MSP430F5529,MSP430F5528,MSP430F5527,MSP430F5526 MSP430F5525,MSP430F5524,MSP430F5522,MSP430F5521 MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
SLAS590M –MARCH 2009–REVISED NOVEMBER 2015
www.ti.com
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision L (June 2013) to Revision M Page
• Formatting and organization changes throughout, including addition of section numbering ............................... 1
• Added Device Information table .................................................................................................... 2
• Added Section 1.4 and moved all functional block diagrams to it.............................................................. 3
• Added Section 3 and moved Family Members table to it ....................................................................... 7
• Added Section 5 and moved all electrical specifications to it ................................................................. 19
• Added Section 5.2, ESD Ratings.................................................................................................. 19
• Moved Section 5.6, Thermal Characteristics .................................................................................... 23
• Changed the TYP value of C
• Corrected MRG0 and MRG1 bit names in f
• Corrected spelling of NMIIFG in Table 6-9, System Module Interrupt Vector Registers................................... 60
• Corrected register names (added "USB" prefix as necessary) in Table 6-45, USB Control Registers .................. 80
• Changed P5.3 schematic (added P5SEL.2 and XT2BYPASS inputs, AND gate, and OR gate after P5SEL.3)....... 89
• Changed P5SEL.3 column from X to 0 for "P5.3 (I/O)" rows.................................................................. 89
• Changed P5.5 schematic (change input from P5SEL.5 to P5SEL.4 and added P5SEL.5 input and the following
OR gate).............................................................................................................................. 91
• Changed P5SEL.5 column from X to 0 for "P5.5 (I/O)" rows.................................................................. 91
• Added Section 7 and moved Tools Support, Device Nomenclature, ESD Caution, and Trademarks sections to it.. 109
• Added Section 8, Mechanical, Packaging, and Orderable Information..................................................... 114
with Test Conditions of "XTS = 0, XCAPx = 0" from 2 pF to 1 pF..................... 28
L,eff
MCLK,MRG
parameter description................................................. 49
6 Revision History Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524
MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513
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MSP430F5529,MSP430F5528,MSP430F5527,MSP430F5526 MSP430F5525,MSP430F5524,MSP430F5522,MSP430F5521
MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
www.ti.com
SLAS590M – MARCH 2009–REVISED NOVEMBER 2015
3 Device Comparison
Table 3-1 summarizes the available family members.
Table 3-1. Family Members
(1)(2)
USCI
FLASH SRAM ADC12_A Comp_B
CHANNEL A: CHANNEL B:
DEVICE Timer_A
(4)
Timer_B
(5)
I/O PACKAGE
(KB) (KB)
(3)
(Ch) (Ch)
UART, IrDA, SPI, I2C
SPI
MSP430F5529 128 8 + 2 5, 3, 3 7 2 2 14 ext, 2 int 12 63 80 PN
64 RGC,
MSP430F5528 128 8 + 2 5, 3, 3 7 2 2 10 ext, 2 int 8 47 64 YFF,
80 ZQE
MSP430F5527 96 6 + 2 5, 3,3 7 2 2 14 ext, 2 int 12 63 80 PN
64 RGC,
MSP430F5526 96 6 + 2 5, 3,3 7 2 2 10 ext, 2 int 8 47 64 YFF,
80 ZQE
MSP430F5525 64 4 + 2 5, 3,3 7 2 2 14 ext, 2 int 12 63 80 PN
64 RGC,
MSP430F5524 64 4 + 2 5, 3,3 7 2 2 10 ext, 2 int 8 47 64 YFF,
80 ZQE
64 RGC,
MSP430F5522 32 8 + 2 5, 3,3 7 2 2 10 ext, 2 int 8 47
80 ZQE MSP430F5521 32 6 + 2 5, 3,3 7 2 2 14 ext, 2 int 12 63 80 PN MSP430F5519 128 8 + 2 5, 3, 3 7 2 2 – 12 63 80 PN MSP430F5517 96 6 + 2 5, 3,3 7 2 2 – 12 63 80 PN MSP430F5515 64 4 + 2 5, 3,3 7 2 2 – 12 63 80 PN
64 RGC,
MSP430F5514 64 4 + 2 5, 3,3 7 2 2 – 8 47
80 ZQE
64 RGC,
MSP430F5513 32 4 + 2 5, 3,3 7 2 2 – 8 47
80 ZQE
(1) For the most current part, package, and orderinginformation forall availabledevices, seethe Package Option Addendum inSection 8, or see the TIwebsite atwww.ti.com. (2) Package drawings, thermal data, and symbolization are availableat www.ti.com/packaging. (3) The additional 2KB USB SRAM that is listedcan beused asgeneral-purpose SRAMwhen USB is not in use. (4) Each number in the sequence represents an instantiationof Timer_Awith itsassociated numberof capture/compare registers and PWMoutput generatorsavailable. Forexample, a
number sequence of 3, 5 wouldrepresent two instantiations of Timer_A,the firstinstantiation having3 andthe second instantiation having 5capture/compare registersand PWMoutput generators, respectively.
(5) Each number in the sequence represents an instantiationof Timer_Bwith itsassociated numberof capture/compare registers and PWMoutput generatorsavailable. Forexample, a
number sequence of 3, 5 wouldrepresent two instantiations of Timer_B,the firstinstantiation having3 andthe second instantiation having 5capture/compare registersand PWMoutput generators, respectively.
Copyright © 2009–2015, Texas Instruments Incorporated Device Comparison 7
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Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524
MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P6.4/CB4/A4 P6.5/CB5/A5 P6.6/CB6/A6 P6.7/CB7/A7
P7.0/CB8/A12
P7.1/CB9/A13
P7.2/CB10/A14
P7.3/CB11/A15 P5.0/A8/VREF+/VeREF+ P5.1/A9/VREF−/VeREF−
AVCC1
AVSS1
P5.4/XIN
P5.5/XOUT
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
DVCC2 DVSS2
VCORE
MSP430F5529 MSP430F5527 MSP430F5525 MSP430F5521
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK
P5.3/XT2OUT
P5.2/XT2IN
AVSS2
V18
VUSB
VBUS
PU.1/DM
PUR
PU.0/DP
VSSU
P1.6/TA1CLK/CBOUT
P1.5/TA0.4
P1.7/TA1.0
P2.2/TA2CLK/SMCLK
P2.0/TA1.1
P2.3/TA2.0
P2.4/TA2.1
P2.5/TA2.2
P2.6/RTCCLK/DMAE0
P2.7/UCB0STE/UCA0CLK
P3.1/UCB0SOMI/UCB0SCL
P3.2/UCB0CLK/UCA0STE
P3.3/UCA0TXD/UCA0SIMO
P3.4/UCA0RXD/UCA0SOMI
P7.4/TB0.2
P7.5/TB0.3
DVSS1
DVCC1
P1.4/TA0.3
P2.1/TA1.2
P3.6/TB0.6
P3.7/TB0OUTH/SVMOUT
P4.2/PM_UCB1SOMI/PM_UCB1SCL P4.1/PM_UCB1SIMO/PM_UCB1SDA P4.0/PM_UCB1STE/PM_UCA1CLK
P4.5/PM_UCA1RXD/PM_UCA1SOMI P4.4/PM_UCA1TXD/PM_UCA1SIMO
P4.3/PM_UCB1CLK/PM_UCA1STE
P4.6/PM_NONE
P4.7/PM_NONE
P5.6/TB0.0
P5.7/TB0.1
P7.6/TB0.4
P7.7/TB0CLK/MCLK
P6.3/CB3/A3
P6.2/CB2/A2
P6.1/CB1/A1
P6.0/CB0/A0
P3.5/TB0.5
P8.0
P8.1
P8.2
MSP430F5529,MSP430F5528,MSP430F5527,MSP430F5526 MSP430F5525,MSP430F5524,MSP430F5522,MSP430F5521 MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
SLAS590M –MARCH 2009–REVISED NOVEMBER 2015
4 Terminal Configuration and Functions
4.1 Pin Diagrams
Figure 4-1 shows the pinout for the MSP430F5529, MSP430F5527, MSP430F5525, and MSP430F5521
devices in the PN package.
www.ti.com
Figure 4-1. Pin Designation – MSP430F5529IPN, MSP430F5527IPN, MSP430F5525IPN, MSP430F5521IPN
(Top View)
8 Terminal Configuration and Functions Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524
MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513
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MSP430F5528 MSP430F5526 MSP430F5524 MSP430F5522
P6.3/CB3/A3
P6.2/CB2/A2
P6.1/CB1/A1
P6.0/CB0/A0
P1.6/TA1CLK/CBOUT
P1.7/TA1.0
P2.0/TA1.1
P2.1/TA1.2
P2.2/TA2CLK/SMCLK
P2.3/TA2.0
P2.4/TA2.1
P2.5/TA2.2
P2.7/UCB0STE/UCA0CLK
P3.0/UCB0SIMO/UCB0SDA
P3.1/UCB0SOMI/UCB0SCL
P3.2/UCB0CLK/UCA0STE
P6.4/CB4/A4 P6.5/CB5/A5 P6.6/CB6/A6 P6.7/CB7/A7
AVCC1
AVSS1
P5.4/XIN
P5.5/XOUT
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
DVSS1
DVCC1
DVCC2 DVSS2
P4.2/PM_UCB1SOMI/PM_UCB1SCL P4.1/PM_UCB1SIMO/PM_UCB1SDA P4.0/PM_UCB1STE/PM_UCA1CLK
P4.5/PM_UCA1RXD/PM_UCA1SOMI P4.4/PM_UCA1TXD/PM_UCA1SIMO P4.3/PM_UCB1CLK/PM_UCA1STE
P3.3/UCA0TXD/UCA0SIMO
P3.4/UCA0RXD/UCA0SOMI
P4.6/PM_NONE
P4.7/PM_NONE
1764186319622061216022
59
29523051315032
49
2358245725562655275428
53
3316
3415
35
14
3613
37
12
38
11
45
4
463
472
48
1
3910
409
41
8
42
7
436
44
5
P1.4/TA0.3
P1.5/TA0.4
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK
P5.3/XT2OUT
P5.2/XT2IN
AVSS2
V18
VUSB
VBUS
PU.1/DM
PUR
PU.0/DP
VSSU
VCORE
www.ti.com
Figure 4-2 shows the pinout for the MSP430F5528, MSP430F5526, MSP430F5524, and MSP430F5522
devices in the RGC package.
MSP430F5529,MSP430F5528,MSP430F5527,MSP430F5526 MSP430F5525,MSP430F5524,MSP430F5522,MSP430F5521
MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
SLAS590M –MARCH 2009–REVISED NOVEMBER 2015
NOTE: TI recommends connecting the exposed thermal pad to VSS.
Figure 4-2. Pin Designation – MSP430F5528IRGC, MSP430F5526IRGC, MSP430F5524IRGC,
Copyright © 2009–2015, Texas Instruments Incorporated Terminal Configuration and Functions 9
Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524
MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513
MSP430F5522IRGC (Top View)
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P6.4/CB4 P6.5/CB5 P6.6/CB6 P6.7/CB7
P7.0/CB8
P7.1/CB9
P7.2/CB10
P7.3/CB11
P5.0 P5.1
AVCC1
AVSS1
P5.4/XIN
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
DVCC2 DVSS2
VCORE
MSP430F5519 MSP430F5517 MSP430F5515
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK
P5.3/XT2OUT
P5.2/XT2IN
AVSS2
V18
VUSB
VBUS
PU.1/DM
PUR
PU.0/DP
VSSU
P1.6/TA1CLK/CBOUT
P1.5/TA0.4
P1.7/TA1.0
P2.2/TA2CLK/SMCLK
P2.0/TA1.1
P2.3/TA2.0
P2.4/TA2.1
P2.5/TA2.2
P2.6/RTCCLK/DMAE0
P2.7/UCB0STE/UCA0CLK
P3.1/UCB0SOMI/UCB0SCL
P3.2/UCB0CLK/UCA0STE
P3.3/UCA0TXD/UCA0SIMO
P3.4/UCA0RXD/UCA0SOMI
P7.4/TB0.2
P7.5/TB0.3
DVSS1
DVCC1
P1.4/TA0.3
P2.1/TA1.2
P3.6/TB0.6
P3.7/TB0OUTH/SVMOUT
P4.2/PM_UCB1SOMI/PM_UCB1SCL P4.1/PM_UCB1SIMO/PM_UCB1SDA P4.0/PM_UCB1STE/PM_UCA1CLK
P4.5/PM_UCA1RXD/PM_UCA1SOMI P4.4/PM_UCA1TXD/PM_UCA1SIMO
P4.3/PM_UCB1CLK/PM_UCA1STE
P4.6/PM_NONE
P4.7/PM_NONE
P5.6/TB0.0
P5.7/TB0.1
P7.6/TB0.4
P7.7/TB0CLK/MCLK
P6.3/CB3
P6.2/CB2
P6.1/CB1
P6.0/CB0
P3.5/TB0.5
P8.0 P8.1 P8.2
MSP430F5529,MSP430F5528,MSP430F5527,MSP430F5526 MSP430F5525,MSP430F5524,MSP430F5522,MSP430F5521 MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
SLAS590M –MARCH 2009–REVISED NOVEMBER 2015
Figure 4-3 shows the pinout for the MSP430F5519, MSP430F5517, and MSP430F5515 devices in the PN
package.
www.ti.com
Figure 4-3. Pin Designation – MSP430F5519IPN, MSP430F5517IPN, MSP430F5515IPN (Top View)
10 Terminal Configuration and Functions Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524
MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513
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MSP430F5514 MSP430F5513
P6.3/CB3
P6.2/CB2
P6.1/CB1
P6.0/CB0
P1.6/TA1CLK/CBOUT
P1.7/TA1.0
P2.0/TA1.1
P2.1/TA1.2
P2.2/TA2CLK/SMCLK
P2.3/TA2.0
P2.4/TA2.1
P2.5/TA2.2
P2.7/UCB0STE/UCA0CLK
P3.0/UCB0SIMO/UCB0SDA
P3.1/UCB0SOMI/UCB0SCL
P3.2/UCB0CLK/UCA0STE
P6.4/CB4 P6.5/CB5 P6.6/CB6 P6.7/CB7
P5.0 P5.1
AVCC1
AVSS1
P5.4/XIN
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
DVSS1
DVCC1
DVCC2 DVSS2
P4.2/PM_UCB1SOMI/PM_UCB1SCL P4.1/PM_UCB1SIMO/PM_UCB1SDA P4.0/PM_UCB1STE/PM_UCA1CLK
P4.5/PM_UCA1RXD/PM_UCA1SOMI P4.4/PM_UCA1TXD/PM_UCA1SIMO P4.3/PM_UCB1CLK/PM_UCA1STE
P3.3/UCA0TXD/UCA0SIMO
P3.4/UCA0RXD/UCA0SOMI
P4.6/PM_NONE
P4.7/PM_NONE
1764186319622061216022
59
29523051315032
49
2358245725562655275428
53
3316
3415
35
14
3613
37
12
38
11
45
4
463
472
48
1
3910
409
41
8
42
7
436
44
5
P1.4/TA0.3
P1.5/TA0.4
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK
P5.3/XT2OUT
P5.2/XT2IN
AVSS2
V18
VUSB
VBUS
PU.1/DM
PUR
PU.0/DP
VSSU
VCORE
www.ti.com
Figure 4-4 shows the pinout for the MSP430F5514 and MSP430F5513 devices in the RGC package.
MSP430F5529,MSP430F5528,MSP430F5527,MSP430F5526 MSP430F5525,MSP430F5524,MSP430F5522,MSP430F5521
MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
SLAS590M –MARCH 2009–REVISED NOVEMBER 2015
NOTE: TI recommends connecting the exposed thermal pad to VSS.
Figure 4-4. Pin Designation – MSP430F5514IRGC, MSP430F5513IRGC (Top View)
Copyright © 2009–2015, Texas Instruments Incorporated Terminal Configuration and Functions 11
Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524
MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513
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A1 A2
A3
A4
A5 A6
A7
A8 A9
B1 B2
B3
B4
B5 B6
B7
B8 B9
C1 C2
D1 D2 D4
D5 D6
D7
D8 D9
E1 E2 E4
E5 E6
E7
E8 E9
F1 F2 F4
F5 F8 F9
G1 G2 G4
G5 G8 G9
J1 J2 J4
J5 J6
J7
J8 J9
H1 H2 H4
H5 H6
H7
H8 H9
C4
C5 C6
C7
C8 C9
D3
E3
F3
G3
J3
H3
F6
G6
F7
G7
P6.0 RST/NMI
PJ.2
TEST
AVSS2 VUSB
VBUS
PU.1
PU.0
P6.2 P6.1
PJ.3
P5.3
P5.2 V18
PUR
VSSU VSSU
P6.4
P6.3
P6.6
P6.5
Reserved
Reserved Reserved
P4.4
P4.3 P4.2
P5.0 P5.1 Reserved
Reserved Reserved
P4.1
P4.0 DVCC2
P5.4 AVCC1 Reserved
Reserved Reserved DVSS2
P5.5 AVSS1 P1.3
P1.6 P3.2 P3.3
DVSS1 VCORE P1.5
P2.0 P2.2
P2.4
P2.5 P2.6
DVCC1 P1.0 P1.4
P1.7 P2.3
P2.7
P3.0 P3.1
PJ.1
PJ.0 Reserved
P4.7
P4.6 P4.5
P6.7
Reserved
Reserved
Reserved
P1.2
P1.1
Reserved
P2.1
Reserved
P3.4
MSP430F5529,MSP430F5528,MSP430F5527,MSP430F5526 MSP430F5525,MSP430F5524,MSP430F5522,MSP430F5521 MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
SLAS590M –MARCH 2009–REVISED NOVEMBER 2015
Figure 4-5 shows the pinout for the MSP430F5528, MSP430F5526, MSP430F5524, MSP430F5522,
MSP430F5514, and MSP430F5513 devices in the ZQE package.
www.ti.com
Figure 4-5. Pin Designation – MSP430F5528IZQE, MSP430F5526IZQE, MSP430F5524IZQE,
MSP430F5522IZQE, MSP430F5514IZQE, MSP430F5513IZQE (Top View)
12 Terminal Configuration and Functions Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524
MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513
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A1A2
A3
A4
A5A6
A7
A8
B1B2
B3
B4
B5B6
B7
B8
C1C2
D1D2D4
D5D6
D7
D8
E1E2E4
E5E6
E7
E8
F1F2F4
F5F8
G1G2G4
G5G8
H1H2H4
H5H6
H7
H8
C4
C5C6
C7
C8
D3
E3
F3
G3
H3
F6
G6
F7
G7
C3
P6.2P6.6
AVCC1
AVSS1
P5.4P5.5
DVCC1
DVSS1
P6.0P6.4
P6.5
P5.0
P5.1P1.1
P1.0
VCORE
PJ.2
PJ.3
P5.3AVSS2PJ.1
RST/NMI
P1.5
P1.6
P1.7
P5.2V18P4.7
P2.0
P2.3
P2.2P2.1
VUSBVBUSP4.3
P4.0P2.4
PU.1
PUR
P4.2
P3.4P3.0
PU.0
VSSU
P4.1
DVCC2DVSS2
P3.1
P2.7
P6.3
P6.7P1.2
P1.4
P1.3
PJ.0
TEST
P4.6
P4.5
P4.4
P2.6
P3.3
P2.5
P3.2
P6.1
TOP VIEW
BALL-SIDE VIEW
A1 A2
A3
A4
A5 A6
A7
A8
B1 B2
B3
B4
B5 B6
B7
B8
C1 C2
D1 D2 D4
D5 D6
D7
D8
E1 E2 E4
E5 E6
E7
E8
F1 F2 F4
F5 F8
G1 G2 G4
G5 G8
H1 H2 H4
H5 H6
H7
H8
C4
C5 C6
C7
C8
D3
E3
F3
G3
H3
F6G6F7
G7
C3
P6.2 P6.6
AVCC1
AVSS1
P5.4 P5.5
DVCC1
DVSS1
P6.0 P6.4
P6.5
P5.0
P5.1 P1.1
P1.0
VCORE
PJ.2
PJ.3
P5.3 AVSS2 PJ.1
RST/NMI
P1.5
P1.6
P1.7
P5.2 V18 P4.7
P2.0
P2.3
P2.2 P2.1
VUSB VBUS P4.3
P4.0 P2.4
PU.1
PUR
P4.2
P3.4 P3.0
PU.0
VSSU
P4.1
DVCC2 DVSS2
P3.1
P2.7
P6.3
P6.7 P1.2
P1.4
P1.3
PJ.0
TEST
P4.6
P4.5
P4.4
P2.6
P3.3
P2.5
P3.2
P6.1
D
E
D
E
www.ti.com
Figure 4-6 shows the pinout for the MSP430F5528, MSP430F5526, and MSP430F5524 devices in the
YFF package.
MSP430F5529,MSP430F5528,MSP430F5527,MSP430F5526 MSP430F5525,MSP430F5524,MSP430F5522,MSP430F5521
MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
SLAS590M –MARCH 2009–REVISED NOVEMBER 2015
Figure 4-6. Pin Designation – MSP430F5528IYFF, MSP430F5526IYFF, MSP430F5524IYFF
Copyright © 2009–2015, Texas Instruments Incorporated Terminal Configuration and Functions 13
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4.2 Signal Descriptions
Table 4-1. Terminal Functions
TERMINAL
NAME
P6.4/CB4/A4 1 5 B2 C1 I/O Comparator_B input CB4
P6.5/CB5/A5 2 6 B3 D2 I/O Comparator_B input CB5
P6.6/CB6/A6 3 7 A2 D1 I/O Comparator_B input CB6
P6.7/CB7/A7 4 8 C5 D3 I/O Comparator_B input CB7
P7.0/CB8/A12 5 N/A N/A N/A I/O Comparator_B input CB8 (not available on F5528, F5526, F5524, F5522, F5514,
P7.1/CB9/A13 6 N/A N/A N/A I/O Comparator_B input CB9 (not available on F5528, F5526, F5524, F5522, F5514,
P7.2/CB10/A14 7 N/A N/A N/A I/O Comparator_B input CB10 (not available on F5528, F5526, F5524, F5522, F5514,
P7.3/CB11/A15 8 N/A N/A N/A I/O Comparator_B input CB11 (not available on F5528, F5526, F5524, F5522, F5514,
P5.0/A8/VREF+/VeREF+ 9 9 B4 E1 I/O
P5.1/A9/VREF-/VeREF- 10 10 B5 E2 I/O reference voltage, or an external applied reference voltage (not available on F551x
AVCC1 11 11 A3 F2 Analog power supply
P5.4/XIN 12 12 A5 F1 I/O
P5.5/XOUT 13 13 A6 G1 I/O
AVSS1 14 14 A4 G2 Analog ground supply P8.0 15 N/A N/A N/A I/O General-purpose digitalI/O P8.1 16 N/A N/A N/A I/O General-purpose digitalI/O P8.2 17 N/A N/A N/A I/O General-purpose digitalI/O
PN RGC YFF ZQE
NO. I/O
(1)
General-purpose digital I/O
Analog input A4 – ADC (not available on F551x devices) General-purpose digital I/O
Analog input A5 – ADC (not available on F551x devices) General-purpose digital I/O
Analog input A6 – ADC (not available on F551x devices) General-purpose digital I/O
Analog input A7 – ADC (not available on F551x devices) General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514,
F5513 devices)
F5513 devices) Analog input A12 – ADC (not available on F551x devices) General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514,
F5513 devices)
F5513 devices) Analog input A13 – ADC (not available on F551x devices) General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514,
F5513 devices)
F5513 devices) Analog input A14 – ADC (not available on F551x devices) General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514,
F5513 devices)
F5513 devices) Analog input A15 – ADC (not available on F551x devices) General-purpose digital I/O Output of reference voltage to the ADC (not available on F551x devices) Input for an external reference voltage to the ADC (not available on F551x devices) Analog input A8 – ADC (not available on F551x devices) General-purpose digital I/O Negative terminal for the ADC reference voltage for both sources, the internal
devices) Analog input A9 – ADC (not available on F551x devices)
General-purpose digital I/O Input terminal for crystal oscillator XT1 General-purpose digital I/O Output terminal of crystal oscillator XT1
DESCRIPTION
(1) I = input, O = output, N/A = not available 14 Terminal Configuration and Functions Copyright © 2009–2015, Texas Instruments Incorporated
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SLAS590M –MARCH 2009–REVISED NOVEMBER 2015
Table 4-1. Terminal Functions (continued)
TERMINAL
NAME
DVCC1 18 15 A7 H1 Digital power supply DVSS1 19 16 A8 J1 Digital ground supply
(2)
VCORE
P1.0/TA0CLK/ACLK 21 18 B7 H2 I/O TA0 clocksignal TA0CLK input
P1.1/TA0.0 22 19 B6 H3 I/O TA0 CCR0 capture: CCI0A input, compare: Out0 output
P1.2/TA0.1 23 20 C6 J3 I/O TA0 CCR1 capture: CCI1A input, compare: Out1 output
P1.3/TA0.2 24 21 C8 G4 I/O
P1.4/TA0.3 25 22 C7 H4 I/O
P1.5/TA0.4 26 23 D6 J4 I/O
P1.6/TA1CLK/CBOUT 27 24 D7 G5 I/O TA1 clock signal TA1CLK input
P1.7/TA1.0 28 25 D8 H5 I/O
P2.0/TA1.1 29 26 E5 J5 I/O
P2.1/TA1.2 30 27 E8 G6 I/O
P2.2/TA2CLK/SMCLK 31 28 E7 J6 I/O TA2 clock signal TA2CLK input
P2.3/TA2.0 32 29 E6 H6 I/O
P2.4/TA2.1 33 30 F8 J7 I/O
P2.5/TA2.2 34 31 F7 J8 I/O
P2.6/RTCCLK/DMAE0 35 32 F6 J9 I/O RTC clock output for calibration
P2.7/UCB0STE/UCA0CLK 36 33 H8 H7 I/O
P3.0/UCB0SIMO/UCB0SDA 37 34 G8 H8 I/O
PN RGC YFF ZQE
20 17 B8 J2 Regulated core power supply output (internal use only, no external current loading)
NO. I/O
(1)
General-purpose digital I/O with port interrupt
ACLK output (divided by 1, 2, 4, 8, 16, or 32) General-purpose digital I/O with port interrupt
BSL transmit output General-purpose digital I/O with port interrupt
BSL receive input General-purpose digital I/O with port interrupt TA0 CCR2 capture: CCI2A input, compare: Out2 output General-purpose digital I/O with port interrupt TA0 CCR3 capture: CCI3A input compare: Out3 output General-purpose digital I/O with port interrupt TA0 CCR4 capture: CCI4A input, compare: Out4 output General-purpose digital I/O with port interrupt
Comparator_B output General-purpose digital I/O with port interrupt TA1 CCR0 capture: CCI0A input, compare: Out0 output General-purpose digital I/O with port interrupt TA1 CCR1 capture: CCI1A input, compare: Out1 output General-purpose digital I/O with port interrupt TA1 CCR2 capture: CCI2A input, compare: Out2 output General-purpose digital I/O with port interrupt
SMCLK output General-purpose digital I/O with port interrupt TA2 CCR0 capture: CCI0A input, compare: Out0 output General-purpose digital I/O with port interrupt TA2 CCR1 capture: CCI1A input, compare: Out1 output General-purpose digital I/O with port interrupt TA2 CCR2 capture: CCI2A input, compare: Out2 output General-purpose digital I/O with port interrupt
DMA external trigger input General-purpose digital I/O with port interrupt Slave transmit enable – USCI_B0 SPI mode Clock signal input – USCI_A0 SPI slave mode Clock signal output – USCI_A0 SPI master mode General-purpose digital I/O Slave in, master out – USCI_B0 SPI mode
I2C data – USCI_B0 I2C mode
DESCRIPTION
(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, C
Copyright © 2009–2015, Texas Instruments Incorporated Terminal Configuration and Functions 15
VCORE
.
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Table 4-1. Terminal Functions (continued)
TERMINAL
NAME
P3.1/UCB0SOMI/UCB0SCL 38 35 H7 H9 I/O
P3.2/UCB0CLK/UCA0STE 39 36 G7 G8 I/O
P3.3/UCA0TXD/UCA0SIMO 40 37 G6 G9 I/O Transmit data – USCI_A0 UART mode
P3.4/UCA0RXD/UCA0SOMI 41 38 G5 G7 I/O Receive data – USCI_A0 UART mode
P3.5/TB0.5 42 N/A N/A N/A I/O
P3.6/TB0.6 43 N/A N/A N/A I/O
P3.7/TB0OUTH/SVMOUT 44 N/A N/A N/A I/O Switch all PWM outputs high impedance input – TB0 (not available on F5528,
P4.0/PM_UCB1STE/ PM_UCA1CLK
P4.1/PM_UCB1SIMO/ PM_UCB1SDA
P4.2/PM_UCB1SOMI/ PM_UCB1SCL
P4.3/PM_UCB1CLK/ PM_UCA1STE
DVSS2 49 39 H6 F9 Digital ground supply DVCC2 50 40 H5 E9 Digital power supply
P4.4/PM_UCA1TXD/ PM_UCA1SIMO
P4.5/PM_UCA1RXD/ PM_UCA1SOMI
P4.6/PM_NONE 53 47 F3 C8 I/O
P4.7/PM_NONE 54 48 E4 C7 I/O
PN RGC YFF ZQE
45 41 F5 E8 I/O
46 42 H4 E7 I/O
47 43 G4 D9 I/O
48 44 F4 D8 I/O
51 45 H3 D7 I/O Default mapping: Transmit data – USCI_A1 UART mode
52 46 G3 C9 I/O Default mapping: Receive data – USCI_A1 UART mode
NO. I/O
(1)
General-purpose digital I/O Slave out, master in – USCI_B0 SPI mode
I2C clock –USCI_B0 I2C mode General-purpose digital I/O Clock signal input – USCI_B0 SPI slave mode Clock signal output – USCI_B0 SPI master mode Slave transmit enable – USCI_A0 SPI mode General-purpose digital I/O
Slave in, master out – USCI_A0 SPI mode General-purpose digital I/O
Slave out, master in – USCI_A0 SPI mode General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514,
F5513 devices) TB0 CCR5 capture: CCI5A input, compare: Out5 output General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514,
F5513 devices) TB0 CCR6 capture: CCI6A input, compare: Out6 output General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514,
F5513 devices)
F5526, F5524, F5522, F5514, F5513 devices) SVM output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices) General-purpose digital I/O with reconfigurable port mapping secondary function Default mapping: Slave transmit enable – USCI_B1 SPI mode Default mapping: Clock signal input – USCI_A1 SPI slave mode Default mapping: Clock signal output – USCI_A1 SPI master mode General-purpose digital I/O with reconfigurable port mapping secondary function Default mapping: Slave in, master out – USCI_B1 SPI mode
Default mapping: I2C data – USCI_B1 I2C mode General-purpose digital I/O with reconfigurable port mapping secondary function Default mapping: Slave out, master in – USCI_B1 SPI mode
Default mapping: I2C clock –USCI_B1 I2C mode General-purpose digital I/O with reconfigurable port mapping secondary function Default mapping: Clock signal input – USCI_B1 SPI slave mode Default mapping: Clock signal output – USCI_B1 SPI master mode Default mapping: Slave transmit enable – USCI_A1 SPI mode
General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Slave in, master out – USCI_A1 SPI mode General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Slave out, master in – USCI_A1 SPI mode General-purpose digital I/O with reconfigurable port mapping secondary function Default mapping: no secondary function. General-purpose digital I/O with reconfigurable port mapping secondary function Default mapping: no secondary function.
DESCRIPTION
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SLAS590M –MARCH 2009–REVISED NOVEMBER 2015
Table 4-1. Terminal Functions (continued)
TERMINAL
NAME
P5.6/TB0.0 55 N/A N/A N/A I/O
P5.7/TB0.1 56 N/A N/A N/A I/O
P7.4/TB0.2 57 N/A N/A N/A I/O
P7.5/TB0.3 58 N/A N/A N/A I/O
P7.6/TB0.4 59 N/A N/A N/A I/O
P7.7/TB0CLK/MCLK 60 N/A N/A N/A I/O
VSSU 61 49 H2 USB PHY ground supply
PU.0/DP 62 50 H1 A9 I/O
PUR 63 51 G2 B7 I/O invoke the default USB BSL. Recommended 1-MΩ resistor to ground. See
PU.1/DM 64 52 G1 A8 I/O
VBUS 65 53 F2 A7 USB LDO input (connect to USB power source) VUSB 66 54 F1 A6 USB LDO output V18 67 55 E2 B6 USB regulated power (internal use only, no external current loading) AVSS2 68 56 D2 A5 Analog ground supply
P5.2/XT2IN 69 57 E1 B5 I/O
P5.3/XT2OUT 70 58 D1 B4 I/O
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
(3)
(4)
(4)
(4)
PN RGC YFF ZQE
71 59 E3 A4 I
72 60 D3 C5 I/O
73 61 D4 C4 I/O JTAG test data input
74 62 C1 A3 I/O
NO. I/O
B8,
B9
(1)
General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
TB0 CCR0 capture: CCI0A input, compare: Out0 output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
TB0 CCR1 capture: CCI1A input, compare: Out1 output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
TB0 CCR2 capture: CCI2A input, compare: Out2 output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
TB0 CCR3 capture: CCI3A input, compare: Out3 output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
TB0 CCR4 capture: CCI4A input, compare: Out4 output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
TB0 clock signal TBCLK input (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
MCLK output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
General-purpose digital I/O. Controlled by USB control register USB data terminal DP USB pullup resistor pin (open drain). The voltage level at the PUR pinis used to
Section 6.5.1 for more information.
General-purpose digital I/O. Controlled by USB control register USB data terminal DM
General-purpose digital I/O Input terminal for crystal oscillator XT2 General-purpose digital I/O Output terminal of crystal oscillator XT2 Test mode pin – Selects four wire JTAG operation Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated General-purpose digital I/O JTAG test data output port General-purpose digital I/O
Test clock input General-purpose digital I/O JTAG test mode select
DESCRIPTION
(3) See Section 6.5and Section 6.6 for use with BSL and JTAG functions. (4) See Section 6.6for use with JTAG function.
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Table 4-1. Terminal Functions (continued)
TERMINAL
NAME
PJ.3/TCK
RST/NMI/SBWTDIO
P6.0/CB0/A0 77 1 B1 A1 I/O Comparator_B input CB0
P6.1/CB1/A1 78 2 C3 B2 I/O Comparator_B input CB1
P6.2/CB2/A2 79 3 A1 B1 I/O Comparator_B input CB2
P6.3/CB3/A3 80 4 C4 C2 I/O Comparator_B input CB3
Reserved N/A N/A N/A QFN Pad N/A Pad N/A N/A QFN package pad. TIrecommends connecting to VSS.
(4)
(3)
PN RGC YFF ZQE
75 63 C2 B3 I/O
76 64 D5 A2 I/O Nonmaskable interrupt input
NO. I/O
(6)
(5) When this pin is configured as reset, the internal pullup resistor is enabled by default. (6) C6, D4, D5, D6, E3, E4, E5, E6, F3, F4, F5, F6, F7, F8, G3 are reserved and should be connected to ground.
(1)
General-purpose digital I/O JTAG test clock Reset input, active low
Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated General-purpose digital I/O
Analog input A0 – ADC (not available on F551x devices) General-purpose digital I/O
Analog input A1 – ADC (not available on F551x devices) General-purpose digital I/O
Analog input A2 – ADC (not available on F551x devices) General-purpose digital I/O
Analog input A3 – ADC (not available on F551x devices) Reserved. Connect to ground.
(5)
DESCRIPTION
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5 Specifications
MSP430F5529,MSP430F5528,MSP430F5527,MSP430F5526 MSP430F5525,MSP430F5524,MSP430F5522,MSP430F5521
MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
SLAS590M –MARCH 2009–REVISED NOVEMBER 2015
5.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Voltage applied at VCCto V
SS
Voltage applied to any pin (excluding VCORE, VBUS, V18)
(2)
–0.3 4.1 V
–0.3 VCC+ 0.3 V Diode current at any device pin ±2 mA Maximum operating junction temperature, T Storage temperature, T
(3)
stg
J
–55 150 °C
95 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied. (3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2 ESD Ratings
VALUE UNIT
V
Electrostatic discharge V
(ESD)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 Charged-device model (CDM), per JEDEC specification JESD22-C101
(1)
(2)
±1000
±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3 Recommended Operating Conditions
Typical values are specified at VCC= 3.3 V and TA= 25°C (unless otherwise noted)
MIN NOM MAX UNIT
PMMCOREVx = 0 1.8 3.6
V
CC
V
CC, USB
V
SS
T
A
T
J
C
VCORE
C
DVCC
C
VCORE
Supply voltage during program execution and flash programming (AVCC= DV
CC1/2
= DVCC)
(1)(2)
Supply voltage during USB operation, USB PLL disabled, USB_EN = 1, UPLLEN = 0
Supply voltage during USB operation, USB PLL enabled USB_EN = 1, UPLLEN = 1
Supply voltage (AVSS= DV
= DVSS) 0 V
SS1/2
Operating free-air temperature I version –40 85 °C Operating junction temperature I version –40 85 °C Recommended capacitor at VCORE
/
Capacitor ratio of DVCC to VCORE 10 ratio
(4)
PMMCOREVx = 0, 1 2.0 3.6 PMMCOREVx = 0, 1, 2 2.2 3.6 PMMCOREVx = 0, 1, 2, 3 2.4 3.6 PMMCOREVx = 0 1.8 3.6 PMMCOREVx = 0, 1 2.0 3.6 PMMCOREVx = 0, 1, 2 2.2 3.6 PMMCOREVx = 0, 1, 2, 3 2.4 3.6
(3)
PMMCOREVx = 2 2.2 3.6
,
PMMCOREVx = 2, 3 2.4 3.6
470 nF
V
V
(1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation. (2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Section 5.22 threshold parameters for
the exact values and further details. (3) USB operation with USB PLL enabled requires PMMCOREVx ≥ 2 for proper operation. (4) A capacitor tolerance of ±20% or better is required.
Copyright © 2009–2015, Texas Instruments Incorporated Specifications 19
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2.01.8
8
0
12
20
25
SystemFrequency-MHz
SupplyVoltage-V
ThenumberswithinthefieldsdenotethesupportedPMMCOREVxsettings.
2.2 2.4 3.6
0,1,2,30,1,20,10
1,2,3
1,2
1
2,3
3
2
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Recommended Operating Conditions (continued)
Typical values are specified at VCC= 3.3 V and TA= 25°C (unless otherwise noted)
MIN NOM MAX UNIT
PMMCOREVx = 0,
1.8 V ≤ VCC≤ 3.6 V 0 8.0 (default condition)
f
SYSTEM
f
SYSTEM_USB
Processor frequency (maximum MCLK frequency) (see Figure 5-1)
Minimum processor frequency for USB operation 1.5 MHz
(5)
USB_wait Wait state cycles during USB operation 16 cycles
(5) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
PMMCOREVx = 1,
2.0 V ≤ VCC≤ 3.6 V PMMCOREVx = 2,
2.2 V ≤ VCC≤ 3.6 V PMMCOREVx = 3,
2.4 V ≤ VCC≤ 3.6 V
0 12.0
0 20.0
0 25.0
MHz
20 Specifications Copyright © 2009–2015, Texas Instruments Incorporated
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Figure 5-1. Maximum System Frequency
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SLAS590M –MARCH 2009–REVISED NOVEMBER 2015
5.4 Active Mode Supply Current Into VCCExcluding External Current
over recommended operating free-air temperature (unless otherwise noted)
PARAMETER V
I
AM, Flash
I
AM, RAM
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. (2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF. (3) Characterized with program executing typical data processing. USB disabled (VUSBEN = 0, SLDOEN = 0).
f
ACLK
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.
EXECUTION
MEMORY
Flash 3.0 V mA
RAM 3.0 V mA
= 32786 Hz, f
DCO
= f
MCLK
CC
= f
PMMCOREVx 1 MHz 8 MHz 12 MHz 20 MHz 25 MHz UNIT
TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX
0 0.36 0.47 2.32 2.60 1 0.40 2.65 4.0 4.4 2 0.44 2.90 4.3 7.1 7.7 3 0.46 3.10 4.6 7.6 10.1 11.0 0 0.20 0.24 1.20 1.30 1 0.22 1.35 2.0 2.2 2 0.24 1.50 2.2 3.7 4.2 3 0.26 1.60 2.4 3.9 5.3 6.2
at specified frequency.
SMCLK
(1) (2) (3)
FREQUENCY (f
DCO
= f
MCLK
= f
SMCLK
)
Copyright © 2009–2015, Texas Instruments Incorporated Specifications 21
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SLAS590M –MARCH 2009–REVISED NOVEMBER 2015
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5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
–40°C 25°C 60°C 85°C
TYP MAX TYP MAX TYP MAX TYP MAX
= 32768 Hz, f
ACLK
= 32768 Hz, f
ACLK
= 32768 Hz, f
ACLK
= f
ACLK
= f
DCO
VLO
ACLK
, f
= f
MCLK
MCLK
MCLK
MCLK
MCLK
= f
= f
= 0 MHz, f
= 0 MHz, f
= f
SMCLK
SMCLK
= f
DCO
SMCLK
= f
DCO
= 0 MHz
ACLK
SMCLK
SMCLK
= f
DCO
= 0 MHz
= f
MCLK
= f
DCO
= f
DCO
= 0 MHz
= f
I
LPM0,1MHz
I
LPM2
PARAMETER V
Low-power mode 0
Low-power mode 2
(3)(4)
(5)(4)
PMMCOREVx UNIT
CC
2.2 V 0 73 77 85 80 85 97
3.0 V 3 79 83 92 88 95 105
2.2 V 0 6.5 6.5 12 10 11 17
3.0 V 3 7.0 7.0 13 11 12 18 0 1.60 1.90 2.6 5.6
2.2 V 1 1.65 2.00 2.7 5.9 2 1.75 2.15 2.9 6.1
I
LPM3,XT1LF
Low-power mode 3, crystal mode
(6)(4)
3.0 V
0 1.8 2.1 2.9 2.8 5.8 8.3 µA 1 1.9 2.3 2.9 6.1 2 2.0 2.4 3.0 6.3 3 2.0 2.5 3.9 3.1 6.4 9.3 0 1.1 1.4 2.7 1.9 4.9 7.4
I
LPM3,VLO
Low-power mode 3, VLO mode
(7)(4)
3.0 V µA
1 1.1 1.4 2.0 5.2 2 1.2 1.5 2.1 5.3 3 1.3 1.6 3.0 2.2 5.4 8.5 0 0.9 1.1 1.5 1.8 4.8 7.3
I
LPM4
Low-power mode 4
(8)(4)
3.0 V µA
1 1.1 1.2 2.0 5.1 2 1.2 1.2 2.1 5.2 3 1.3 1.3 1.6 2.2 5.3 8.1
I
LPM4.5
Low-power mode 4.5
(9)
3.0 V 0.15 0.18 0.35 0.26 0.5 1.0 µA
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. (2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0); f USB disabled (VUSBEN = 0, SLDOEN = 0).
(4) Current for brownout, high-side supervisor (SVSH) normal mode included. Low-side supervisor and monitor disabled (SVSL, SVML).
High-side monitor disabled (SVMH). RAM retention enabled.
(5) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2); f MHz operation, DCO bias generator enabled. USB disabled (VUSBEN = 0, SLDOEN = 0)
(6) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); f USB disabled (VUSBEN = 0, SLDOEN = 0)
(7) Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); f USB disabled (VUSBEN = 0, SLDOEN = 0)
(8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4); f
USB disabled (VUSBEN = 0, SLDOEN = 0)
(9) Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5); f
(1) (2)
= 1 MHz
= 0 MHz; DCO setting = 1
= 0 MHz
SMCLK
µA
µA
22 Specifications Copyright © 2009–2015, Texas Instruments Incorporated
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5.6 Thermal Characteristics
θ
θ
θ
Junction-to-ambient thermal resistance, still air °C/W
JA
Junction-to-case thermal resistance VQFN (RGC) 12 °C/W
JC
Junction-to-board thermal resistance VQFN (RGC) 6 °C/W
JB
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SLAS590M –MARCH 2009–REVISED NOVEMBER 2015
PARAMETER VALUE UNIT
LQFP (PN) 70
Low-K board (JESD51-3) VQFN (RGC) 55
BGA (ZQE) 84 LQFP (PN) 45
High-K board (JESD51-7) VQFN (RGC) 25
BGA (ZQE) 46 LQFP (PN) 12
BGA (ZQE) 30 LQFP (PN) 22
BGA (ZQE) 20
Copyright © 2009–2015, Texas Instruments Incorporated Specifications 23
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SLAS590M –MARCH 2009–REVISED NOVEMBER 2015
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5.7 Schmitt-Trigger Inputs – General-Purpose I/O
(1)
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
V
V
V
R C
Positive-going input threshold voltage V
IT+
Negative-going input threshold voltage V
IT–
Input voltage hysteresis (V
hys
Pullup and pulldown resistor
Pull
Input capacitance VIN= VSSor V
I
IT+
– V
) V
IT–
(2)
For pullup: VIN= V For pulldown: VIN= V
SS
CC
CC
CC
1.8 V 0.80 1.40 3 V 1.50 2.10
1.8 V 0.45 1.00 3 V 0.75 1.65
1.8 V 0.3 0.85 3 V 0.4 1.0
(1) Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN). (2) Also applies toRST pin when pullup or pulldown resistor is enabled.
5.8 Inputs – Ports P1 and P2
(1)
MIN TYP MAX UNIT
20 35 50 kΩ
(P1.0 to P1.7, P2.0 to P2.7)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
t
External interrupt timing
(int)
(2)
External trigger pulse duration to set interrupt flag 2.2 V, 3 V 20 ns
(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions. (2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t
shorter than t
(int)
.
is met. It may be set by trigger signals
(int)
CC
5 pF
MIN MAX UNIT
5.9 Leakage Current – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
I
lkg(Px.x)
PARAMETER TEST CONDITIONS V
High-impedance leakage current
(1) (2)
CC
1.8 V, 3 V –50 50 nA
(1) The leakage current is measured with VSSor VCCapplied to the corresponding pin(s), unless otherwise noted. (2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
MIN MAX UNIT
5.10 Outputs – General-Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
V
V
High-level output voltage V
OH
Low-level output voltage V
OL
(1) The maximum total current, I
specified.
(2) The maximum total current, I
drop specified.
(OHmax)
(OHmax)
and I and I
I
= –3 mA
(OHmax)
I
= –10 mA
(OHmax)
I
= –5 mA
(OHmax)
I
= –15 mA
(OHmax)
I
= 3 mA
(OLmax)
I
= 10 mA
(OLmax)
I
= 5 mA
(OLmax)
I
= 15 mA
(OLmax)
, for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
(OLmax)
, for all outputs combined should not exceed ±100 mA to hold the maximum voltage
(OLmax)
(1)
(2)
(1)
(2)
(1)
(2)
(1)
(2)
CC
1.8 V
3 V
1.8 V
3 V
MIN MAX UNIT
VCC– 0.25 V VCC– 0.60 V VCC– 0.25 V VCC– 0.60 V
VSSVSS+ 0.25 VSSVSS+ 0.60 VSSVSS+ 0.25 VSSVSS+ 0.60
CC CC CC CC
24 Specifications Copyright © 2009–2015, Texas Instruments Incorporated
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SLAS590M –MARCH 2009–REVISED NOVEMBER 2015
5.11 Outputs – General-Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
I
(OHmax)
I
V
V
High-level output voltage V
OH
Low-level output voltage V
OL
(OHmax)
I
(OHmax)
I
(OHmax)
I
(OLmax)
I
(OLmax)
I
(OLmax)
I
(OLmax)
(1) Selecting reduced drive strength may reduce EMI. (2) The maximum total current, I
specified.
(3) The maximum total current, I
drop specified.
(OHmax)
(OHmax)
and I and I
(OLmax)
(OLmax)
= –1 mA = –3 mA = –2 mA
= –6 mA = 1 mA = 3 mA = 2 mA = 6 mA
(2) (3) (2)
(3) (2) (3) (2) (3)
, for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop , for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
CC
1.8 V
3.0 V
1.8 V
3.0 V
VCC– 0.25 V VCC– 0.60 V VCC– 0.25 V VCC– 0.60 V
(1)
MIN MAX UNIT
CC CC CC CC
VSSVSS+ 0.25 VSSVSS+ 0.60 VSSVSS+ 0.25 VSSVSS+ 0.60
5.12 Output Frequency – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
VCC= 1.8 V,
f
Px.y
Port output frequency (with load)
See
(1)(2)
PMMCOREVx = 0 VCC= 3 V,
PMMCOREVx = 3 VCC= 1.8 V,
PMMCOREVx = 0 VCC= 3 V,
PMMCOREVx = 3
f
Port_CLK
ACLK,
Clock output frequency MHz
SMCLK, MCLK, CL= 20 pF
(2)
(1) A resistive divider with 2 × R1 between VCCand VSSis used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL= 20 pF is connected to the output to VSS.
(2) The output voltage reaches at least 10% and 90% VCCat the specified toggle frequency.
16
MHz
25
16
25
Copyright © 2009–2015, Texas Instruments Incorporated Specifications 25
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-25.0
-20.0
-15.0
-10.0
-5.0
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
T = 25°C
A
T = 85°C
A
V = 3.0 V Px.y
CC
V – High-Level Output Voltage – V
OH
I – Typical High-Level Output Current – mA
OH
-8.0
-7.0
-6.0
-5.0
-4.0
-3.0
-2.0
-1.0
0.0
0.0 0.5 1.0 1.5 2.0
T = 25°C
A
T = 85°C
A
V = 1.8 V Px.y
CC
V – High-Level Output Voltage – V
OH
I – Typical High-Level Output Current – mA
OH
0.0
5.0
10.0
15.0
20.0
25.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
T = 25°C
A
T = 85°C
A
V = 3.0 V Px.y
CC
V – Low-Level Output Voltage – V
OL
I – Typical Low-Level Output Current – mA
OL
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
0.0 0.5 1.0 1.5 2.0
T = 25°C
A
T = 85°C
A
V = 1.8 V Px.y
CC
V – Low-Level Output Voltage – V
OL
I – Typical Low-Level Output Current – mA
OL
MSP430F5529,MSP430F5528,MSP430F5527,MSP430F5526 MSP430F5525,MSP430F5524,MSP430F5522,MSP430F5521 MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
SLAS590M –MARCH 2009–REVISED NOVEMBER 2015
5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
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Figure 5-2. Typical Low-Level Output Current vs Low-Level
Figure 5-4. Typical High-Level Output Current vs High-Level
Output Voltage
Output Voltage
Figure 5-3. Typical Low-Level Output Current vs Low-Level
Figure 5-5. Typical High-Level Output Current vs High-Level
Output Voltage
Output Voltage
26 Specifications Copyright © 2009–2015, Texas Instruments Incorporated
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-20
-16
-12
-8
-4
0
0.0 0.5 1.0 1.5 2.0
T = 25°C
A
T = 85°C
A
V = 1.8 V Px.y
CC
V – High-Level Output Voltage – V
OH
I – Typical High-Level Output Current – mA
OH
-60.0
-55.0
-50.0
-45.0
-40.0
-35.0
-30.0
-25.0
-20.0
-15.0
-10.0
-5.0
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
T = 25°C
A
T = 85°C
A
V = 3.0 V Px.y
CC
V – High-Level Output Voltage – V
OH
I – Typical High-Level Output Current – mA
OH
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
40.0
45.0
50.0
55.0
60.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
T = 25°C
A
T = 85°C
A
V = 3.0 V Px.y
CC
V – Low-Level Output Voltage – V
OL
I – Typical Low-Level Output Current – mA
OL
0
4
8
12
16
20
24
0.0 0.5 1.0 1.5 2.0
T = 25°C
A
T = 85°C
A
V = 1.8 V Px.y
CC
V – Low-Level Output Voltage – V
OL
I – Typical Low-Level Output Current – mA
OL
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SLAS590M –MARCH 2009–REVISED NOVEMBER 2015
5.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
Figure 5-6. Typical Low-Level Output Current vs Low-Level
Figure 5-8. Typical High-Level Output Current vs High-Level
Copyright © 2009–2015, Texas Instruments Incorporated Specifications 27
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Output Voltage
Output Voltage
Figure 5-7. Typical Low-Level Output Current vs Low-Level
Figure 5-9. Typical High-Level Output Current vs High-Level
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Output Voltage
Output Voltage
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5.15 Crystal Oscillator, XT1, Low-Frequency Mode
(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
ΔI
DVCC.LF
f
XT1,LF0
f
XT1,LF,SW
PARAMETER TEST CONDITIONS V
f
= 32768 Hz, XTS = 0, XT1BYPASS = 0,
OSC
Differential XT1 oscillator crystal current consumption f from lowest drive setting, LF XT1DRIVEx = 2, TA= 25°C mode
XT1 oscillator crystal frequency, LF mode
XT1 oscillator logic-level square-wave input frequency, XTS = 0, XT1BYPASS = 1
XT1DRIVEx = 1, TA= 25°C
= 32768 Hz, XTS = 0, XT1BYPASS = 0,
OSC
f
= 32768 Hz, XTS = 0, XT1BYPASS = 0,
OSC
XT1DRIVEx = 3, TA= 25°C XTS = 0, XT1BYPASS = 0 32768 Hz
(2) (3)
LF mode
CC
3.0 V 0.170 µA
XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0,
OA
C
L,eff
= 32768 Hz, C
LF
Oscillation allowance for LF crystals
(4)
XT1,LF
XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1, f
= 32768 Hz, C
XT1,LF
XTS = 0, XCAPx = 0
Integrated effective load capacitance, LF mode
(5)
XTS = 0, XCAPx = 1 5.5 XTS = 0, XCAPx = 2 8.5
L,eff
L,eff
(6)
= 6 pF
= 12 pF
f
XTS = 0, XCAPx = 3 12.0 XTS = 0, Measured at ACLK,
f
= 32768 Hz
XT1,LF
(8)
XTS = 0 f
= 32768 Hz, XTS = 0, XT1BYPASS = 0,
OSC
XT1DRIVEx = 0, TA= 25°C, C f
= 32768 Hz, XTS = 0, XT1BYPASS = 0,
OSC
XT1DRIVEx = 3, TA= 25°C, C
L,eff
L,eff
= 6 pF
= 12 pF
f
Fault,LF
t
START,LF
Duty cycle, LF mode 30% 70% Oscillator fault frequency,
LF mode
(7)
Start-up time, LF mode 3.0 V ms
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this data sheet. (3) Maximum frequency of operation of the entire device cannot be exceeded. (4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
• For XT1DRIVEx = 0, C
• For XT1DRIVEx = 1, 6 pF ≤ C
• For XT1DRIVEx = 2, 6 pF ≤ C
• For XT1DRIVEx = 3, C
(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
L,eff
L,eff
≤ 6 pF.
L,eff L,eff
≥ 6 pF.
≤ 9 pF. ≤ 10 pF.
Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal. (6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. (7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies between the MIN and MAX specifications might set the flag. (8) Measured with logic-level input frequency but also applies to operation with crystals.
MIN TYP MAX UNIT
0.075
0.290
10 32.768 50 kHz
210
kΩ
300
1
pF
10 10000 Hz
1000
500
28 Specifications Copyright © 2009–2015, Texas Instruments Incorporated
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SLAS590M –MARCH 2009–REVISED NOVEMBER 2015
5.16 Crystal Oscillator, XT2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
f
= 4 MHz, XT2OFF = 0, XT2BYPASS = 0,
OSC
XT2DRIVEx = 0, TA= 25°C f
= 12 MHz, XT2OFF = 0, XT2BYPASS = 0,
OSC
I
DVCC.XT2
f
XT2,HF0
f
XT2,HF1
f
XT2,HF2
f
XT2,HF3
f
XT2,HF,SW
XT2 oscillator crystal current consumption
XT2 oscillator crystal frequency, mode 0
XT2 oscillator crystal frequency, mode 1
XT2 oscillator crystal frequency, mode 2
XT2 oscillator crystal frequency, mode 3
XT2 oscillator logic-level square-wave input XT2BYPASS = 1 frequency, bypass mode
XT2DRIVEx = 1, TA= 25°C f
= 20 MHz, XT2OFF = 0, XT2BYPASS = 0,
OSC
XT2DRIVEx = 2, TA= 25°C f
= 32 MHz, XT2OFF = 0, XT2BYPASS = 0,
OSC
XT2DRIVEx = 3, TA= 25°C XT2DRIVEx = 0, XT2BYPASS = 0
XT2DRIVEx = 1, XT2BYPASS = 0
XT2DRIVEx = 2, XT2BYPASS = 0
XT2DRIVEx = 3, XT2BYPASS = 0
(4) (3)
(3)
(3)
(3)
(3)
XT2DRIVEx = 0, XT2BYPASS = 0, f
XT2,HF0
= 6 MHz, C
L,eff
= 15 pF
XT2DRIVEx = 1, XT2BYPASS = 0,
OA
= 12 MHz, C
HF
Oscillation allowance for HF crystals
(5)
XT2,HF1
XT2DRIVEx = 2, XT2BYPASS = 0, f
= 20 MHz, C
XT2,HF2
L,eff
L,eff
= 15 pF
= 15 pF
f
XT2DRIVEx = 3, XT2BYPASS = 0, f
t
START,HF
= 32 MHz, C
XT2,HF3
f
= 6 MHz, XT2BYPASS = 0, XT2DRIVEx = 0,
OSC
Start-up time 3.0 V ms
TA= 25°C, C f
OSC
TA= 25°C, C
L,eff
= 20 MHz, XT2BYPASS = 0, XT2DRIVEx = 2,
L,eff
L,eff
= 15 pF
= 15 pF
= 15 pF
Integrated effective load
C
L,eff
f
Fault,HF
capacitance, HF 1 pF
(6)(1)
mode Duty cycle Measured at ACLK, f Oscillator fault
frequency
(7)
XT2BYPASS = 1
(8)
= 20 MHz 40% 50% 60%
XT2,HF2
(1) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. In general, an effective load capacitance
of up to 18 pF can be supported. (2) To improve EMI on the XT2 oscillator the following guidelines should be observed.
• Keep the traces between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
• Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
• If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(3) This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device
operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation. (4) When XT2BYPASS is set, the XT2 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined
in the Schmitt-trigger Inputs section of this data sheet. (5) Oscillation allowance is based on a safety factor of 5 for recommended crystals. (6) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal. (7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies between the MIN and MAX specifications might set the flag. (8) Measured with logic-level input frequency but also applies to operation with crystals.
CC
3.0 V µA
(1) (2)
MIN TYP MAX UNIT
200
260
325
450
4 8 MHz
8 16 MHz
16 24 MHz
24 32 MHz
0.7 32 MHz
450
320
Ω
200
200
0.5
0.3
30 300 kHz
Copyright © 2009–2015, Texas Instruments Incorporated Specifications 29
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SLAS590M –MARCH 2009–REVISED NOVEMBER 2015
5.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
f
VLO
df
VLO/dT
df
VLO
VLO frequency Measured at ACLK 1.8 V to 3.6 V 6 9.4 14 kHz VLO frequency temperature drift Measured at ACLK
/dVCCVLO frequency supply voltage drift Measured at ACLK
(1) (2)
CC
1.8 V to 3.6 V 0.5 %/°C
1.8 V to 3.6 V 4 %/V
Duty cycle Measured at ACLK 1.8 V to 3.6 V 40% 50% 60%
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C)) (2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
MIN TYP MAX UNIT
5.18 Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
I
REFO
PARAMETER TEST CONDITIONS V
REFO oscillator current consumption TA= 25°C 1.8 V to 3.6 V 3 µA
CC
REFO frequency calibrated Measured at ACLK 1.8 V to 3.6 V 32768 Hz
f
REFO
df
REFO/dT
df
REFO
/dV
REFO absolute tolerance calibrated
REFO frequency temperature drift Measured at ACLK REFO frequency supply voltage drift Measured at ACLK
CC
Full temperature range 1.8 V to 3.6 V –3.5% 3.5% TA= 25°C 3 V –1.5% 1.5%
(1) (2)
1.8 V to 3.6 V 0.01 %/°C
1.8 V to 3.6 V 1.0 %/V
Duty cycle Measured at ACLK 1.8 V to 3.6 V 40% 50% 60%
t
START
REFO start-up time 40%/60% duty cycle 1.8 V to 3.6 V 25 µs
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C)) (2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
MIN TYP MAX UNIT
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30 Specifications Copyright © 2009–2015, Texas Instruments Incorporated
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