Texas Instruments MSP430F533x, MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333 User Manual

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MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333

SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

MSP430F533x Mixed-Signal Microcontrollers

1 Device Overview

1.1 Features

• Low Supply Voltage Range: 1.8 V to 3.6 V • Four 16-Bit Timers With 3, 5, or 7

• Ultra-Low Power Consumption – Active Mode (AM):

All System Clocks Active: 270 µA/MHz at 8 MHz, 3.0 V, Flash Program – USCI_A0 and USCI_A1 Each Support: Execution (Typical)

– Standby Mode (LPM3):

Watchdog With Crystal and Supply Supervisor Operational, Full RAM Retention, Fast Wakeup:

1.8 µA at 2.2 V, 2.1 µA at 3.0 V (Typical)

– Shutdown Real-Time Clock (RTC) Mode

(LPM3.5): Shutdown Mode, Active RTC With Crystal:

1.1 µA at 3.0 V (Typical)

– Shutdown Mode (LPM4.5):

0.3 µA at 3.0 V (Typical)

• Wake up From Standby Mode in 3 µs (Typical)

• 16-Bit RISC Architecture, Extended Memory, up to 20-MHz System Clock

• Flexible Power-Management System – Fully Integrated LDO With Programmable

Regulated Core Supply Voltage

– Supply Voltage Supervision, Monitoring, and

Brownout

• Unified Clock System – FLL Control Loop for Frequency Stabilization – Low-Power Low-Frequency Internal Clock

Source (VLO)

– Low-Frequency Trimmed Internal Reference

Source (REFO) – 32-kHz Crystals (XT1) – High-Frequency Crystals up to 32 MHz (XT2)

Capture/Compare Registers

• Two Universal Serial Communication Interfaces (USCIs)

• Enhanced UART Supports Automatic BaudRate Detection

• IrDA Encoder and Decoder

• Synchronous SPI

– USCI_B0 and USCI_B1 Each Support:

• I2C

• Synchronous SPI

• Integrated 3.3-V Power System

• 12-Bit Analog-to-Digital Converter (ADC) With Internal Shared Reference, Sample-and-Hold, and Autoscan Feature

• Dual 12-Bit Digital-to-Analog Converters (DACs) With Synchronization

• Voltage Comparator

• Hardware Multiplier Supports 32-Bit Operations

• Serial Onboard Programming, No External Programming Voltage Needed

• Six-Channel Internal DMA

• RTC Module With Supply Voltage Backup Switch

• Table 3-1 Summarizes the Available Family Members

• For Complete Module Descriptions, See the

MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208)

1.2 Applications

• Analog and Digital Sensor Systems • Thermostats

• Digital Motor Control • Digital Timers

• Remote Controls • Hand-Held Meters

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333

SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

1.3 Description

The TI MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from lowpower modes to active mode in 3 µs (typical).

The MSP430F533x devices are microcontrollers with an integrated 3.3-V LDO, a high-performance 12-bit ADC, a comparator, two USCIs, a hardware multiplier, DMA, four 16-bit timers, an RTC module with alarm capabilities, and up to 74 I/O pins.

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Device Information

PART NUMBER PACKAGE BODY SIZE

MSP430F5338IPZ LQFP (100) 14 mm × 14 mm MSP430F5338IZQW BGA (113) 7 mm × 7 mm

(1) For the most current device, package, and ordering information, see the Package Option Addendum in

Section 8, or see the TI website at www.ti.com.

(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the

Mechanical Data in Section 8.

(1)

(2)

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Unified

Clock

System

256KB 128KB

Flash

18KB/

10KB

RAM

+8B Backup

RAM

MCLK

ACLK

SMCLK

I/O Ports

P1/P2

2×8 I/Os

Interrupt

Capability

1×16 I/Os

CPUXV2

and

Working

Registers

EEM

(L: 8+2)

XIN

XOUT

JTAG/

SBW

Interface/

Port PJ

PA PB PC PD

DMA

6 Channel

XT2IN

XT2OUT

Power

Management

LDO SVM/SVS Brownout

SYS

Watchdog

P2 Port

Mapping

Controller

I/O Ports

P3/P4

2×8 I/Os

Interrupt

Capability

1×16 I/Os

I/O Ports

P5/P6

2×8 I/Os

1×16 I/Os

I/O Ports

P7/P8

1×6 I/Os

1×14 I/Os

1×8 I/Os

I/O Ports

1×8 I/Os

MPY32

TA0

Timer_A

5 CC

Registers

TA1 and

TA2

2 Timer_A

each with

3 CC

Registers

TB0

Timer_B

7 CC

Registers

CRC16

USCI0,1

Ax: UART,

IrDA, SPI

Bx: SPI, I2C

ADC12_A

200 KSPS

16 Channels (12 ext/4 int)

Autoscan

12 Bit

DVCCDVSSAVCCAV

P1.x P2.x

P3.x

P4.x

P5.x P6.x

P7.x

P8.x P9.x

RST/NMI

REF

Reference

1.5V, 2.0V,

2.5V

Comp_B

PJ.x

RTC_B

Battery Backup System

PU Port

LDO

PU.0 PU.1

LDOO

LDOI

Unified

Clock

System

256KB 128KB

Flash

MCLK

ACLK

SMCLK

I/O Ports

P1/P2

2×8 I/Os

Interrupt

Capability

1×16 I/Os

CPUXV2

and

Working

Registers

EEM

(L: 8+2)

XIN

XOUT

JTAG/

SBW

Interface/

Port PJ

PA PB PC PD

DMA

6 Channel

XT2IN

XT2OUT

Power

Management

LDO SVM/SVS Brownout

SYS

Watchdog

P2 Port

Mapping

Controller

I/O Ports

P3/P4

2×8 I/Os

Interrupt

Capability

1×16 I/Os

I/O Ports

P5/P6

2×8 I/Os

1×16 I/Os

I/O Ports

P7/P8

1×6 I/Os

1×14 I/Os

1×8 I/Os

I/O Ports

1×8 I/Os

MPY32

TA0

Timer_A

5 CC

Registers

TA1 and

TA2

2 Timer_A

each with

3 CC

Registers

TB0

Timer_B

7 CC

Registers

RTC_B

Battery Backup System

CRC16

USCI0,1

Ax: UART,

IrDA, SPI

Bx: SPI, I2C

ADC12_A

200 KSPS

16 Channels (12 ext/4 int)

Autoscan

12 Bit

DVCCDVSSAVCCAV

P1.x P2.x

P3.x

P4.x

P5.x P6.x

P7.x

P8.x P9.x

RST/NMI

REF

Reference

1.5V, 2.0V,

2.5V

DAC12_A

12 bit 2 channels voltage out

Comp_B

PJ.x

18KB

RAM

+8B Backup

RAM

PU Port

LDO

PU.0 PU.1

LDOO

LDOI

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1.4 Functional Block Diagrams

Figure 1-1 shows the functional block diagram for the MSP430F5338 and MSP430F5336 devices.

MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333

SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

Figure 1-1. Functional Block Diagram – MSP430F5338, MSP430F5336

Figure 1-2 shows the functional block diagram for the MSP430F5335 and MSP430F5333 devices.

Figure 1-2. Functional Block Diagram – MSP430F5335, MSP430F5333

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MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333

SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

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Table of Contents

1 Device Overview ......................................... 1 5.30 USCI (UART Mode) ................................. 31

1.1 Features .............................................. 1 5.31 USCI (SPI Master Mode)............................ 31

1.2 Applications........................................... 1 5.32 USCI (SPI Slave Mode)............................. 33

1.3 Description............................................ 2 5.33 USCI (I2C Mode) .................................... 35

1.4 Functional Block Diagrams........................... 3

2 Revision History ......................................... 5

3 Device Comparison ..................................... 6

4 Terminal Configuration and Functions.............. 7

4.1 Pin Designation – MSP430F5338IPZ,

MSP430F5336IPZ.................................... 7

4.2 Pin Designation – MSP430F5335IPZ,

MSP430F5333IPZ.................................... 8

4.3 Pin Designation – MSP430F5338IZQW, MSP430F5336IZQW, MSP430F5335IZQW,

MSP430F5333IZQW ................................. 9 5.40 REF, External Reference ........................... 39

4.4 Signal Descriptions.................................. 10 5.41 REF, Built-In Reference............................. 40

5 Specifications........................................... 15 5.42 12-Bit DAC, Supply Specifications.................. 41

5.1 Absolute Maximum Ratings......................... 15 5.43 12-Bit DAC, Linearity Specifications ................ 41

5.2 ESD Ratings ........................................ 15 5.44 12-Bit DAC, Output Specifications .................. 43

5.3 Recommended Operating Conditions............... 15 5.45 12-Bit DAC, Reference Input Specifications ........ 44

5.4 Active Mode Supply Current Into VCCExcluding

External Current..................................... 17

5.5 Low-Power Mode Supply Currents (Into VCC)

Excluding External Current.......................... 17

5.6 Thermal Resistance Characteristics ................ 18

5.7 Schmitt-Trigger Inputs – General-Purpose I/O...... 19

5.8 Inputs – Ports P1, P2, P3, and P4.................. 19

5.9 Leakage Current – General-Purpose I/O ........... 19

5.10 Outputs – General-Purpose I/O (Full Drive

Strength) ............................................ 19

5.11 Outputs – General-Purpose I/O (Reduced Drive

Strength) ............................................ 20

5.12 Output Frequency – Ports P1, P2, and P3.......... 20

5.13 Typical Characteristics – Outputs, Reduced Drive

Strength (PxDS.y = 0)............................... 21

5.14 Typical Characteristics – Outputs, Full Drive

Strength (PxDS.y = 1)............................... 22

5.15 Crystal Oscillator, XT1, Low-Frequency Mode ..... 23

5.16 Crystal Oscillator, XT2 .............................. 24

5.17 Internal Very-Low-Power Low-Frequency Oscillator

(VLO)................................................ 25

5.18 Internal Reference, Low-Frequency Oscillator 6.12 Peripherals .......................................... 57

(REFO) .............................................. 25

5.19 DCO Frequency..................................... 26

5.20 PMM, Brownout Reset (BOR)....................... 27

5.21 PMM, Core Voltage ................................. 27

5.22 PMM, SVS High Side ............................... 28

5.23 PMM, SVM High Side............................... 28

5.24 PMM, SVS Low Side................................ 29

5.25 PMM, SVM Low Side ............................... 29

5.26 Wake-up Times From Low-Power Modes and

Reset ................................................ 29

5.27 Timer_A, Timers TA0, TA1, and TA2............... 30

5.28 Timer_B, Timer TB0 ................................ 30

5.29 Battery Backup ...................................... 30

5.34 12-Bit ADC, Power Supply and Input Range

Conditions ........................................... 36

5.35 12-Bit ADC, Timing Parameters .................... 36

5.36 12-Bit ADC, Linearity Parameters Using an External

Reference Voltage .................................. 37

5.37 12-Bit ADC, Linearity Parameters Using AVCC as

Reference Voltage .................................. 37

5.38 12-Bit ADC, Linearity Parameters Using the Internal

Reference Voltage .................................. 37

5.39 12-Bit ADC, Temperature Sensor and Built-In V

5.46 12-Bit DAC, Dynamic Specifications................ 44

5.47 12-Bit DAC, Dynamic Specifications (Continued)... 45

5.48 Comparator_B....................................... 46

5.49 Ports PU.0 and PU.1................................ 47

5.50 LDO-PWR (LDO Power System) ................... 48

5.51 Flash Memory ....................................... 49

5.52 JTAG and Spy-Bi-Wire Interface.................... 49

MID

6 Detailed Description ................................... 50

6.1 Overview ............................................ 50

6.2 CPU ................................................. 50

6.3 Instruction Set....................................... 51

6.4 Operating Modes.................................... 52

6.5 Interrupt Vector Addresses.......................... 53

6.6 Memory.............................................. 54

6.7 Bootloader (BSL).................................... 55

6.8 JTAG Operation ..................................... 55

6.9 Flash Memory (Link to User's Guide)............... 56

6.10 RAM (Link to User's Guide)......................... 57

6.11 Backup RAM ........................................ 57

6.13 Input/Output Schematics ............................ 79

6.14 Device Descriptors................................. 100

7 Device and Documentation Support.............. 101

7.1 Device Support..................................... 101

7.2 Documentation Support............................ 104

7.3 Related Links ...................................... 104

7.4 Community Resources............................. 105

7.5 Trademarks ........................................ 105

7.6 Electrostatic Discharge Caution ................... 105

7.7 Export Control Notice .............................. 105

7.8 Glossary............................................ 105

8 Mechanical, Packaging, and Orderable

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Information............................................. 105

SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from August 5, 2013 to December 8, 2015 Page

• Document format and organization changes throughout, including addition of section numbering........................ 1

• Moved all functional block diagrams to Section 1.4, Functional Block Diagrams ............................................ 3

• Added USB column to Table 3-1, Family Members ............................................................................. 6

• Added Section 3, Device Comparison, and moved Table 3-1, Family Members to it ....................................... 6

• Added "Port U is supplied by the LDOO rail" to the PU.0 and PU.1 descriptions in Table 4-1, Signal Descriptions .. 13

• Moved all electrical specifications to Section 5 ................................................................................. 15

• Added Section 5.2, ESD Ratings.................................................................................................. 15

• Added note to C

• Added Section 5.6, Thermal Characteristics .................................................................................... 18

• Added note to R

• Changed TYP value of C

• In V

parameter description, changed from "V

BAT3

• Changed from f

crosstalk" parameter ................................................................................................................ 45

• Changed the value of DAC12_xDAT from 7F7h to F7Fh and changed the x-axis label from f

Figure 5-22, Crosstalk Test Conditions .......................................................................................... 45

• Corrected the spelling of the MRG bits in the f

• Removed RTC_B from LPM4.5 wake-up options............................................................................... 52

• Throughout document, changed all instances of "bootstrap loader" to "bootloader"....................................... 55

• Added the paragraph that starts "The application report Using the MSP430 RTC_B..." .................................. 59

• Corrected names of interrupt events PMMSWBOR (BOR) and PMMSWPOR (POR) in Table 6-10, System

Module Interrupt Vector Registers ................................................................................................ 60

• Corrected spelling of NMIIFG (added missing "I") in Table 6-10, System Module Interrupt Vector Registers.......... 60

• Added P7SEL.2 and XT2BYPASS inputs with AND and OR gates in Figure 6-10, Port P7 (P7.3) Schematic ........ 92

• Changed P7SEL.3 column from X to 0 for "P7.3 (I/O)" rows.................................................................. 92

• Changed Table 6-60, Port PU.0, PU.1 Functions............................................................................... 97

• Added Section 7 and moved Development Tools Support, Device and Development Tool Nomenclature,

Trademarks, and Electrostatic Discharge Caution sections to it ............................................................ 101

• Added Section 8, Mechanical, Packaging, and Orderable Information..................................................... 105

............................................................................................................... 15

VCORE

.................................................................................................................. 19

Pull

DAC12_0OUT

with Test Conditions of "XTS = 0, XCAPx = 0" from 2 pF to 1 pF ......................... 23

L,eff

to f

DAC12_1OUT

in the first row of the Test Conditions for the "Channel-to-channel

BAT3

MCLK,MRG

≠ V

/3" to "V

BAT

BAT3

= V

/3" ........................................ 30

BAT

to 1/f

Toggle

parameter........................................................... 49

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SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

3 Device Comparison

Table 3-1 summarizes the available family members.

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Table 3-1. Family Members

USCI

DEVICE Timer_A

MSP430F5338 256 18 5, 3, 3 7 2 2 2 12 No 74

MSP430F5336 128 18 5, 3, 3 7 2 2 2 12 No 74

MSP430F5335 256 18 5, 3, 3 7 2 2 - 12 No 74

MSP430F5333 128 10 5, 3, 3 7 2 2 - 12 No 74

FLASH SRAM ADC12_A DAC12_A Comp_B

(KB) (KB) (Ch) (Ch) (Ch)

(3)

Timer_B

CHANNEL CHANNEL

(4)

A: B:

UART,

IrDA, SPI

SPI, I2C

(1)(2)

USB I/O PACKAGE

12 ext, 100 PZ,

4 int 113 ZQW

12 ext, 100 PZ,

4 int 113 ZQW

12 ext, 100 PZ,

4 int 113 ZQW

12 ext, 100 PZ,

4 int 113 ZQW

(1) For the most current package and ordering information, see the Package Option Addendum in Section 8, or see the TI website at

www.ti.com.

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/packaging.

(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM

output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.

(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM

output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.

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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

100

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

P6.4/CB4/A4

P6.5/CB5/A5 P6.6/CB6/A6/DAC0 P6.7/CB7/A7/DAC1

P7.4/CB8/A12 P7.5/CB9/A13

P7.6/CB10/A14/DAC0

P7.7/CB11/A15/DAC1

P5.0/VREF+/VeREF+ P5.1/VREF−/VeREF−

AVCC1 AVSS1

XIN

XOUT

DVCC1

DVSS1

VCORE

P5.2

DVSS

DNC

P5.3

P9.7

P9.6 P9.5 P9.4 P9.3 P9.2 P9.1 P9.0 P8.7 P8.6/UCB1SOMI/UCB1SCL P8.5/UCB1SIMO/UCB1SDA DVCC2 DVSS2

P2.0/P2MAP0

MSP430F5338 MSP430F5336

PZ PACKAGE

(TOP VIEW)

P6.3/CB3/A3

P6.2/CB2/A2

P6.1/CB1/A1

P6.0/CB0/A0

RST/NMI/SBWTDIO

PJ.3/TCK

PJ.2/TMS

PJ.1/TDI/TCLK

PJ.0/TDO

TEST/SBWTCK

P7.3/XT2OUT

P7.2/XT2IN

LDOI

LDOO

PU.1

PU.0

VSSU

AVSS3

P1.3/TA0.2

P1.4/TA0.3

AVSS2

P5.6/ADC12CLK/DMAE0

P5.4

P5.5

P1.0/TA0CLK/ACLK

P3.0/TA1CLK/CBOUT

P3.1/TA1.0

P3.2/TA1.1

P1.6/TA0.1

P1.7/TA0.2

P1.1/TA0.0

P1.2/TA0.1

P1.5/TA0.4

P3.3/TA1.2

P3.4/TA2CLK/SMCLK

P3.5/TA2.0

P3.6/TA2.1

P3.7/TA2.2

P4.0/TB0.0

P4.2/TB0.2 P4.1/TB0.1

P4.4/TB0.4 P4.3/TB0.3

P4.6/TB0.6 P4.5/TB0.5

P8.0/TB0CLK P4.7/TB0OUTH/SVMOUT

P8.4/UCB1CLK/UCA1STE

VBAK

P2.1/P2MAP1 P2.2/P2MAP2 P2.3/P2MAP3 P2.4/P2MAP4 P2.5/P2MAP5 P2.6/P2MAP6 P2.7/P2MAP7

DVCC3

DVSS3

VBAT

P5.7/RTCCLK

P8.1/UCB1STE/UCA1CLK

P8.2/UCA1TXD/UCA1SIMO

P8.3/UCA1RXD/UCA1SOMI

MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333

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4 Terminal Configuration and Functions

4.1 Pin Designation – MSP430F5338IPZ, MSP430F5336IPZ

Figure 4-1 shows the pinout for the MSP430F5338 and MSP430F5336 devices in the PZ package.

SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

NOTE: DNC = Do not connect

Figure 4-1. 100-Pin PZ Package (Top View) – MSP430F5338, MSP430F5336

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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

100

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

P6.4/CB4/A4

P6.5/CB5/A5

P6.6/CB6/A6

P6.7/CB7/A7

P7.4/CB8/A12 P7.5/CB9/A13

P7.6/CB10/A14

P7.7/CB11/A15 P5.0/VREF+/VeREF+ P5.1/VREF−/VeREF−

AVCC1 AVSS1

XIN

XOUT

DVCC1

DVSS1

VCORE

P5.2

DVSS

DNC

P5.3

P9.7

P9.6 P9.5 P9.4 P9.3 P9.2 P9.1 P9.0 P8.7 P8.6/UCB1SOMI/UCB1SCL P8.5/UCB1SIMO/UCB1SDA DVCC2 DVSS2

P2.0/P2MAP0

MSP430F5335 MSP430F5333

PZ PACKAGE

(TOP VIEW)

P6.3/CB3/A3

P6.2/CB2/A2

P6.1/CB1/A1

P6.0/CB0/A0

RST/NMI/SBWTDIO

PJ.3/TCK

PJ.2/TMS

PJ.1/TDI/TCLK

PJ.0/TDO

TEST/SBWTCK

P7.3/XT2OUT

P7.2/XT2IN

LDOI

LDOO

PU.1

PU.0

VSSU

AVSS3

P1.3/TA0.2

P1.4/TA0.3

AVSS2

P5.6/ADC12CLK/DMAE0

P5.4

P5.5

P1.0/TA0CLK/ACLK

P3.0/TA1CLK/CBOUT

P3.1/TA1.0

P3.2/TA1.1

P1.6/TA0.1

P1.7/TA0.2

P1.1/TA0.0

P1.2/TA0.1

P1.5/TA0.4

P3.3/TA1.2

P3.4/TA2CLK/SMCLK

P3.5/TA2.0

P3.6/TA2.1

P3.7/TA2.2

P4.0/TB0.0

P4.2/TB0.2 P4.1/TB0.1

P4.4/TB0.4 P4.3/TB0.3

P4.6/TB0.6 P4.5/TB0.5

P8.0/TB0CLK P4.7/TB0OUTH/SVMOUT

P8.4/UCB1CLK/UCA1STE

VBAK

P2.1/P2MAP1 P2.2/P2MAP2 P2.3/P2MAP3 P2.4/P2MAP4 P2.5/P2MAP5 P2.6/P2MAP6 P2.7/P2MAP7

DVCC3

DVSS3

VBAT

P5.7/RTCCLK

P8.1/UCB1STE/UCA1CLK

P8.2/UCA1TXD/UCA1SIMO

P8.3/UCA1RXD/UCA1SOMI

MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333

SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

4.2 Pin Designation – MSP430F5335IPZ, MSP430F5333IPZ

Figure 4-2 shows the pinout for the MSP430F5335 and MSP430F5333 devices in the PZ package.

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NOTE: DNC = Do not connect

Figure 4-2. 100-Pin PZ Package (Top View) – MSP430F5335, MSP430F5333

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A1 A2

A5 A6

A8 A9 A10

A11 A12

B1 B2

B5 B6

B8 B9 B10

B11 B12

C1 C2 C3 C11 C12

D1 D2 D4

D5 D6

D8 D9

D11 D12

E1 E2 E4

E5 E6

E8 E9

E11 E12

F1 F2 F4

F5 F8 F9

F11 F12

G1 G2 G4

G5 G8 G9

G11 G12

J1 J2 J4

J5 J6

J8 J9

J11 J12

H1 H2 H4

H5 H6

H8 H9

H11 H12

K1 K2 K11 K12

L1 L2

L5 L6

L8 L9 L10

L11 L12

M1 M2

M3 M5 M6

M8 M9 M10

M11 M12

ZQW PACKAGE

(TOP VIEW)

MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333

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4.3 Pin Designation – MSP430F5338IZQW, MSP430F5336IZQW, MSP430F5335IZQW, MSP430F5333IZQW

Figure 4-3 shows the pin diagram for all devices in the ZQW package. See Section 4.4 for pin

assignments and descriptions.

NOTE: For terminal assignments, see Table 4-1

Figure 4-3. 113-Pin ZQW Package (Top View) – MSP430F5338, MSP430F5336, MSP430F5335,

MSP430F5333

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4.4 Signal Descriptions

Table 4-1 describes the signals for all device variants and packages.

Table 4-1. Signal Descriptions

TERMINAL

NAME

P6.4/CB4/A4 1 A1 I/O Comparator_B input CB4

P6.5/CB5/A5 2 B2 I/O Comparator_B input CB5

P6.6/CB6/A6/DAC0 3 B1 I/O

P6.7/CB7/A7/DAC1 4 C2 I/O

P7.4/CB8/A12 5 C1 I/O Comparator_B input CB8

P7.5/CB9/A13 6 C3 I/O Comparator_B input CB9

P7.6/CB10/A14/DAC0 7 D2 I/O

P7.7/CB11/A15/DAC1 8 D1 I/O

P5.0/VREF+/VeREF+ 9 D4 I/O Output of reference voltage to the ADC

P5.1/VREF-/VeREF- 10 E4 I/O

AVCC1 11 Analog power supply AVSS1 12 F2 Analog ground supply

XIN 13 F1 I Input terminal for crystal oscillator XT1 XOUT 14 G1 O Output terminal of crystal oscillator XT1

NO. I/O

PZ ZQW

E1,

(1)

General-purpose digital I/O

Analog input A4 – ADC General-purpose digital I/O

Analog input A5 – ADC General-purpose digital I/O

Comparator_B input CB6 Analog input A6 – ADC DAC12.0 output (not available on F5335 and F5333 devices)

General-purpose digital I/O Comparator_B input CB7 Analog input A7 – ADC DAC12.1 output (not available on F5335 and F5333 devices)

General-purpose digital I/O

Analog input A12 –ADC General-purpose digital I/O

Analog input A13 – ADC General-purpose digital I/O

Comparator_B input CB10 Analog input A14 – ADC DAC12.0 output (not available on F5335 and F5333 devices)

General-purpose digital I/O Comparator_B input CB11 Analog input A15 – ADC DAC12.1 output (not available on F5335 and F5333 devices)

General-purpose digital I/O

Input for an external reference voltage to the ADC General-purpose digital I/O

Negative terminal for the reference voltage of the ADC for both sources, the internal reference voltage, or an external applied reference voltage

DESCRIPTION

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Table 4-1. Signal Descriptions (continued)

TERMINAL

NAME

NO. I/O

PZ ZQW

AVSS2 15 G2 Analog ground supply

P5.6/ADC12CLK/DMAE0 16 H1 I/O Conversion clock output ADC

P2.0/P2MAP0 17 G4 I/O

P2.1/P2MAP1 18 H2 I/O

P2.2/P2MAP2 19 J1 I/O

P2.3/P2MAP3 20 H4 I/O

P2.4/P2MAP4 21 J2 I/O

P2.5/P2MAP5 22 K1 I/O

P2.6/P2MAP6 23 K2 I/O

P2.7/P2MAP7 24 L2 I/O

DVCC1 25 L1 Digital power supply DVSS1 26 M1 Digital ground supply

(2)

VCORE

27 M2 Regulated core power supply (internal use only, no external current loading) P5.2 28 L3 I/O General-purpose digital I/O DVSS 29 M3 Digital ground supply DNC 30 J4 Do not connect. It is strongly recommended to leave this terminal open. P5.3 31 L4 I/O General-purpose digital I/O P5.4 32 M4 I/O General-purpose digital I/O P5.5 33 J5 I/O General-purpose digital I/O

P1.0/TA0CLK/ACLK 34 L5 I/O Timer TA0 clock signal TACLK input

P1.1/TA0.0 35 M5 I/O Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output

P1.2/TA0.1 36 J6 I/O Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output

P1.3/TA0.2 37 H6 I/O

(1)

DESCRIPTION

General-purpose digital I/O

DMA external trigger input General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_B0 SPI slave transmit enable; USCI_A0 clock input/output General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_B0 SPI slave in/master out; USCI_B0 I2C data General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_B0 SPI slave out/master in; USCI_B0 I2C clock General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in/master out General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_A0 UART receive data; USCI_A0 slave out/master in General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: no secondary function General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: no secondary function

General-purpose digital I/O with port interrupt

ACLK output (divided by 1, 2, 4, 8, 16, or 32) General-purpose digital I/O with port interrupt

BSL transmit output General-purpose digital I/O with port interrupt

BSL receive input General-purpose digital I/O with port interrupt

Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output

(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended

capacitor value, C

VCORE

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Table 4-1. Signal Descriptions (continued)

TERMINAL

NAME

P1.4/TA0.3 38 M6 I/O

P1.5/TA0.4 39 L6 I/O

P1.6/TA0.1 40 J7 I/O

P1.7/TA0.2 41 M7 I/O

P3.0/TA1CLK/CBOUT 42 L7 I/O Timer TA1 clock input

P3.1/TA1.0 43 H7 I/O

P3.2/TA1.1 44 M8 I/O

P3.3/TA1.2 45 L8 I/O

P3.4/TA2CLK/SMCLK 46 J8 I/O Timer TA2 clock input

P3.5/TA2.0 47 M9 I/O

P3.6/TA2.1 48 L9 I/O

P3.7/TA2.2 49 M10 I/O

P4.0/TB0.0 50 J9 I/O

P4.1/TB0.1 51 M11 I/O

P4.2/TB0.2 52 L10 I/O

P4.3/TB0.3 53 M12 I/O

P4.4/TB0.4 54 L12 I/O

P4.5/TB0.5 55 L11 I/O

P4.6/TB0.6 56 K11 I/O

NO. I/O

PZ ZQW

(1)

General-purpose digital I/O with port interrupt Timer TA0 CCR3 capture: CCI3A input compare: Out3 output

General-purpose digital I/O with port interrupt Timer TA0 CCR4 capture: CCI4A input, compare: Out4 output

General-purpose digital I/O with port interrupt Timer TA0 CCR1 capture: CCI1B input, compare: Out1 output

General-purpose digital I/O with port interrupt Timer TA0 CCR2 capture: CCI2B input, compare: Out2 output

General-purpose digital I/O with port interrupt

Comparator_B output General-purpose digital I/O with port interrupt

Timer TA1 capture CCR0: CCI0A/CCI0B input, compare: Out0 output General-purpose digital I/O with port interrupt

Timer TA1 capture CCR1: CCI1A/CCI1B input, compare: Out1 output General-purpose digital I/O with port interrupt

Timer TA1 capture CCR2: CCI2A/CCI2B input, compare: Out2 output General-purpose digital I/O with port interrupt

SMCLK output General-purpose digital I/O with port interrupt

Timer TA2 capture CCR0: CCI0A/CCI0B input, compare: Out0 output General-purpose digital I/O with port interrupt

Timer TA2 capture CCR1: CCI1A/CCI1B input, compare: Out1 output General-purpose digital I/O with port interrupt

Timer TA2 capture CCR2: CCI2A/CCI2B input, compare: Out2 output General-purpose digital I/O with port interrupt

Timer TB0 capture CCR0: CCI0A/CCI0B input, compare: Out0 output General-purpose digital I/O with port interrupt

Timer TB0 capture CCR1: CCI1A/CCI1B input, compare: Out1 output General-purpose digital I/O with port interrupt

Timer TB0 capture CCR2: CCI2A/CCI2B input, compare: Out2 output General-purpose digital I/O with port interrupt

Timer TB0 capture CCR3: CCI3A/CCI3B input, compare: Out3 output General-purpose digital I/O with port interrupt

Timer TB0 capture CCR4: CCI4A/CCI4B input, compare: Out4 output General-purpose digital I/O with port interrupt

Timer TB0 capture CCR5: CCI5A/CCI5B input, compare: Out5 output General-purpose digital I/O with port interrupt

Timer TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output

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DESCRIPTION

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Table 4-1. Signal Descriptions (continued)

TERMINAL

NAME

NO. I/O

PZ ZQW

P4.7/TB0OUTH/SVMOUT 57 K12 I/O Timer TB0: Switch all PWM outputs high impedance

P8.0/TB0CLK 58 J11 I/O

P8.1/UCB1STE/UCA1CLK 59 J12 I/O

P8.2/UCA1TXD/UCA1SIMO 60 H11 I/O

(1)

DESCRIPTION

General-purpose digital I/O with port interrupt

SVM output General-purpose digital I/O

Timer TB0 clock input General-purpose digital I/O

USCI_B1 SPI slave transmit enable; USCI_A1 clock input/output General-purpose digital I/O

USCI_A1 UART transmit data; USCI_A1 SPI slave in/master out

P8.3/UCA1RXD/UCA1SOMI 61 H12 I/O

General-purpose digital I/O USCI_A1 UART receive data; USCI_A1 SPI slave out/master in

P8.4/UCB1CLK/UCA1STE 62 G11 I/O

General-purpose digital I/O

USCI_B1 clock input/output; USCI_A1 SPI slave transmit enable DVSS2 63 G12 Digital ground supply DVCC2 64 F12 Digital power supply

P8.5/UCB1SIMO/UCB1SDA 65 F11 I/O

P8.6/UCB1SOMI/UCB1SCL 66 G9 I/O

General-purpose digital I/O

USCI_B1 SPI slave in/master out; USCI_B1 I2C data

General-purpose digital I/O

USCI_B1 SPI slave out/master in; USCI_B1 I2C clock P8.7 67 E12 I/O General-purpose digital I/O P9.0 68 E11 I/O General-purpose digital I/O P9.1 69 F9 I/O General-purpose digital I/O P9.2 70 D12 I/O General-purpose digital I/O

P9.3 71 D11 I/O

General-purpose digital I/O P9.4 72 E9 I/O General-purpose digital I/O P9.5 73 C12 I/O General-purpose digital I/O P9.6 74 C11 I/O General-purpose digital I/O P9.7 75 D9 I/O General-purpose digital I/O

VSSU 76 PU ground supply

PU.0 77 A12 I/O

B11,

B12

General-purpose digital I/O, controlled by PU control register. Port U is supplied by

the LDOO rail. NC 78 B10 No connect

PU.1 79 A11 I/O

General-purpose digital I/O, controlled by PU control register. Port U is supplied by

the LDOO rail. LDOI 80 A10 LDO input LDOO 81 A9 LDO output NC 82 B9 No connect AVSS3 83 A8 Analog ground supply

P7.2/XT2IN 84 B8 I/O

P7.3/XT2OUT 85 B7 I/O

General-purpose digital I/O

Input terminal for crystal oscillator XT2

General-purpose digital I/O

Output terminal of crystal oscillator XT2

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Table 4-1. Signal Descriptions (continued)

TERMINAL

NAME

NO. I/O

PZ ZQW

VBAK 86 A7

VBAT 87 D8

P5.7/RTCCLK 88 D7 I/O

DVCC3 89 A6 Digital power supply DVSS3 90 A5 Digital ground supply

TEST/SBWTCK 91 B6 I

PJ.0/TDO 92 B5 I/O

PJ.1/TDI/TCLK 93 A4 I/O

PJ.2/TMS 94 E7 I/O

PJ.3/TCK 95 D6 I/O

RST/NMI/SBWTDIO 96 A3 I/O Nonmaskable interrupt input

P6.0/CB0/A0 97 B4 I/O Comparator_B input CB0

P6.1/CB1/A1 98 B3 I/O Comparator_B input CB1

P6.2/CB2/A2 99 A2 I/O Comparator_B input CB2

P6.3/CB3/A3 100 D5 I/O Comparator_B input CB3

E5, E6, E8, F4, F5,

Reserved N/A F8, Reserved. TI recommends connecting to ground (DVSS, AVSS).

G5, G8, H5, H8,

(3) When this pin is configured as reset, the internal pullup resistor is enabled by default.

(1)

DESCRIPTION

Capacitor for backup subsystem. Do not load this pin externally. For capacitor

values, see C

in Recommended Operating Conditions.

BAK

Backup or secondary supply voltage. If backup voltage is not supplied, connect to

DVCC externally.

General-purpose digital I/O

RTCCLK output

Test mode pin; selects digital I/O on JTAG pins

Spy-Bi-Wire input clock

General-purpose digital I/O

Test data output port

General-purpose digital I/O

Test data input or test clock input

General-purpose digital I/O

Test mode select

General-purpose digital I/O

Test clock

Reset input (active low)

(3)

Spy-Bi-Wire data input/output

General-purpose digital I/O

Analog input A0 – ADC

General-purpose digital I/O

Analog input A1 – ADC

General-purpose digital I/O

Analog input A2 – ADC

General-purpose digital I/O

Analog input A3 – ADC

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5 Specifications

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SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

5.1 Absolute Maximum Ratings

(1)

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

Voltage applied at VCCto V

Voltage applied to any pin (excluding VCORE, VBUS, V18)

(2)

–0.3 4.1 V

–0.3 VCC+ 0.3 V Diode current at any device pin ±2 mA Maximum junction temperature, T Storage temperature, T

(3)

stg

–55 150 °C

95 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied. (3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

5.2 ESD Ratings

VALUE UNIT

Electrostatic discharge V

(ESD)

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 Charged-device model (CDM), per JEDEC specification JESD22-C101

(1)

(2)

±1000

±250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as

±1000 V may actually have higher performance. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V

may actually have higher performance.

5.3 Recommended Operating Conditions

MIN NOM MAX UNIT

PMMCOREVx = 0 1.8 3.6

BAT,RTC

BAT,MEM

BAK

VCORE

DVCC

VCORE

Supply voltage during program execution and flash programming (AVCC1 = DVCC1 = DVCC2 = DVCC3 = V DVCC= VCC)

(1)(2)

Supply voltage (AVSS1 = AVSS2 = AVSS3 = DVSS1 = DVSS2 = DVSS3 = VSS)

Backup-supply voltage with RTC operational V

Backup-supply voltage with backup memory retained TA= –40°C to +85°C 1.20 3.6 V Operating free-air temperature I version –40 85 °C Operating junction temperature I version –40 85 °C Capacitance at pin VBAK 1 4.7 10 nF Capacitor at VCORE

Capacitor ratio of DVCC to VCORE 10

(3)

PMMCOREVx = 0, 1 2.0 3.6 PMMCOREVx = 0, 1, 2 2.2 3.6 PMMCOREVx = 0, 1, 2, 3 2.4 3.6

0 V

TA= 0°C to 85°C 1.55 3.6 TA= –40°C to +85°C 1.70 3.6

470 nF

(1) TI recommends powering AVCCand DVCCfrom the same source. A maximum difference of 0.3 V between AVCCand DVCCcan be

tolerated during power up and operation. (2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the threshold parameters in Section 5.22

for the exact values and further details. (3) A capacitor tolerance of ±20% or better is required.

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2.01.8

SystemFrequency-MHz

SupplyVoltage-V

ThenumberswithinthefieldsdenotethesupportedPMMCOREVxsettings.

2.2 2.4 3.6

0,1,2,30,1,20,10

1,2,3

1,2

2,3

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Recommended Operating Conditions (continued)

MIN NOM MAX UNIT

PMMCOREVx = 0,

1.8 V ≤ VCC≤ 3.6 V 0 8.0 (default condition)

SYSTEM

(4) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the

specified maximum frequency. (5) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.

Processor frequency (maximum MCLK frequency) (see Figure 5-1)

(4)(5)

PMMCOREVx = 1, 2 V ≤ VCC≤ 3.6 V

PMMCOREVx = 2,

2.2 V ≤ VCC≤ 3.6 V PMMCOREVx = 3,

2.4 V ≤ VCC≤ 3.6 V

0 12.0

0 16.0

0 20.0

MHz

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Figure 5-1. Frequency vs Supply Voltage

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5.4 Active Mode Supply Current Into VCCExcluding External Current

over recommended operating free-air temperature (unless otherwise noted)

PARAMETER V

AM, Flash

AM, RAM

(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. (2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load

capacitance are chosen to closely match the required 12.5 pF. (3) Characterized with program executing typical data processing. LDO disabled (LDOEN = 0).

ACLK

XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.

EXECUTION

MEMORY

= 32786 Hz, f

PMMCOREVx 1 MHz 8 MHz 12 MHz 20 MHz UNIT

TYP MAX TYP MAX TYP MAX TYP MAX

0 0.32 0.36 2.1 2.4

Flash 3 V mA

1 0.36 2.4 3.6 4.0 2 0.37 2.5 3.8 3 0.39 2.7 4.0 6.6 0 0.18 0.21 1.0 1.2

RAM 3 V mA

1 0.20 1.2 1.7 1.9 2 0.22 1.3 2.0 3 0.23 1.4 2.1 3.6

= f

DCO

MCLK

= f

at specified frequency.

SMCLK

(1)(2)(3)

FREQUENCY (f

DCO

= f

MCLK

= f

SMCLK

)

5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

–40°C 25°C 60°C 85°C

TYP MAX TYP MAX TYP MAX TYP MAX

LPM0,1MHz

LPM2

LPM3,XT1LF

PARAMETER V

2.2 V 0 71 75 87 81 85 99

Low-power mode 0

Low-power mode 2

(3)(4)

2.2 V 0 6.3 6.7 9.9 9.0 11 16

(5)(4)

2.2 V 1 1.6 1.9 4.8 6.6

Low-power mode 3, crystal mode

(6)(4)

PMMCOREVx UNIT

3 V 3 78 83 98 89 94 108

3 V 3 6.6 7.0 11 10 12 18

0 1.6 1.8 2.4 4.7 6.5 10.5

2 1.7 2.0 4.9 6.7 0 1.9 2.1 2.7 5.0 6.8 10.8 µA

3 V

1 1.9 2.1 5.1 7.0 2 2.0 2.2 5.2 7.1 3 2.0 2.2 2.9 5.4 7.3 12.6

(1)(2)

µA

(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. (2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external

load capacitance are chosen to closely match the required 9 pF. (3) Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), f

LDO disabled (LDOEN = 0). (4) Current for brownout included. Low-side supervisor and monitors disabled (SVSL, SVML). High-side supervisor and monitor disabled

(SVSH, SVMH). RAM retention enabled. (5) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low-frequency crystal operation

(XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), f

setting = 1 MHz operation, DCO bias generator enabled.

LDO disabled (LDOEN = 0). (6) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low-frequency crystal operation

(XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), f

LDO disabled (LDOEN = 0).

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= 32768 Hz, f

ACLK

= 32768 Hz, f

ACLK

= 32768 Hz, f

ACLK

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MCLK

= 0 MHz, f

= f

SMCLK

= f

DCO

= f

DCO

= f

DCO

= 0 MHz

= 1 MHz

= 0 MHz; DCO

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Low-Power Mode Supply Currents (Into VCC) Excluding External Current (continued)

= f

(1)(2)

SMCLK

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER V

PMMCOREVx UNIT

0 0.9 1.2 1.9 4.0 5.9 10.3

LPM3,

VLO,WDT

Low-power mode 3, VLO mode, Watchdog 3 V µA

(7)(4)

enabled

1 0.9 1.2 4.1 6.0 2 1.0 1.3 4.2 6.1 3 1.0 1.3 2.2 4.3 6.3 11.3 0 0.9 1.1 1.8 3.9 5.8 10

LPM4

Low-power mode 4

(8)(4)

3 V µA

1 0.9 1.1 4.0 5.9 2 1.0 1.2 4.1 6.1 3 1.0 1.2 2.1 4.2 6.2 11

Low-power mode 3.5

LPM3.5,

RTC,VCC

(LPM3.5) current with active RTC into primary supply pin DV

(9)

3 V 0.5 0.8 1.4 µA

Low-power mode 3.5

LPM3.5,

RTC,VBAT

LPM3.5,

RTC,TOT

LPM4.5

(LPM3.5) current with active RTC into backup supply pin VBAT

(10)

3 V 0.6 0.8 1.4 µA

Total low-power mode

3.5 (LPM3.5) current 3 V 1.0 1.1 1.3 1.6 2.8 µA with active RTC

Low-power mode 4.5 (LPM4.5)

(12)

(11)

3 V 0.2 0.3 0.6 0.7 0.9 1.4 µA

(7) Current for watchdog timer clocked by VLO included.

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), f

LDO disabled (LDOEN = 0). (8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), f

LDO disabled (LDOEN = 0). (9) V (10) V

(11) f (12) Internal regulator disabled. No data retention.

= VCC- 0.2 V, f

VBAT

= VCC- 0.2 V, f

VBAT

current drawn on VBAK

DCO

= f

MCLK

= f

SMCLK

= f

DCO

= f

DCO

= 0 MHz, f

MCLK

= f = f

ACLK

= 0 MHz, f

SMCLK

= 0 MHz, f

SMCLK

= 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no current drawn on VBAK

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), f

–40°C 25°C 60°C 85°C

TYP MAX TYP MAX TYP MAX TYP MAX

= f

ACLK

= f

DCO

= 32768 Hz, PMMREGOFF = 1, RTC in backup domain active

ACLK

= 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no

ACLK

MCLK

ACLK

= f

MCLK

SMCLK

= f

DCO

= f

DCO

SMCLK

= f

= 0 MHz

ACLK

= f

MCLK

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= 0 MHz

5.6 Thermal Resistance Characteristics

PARAMETER VALUE UNIT

JC(TOP)

Junction-to-ambient thermal resistance, still air

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

(3)

(1)

(2)

(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as

specified in JESD51-7, in an environment described in JESD51-2a. (2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

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5.7 Schmitt-Trigger Inputs – General-Purpose I/O

(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

Positive-going input threshold voltage V

IT+

Negative-going input threshold voltage V

IT–

Input voltage hysteresis (V

hys

Pullup or pulldown resistor

Pull

Input capacitance VIN= VSSor V

IT+

(2)

– V

) V

IT–

For pullup: VIN= V For pulldown: VIN= V

1.8 V 0.80 1.40 3 V 1.50 2.10

1.8 V 0.45 1.00 3 V 0.75 1.65

1.8 V 0.3 0.8 3 V 0.4 1.0

(1) Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN). (2) Also applies to RST pin when pullup or pulldown resistor is enabled.

5.8 Inputs – Ports P1, P2, P3, and P4

(1)

MIN TYP MAX UNIT

20 35 50 kΩ

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

External interrupt timing

(int)

(2)

Port P1, P2, P3, P4: P1.x to P4.x, External trigger pulse duration to set interrupt flag

(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions. (2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t

shorter than t

(int)

is met. It may be set by trigger signals

(int)

2.2 V, 3 V 20 ns

5 pF

MIN MAX UNIT

5.9 Leakage Current – General-Purpose I/O

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

lkg(Px.x)

PARAMETER TEST CONDITIONS V

High-impedance leakage current

(1)(2)

1.8 V, 3 V ±50 nA

(1) The leakage current is measured with VSSor VCCapplied to the corresponding pin(s), unless otherwise noted. (2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is

disabled.

MIN MAX UNIT

5.10 Outputs – General-Purpose I/O (Full Drive Strength)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

High-level output voltage V

Low-level output voltage V

(1) The maximum total current, I

specified.

(2) The maximum total current, I

drop specified.

(OHmax)

and I and I

= –3 mA

(OHmax)

= –10 mA

(OHmax)

= –5 mA

(OHmax)

= –15 mA

(OHmax)

= 3 mA

(OLmax)

= 10 mA

(OLmax)

= 5 mA

(OLmax)

= 15 mA

(OLmax)

, for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop

(OLmax)

, for all outputs combined should not exceed ±100 mA to hold the maximum voltage

(OLmax)

(1)

(2)

(1)

(2)

(1)

(2)

(1)

(2)

1.8 V

3 V

1.8 V

3 V

MIN MAX UNIT

VCC– 0.25 V VCC– 0.60 V VCC– 0.25 V VCC– 0.60 V

VSSVSS+ 0.25 VSSVSS+ 0.60 VSSVSS+ 0.25 VSSVSS+ 0.60

CC CC CC CC

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5.11 Outputs – General-Purpose I/O (Reduced Drive Strength)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

(OHmax)

High-level output voltage V

Low-level output voltage V

(OHmax)

(OLmax)

(1) Selecting reduced drive strength may reduce EMI. (2) The maximum total current, I

specified.

(3) The maximum total current, I

drop specified.

(OHmax)

and I and I

, for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop

(OLmax)

, for all outputs combined, should not exceed ±100 mA to hold the maximum voltage

(OLmax)

= –1 mA = –3 mA = –2 mA

= –6 mA = 1 mA = 3 mA = 2 mA = 6 mA

(2) (3) (2)

(3) (2) (3) (2) (3)

1.8 V

3 V

1.8 V

3 V

VCC– 0.25 V VCC– 0.60 V VCC– 0.25 V VCC– 0.60 V

(1)

MIN MAX UNIT

CC CC CC CC

VSSVSS+ 0.25 VSSVSS+ 0.60 VSSVSS+ 0.25 VSSVSS+ 0.60

5.12 Output Frequency – Ports P1, P2, and P3

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

VCC= 1.8 V,

Px.y

Port output frequency P3.4/TA2CLK/SMCLK/S27, (with load) CL= 20 pF, RL= 1 kΩ

(1)

or 3.2 kΩ

(2)(3)

PMMCOREVx = 0 VCC= 3 V,

PMMCOREVx = 3 VCC= 1.8 V,

PMMCOREVx = 0 VCC= 3 V,

PMMCOREVx = 3

Port_CLK

P1.0/TA0CLK/ACLK/S39,

Clock output frequency MHz

P3.4/TA2CLK/SMCLK/S27, P2.0/P2MAP0 (P2MAP0 = PM_MCLK ), CL= 20 pF

(3)

(1) Full drive strength of port: A resistive divider with 2 × 0.5 kΩ between VCCand VSSis used as load. The output is connected to the

center tap of the divider.

(2) Reduced drive strength of port: A resistive divider with 2 × 1.6 kΩ between VCCand VSSis used as load. The output is connected to the

center tap of the divider.

(3) The output voltage reaches at least 10% and 90% VCCat the specified toggle frequency.

MHz

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−25.0

−20.0

−15.0

−10.0

−5.0

0.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

T = 25°C

T = 85°C

V = 3.0 V P3.2

V – High-Level Output Voltage – V

I – Typical High-Level Output Current – mA

−8.0

−7.0

−6.0

−5.0

−4.0

−3.0

−2.0

−1.0

0.0

0.0 0.5 1.0 1.5 2.0

T = 25°C

T = 85°C

V = 1.8 V P3.2

V – High-Level Output Voltage – V

I – Typical High-Level Output Current – mA

0.0

5.0

10.0

15.0

20.0

25.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

T = 25°C

T = 85°C

V = 3.0 V P3.2

V – Low-Level Output Voltage – V

I – Typical Low-Level Output Current – mA

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

0.0 0.5 1.0 1.5 2.0

T = 25°C

T = 85°C

V = 1.8 V P3.2

V – Low-Level Output Voltage – V

I – Typical Low-Level Output Current – mA

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5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

Figure 5-2. Typical Low-Level Output Current vs Low-Level

Figure 5-4. Typical High-Level Output Current vs High-Level

Output Voltage

Figure 5-3. Typical Low-Level Output Current vs Low-Level

Figure 5-5. Typical High-Level Output Current vs High-Level

Output Voltage

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−20

−16

−12

−8

−4

0.0 0.5 1.0 1.5 2.0

T = 25°C

T = 85°C

V = 1.8 V P3.2

V – High-Level Output Voltage – V

I – Typical High-Level Output Current – mA

−60.0

−55.0

−50.0

−45.0

−40.0

−35.0

−30.0

−25.0

−20.0

−15.0

−10.0

−5.0

0.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

T = 25°C

T = 85°C

V = 3.0 V P3.2

V – High-Level Output Voltage – V

I – Typical High-Level Output Current – mA

0.0

5.0

10.0

15.0

20.0

25.0

30.0

35.0

40.0

45.0

50.0

55.0

60.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

T = 25°C

T = 85°C

V = 3.0 V P3.2

V – Low-Level Output Voltage – V

I – Typical Low-Level Output Current – mA

0.0 0.5 1.0 1.5 2.0

T = 25°C

T = 85°C

V = 1.8 V P3.2

V – Low-Level Output Voltage – V

I – Typical Low-Level Output Current – mA

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5.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

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Figure 5-6. Typical Low-Level Output Current vs Low-Level

Figure 5-8. Typical High-Level Output Current vs High-Level

Output Voltage

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Figure 5-7. Typical Low-Level Output Current vs Low-Level

Figure 5-9. Typical High-Level Output Current vs High-Level

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Output Voltage

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5.15 Crystal Oscillator, XT1, Low-Frequency Mode

(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

= 32768 Hz, XTS = 0,

OSC

XT1BYPASS = 0, XT1DRIVEx = 1, 0.075

TA= 25°C

ΔI

DVCC,LF

Differential XT1 oscillator crystal f current consumption from lowest XT1BYPASS = 0, XT1DRIVEx = 2, 3 V 0.170 µA drive setting, LF mode TA= 25°C

= 32768 Hz, XTS = 0,

OSC

= 32768 Hz, XTS = 0,

OSC

XT1BYPASS = 0, XT1DRIVEx = 3, 0.290 TA= 25°C

XT1,LF0

XT1,LF,SW

XT1 oscillator crystal frequency, LF mode

XT1 oscillator logic-level squarewave input frequency, LF mode

XTS = 0, XT1BYPASS = 0 32768 Hz

XTS = 0, XT1BYPASS = 1

(2) (3)

XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0, 210

= 32768 Hz, C

Oscillation allowance for LF crystals

(4)

XT1,LF

XTS = 0,

L,eff

= 6 pF

XT1BYPASS = 0, XT1DRIVEx = 1, 300 f

= 32768 Hz, C

XT1,LF

XTS = 0, XCAPx = 0

L,eff

Integrated effective load capacitance, LF mode

(5)

XTS = 0, XCAPx = 1 5.5 XTS = 0, XCAPx = 2 8.5

= 12 pF

L,eff

(6)

XTS = 0, XCAPx = 3 12.0 XTS = 0, Measured at ACLK,

= 32768 Hz

XT1,LF

XTS = 0 f

XT1BYPASS = 0, XT1DRIVEx = 0,

(8)

= 32768 Hz, XTS = 0,

OSC

Fault,LF

Duty cycle, LF mode 30% 70% Oscillator fault frequency,

LF mode

(7)

TA= 25°C, C

= 6 pF

START,LF

Start-up time, LF mode 3 V ms

L,eff

= 32768 Hz, XTS = 0,

OSC

XT1BYPASS = 0, XT1DRIVEx = 3, TA= 25°C, C

= 12 pF

L,eff

(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.

• Keep the trace between the device and the crystal as short as possible.

• Design a good ground plane around the oscillator pins.

• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.

• If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.

(2) When XT1BYPASS is set, XT1 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined in

the Schmitt-trigger Inputs section of this datasheet. (3) Maximum frequency of operation of the entire device cannot be exceeded. (4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the

XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following

guidelines, but should be evaluated based on the actual crystal selected for the application:

• For XT1DRIVEx = 0, C

• For XT1DRIVEx = 1, 6 pF ≤ C

• For XT1DRIVEx = 2, 6 pF ≤ C

• For XT1DRIVEx = 3, C

(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

L,eff

≤ 6 pF.

L,eff L,eff

≥ 6 pF.

≤ 9 pF. ≤ 10 pF.

Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a

correct setup, the effective load capacitance should always match the specification of the used crystal. (6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. (7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies in between might set the flag. (8) Measured with logic-level input frequency but also applies to operation with crystals.

MIN TYP MAX UNIT

10 32.768 50 kHz

kΩ

10 10000 Hz

1000

500

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5.16 Crystal Oscillator, XT2

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

= 4 MHz, XT2OFF = 0,

OSC

XT2BYPASS = 0, XT2DRIVEx = 0, 200 TA= 25°C

= 12 MHz, XT2OFF = 0,

OSC

XT2BYPASS = 0, XT2DRIVEx = 1, 260

DVCC,XT2

XT2 oscillator crystal current consumption

TA= 25°C f

= 20 MHz, XT2OFF = 0,

OSC

XT2BYPASS = 0, XT2DRIVEx = 2, 325 TA= 25°C

= 32 MHz, XT2OFF = 0,

OSC

XT2BYPASS = 0, XT2DRIVEx = 3, 450 TA= 25°C

XT2,HF0

XT2,HF1

XT2,HF2

XT2,HF3

XT2,HF,SW

XT2 oscillator crystal frequency, mode 0

XT2 oscillator crystal frequency, mode 1

XT2 oscillator crystal frequency, mode 2

XT2 oscillator crystal frequency, mode 3

XT2 oscillator logic-level squarewave input frequency

XT2DRIVEx = 0, XT2BYPASS = 0

XT2DRIVEx = 1, XT2BYPASS = 0

XT2DRIVEx = 2, XT2BYPASS = 0

XT2DRIVEx = 3, XT2BYPASS = 0

XT2BYPASS = 1

(4) (3)

(3)

XT2DRIVEx = 0, XT2BYPASS = 0, f

XT2,HF0

= 6 MHz, C

L,eff

= 15 pF

XT2DRIVEx = 1, XT2BYPASS = 0,

Oscillation allowance for HF crystals

(5)

f XT2DRIVEx = 2, XT2BYPASS = 0,

XT2,HF1

XT2,HF2

= 12 MHz, C

= 20 MHz, C

L,eff

= 15 pF

XT2DRIVEx = 3, XT2BYPASS = 0,

START,HF

L,eff

Fault,HF

f f

XT2BYPASS = 0, XT2DRIVEx = 0, 0.5

Start-up time 3 V ms

TA= 25°C, C f

XT2BYPASS = 0, XT2DRIVEx = 3, 0.3 TA= 25°C, C

Integrated effective load capacitance, HF mode

(6) (1)

Duty cycle Measured at ACLK, f Oscillator fault frequency

(7)

XT2BYPASS = 1

XT2,HF3

= 6 MHz

OSC

= 20 MHz

OSC

= 32 MHz, C

= 15 pF

L,eff

= 15 pF

L,eff

(8)

= 15 pF

L,eff

= 20 MHz 40% 50% 60%

XT2,HF2

(1) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. (2) To improve EMI on the XT2 oscillator the following guidelines should be observed.

• Keep the traces between the device and the crystal as short as possible.

• Design a good ground plane around the oscillator pins.

• Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.

• Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.

• Use assembly materials and processes that avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.

• If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. (3) Maximum frequency of operation of the entire device cannot be exceeded. (4) When XT2BYPASS is set, the XT2 circuit is automatically powered down. (5) Oscillation allowance is based on a safety factor of 5 for recommended crystals. (6) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal.

(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies in between might set the flag.

(8) Measured with logic-level input frequency but also applies to operation with crystals.

3 V µA

(1) (2)

MIN TYP MAX UNIT

4 8 MHz

8 16 MHz

16 24 MHz

24 32 MHz

0.7 32 MHz

450

320

200

1 pF

30 300 kHz

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Ω

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5.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

VLO

VLO/dT

VLO

VLO frequency Measured at ACLK 1.8 V to 3.6 V 6 9.4 14 kHz VLO frequency temperature drift Measured at ACLK

/dVCCVLO frequency supply voltage drift Measured at ACLK

(1) (2)

1.8 V to 3.6 V 0.5 %/°C

1.8 V to 3.6 V 4 %/V

Duty cycle Measured at ACLK 1.8 V to 3.6 V 40% 50% 60%

(1) Calculated using the box method: (MAX(–40°C to +85°C) – MIN(–40°C to +85°C)) / MIN(–40°C to +85°C) / (85°C – (–40°C)) (2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

MIN TYP MAX UNIT

5.18 Internal Reference, Low-Frequency Oscillator (REFO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

REFO

PARAMETER TEST CONDITIONS V

REFO oscillator current consumption

TA= 25°C 1.8 V to 3.6 V 3 µA

REFO frequency calibrated Measured at ACLK 1.8 V to 3.6 V 32768 Hz

REFO

REFO/dT

REFO

/dV

REFO absolute tolerance calibrated

REFO frequency temperature drift Measured at ACLK REFO frequency supply voltage

drift

Full temperature range 1.8 V to 3.6 V ±3.5% TA= 25°C 3 V ±1.5%

Measured at ACLK

(1)

(2)

1.8 V to 3.6 V 0.01 %/°C

1.8 V to 3.6 V 1.0 %/V

Duty cycle Measured at ACLK 1.8 V to 3.6 V 40% 50% 60%

START

REFO start-up time 40%/60% duty cycle 1.8 V to 3.6 V 25 µs

MIN TYP MAX UNIT

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1 2

Typical DCO Frequency,V = 3.0 V,T = 25°C

CC A

DCORSEL

100

0.1

f – MHz

DCO

DCOx = 31

DCOx = 0

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5.19 DCO Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DCO(0,0)

DCO(0,31)

DCO(1,0)

DCO(1,31)

DCO(2,0)

DCO(2,31)

DCO(3,0)

DCO(3,31)

DCO(4,0)

DCO(4,31)

DCO(5,0)

DCO(5,31)

DCO(6,0)

DCO(6,31)

DCO(7,0)

DCO(7,31)

DCORSEL

DCO

/dT DCO frequency temperature drift f

DCO

/dV

DCO

DCO frequency (0, 0) DCORSELx = 0, DCOx = 0, MODx = 0 0.07 0.20 MHz DCO frequency (0, 31) DCORSELx = 0, DCOx = 31, MODx = 0 0.70 1.70 MHz DCO frequency (1, 0) DCORSELx = 1, DCOx = 0, MODx = 0 0.15 0.36 MHz DCO frequency (1, 31) DCORSELx = 1, DCOx = 31, MODx = 0 1.47 3.45 MHz DCO frequency (2, 0) DCORSELx = 2, DCOx = 0, MODx = 0 0.32 0.75 MHz DCO frequency (2, 31) DCORSELx = 2, DCOx = 31, MODx = 0 3.17 7.38 MHz DCO frequency (3, 0) DCORSELx = 3, DCOx = 0, MODx = 0 0.64 1.51 MHz DCO frequency (3, 31) DCORSELx = 3, DCOx = 31, MODx = 0 6.07 14.0 MHz DCO frequency (4, 0) DCORSELx = 4, DCOx = 0, MODx = 0 1.3 3.2 MHz DCO frequency (4, 31) DCORSELx = 4, DCOx = 31, MODx = 0 12.3 28.2 MHz DCO frequency (5, 0) DCORSELx = 5, DCOx = 0, MODx = 0 2.5 6.0 MHz DCO frequency (5, 31) DCORSELx = 5, DCOx = 31, MODx = 0 23.7 54.1 MHz DCO frequency (6, 0) DCORSELx = 6, DCOx = 0, MODx = 0 4.6 10.7 MHz DCO frequency (6, 31) DCORSELx = 6, DCOx = 31, MODx = 0 39.0 88.0 MHz DCO frequency (7, 0) DCORSELx = 7, DCOx = 0, MODx = 0 8.5 19.6 MHz DCO frequency (7, 31) DCORSELx = 7, DCOx = 31, MODx = 0 60 135 MHz Frequency step between range

DCORSEL and DCORSEL + 1 Frequency step between tap

DCO and DCO + 1

= f

RSEL

DCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)

= f

DCO

DCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)

1.2 2.3 ratio

1.02 1.12 ratio

Duty cycle Measured at SMCLK 40% 50% 60%

= 1 MHz 0.1 %/°C

DCO

DCO frequency voltage drift f

= 1 MHz 1.9 %/V

DCO

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Figure 5-10. Typical DCO frequency

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5.20 PMM, Brownout Reset (BOR)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V(DVCC_BOR_IT–) | dDVCC/dt| < 3 V/s 1.45 V

V(DVCC_BOR_IT+) | dDVCC/dt| < 3 V/s 0.80 1.30 1.50 V V(DVCC_BOR_hys) BORHhysteresis 60 250 mV

RESET

BORHon voltage, DVCCfalling level

BORHoff voltage, DVCCrising level

Pulse length required at RST/NMI pin to accept a 2 µs reset

5.21 PMM, Core Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(AM) 2.4 V ≤ DVCC≤ 3.6 V, 0 mA ≤ I(V

CORE3

(AM) 2.2 V ≤ DVCC≤ 3.6 V, 0 mA ≤ I(V

CORE2

(AM) 2 V ≤ DVCC≤ 3.6 V, 0 mA ≤ I(V

CORE1

(AM) 1.8 V ≤ DVCC≤ 3.6 V, 0 mA ≤ I(V

CORE0

(LPM) 2.4 V ≤ DVCC≤ 3.6 V, 0 µA ≤ I(V

CORE3

(LPM) 2.2 V ≤ DVCC≤ 3.6 V, 0 µA ≤ I(V

CORE2

(LPM) 2 V ≤ DVCC≤ 3.6 V, 0 µA ≤ I(V

CORE1

(LPM) 1.8 V ≤ DVCC≤ 3.6 V, 0 µA ≤ I(V

CORE0

Core voltage, active mode, PMMCOREV = 3

Core voltage, active mode, PMMCOREV = 2

Core voltage, active mode, PMMCOREV = 1

Core voltage, active mode, PMMCOREV = 0

Core voltage, low-current mode, PMMCOREV = 3

Core voltage, low-current mode, PMMCOREV = 2

Core voltage, low-current mode, PMMCOREV = 1

Core voltage, low-current mode, PMMCOREV = 0

) ≤ 21 mA 1.90 V

CORE

) ≤ 21 mA 1.80 V

CORE

) ≤ 17 mA 1.60 V

CORE

) ≤ 13 mA 1.40 V

CORE

) ≤ 30 µA 1.94 V

CORE

) ≤ 30 µA 1.84 V

CORE

) ≤ 30 µA 1.64 V

CORE

) ≤ 30 µA 1.44 V

CORE

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5.22 PMM, SVS High Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SVSHE = 0, DVCC= 3.6 V 0

(SVSH)

SVS current consumption SVSHE = 1, DVCC= 3.6 V, SVSHFP = 0 200

SVSHE = 1, DVCC= 3.6 V, SVSHFP = 1 2.0 µA SVSHE = 1, SVSHRVL = 0 1.59 1.64 1.69

(SVSH_IT–)

SVSHon voltage level

(1)

SVSHE = 1, SVSHRVL = 1 1.79 1.84 1.91 SVSHE = 1, SVSHRVL = 2 1.98 2.04 2.11 SVSHE = 1, SVSHRVL = 3 2.10 2.16 2.23 SVSHE = 1, SVSMHRRL = 0 1.62 1.74 1.81 SVSHE = 1, SVSMHRRL = 1 1.88 1.94 2.01 SVSHE = 1, SVSMHRRL = 2 2.07 2.14 2.21

(SVSH_IT+)

SVSHoff voltage level

(1)

SVSHE = 1, SVSMHRRL = 3 2.20 2.26 2.33 SVSHE = 1, SVSMHRRL = 4 2.32 2.40 2.48 SVSHE = 1, SVSMHRRL = 5 2.56 2.70 2.84 SVSHE = 1, SVSMHRRL = 6 2.85 3.00 3.15 SVSHE = 1, SVSMHRRL = 7 2.85 3.00 3.15

pd(SVSH)

(SVSH)

DVCC

SVSHpropagation delay µs

SVSHon or off delay time µs

/dt DVCCrise time 0 1000 V/s

SVSHE = 1, dV SVSHE = 1, dV SVSHE = 0→1, SVSHFP = 1 12.5 SVSHE = 0→1, SVSHFP = 0 100

/dt = 10 mV/µs, SVSHFP = 1 2.5

DVCC

/dt = 1 mV/µs, SVSHFP = 0 20

DVCC

(1) The SVSHsettings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage

Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and usage.

5.23 PMM, SVM High Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SVMHE = 0, DVCC = 3.6 V 0

(SVMH)

SVMHcurrent consumption SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0 200

SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1 2.0 µA SVMHE = 1, SVSMHRRL = 0 1.65 1.74 1.86 SVMHE = 1, SVSMHRRL = 1 1.85 1.94 2.02 SVMHE = 1, SVSMHRRL = 2 2.02 2.14 2.22 SVMHE = 1, SVSMHRRL = 3 2.18 2.26 2.35

(SVMH)

SVMHon or off voltage level

(1)

SVMHE = 1, SVSMHRRL = 4 2.32 2.40 2.48 V SVMHE = 1, SVSMHRRL = 5 2.56 2.70 2.84 SVMHE = 1, SVSMHRRL = 6 2.85 3.00 3.15 SVMHE = 1, SVSMHRRL = 7 2.85 3.00 3.15 SVMHE = 1, SVMHOVPE = 1 3.75

pd(SVMH)

(SVMH)

SVMHpropagation delay µs

SVMHon or off delay time µs

SVMHE = 1, dV SVMHE = 1, dV SVMHE = 0→1, SVSMFP = 1 12.5 SVMHE = 0→1, SVMHFP = 0 100

/dt = 10 mV/µs, SVMHFP = 1 2.5

DVCC

/dt = 1 mV/µs, SVMHFP = 0 20

DVCC

(1) The SVMHsettings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage

Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and usage.

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5.24 PMM, SVS Low Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SVSLE = 0, PMMCOREV = 2 0

(SVSL)

pd(SVSL)

(SVSL)

SVSLcurrent consumption SVSLE = 1, PMMCOREV = 2, SVSLFP = 0 200

SVSLE = 1, PMMCOREV = 2, SVSLFP = 1 2.0 µA

SVSLpropagation delay µs

SVSLon/off delay time µs

SVSLE = 1, dV SVSLE = 1, dV SVSLE = 0→1, SVSLFP = 1 12.5 SVSLE = 0→1, SVSLFP = 0 100

/dt = 10 mV/µs, SVSLFP = 1 2.5

CORE

/dt = 1 mV/µs, SVSLFP = 0 20

CORE

5.25 PMM, SVM Low Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SVMLE = 0, PMMCOREV = 2 0

(SVML)

pd(SVML)

(SVML)

SVMLcurrent consumption SVMLE = 1, PMMCOREV = 2, SVMLFP = 0 200

SVMLE = 1, PMMCOREV = 2, SVMLFP = 1 2.0 µA

SVMLpropagation delay µs

SVMLon or off delay time µs

SVMLE = 1, dV SVMLE = 1, dV SVMLE = 0→1, SVMLFP = 1 12.5 SVMLE = 0→1, SVMLFP = 0 100

/dt = 10 mV/µs, SVMLFP = 1 2.5

CORE

/dt = 1 mV/µs, SVMLFP = 0 20

CORE

5.26 Wake-up Times From Low-Power Modes and Reset

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

≥ 4 MHz 3 6.5

WAKE-UP-FAST

LPM3, or LPM4 to active (where n = 0, 1, 2, or 3), µs

(1)

mode

SVSLFP = 1

Wake-up time from LPM2, PMMCOREV = SVSMLRRL = n

WAKE-UP-SLOW

WAKE-UP-LPM5

WAKE-UP-RESET

LPM3 or LPM4 to active (where n = 0, 1, 2, or 3), 150 165 µs

(2)

mode Wake-up time from LPM3.5 or

LPM4.5 to active mode

(3)

Wake-up time from RST or BOR event to active mode

SVSLFP = 0

(3)

(1) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance

mode of the low-side supervisor (SVSL) and low-side monitor (SVML). Fastest wake-up times are possible with SVSLand SVMLin full performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVMLwhile operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).

(2) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance

mode of the low-side supervisor (SVSL) and low-side monitor (SVML). In this case, the SVSLand SVMLare in normal mode (low current) mode when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVMLwhile operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).

(3) This value represents the time from the wake-up event to the reset vector execution.

MCLK

1 MHz < f 4 MHz

MCLK

4 8.0

2 3 ms

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5.27 Timer_A, Timers TA0, TA1, and TA2

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TA,cap

PARAMETER TEST CONDITIONS V

Internal: SMCLK, ACLK

Timer_A input clock frequency External: TACLK 1.8 V, 3 V 20 MHz

Duty cycle = 50% ±10% All capture inputs,

Timer_A capture timing Minimum pulse duration required for 1.8 V, 3 V 20 ns

capture

5.28 Timer_B, Timer TB0

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TB,cap

PARAMETER TEST CONDITIONS V

Internal: SMCLK, ACLK

Timer_B input clock frequency External: TBCLK 1.8 V, 3 V 20 MHz

Duty cycle = 50% ±10% All capture inputs,

Timer_B capture timing Minimum pulse duration required for 1.8 V, 3 V 20 ns

capture

5.29 Battery Backup

over operating free-air temperature range (unless otherwise noted)

VBAT

SWITCH

ON_VBAT

BAT3

Sample,

VBAT3

CHVx

CHARGE

PARAMETER TEST CONDITIONS V

TA= –40°C 0.43

VBAT = 1.7 V, DVCC not connected, RTC running

TA= 25°C 0.52 TA= 60°C 0.58 TA= 85°C 0.64 TA= –40°C 0.50

Current into VBAT terminal if no primary battery is connected

VBAT = 2.2 V, DVCC not connected, µA RTC running

TA= 25°C 0.59 TA= 60°C 0.64 TA= 85°C 0.71 TA= –40°C 0.68

VBAT = 3 V, DVCC not connected, RTC running

TA= 25°C 0.75 TA= 60°C 0.79 TA= 85°C 0.86 General V SVSHRL = 0 1.59 1.69

Switch-over level (VCCto VBAT) C

= 4.7 µF SVSHRL = 1 1.79 1.91 V

VCC

SVSHRL = 2 1.98 2.11 SVSHRL = 3 2.10 2.23

ON-resistance of switch between VBAT and VBAK

= 1.8 V 0 V 0.35 1 kΩ

BAT

1.8 V 0.6 ±5% VBAT to ADC input channel 12: V

BAT

divided, V

BAT3

= V

BAT

3 V 1.0 ±5% V

3.6 V 1.2 ±5% VBAT to ADC: Sampling time ADC12ON = 1,

required if VBAT3 selected Error of conversion result ≤ 1 LSB Charger end voltage CHVx = 2 2.65 2.7 2.9 V

CHCx = 1 5

Charge limiting resistor CHCx = 2 10 kΩ

CHCx = 3 20

MIN TYP MAX UNIT

1000 ns

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MIN MAX UNIT

SVSH_IT-

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5.30 USCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

Internal: SMCLK, ACLK

USCI

BITCLK

USCI input clock frequency External: UCLK f

Duty cycle = 50% ±10%

BITCLK clock frequency (equals baud rate in MBaud)

UART receive deglitch time

(1)

2.2 V 50 600 3 V 50 600

(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are

correctly recognized their width should exceed the maximum specification of the deglitch time.

MIN MAX UNIT

SYSTEM

MHz

1 MHz

5.31 USCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-11 and Figure 5-12)

PARAMETER TEST CONDITIONS V

USCI

USCI input clock frequency f

SMCLK, ACLK, Duty cycle = 50% ±10%

PMMCOREV = 0

SU,MI

SOMI input data setup time ns

PMMCOREV = 3

PMMCOREV = 0

HD,MI

SOMI input data hold time ns

PMMCOREV = 3

UCLK edge to SIMO valid, 1.8 V 20 CL= 20 pF,

VALID,MO

SIMO output data valid time

(2)

PMMCOREV = 0 UCLK edge to SIMO valid,

CL= 20 pF, PMMCOREV = 3

CL= 20 pF, PMMCOREV = 0

HD,MO

SIMO output data hold time

(3)

CL= 20 pF, PMMCOREV = 3

(1) f (2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams

= 1/2t

UCxCLK

For the slave parameters t

LO/HI

with t

LO/HI

≥ max(t

SU,SI(Slave)

VALID,MO(USCI)

and t

VALID,SO(Slave)

+ t

SU,SI(Slave)

, t

, see the SPI parameters of the attached slave.

SU,MI(USCI)

+ t

VALID,SO(Slave)

in Figure 5-11 and Figure 5-12.

(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data

on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-

11 and Figure 5-12.

1.8 V 55 3 V 38

2.4 V 30 3 V 25

1.8 V 0 3 V 0

2.4 V 0 3 V 0

3 V 18

2.4 V 16 3 V 15

1.8 V –10 3 V –8

2.4 V –10 3 V –8

(1)

MIN MAX UNIT

SYSTEM

MHz

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SU,MI

HD,MI

UCLK

SOMI

SIMO

VALID,MO

CKPL =0

CKPL =1

1/f

UCxCLK

HD,MO

LO/HI

SU,MI

HD,MI

UCLK

SOMI

SIMO

VALID,MO

HD,MO

CKPL =0

CKPL =1

LO/HI

1/f

UCxCLK

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Figure 5-11. SPI Master Mode, CKPH = 0

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Figure 5-12. SPI Master Mode, CKPH = 1

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5.32 USCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-13 and Figure 5-14)

PARAMETER TEST CONDITIONS V

PMMCOREV = 0

STE,LEAD

STE lead time, STE low to clock ns

PMMCOREV = 3

PMMCOREV = 0

STE,LAG

STE lag time, Last clock to STE high ns

PMMCOREV = 3

PMMCOREV = 0

STE,ACC

STE access time, STE low to SOMI data out ns

PMMCOREV = 3

PMMCOREV = 0

STE,DIS

STE disable time, STE high to SOMI high impedance

PMMCOREV = 3

PMMCOREV = 0

SU,SI

SIMO input data setup time ns

PMMCOREV = 3

PMMCOREV = 0

HD,SI

SIMO input data hold time ns

PMMCOREV = 3

UCLK edge to SOMI valid, 1.8 V 76 CL= 20 pF,

VALID,SO

SOMI output data valid time

(2)

PMMCOREV = 0 UCLK edge to SOMI valid, 2.4 V 44

CL= 20 pF, PMMCOREV = 3

CL= 20 pF,

HD,SO

SOMI output data hold time

(3)

PMMCOREV = 0 CL= 20 pF,

PMMCOREV = 3

(1) f (2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams

= 1/2t

UCxCLK

For the master parameters t

LO/HI

with t

LO/HI

≥ max(t

VALID,MO(Master)

SU,MI(Master)

and t

VALID,MO(Master)

+ t

SU,SI(USCI)

, t

SU,MI(Master)

, see the SPI parameters of the attached slave.

+ t

VALID,SO(USCI)

in Figure 5-13 and Figure 5-14.

(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-13

and Figure 5-14.

1.8 V 11 3 V 8

2.4 V 7 3 V 6

1.8 V 3 3 V 3

2.4 V 3 3 V 3

1.8 V 66 3 V 50

2.4 V 36 3 V 30

1.8 V 30 3 V 23

2.4 V 16 3 V 13

1.8 V 5 3 V 5

2.4 V 2 3 V 2

1.8 V 5 3 V 5

2.4 V 5 3 V 5

3 V 60

3 V 40

1.8 V 18 3 V 12

2.4 V 10 3 V 8

(1)

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STE

UCLK

CKPL =0

CKPL =1

SOMI

SIMO

SU,SI

HD,SI

VALID,SO

STE,LEAD

1/f

UCxCLK

STE,LAG

STE,DIS

STE,ACC

HD,MO

LO/HI

STE

UCLK

CKPL =0

CKPL =1

SOMI

SIMO

SU,SI

HD,SI

VALID,SO

STE,LEAD

1/f

UCxCLK

LO/HI

STE,LAG

STE,DIS

STE,ACC

HD,SO

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Figure 5-13. SPI Slave Mode, CKPH = 0

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Figure 5-14. SPI Slave Mode, CKPH = 1

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SDA

SCL

HD,DAT

SU,DAT

HD,STA

HIGH

LOW

BUF

HD,STA

SU,STA

SU,STO

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5.33 USCI (I2C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-15)

USCI

SCL

HD,STA

SU,STA

HD,DAT

SU,DAT

SU,STO

PARAMETER TEST CONDITIONS V

Internal: SMCLK, ACLK

USCI input clock frequency External: UCLK f

Duty cycle = 50% ±10%

SCL clock frequency 2.2 V, 3 V 0 400 kHz

≤ 100 kHz 4.0

Hold time (repeated) START 2.2 V, 3 V µs

Setup time for a repeated START 2.2 V, 3 V µs

SCL

> 100 kHz 0.6

SCL

≤ 100 kHz 4.7

SCL

> 100 kHz 0.6

SCL

Data hold time 2.2 V, 3 V 0 ns Data setup time 2.2 V, 3 V 250 ns

≤ 100 kHz 4.0

Setup time for STOP 2.2 V, 3 V µs

Pulse duration of spikes suppressed by input filter

SCL

> 100 kHz 0.6

SCL

2.2 V 50 600 3 V 50 600

MIN MAX UNIT

SYSTEM

MHz

Figure 5-15. I2C Mode Timing

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5.34 12-Bit ADC, Power Supply and Input Range Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

AVCC and DVCC are connected together,

(Ax)

ADC12_A

Analog supply voltage AVSS and DVSS are connected together, 2.2 3.6 V

V(AVSS) = V(DVSS) = 0 V

Analog input voltage range Operating supply current into

AVCCterminal

(3)

Input capacitance 2.2 V 20 25 pF

(2)

All ADC12 analog input pins Ax 0 AV

ADC12CLK

= 5 MHz

(4)

Only one terminal Ax can be selected at one time

Input MUX ON resistance 0 V ≤ VIN ≤ V(AVCC) 10 200 1900 Ω

(1) The leakage current is specified by the digital I/O input leakage. (2) The analog input voltage range must be within the selected reference voltage range VR+to VR–for valid conversion results. If the

reference voltage is supplied by an external source or if the internal voltage is used and REFOUT = 1, then decoupling capacitors are

required. See Section 5.40 and Section 5.41. (3) The internal reference supply current is not included in current consumption parameter I (4) ADC12ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV = 0

2.2 V 150 200 3 V 150 250

ADC12

(1)

MIN TYP MAX UNIT

µA

5.35 12-Bit ADC, Timing Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

For specified performance of ADC12 linearity

ADC12CLK

ADC12OSC

CONVERT

Sample

parameters using an external reference voltage or 0.45 4.8 5.0 AVCC as reference

ADC conversion clock For specified performance of ADC12 linearity 2.2 V, 3 V MHz

parameters using the internal reference For specified performance of ADC12 linearity

parameters using the internal reference

Internal ADC12 oscillator

(4)

ADC12DIV = 0, f REFON = 0, Internal oscillator,

Conversion time µs

Sampling time 2.2 V, 3 V 1000 ns

ADC12OSC used for ADC conversion clock External f

ADC12SSEL ≠ 0

ADC12CLK

RS= 400 Ω, RI= 200 Ω, CI= 20 pF, τ = [RS+ RI] × C

(1)

(2)

(3)

ADC12CLK

= f

ADC12OSC

from ACLK, MCLK or SMCLK,

(6)

2.2 V, 3 V 4.2 4.8 5.4 MHz

2.2 V, 3 V 2.4 3.1

(1) REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AVCC as reference voltage: SREF2 = 0, SREF1 = 0,

SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock sources, the specified performance of the ADC12 linearity is ensured with f

(2) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1

ADC12CLK

maximum of 5 MHz.

(3) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured when

using the ADC12OSC divided by 2. (4) The ADC12OSC is sourced directly from MODOSC inside the UCS. (5) 13 × ADC12DIV × 1/f (6) Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB:

Sample

= ln(2

n+1

ADC12CLK

) x (RS+ RI) × CI+ 800 ns, where n = ADC resolution = 12, RS= external source resistance

MIN TYP MAX UNIT

0.45 2.4 4.0

0.45 2.4 2.7

(5)

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5.36 12-Bit ADC, Linearity Parameters Using an External Reference Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

Integral linearity error

Differential linearity error

Offset error

Gain error

(1)

(3)

(3) (2)

Total unadjusted error

1.4 V ≤ dVREF ≤ 1.6 V

1.6 V < dVREF

(2)

dVREF ≤ 2.2 V dVREF > 2.2 V

(2)

(2) (2)

2.2 V, 3 V LSB

2.2 V, 3 V ±1 LSB

2.2 V, 3 V ±3 ±5.6

2.2 V, 3 V ±1.5 ±3.5

2.2 V, 3 V ±1 ±2.5 LSB

2.2 V, 3 V ±3.5 ±7.1

2.2 V, 3 V ±2 ±5

(1) Parameters are derived using the histogram method. (2) The external reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 0. dVREF = VR+- VR-. VR+< AVCC. VR-> AVSS.

Unless otherwise mentioned, dVREF > 1.5 V. Impedance of the external reference voltage R < 100 Ω, and two decoupling capacitors,

10 µF and 100 nF, should be connected to VREF+/VREF- to decouple the dynamic current. See also the MSP430F5xx and

MSP430F6xx Family User's Guide (SLAU208). (3) Parameters are derived using a best fit curve.

MIN TYP MAX UNIT

±2

±1.7

LSB

5.37 12-Bit ADC, Linearity Parameters Using AVCC as Reference Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

E E E E E

Integral linearity error

Differential linearity error

Offset error

Gain error

Total unadjusted error See

(3)

(1)

See See See See

(2) (2) (2) (2) (2)

(1) Parameters are derived using the histogram method. (2) AVCC as reference voltage is selected by: SREF2 = 0, SREF1 = 0, SREF0 = 0. (3) Parameters are derived using a best fit curve.

2.2 V, 3 V ±1.7 LSB

2.2 V, 3 V ±1 LSB

2.2 V, 3 V ±1 ±2 LSB

2.2 V, 3 V ±2 ±4 LSB

2.2 V, 3 V ±2 ±5 LSB

MIN TYP MAX UNIT

5.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS

Integral linearity error

(2)

ADC12SR = 0, REFOUT = 1 f ADC12SR = 0, REFOUT = 0 f ADC12SR = 0, REFOUT = 1 f

Differential

linearity error

(2)

ADC12SR = 0, REFOUT = 1 f ADC12SR = 0, REFOUT = 0 f

Offset error

Gain error

(3)

Total unadjusted error

ADC12SR = 0, REFOUT = 1 f ADC12SR = 0, REFOUT = 0 f ADC12SR = 0, REFOUT = 1 f ADC12SR = 0, REFOUT = 0 f ADC12SR = 0, REFOUT = 1 f ADC12SR = 0, REFOUT = 0 f

(1) The external reference voltage is selected by: SREF2 = 0, SREF1 = 0, SREF0 = 1. dVREF = VR+- VR-. (2) Parameters are derived using the histogram method. (3) Parameters are derived using a best fit curve. (4) The gain error and the total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy. In

this mode the reference voltage used by the ADC12_A is not available on a pin.

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(1)

ADC12CLK ADC12CLK ADC12CLK ADC12CLK ADC12CLK ADC12CLK ADC12CLK ADC12CLK ADC12CLK ADC12CLK ADC12CLK

≤ 4.0 MHz ±1.7 ≤ 2.7 MHz ±2.5

2.2 V, 3 V LSB

MIN TYP MAX UNIT

≤ 4.0 MHz -1 +1.5 ≤ 2.7 MHz 2.2 V, 3 V ±1 LSB ≤ 2.7 MHz -1 +2.5 ≤ 4.0 MHz ±2 ±4 ≤ 2.7 MHz ±2 ±4 ≤ 4.0 MHz ±1 ±2.5 LSB ≤ 2.7 MHz ±1% ≤ 4.0 MHz ±2 ±5 LSB ≤ 2.7 MHz ±1%

2.2 V, 3 V LSB

2.2 V, 3 V

(4)

VREF

(4)

VREF

Ambient Temperature (°C)

500

550

600

650

700

750

800

850

900

950

1000

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80

Typical Temperature Sensor Voltage (mV)

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5.39 12-Bit ADC, Temperature Sensor and Built-In V

MID

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

SENSOR

SENSOR(sample)

MID

VMID(sample)

(1)

See

Temperature coefficient of sensor ADC12ON = 1, INCH = 0Ah mV/°C

Sample time required if ADC12ON = 1, INCH = 0Ah, channel 10 is selected

(2)(3)

AVCCdivider at channel 11 V

Sample time required if ADC12ON = 1, INCH = 0Bh, channel 11 is selected

(4)

ADC12ON = 1, INCH = 0Ah, TA= 0°C

Error of conversion result ≤ 1 LSB ADC12ON = 1, INCH = 0Bh,

is approximately 0.5 × V

MID

AVCC

Error of conversion result ≤ 1 LSB

(1) The temperature sensor is provided by the REF module. See the REF module parametric, I

the temperature sensor.

2.2 V 680 3 V 680

2.2 V 2.25 3 V 2.25

2.2 V 100 3 V 100

2.2 V 1.06 1.1 1.14 3 V 1.46 1.5 1.54

2.2 V, 3 V 1000 ns , regarding the current consumption of

REF+

(2) The temperature sensor offset can be significant. A single-point calibration is recommended to minimize the offset error of the built-in

temperature sensor. The TLV structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each of the available reference voltage levels. The sensor voltage can be computed as V V Guide (SLAU208).

can be computed from the calibration values for higher accuracy. See also the MSP430F5xx and MSP430F6xx Family User's

SENSOR

SENSE

= TC

× (Temperature,°C) + V

SENSOR

(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time t (4) The on-time t

is included in the sampling time t

VMID(on)

VMID(sample)

; no additional on time is needed.

MIN TYP MAX UNIT

, where TC

SENSOR

SENSOR(on)

and

µs

Figure 5-16. Typical Temperature Sensor Voltage

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5.40 REF, External Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

eREF+

REF-/VeREF-

– Differential external

eREF+

REF-/VeREF-

, I

VeREF+

/VeREF-

VREF-

VREF+/-

Positive external reference voltage input

Negative external reference voltage input

reference voltage input

Static input current µA

Capacitance at VREF+ or VREF- terminal

> V

eREF+

1.4 V ≤ V f

ADC12CLK

Conversion rate 200 ksps

1.4 V ≤ V f

ADC12CLK

Conversion rate 20 ksps

(5)

REF-/VeREF-

> V

REF-/VeREF-

> V

REF-/VeREF-

eREF+

= 5 MHz, ADC12SHTx = 1h, 2.2 V, 3 V –26 26

eREF+

= 5 MHZ, ADC12SHTx = 8h, 2.2 V, 3 V –1.2 +1.2

≤ V

AVCC

(2)

(3)

(4)

, V

eREF-

= 0 V,

(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also

the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to let the charge settle for 12-bit accuracy.

(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced

accuracy requirements.

(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced

accuracy requirements.

(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with

reduced accuracy requirements.

(5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external

reference source if it is used for the ADC12_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).

(1)

MIN TYP MAX UNIT

1.4 AV

0 1.2 V

1.4 AV

10 µF

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5.41 REF, Built-In Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

REFVSEL = {2} for 2.5 V, REFON = REFOUT = 1 , 3 V 2.5 ±1% I

= 0 A

VREF+

REF+

Positive built-in reference voltage output

REFVSEL = {1} for 2 V, REFON = REFOUT = 1, 3 V 2.0 ±1% V I

= 0 A

VREF+

REFVSEL = {0} for 1.5 V, REFON = REFOUT = 1, 2.2 V, 3 V 1.5 ±1% I

= 0 A

VREF+

REFVSEL = {0} for 1.5 V 2.2

REFVSEL = {2} for 2.5 V 2.8 ADC12SR = 1

(4)

, REFON = 1, REFOUT = 0,

CC(min)

AVCC minimum voltage, Positive built-in reference REFVSEL = {1} for 2 V 2.3 V active

REFBURST = 0

(4)

, REFON = 1, REFOUT = 1,

(4)

, REFON = 1, REFOUT = 0,

REF+

Operating supply current into AVCC terminal

(2) (3)

ADC12SR = 1 REFBURST = 0

ADC12SR = 0 REFBURST = 0

ADC12SR = 0

(4)

, REFON = 1, REFOUT = 1,

REFBURST = 0 REFVSEL = {0, 1, 2}

L(VREF+)

VREF+

REF+

PSRR_DC TA= 25°C, REFVSEL = {0, 1, 2}, REFON = 1, 120 300 µV/V

PSRR_AC TA= 25°C, REFVSEL = {0, 1, 2}, REFON = 1, 1 mV/V

SETTLE

Load-current regulation, I VREF+ terminal

(5)

Capacitance at VREF+ REFON = REFOUT = 1, terminal 0 mA ≤ I

Temperature coefficient I of built-in reference

(7)

Power supply rejection ratio (DC)

Power supply rejection ratio (AC)

Settling time of reference

(8)

voltage

= +10 µA , –1000 µA

VREF+

AVCC= AV REFVSEL = {0, 1, 2}, REFON = REFOUT = 1

VREF+

is a constant in the range ppm/

VREF+

of 0 mA ≤ I

is a constant in the range ppm/

VREF+

of 0 mA ≤ I AVCC= AV

for each reference level,

CC(min)

(6)

≤ I

(max)

VREF+

≤ –1 mA °C

VREF+

≤ –1 mA °C

VREF+

through AV

CC(min)

REFOUT = 0 2.2 V, 3 V 20

REFOUT = 1 2.2 V, 3 V 20 50 ,

CC(max)

REFOUT = 0 or 1 AVCC= AV

CC(min)

through AV

CC(max)

REFOUT = 0 or 1 AVCC= AV

REFVSEL = {0, 1, 2}, REFOUT = 0, 75

CC(min)

through AV

CC(max)

REFON = 0 → 1 AVCC= AV

= C

VREF

REFVSEL = {0, 1, 2}, REFOUT = 1,

CC(min)

VREF

through AV

(max),

CC(max)

REFON = 0 → 1

(1) The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internal buffers, one

smaller and one larger for driving the V used as the reference for the conversion and uses the larger buffer. When REFOUT = 0, the reference is only used as the reference for

terminal. When REFOUT = 1, the reference is available at the V

REF+

the conversion and uses the smaller buffer.

(2) The internal reference current is supplied by the AVCC terminal. Consumption is independent of the ADC12ON control bit, unless a

conversion is active. REFOUT = 0 represents the current contribution of the smaller buffer. REFOUT = 1 represents the current contribution of the larger buffer without external load.

(3) The temperature sensor is provided by the REF module. Its current is supplied by terminal AVCC and is equivalent to I

REFON = 1 and REFOUT = 0. (4) For devices without the ADC12, the parametric with ADC12SR = 0 are applicable. (5) Contribution only due to the reference and buffer including package. This does not include resistance due to PCB traces or other

external factors. (6) Connect two decoupling capacitors, 10 µF and 100 nF, to VREF to decouple the dynamic current required for an external reference

source if it is used for the ADC12_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). (7) Calculated using the box method: (MAX(–40°C to +85°C) – MIN(–40°C to +85°C)) / MIN(–40°C to +85°C)/(85°C – (–40°C)). (8) The condition is that the error in a conversion started after t

capacitive load when REFOUT = 1.

is less than ±0.5 LSB. The settling time depends on the external

REFON

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3 V

2.2 V, 3 V 20 100 pF

(1)

MIN TYP MAX UNIT

70 100 µA

0.45 0.75 mA

210 310 µA

0.95 1.7 mA

1500 2500 µV/mA

µs

terminal, as well as,

REF+

with

REF+

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5.42 12-Bit DAC, Supply Specifications

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

Analog supply voltage AVCC= DVCC, AVSS= DVSS= 0 V 2.20 3.60 V

DAC12AMPx = 2, DAC12IR = 0, DAC12OG = 1, DAC12_xDAT = 0800h,

3 V 65 110 VeREF+ = VREF+ = 1.5 V DAC12AMPx = 2, DAC12IR = 1,

Supply current, single DAC channel

(1) (2)

DAC12_xDAT = 0800h, 125 165 VeREF+ = VREF+ = AV

DAC12AMPx = 5, DAC12IR = 1, DAC12_xDAT = 0800h, 2.2 V, 3 V 250 350 VeREF+ = VREF+ = AV

DAC12AMPx = 7, DAC12IR = 1, DAC12_xDAT = 0800h, 750 1100

PSRR Power supply rejection ratio

(3) (4)

VeREF+ = VREF+ = AV DAC12_xDAT = 800h,

VeREF+ = 1.5 V, ΔAVCC= 100 mV DAC12_xDAT = 800h,

2.2 V 70

VeREF+ = 1.5 V or 2.5 V, 3 V 70 ΔAVCC= 100 mV

(1) No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly. (2) Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input specifications. (3) PSRR = 20 log (ΔAVCC/ ΔV (4) The internal reference is not used.

DAC12_xOUT

)

MIN TYP MAX UNIT

µA

5.43 12-Bit DAC, Linearity Specifications

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-17)

PARAMETER TEST CONDITIONS V

Resolution 12-bit monotonic 12 bits

INL LSB

DNL LSB

Integral nonlinearity

Differential nonlinearity

(1)

VeREF+ = 1.5 V, DAC12AMPx = 7, DAC12IR = 1 2.2 V ±2 ±4 VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1 3 V ±2 ±4 VeREF+ = 1.5 V, DAC12AMPx = 7, DAC12IR = 1 2.2 V ±0.4 ±1 VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1 3 V ±0.4 ±1

VeREF+ = 1.5 V, DAC12AMPx = 7, 2.2 V ±21

Without calibration

(1) (3)

DAC12IR = 1 VeREF+ = 2.5 V,

DAC12AMPx = 7, 3 V ±21

Offset voltage mV

DAC12IR = 1 VeREF+ = 1.5 V,

DAC12AMPx = 7, 2.2 V ±1.5

With calibration

(1) (3)

DAC12IR = 1 VeREF+ = 2.5 V,

DAC12AMPx = 7, 3 V ±1.5 DAC12IR = 1

Offset error

E(O)/dT

temperature With calibration 2.2 V, 3 V ±10 µV/°C coefficient

Gain error %FSR

(1)

VeREF+ = 1.5 V 2.2 V ±2.5 VeREF+ = 2.5 V 3 V ±2.5

MIN TYP MAX UNIT

(2)

(1) Parameters calculated from the best-fit curve from 0x0F to 0xFFF. The best-fit curve method is used to deliver coefficients "a" and "b" of

the first-order equation: y = a + bx. V

(2) This parameter is not production tested.

DAC12_xOUT

(3) The offset calibration works on the output operational amplifier. Offset calibration is triggered by setting the DAC12CALON bit.

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= EO+ (1 + EG) × (VeREF+ / 4095) × DAC12_xDAT, DAC12IR = 1.

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R+

Gain Error

Offset Error

DAC Code

DACV

OUT

Ideal transfer function

R =

Load

C = 100 pF

Load

DAC Output

Positive

Negative

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12-Bit DAC, Linearity Specifications (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-17)

E(G)/dT

PARAMETER TEST CONDITIONS V

Gain temperature of coefficient

(1)

2.2 V, 3 V 10

DAC12AMPx = 2 165

Offset_Cal

Time for offset calibration

(4)

DAC12AMPx = 3, 5 2.2 V, 3 V 66 ms DAC12AMPx = 4, 6, 7 16.5

(4) The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx =

{0, 1}. TI recommends configuring the DAC12 module before initiating calibration. Port activity during calibration may effect accuracy and is not recommended.

MIN TYP MAX UNIT

ppm

FSR/

°C

Figure 5-17. Linearity Test Load Conditions and Gain/Offset Definition

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O/P(DAC12_x)

Max

0.3

AV – 0.3 VCCV

OUT

Min

Load

C = 100 pF

Load

DAC12

O/P(DAC12_x)

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5.44 12-Bit DAC, Output Specifications

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

No load, VeREF+ = AVCC, DAC12_xDAT = 0h, DAC12IR = 1, 0 0.005 DAC12AMPx = 7

No load, VeREF+ = AVCC,

Output voltage

(1)

range

(see 2.2 V, 3 V V

Figure 5-18)

DAC12_xDAT = 0FFFh, DAC12IR = 1, AV DAC12AMPx = 7

= 3 kΩ, VeREF+ = AVCC,

Load

DAC12_xDAT = 0h, DAC12IR = 1, 0 0.1 DAC12AMPx = 7

= 3 kΩ, VeREF+ = AVCC,

Load

DAC12_xDAT = 0FFFh, DAC12IR = 1, AV DAC12AMPx = 7

L(DAC12)

Maximum DAC12 load capacitance

DAC12AMPx = 2, DAC12_xDAT = 0FFFh,

L(DAC12)

O/P(DAC12)

Maximum DAC12 load current

Output resistance R (see Figure 5-18) DAC12_xDAT = 0FFFh

O/P(DAC12)

DAC12AMPx = 2, DAC12_xDAT = 0h, V

O/P(DAC12)

Load

DAC12AMPx = 2, DAC12_xDAT = 0h

Load

0.3 V ≤ V

> AVCC– 0.3

< 0.3 V

= 3 kΩ, VO/P(DAC12) < 0.3 V,

= 3 kΩ, V

O/P(DAC12)

> AVCC– 0.3 V,

= 3 kΩ,

O/P(DAC12)

≤ AVCC– 0.3 V

(1) Data is valid after the offset calibration of the output amplifier.

2.2 V, 3 V 100 pF

2.2 V, 3 V mA

2.2 V, 3 V 150 250 Ω

MIN TYP MAX UNIT

AVCC–

0.05

AVCC–

0.13

–1

150 250

Figure 5-18. DAC12_x Output Resistance Tests

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R = 3 k

Load

C = 100 pF

Load

DAC Output

O/P(DAC12.x)

Load

Conversion 1 Conversion 2

OUT

Conversion 3

Glitch

Energy

±1/2 LSB

settleLH

settleHL

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5.45 12-Bit DAC, Reference Input Specifications

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

VeREF+ 2.2 V, 3 V V

Reference input voltage range

DAC12IR = 0

DAC12IR = 1

(1) (2)

(3) (4)

DAC12_0 IR = DAC12_1 IR = 0 20 MΩ

(VREF+)

(VeREF+)

Reference input resistance

DAC12_0 IR = 1, DAC12_1 IR = 0 48

(5)

DAC12_0 IR = 0, DAC12_1 IR = 1 48 DAC12_0 IR = DAC12_1 IR = 1,

DAC12_0 SREFx = DAC12_1 SREFx

(6)

2.2 V, 3 V

(1) For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC). (2) The maximum voltage applied at reference input voltage terminal VeREF+ = (AVCC– V (3) For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC). (4) The maximum voltage applied at reference input voltage terminal VeREF+ = (AVCC– V (5) This impedance depends on tradeoff in power savings. Current devices have 48 kΩ for each channel when divide is enabled. Can be

) / (3 × (1 + EG)).

E(O)

) / (1 + EG).

E(O)

increased if performance can be maintained.

(6) When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel

reducing the reference input resistance.

MIN TYP MAX UNIT

/ 3 + 0.2

+ 0.2

5.46 12-Bit DAC, Dynamic Specifications

= VCC, DAC12IR = 1 (see Figure 5-19 and Figure 5-20), over recommended ranges of supply voltage and operating free-

REF

air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

DAC12 on time Error

DAC12_xDAT = 800h,

< ±0.5 LSB

V(O)

(see Figure 5-19)

DAC12AMPx = 0 → {2, 3, 4} 60 120

(1)

DAC12AMPx = 0 → {5, 6} 2.2 V, 3 V 15 30 µs DAC12AMPx = 0 → 7 6 12

DAC12AMPx = 2 100 200

Settling time, full scale DAC12AMPx = 3, 5 2.2 V, 3 V 40 80 µs

S(FS)

DAC12_xDAT = 80h → F7Fh → 80h

DAC12AMPx = 4, 6, 7 15 30

Settling time, code to

S(C-C)

code

DAC12_xDAT = 3F8h → 408h → 3F8h, DAC12AMPx = 3, 5 2.2 V, 3 V 2 µs BF8h → C08h → BF8h

DAC12AMPx = 2 5

DAC12AMPx = 4, 6, 7 1 DAC12AMPx = 2 0.05 0.35

SR Slew rate DAC12AMPx = 3, 5 2.2 V, 3 V 0.35 1.10 V/µs

DAC12_xDAT = 80h → F7Fh → 80h

(2)

DAC12AMPx = 4, 6, 7 1.50 5.20

Glitch energy DAC12AMPx = 7 2.2 V, 3 V 35 nV-s

(1) R (2) Slew rate applies to output voltage steps ≥ 200 mV.

Load

and C

connected to AVSS(not AVCC/2) in Figure 5-19.

Load

DAC12_xDAT = 800h → 7FFh → 800h

MIN TYP MAX UNIT

kΩ

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Figure 5-19. Settling Time and Glitch Energy Testing

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DAC12_xDAT

080h

OUT

1/f

Toggle

F7Fh

DAC12_yOUT

080h

F7Fh

080h

DAC12_xOUT

Load

C = 100 pF

Load

DAC12_1

Load

C = 100 pF

Load

DAC12_0

DAC0

DAC1

REF+

R =3k

Load

C =100pF

Load

DAC12_x

DACx

Conversion 1 Conversion 2

OUT

Conversion 3

10%

SRLH

SRHL

90%

10%

90%

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Figure 5-20. Slew Rate Testing

5.47 12-Bit DAC, Dynamic Specifications (Continued)

over recommended ranges of supply voltage and TA= 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS V

DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2, DAC12IR = 1, DAC12_xDAT = 800h

DAC12IR = 1, DAC12_xDAT = 800h DAC12AMPx = 7, DAC12SREFx = 2,

DAC12IR = 1, DAC12_xDAT = 800h DAC12_0DAT = 800h, No load,

DAC12_1DAT = 80h ↔ F7Fh, R f

DAC12_1OUT

= 10 kHz at 50/50 duty cycle

DAC12_0DAT = 80h ↔ F7Fh, R DAC12_1DAT = 800h, No load, –80 f

DAC12_0OUT

= 10 kHz at 50/50 duty cycle

= 3 kΩ, –80

Load

= 3 kΩ,

Load

–3dB

(1) R

3-dB bandwidth, VDC= 1.5 V, DAC12AMPx = {5, 6}, DAC12SREFx = 2, VAC= 0.1 V (see Figure 5-21)

Channel-to-channel crosstalk

(1)

(see 2.2 V, 3 V dB

Figure 5-22)

Load

= 3 kΩ, C

Load

= 100 pF

MIN TYP MAX UNIT

2.2 V, 3 V 180 kHz

550

Figure 5-21. Test Conditions for 3-dB Bandwidth Specification

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Figure 5-22. Crosstalk Test Conditions

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5.48 Comparator_B

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

AVCC_COMP

AVCC_REF

OFFSET

SIN

PD,filter

EN_CMP

EN_REF

CB_REF

PARAMETER TEST CONDITIONS V

Supply voltage 1.8 3.6 V

1.8 V 40

Comparator operating supply current into AVCC terminal, Excludes reference resistor ladder

CBPWRMD = 00 2.2 V 30 50

3 V 40 65 µA CBPWRMD = 01 2.2 V, 3 V 10 30 CBPWRMD = 10 2.2 V, 3 V 0.1 0.5

Quiescent current of local reference voltage amplifier CBREFACC = 1, CBREFLx = 01 22 µA into AVCC terminal

Common-mode input range

Input offset voltage mV

CBPWRMD = 00 ±20 CBPWRMD = 01, 10 ±10

Input capacitance 5 pF

Series input resistance

ON (switch closed) 3 4 kΩ OFF (switch open) 50 MΩ CBPWRMD = 00, CBF = 0 450

Propagation delay, response time

CBPWRMD = 01, CBF = 0 600 CBPWRMD = 10, CBF = 0 50 µs CBPWRMD = 00, CBON = 1, CBF = 1,

CBFDLY = 00 CBPWRMD = 00, CBON = 1, CBF = 1,

Propagation delay with filter active

CBFDLY = 01 CBPWRMD = 00, CBON = 1, CBF = 1,

CBFDLY = 10 CBPWRMD = 00, CBON = 1, CBF = 1,

CBFDLY = 11

Comparator enable time, CBON = 0 to CBON = 1 settling time CBPWRMD = 00, 01, 10

Resistor reference enable time

CBON = 0 to CBON = 1 0.3 1.5 µs

Reference voltage for a VIN = reference into resistor ladder, given tap n = 0 to 31

MIN TYP MAX UNIT

0 VCC- 1 V

0.35 0.6 1.0

0.6 1.0 1.8

1.0 1.8 3.4

1.8 3.4 6.5

VIN × VIN × VIN ×

(n + 0.5) (n + 1) (n + 1.5) V

/ 32 / 32 / 32

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µs

1 2 µs

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-90

-80

-70

-60

-50

-40

-30

-20

-10

0.5 1 1.5 2 2.5 3

V – High-Level Output Voltage – V

I – High-Level Output Current – mA

V = 1.8 V

T = 85ºC

V = 1.8 V

T = 25ºC

V = 3.0 V

T = 85ºC

V = 3.0 V

T = 25ºC

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2

V – Low-Level Output Voltage – V

I – Typical Low-Level Output Current – mA

V = 3.0 V

T = 85ºC

V = 1.8 V

T = 85ºC

V = 1.8 V

T = 25ºC

V = 3.0 V

T = 25ºC

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5.49 Ports PU.0 and PU.1

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

= 3.3 V ±10%, IOH= –25 mA,

High-level output voltage 2.4 V

Low-level output voltage 0.4 V

High-level input voltage 2.0 V

Low-level input voltage 0.8 V

LDOO

See Figure 5-24 for typical characteristics V

= 3.3 V ±10%, IOL= 25 mA,

LDOO

See Figure 5-23 for typical characteristics V

= 3.3 V ±10%,

LDOO

See Figure 5-25 for typical characteristics V

= 3.3 V ±10%,

LDOO

See Figure 5-25 for typical characteristics

Figure 5-23. Ports PU.0, PU.1 Typical Low-Level Output Characteristics

Figure 5-24. Ports PU.0, PU.1 Typical High-Level Output Characteristics

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0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

1.8 2.2 2.6 3 3.4

V – LDOO Supply Voltage – V

LDOO

IT+

, postive-going input threshold

V , negative-going input threshold

IT–

T = 25°C, 8A5°C

Input Threshold – V

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Figure 5-25. Ports PU.0, PU.1 Typical Input Threshold Characteristics

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5.50 LDO-PWR (LDO Power System)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

LAUNCH

LDOI

LDO

LDO_EXT

LDOO

DET

LDOI

LDOO

ENABLE

LDO input detection threshold 3.75 V LDO input voltage Normal operation 3.76 5.5 V LDO output voltage 3.3 ±9% V LDOO terminal input voltage with LDO

disabled

LDO disabled 1.8 3.6 V

Maximum external current from LDOO terminal LDO is on 20 mA LDO current overload detection

(1)

LDOI terminal recommended capacitance 4.7 µF LDOO terminal recommended capacitance 220 nF

Settling time V

LDO

Within 2%, recommended capacitances

(1) A current overload is detected when the total current supplied from the LDO exceeds this value.

MIN TYP MAX UNIT

60 100 mA

2 ms

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5.51 Flash Memory

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CC(PGM/ERASE)

PGM

ERASE

, I

MERASE

CPT

Retention

Word

Block, 0

Block, 1–(N–1)

Block, N

Seg Erase

MCLK,MRG

BANK

(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming

methods: individual word or byte write and block write modes.

(2) These values are hardwired into the flash controller state machine.

Program and erase supply voltage 1.8 3.6 V Average supply current from DVCC during program 3 5 mA Average supply current from DVCC during erase 6 11 mA Average supply current from DVCC during mass erase or

bank erase Cumulative program time See

(1)

Program and erase endurance 10

6 11 mA

16 ms

cycles

Data retention duration TJ= 25°C 100 years

See

(2) (2)

(2)

64 85 µs 49 65 µs

37 49 µs 55 73 µs 23 32 ms

0 1 MHz

Word or byte program time See Block program time for first byte or word See Block program time for each additional byte or word, except

for last byte or word Block program time for last byte or word See Erase time for segment, mass erase, and bank erase when

available MCLK frequency in marginal read mode

(FCTL4.MRG0 = 1 or FCTL4.MRG1 = 1)

5.52 JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER MIN TYP MAX UNIT

SBW

SBW,Low

SBW, En

SBW,Rst

TCK

internal

Spy-Bi-Wire input frequency 2.2 V, 3 V 0 20 MHz Spy-Bi-Wire low clock pulse duration 2.2 V, 3 V 0.025 15 µs Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge) Spy-Bi-Wire return to normal operation time 15 100 µs

TCK input frequency (4-wire JTAG)

(2)

Internal pulldown resistance on TEST 2.2 V, 3 V 45 60 80 kΩ

(1) Tools that access the Spy-Bi-Wire interface must wait for the t

first SBWTCK clock edge.

(2) f

may be restricted to meet the timing requirements of the module selected.

TCK

(1)

time after pulling the TEST/SBWTCK pin high before applying the

SBW,En

TEST

CONDITIONS

2.2 V, 3 V 1 µs

2.2 V 0 5 MHz 3 V 0 10 MHz

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Program Counter

PC/R0

Stack Pointer SP/R1

Status Register

SR/CG1/R2

Constant Generator CG2/R3

General-Purpose Register

R10

General-Purpose Register

R11

General-Purpose Register

R12

General-Purpose Register

R13

General-Purpose Register

R15

General-Purpose Register

R14

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6 Detailed Description

6.1 Overview

The MSP430F533x devices include an integrated 3.3-V LDO, a high-performance 12-bit ADC, a comparator, two USCIs, a hardware multiplier, DMA, four 16-bit timers, an RTC module with alarm capabilities, and up to 74 I/O pins.

6.2 CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers (see Figure 6-1).

Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be managed with all instructions.

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Figure 6-1. CPU Registers

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6.3 Instruction Set

The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data. Table 6-1 shows examples of the three types of instruction formats; Table 6-2 shows the address modes.

Table 6-1. Instruction Word Formats

INSTRUCTION WORD FORMAT EXAMPLE OPERATION

Dual operands, source-destination ADD R4,R5 R4 + R5 → R5 Single operands, destination only CALL R8 PC → (TOS), R8 → PC Relative jump, un/conditional JNE Jump-on-equal bit = 0

Table 6-2. Address Mode Descriptions

ADDRESS MODE S

Symbolic (PC relative) + + MOV EDE,TONI M(EDE) → M(TONI)

Absolute + + MOV &MEM, &TCDAT M(MEM) → M(TCDAT)

Indirect + MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) → M(Tab+R6)

Indirect auto-increment + MOV @Rn+,Rm MOV @R10+,R11

Immediate + MOV #X,TONI MOV #45,TONI #45 → M(TONI)

(1) S = source, D = destination

(1)

SYNTAX EXAMPLE OPERATION

M(R10) → R11

R10 + 2 → R10

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6.4 Operating Modes

These devices have one active mode and seven software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.

Software can configure the following operating modes:

• Active mode (AM) – All clocks are active

• Low-power mode 0 (LPM0) – CPU is disabled – ACLK and SMCLK remain active, MCLK is disabled – FLL loop control remains active

• Low-power mode 1 (LPM1) – CPU is disabled – FLL loop control is disabled – ACLK and SMCLK remain active, MCLK is disabled

• Low-power mode 2 (LPM2) – CPU is disabled – MCLK, FLL loop control, and DCOCLK are disabled – DC generator of the DCO remains enabled – ACLK remains active

• Low-power mode 3 (LPM3) – CPU is disabled – MCLK, FLL loop control, and DCOCLK are disabled – DC generator of the DCO is disabled – ACLK remains active

• Low-power mode 4 (LPM4) – CPU is disabled – ACLK is disabled – MCLK, FLL loop control, and DCOCLK are disabled – DC generator of the DCO is disabled – Crystal oscillator is stopped – Complete data retention

• Low-power mode 3.5 (LPM3.5) – Internal regulator disabled – No data retention – RTC enabled and clocked by low-frequency oscillator – Wake-up signal from RST/NMI, RTC_B, P1, P2, P3, and P4

• Low-power mode 4.5 (LPM4.5) – Internal regulator disabled – No data retention – Wake-up signal from RST/NMI, P1, P2, P3, and P4

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6.5 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence (see

Table 6-3).

Table 6-3. Interrupt Sources, Flags, and Vectors of MSP430F533x Configurations

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INTERRUPT SOURCE INTERRUPT FLAG PRIORITY

SYSTEM WORD

INTERRUPT ADDRESS

System Reset

Power-Up, External Reset

Watchdog Time-out, Key Violation

WDTIFG, KEYV (SYSRSTIV)

(1)(2)

Reset 0FFFEh 63, highest

Flash Memory Key Violation

System NMI

PMM

Vacant Memory Access

JTAG Mailbox

SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,

VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, (Non)maskable 0FFFCh 62

JMBOUTIFG (SYSSNIV)

(1)

User NMI

NMI NMIIFG, OFIFG, ACCVIFG, BUSIFG

Oscillator Fault (SYSUNIV)

(1)(2)

(Non)maskable 0FFFAh 61

Flash Memory Access Violation

Comp_B Comparator B interrupt flags (CBIV)

Timer TB0 TB0CCR0 CCIFG0 Timer TB0 Maskable 0FFF4h 58

TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,

TB0IFG (TBIV)

(1) (3)

(1)(3)

(3)

Maskable 0FFF8h 60 Maskable 0FFF6h 59

Watchdog Interval Timer Mode WDTIFG Maskable 0FFF2h 57

USCI_A0 Receive or Transmit UCA0RXIFG, UCA0TXIFG (UCA0IV) USCI_B0 Receive or Transmit UCB0RXIFG, UCB0TXIFG (UCB0IV)

ADC12_A ADC12IFG0 to ADC12IFG15 (ADC12IV)

Timer TA0 TA0CCR0 CCIFG0 Timer TA0 Maskable 0FFE8h 52

TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,

TA0IFG (TA0IV)

(1)(3)

(1)(3) (1)(3)

(1)(3)

(3)

Maskable 0FFF0h 56 Maskable 0FFEEh 55 Maskable 0FFECh 54 Maskable 0FFEAh 53

LDO-PWR LDOOFFIG, LDOONIFG, LDOOVLIFG Maskable 0FFE6h 51

DMA Maskable 0FFE4h 50 Timer TA1 TA1CCR0 CCIFG0 Timer TA1 Maskable 0FFE0h 48

I/O Port P1 P1IFG.0 to P1IFG.7 (P1IV) USCI_A1 Receive or Transmit UCA1RXIFG, UCA1TXIFG (UCA1IV) USCI_B1 Receive or Transmit UCB1RXIFG, UCB1TXIFG (UCB1IV)

I/O Port P2 P2IFG.0 to P2IFG.7 (P2IV)

DMA0IFG, DMA1IFG, DMA2IFG, DMA3IFG,

DMA4IFG, DMA5IFG (DMAIV)

TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,

TA1IFG (TA1IV)

(1)(3)

(3)

(1)(3)

(1) (3)

(1)(3) (1)(3)

(1) (3)

Maskable 0FFE2h 49

Maskable 0FFDEh 47 Maskable 0FFDCh 46 Maskable 0FFDAh 45 Maskable 0FFD8h 44

Reserved Reserved Maskable 0FFD6h 43

RTC_B Maskable 0FFD4h 42

DAC12_A

(4)

Timer TA2 TA2CCR0 CCIFG0 Timer TA2 Maskable 0FFCEh 39

I/O Port P3 P3IFG.0 to P3IFG.7 (P3IV)

I/O Port P4 P4IFG.0 to P4IFG.7 (P4IV)

RTCRDYIFG, RTCTEVIFG, RTCAIFG,

RT0PSIFG, RT1PSIFG, RTCOFIFG (RTCIV)

DAC12_0IFG, DAC12_1IFG

TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,

TA2IFG (TA2IV)

(1)(3)

(3)

(1)(3)

(1)(3) (1)(3)

(1)(3)

Maskable 0FFD2h 41 Maskable 0FFD0h 40

Maskable 0FFCCh 38 Maskable 0FFCAh 37

(1) Multiple source flags (2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.

(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it. (3) Interrupt flags are located in the module. (4) Only on devices with peripheral module DAC12_A, otherwise reserved.

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Table 6-3. Interrupt Sources, Flags, and Vectors of MSP430F533x Configurations (continued)

INTERRUPT SOURCE INTERRUPT FLAG PRIORITY

Reserved Reserved

(5) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain

compatibility with other devices, TI recommends reserving these locations.

(5)

SYSTEM WORD

INTERRUPT ADDRESS

0FFC8h 36

⋮ ⋮

0FF80h 0, lowest

6.6 Memory

Table 6-4 shows the memory organization for all device variants.

Table 6-4. Memory Organization

MSP430F5333 MSP430F5336

Memory (flash) Total Size 128KB 128KB 256KB Main: interrupt vector 00FFFFh-00FF80h 00FFFFh-00FF80h 00FFFFh-00FF80h

Bank 3 N/A N/A 64KB

Bank 2 N/A N/A 64KB

Main: code memory

RAM

Information memory (flash)

Bootloader (BSL) memory (flash)

Peripherals

(1) N/A = Not available. (2) Backup RAM is accessed through the control registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3.

Bank 1 64KB 64KB 64KB

027FFF-018000h 027FFF-018000h 027FFF-018000h

Bank 0 64KB 64KB 64KB

017FFF-008000h 017FFF-008000h 017FFF-008000h

Sector 3 N/A 4KB 4KB

0063FFh-005400h 0063FFh-005400h

Sector 2 N/A 4KB 4KB

0053FFh-004400h 0053FFh-004400h

Sector 1 4KB 4KB 4KB

0043FFh-003400h 0043FFh-003400h 0043FFh-003400h

Sector 0 4KB 4KB 4KB

0033FFh-002400h 0033FFh-002400h 0033FFh-002400h

Sector 7 2KB 2KB 2KB

0023FFh-001C00h 0023FFh-001C00h 0023FFh-001C00h

Info A 128 B 128 B 128 B

0019FFh-001980h 0019FFh-001980h 0019FFh-001980h

Info B 128 B 128 B 128 B

00197Fh-001900h 00197Fh-001900h 00197Fh-001900h

Info C 128 B 128 B 128 B

0018FFh-001880h 0018FFh-001880h 0018FFh-001880h

Info D 128 B 128 B 128 B

00187Fh-001800h 00187Fh-001800h 00187Fh-001800h

BSL 3 512 B 512 B 512 B

0017FFh-001600h 0017FFh-001600h 0017FFh-001600h

BSL 2 512 B 512 B 512 B

0015FFh-001400h 0015FFh-001400h 0015FFh-001400h

BSL 1 512 B 512 B 512 B

0013FFh-001200h 0013FFh-001200h 0013FFh-001200h

BSL 0 512 B 512 B 512 B

0011FFh-001000h 0011FFh-001000h 0011FFh-001000h

Size 4KB 4KB 4KB

000FFFh-000000h 000FFFh-000000h 000FFFh-000000h

(1) (2)

MSP430F5338 MSP430F5335

047FFF-038000h

037FFF-028000h

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6.7 Bootloader (BSL)

The BSL enables users to program the flash memory or RAM using a UART serial interfaces. Access to the device memory by the BSL is protected by an user-defined password. Use of the BSL requires external access to six pins (see Table 6-5). BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For complete description of the features of the BSL and its implementation, see MSP430 Programming With the Bootloader (BSL) (SLAU319).

Table 6-5. UART BSL Pin Requirements and Functions

DEVICE SIGNAL BSL FUNCTION

RST/NMI/SBWTDIO Entry sequence signal

6.8 JTAG Operation

6.8.1 JTAG Standard Interface

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TEST/SBWTCK Entry sequence signal

P1.1 Data transmit P1.2 Data receive VCC Power supply VSS Ground supply

The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430 development tools and device programmers. Table 6-6 lists the JTAG pin requirements. For further details on interfacing to development tools and device programmers, see the MSP430™ Hardware Tools User's Guide (SLAU278). For a complete description of the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface (SLAU320).

Table 6-6. JTAG Pin Requirements and Functions

DEVICE SIGNAL DIRECTION FUNCTION

PJ.3/TCK IN JTAG clock input PJ.2/TMS IN JTAG state control

PJ.1/TDI/TCLK IN JTAG data input, TCLK input

PJ.0/TDO OUT JTAG data output

TEST/SBWTCK IN Enable JTAG pins

RST/NMI/SBWTDIO IN External reset

VCC Power supply VSS Ground supply

6.8.2 Spy-Bi-Wire Interface

In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface. Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers.

Table 6-7 lists the Spy-Bi-Wire interface pin requirements. For further details on interfacing to

development tools and device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278). For a complete description of the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface (SLAU320).

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Table 6-7. Spy-Bi-Wire Pin Requirements and Functions

DEVICE SIGNAL DIRECTION FUNCTION

TEST/SBWTCK IN Spy-Bi-Wire clock input

RST/NMI/SBWTDIO IN, OUT Spy-Bi-Wire data input/output

VCC Power supply VSS Ground supply

6.9 Flash Memory (Link to User's Guide)

The flash memory can be programmed by the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the flash memory include:

• Flash memory has n segments of main memory and four segments of information memory (A to D) of 128 bytes each. Each segment in main memory is 512 bytes in size.

• Segments 0 to n may be erased in one step, or each segment may be individually erased.

• Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also called information memory.

• Segment A can be locked separately.

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6.10 RAM (Link to User's Guide)

The RAM is made up of n sectors. Each sector can be completely powered down to save leakage; however, all data is lost. Features of the RAM include:

• RAM has n sectors. The size of a sector can be found in Memory Organization.

• Each sector 0 to n can be complete disabled; however, data retention is lost.

• Each sector 0 to n automatically enters low power retention mode when possible.

6.11 Backup RAM

The backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5 and during operation from a backup supply if the Battery Backup System module is implemented.

There are 8 bytes of backup RAM available on MSP430F533x. It can be wordwise accessed by the control registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3.

6.12 Peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).

6.12.1 Digital I/O (Link to User's Guide)

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Up to nine 8-bit I/O ports are implemented: P1 through P6, P8, and P9 are complete, P7 contains six individual I/O ports, and PJ contains four individual I/O ports.

• All individual I/O bits are independently programmable.

• Any combination of input, output, and interrupt conditions is possible.

• Programmable pullup or pulldown on all ports.

• Programmable drive strength on all ports.

• Edge-selectable interrupt input capability for all the eight bits of ports P1, P2, P3, and P4.

• Read and write access to port-control registers is supported by all instructions.

• Ports can be accessed byte-wise (P1 through P9) or word-wise in pairs (PA through PD).

6.12.2 Port Mapping Controller (Link to User's Guide)

The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P2.

Table 6-8 lists the mnemonic for each function that can be assigned.

Table 6-8. Port Mapping Mnemonics and Functions

VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION

0 PM_NONE None DV

4 PM_TB0CCR0B Timer TB0 CCR0 capture input CCI0B Timer TB0: TB0.0 compare output Out0 5 PM_TB0CCR1B Timer TB0 CCR1 capture input CCI1B Timer TB0: TB0.1 compare output Out1 6 PM_TB0CCR2B Timer TB0 CCR2 capture input CCI2B Timer TB0: TB0.2 compare output Out2 7 PM_TB0CCR3B Timer TB0 CCR3 capture input CCI3B Timer TB0: TB0.3 compare output Out3 8 PM_TB0CCR4B Timer TB0 CCR4 capture input CCI4B Timer TB0: TB0.4 compare output Out4

PM_CBOUT - Comparator_B output

PM_TB0CLK Timer TB0 clock input -

PM_ADC12CLK - ADC12CLK

PM_DMAE0 DMAE0 Input -

PM_SVMOUT - SVM output

PM_TB0OUTH -

Timer TB0 high impedance input

TB0OUTH

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Table 6-8. Port Mapping Mnemonics and Functions (continued)

VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION

9 PM_TB0CCR5B Timer TB0 CCR5 capture input CCI5B Timer TB0: TB0.5 compare output Out5

10 PM_TB0CCR6B Timer TB0 CCR6 capture input CCI6B Timer TB0: TB0.6 compare output Out6

17 PM_MCLK - MCLK 18 Reserved Reserved for test purposes. Do not use this setting. 19 Reserved Reserved for test purposes. Do not use this setting.

20-30 Reserved None DVSS

31 (0FFh)

(1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are 5 bits wide and the upper bits are ignored,

(1)

which results in a maximum value of 31.

PM_UCA0RXD USCI_A0 UART RXD (Direction controlled by USCI – input)

PM_UCA0SOMI USCI_A0 SPI slave out master in (direction controlled by USCI)

PM_UCA0TXD USCI_A0 UART TXD (Direction controlled by USCI – output)

PM_UCA0SIMO USCI_A0 SPI slave in master out (direction controlled by USCI)

PM_UCA0CLK USCI_A0 clock input/output (direction controlled by USCI) PM_UCB0STE USCI_B0 SPI slave transmit enable (direction controlled by USCI – input)

PM_UCB0SOMI USCI_B0 SPI slave out master in (direction controlled by USCI)

PM_UCB0SCL USCI_B0 I2C clock (open drain and direction controlled by USCI)

PM_UCB0SIMO USCI_B0 SPI slave in master out (direction controlled by USCI)

PM_UCB0SDA USCI_B0 I2C data (open drain and direction controlled by USCI)

PM_UCB0CLK USCI_B0 clock input/output (direction controlled by USCI) PM_UCA0STE USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)

PM_ANALOG

Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents

when applying analog signals.

Table 6-9 lists the default port mapping for all supported pins.

Table 6-9. Default Mapping

PIN INPUT PIN FUNCTION OUTPUT PIN FUNCTION

P2.0/P2MAP0

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P2.5/P2MAP5 P2.6/P2MAP6 PM_NONE - DVSS

P2.7/P2MAP7 PM_NONE - DVSS

PxMAPy

MNEMONIC

PM_UCB0STE, USCI_B0 SPI slave transmit enable (direction controlled by USCI – input),

PM_UCA0CLK USCI_A0 clock input/output (direction controlled by USCI)

PM_UCB0SIMO, USCI_B0 SPI slave in master out (direction controlled by USCI),

PM_UCB0SDA USCI_B0 I2C data (open drain and direction controlled by USCI)

PM_UCB0SOMI, USCI_B0 SPI slave out master in (direction controlled by USCI),

PM_UCB0SCL USCI_B0 I2C clock (open drain and direction controlled by USCI)

PM_UCB0CLK, USCI_B0 clock input/output (direction controlled by USCI),

PM_UCA0STE USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)

PM_UCA0TXD, USCI_A0 UART TXD (direction controlled by USCI – output),

PM_UCA0SIMO USCI_A0 SPI slave in master out (direction controlled by USCI) PM_UCA0RXD, USCI_A0 UART RXD (direction controlled by USCI – input),

PM_UCA0SOMI USCI_A0 SPI slave out master in (direction controlled by USCI)

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6.12.3 Oscillator and System Clock (Link to User's Guide)

The clock system is supported by the Unified Clock System (UCS) module that includes support for a 32kHz watch crystal oscillator (in XT1 LF mode; XT1 HF mode is not supported), an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an integrated internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator XT2. The UCS module is designed to meet the requirements of both low system cost and low power consumption. The UCS module features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turnon clock source and stabilizes in 3 µs (typical). The UCS module provides the following clock signals:

• Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1), a high-frequency crystal (XT2), the

internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitally-controlled oscillator DCO.

• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources

available to ACLK.

• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be

sourced by same sources available to ACLK.

• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.

6.12.4 Power-Management Module (PMM) (Link to User's Guide)

The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is implemented to provide the proper internal reset signal to the device during poweron and power-off. The SVS and SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.

6.12.5 Hardware Multiplier (MPY) (Link to User's Guide)

The multiplication operation is supported by a dedicated peripheral module. The module performs operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication as well as signed and unsigned multiply-and-accumulate operations.

6.12.6 Real-Time Clock (RTC_B) (Link to User's Guide)

The RTC_B module can be configured for real-time clock (RTC) or calendar mode providing seconds, minutes, hours, day of week, day of month, month, and year. Calendar mode integrates an internal calendar which compensates for months with less than 31 days and includes leap year correction. The RTC_B also supports flexible alarm functions and offset-calibration hardware. The implementation on this device supports operation in LPM3.5 mode and operation from a backup supply.

The application report Using the MSP430 RTC_B Module With Battery Backup Supply (SLAA665) describes how to use the RTC_B with battery backup supply functionality to retain the time and keep the RTC counting through loss of main power supply, and how to perform correct reinitialization when the main power supply is restored.

6.12.7 Watchdog Timer (WDT_A) (Link to User's Guide)

The primary function of the WDT_A module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.

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6.12.8 System Module (SYS) (Link to User's Guide)

The SYS module handles many of the system functions within the device. These include power-on reset and power-up clear handling, NMI source selection and management, reset interrupt vector generators, bootloader entry mechanisms, and configuration management (device descriptors). SYS also includes a data exchange mechanism through JTAG called a JTAG mailbox that can be used in the application.

Table 6-10 lists the SYS interrupt vector registers.

Table 6-10. System Module Interrupt Vector Registers

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INTERRUPT VECTOR

SYSRSTIV, System Reset 019Eh

SYSSNIV, System NMI VMAIFG 019Ch 0Ah

SYSUNIV, User NMI OFIFG 019Ah 04h

INTERRUPT EVENT WORD ADDRESS OFFSET PRIORITY

No interrupt pending 00h

Brownout (BOR) 02h Highest RST/NMI (BOR) 04h

PMMSWBOR (BOR) 06h

LPM3.5 or LPM4.5 wakeup (BOR) 08h

Security violation (BOR) 0Ah

SVSL (POR) 0Ch

SVSH (POR) 0Eh

SVML_OVP (POR) 10h

SVMH_OVP (POR) 12h

PMMSWPOR (POR) 14h

WDT time-out (PUC) 16h

WDT key violation (PUC) 18h

KEYV flash key violation (PUC) 1Ah

Reserved 1Ch

Peripheral area fetch (PUC) 1Eh

PMM key violation (PUC) 20h

Reserved 22h to 3Eh Lowest

No interrupt pending 00h

SVMLIFG 02h Highest

SVMHIFG 04h

DLYLIFG 06h

DLYHIFG 08h

JMBINIFG 0Ch

JMBOUTIFG 0Eh SVMLVLRIFG 10h SVMHVLRIFG 12h

Reserved 14h to 1Eh Lowest

No interrupt pending 00h

NMIIFG 02h Highest

ACCVIFG 06h

Reserved 08h to 1Eh Lowest

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6.12.9 DMA Controller (Link to User's Guide)

The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or from a peripheral. Table 6-11 lists the trigger assignments for each DMA channel.

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Table 6-11. DMA Trigger Assignments

TRIGGER

0 DMAREQ 1 TA0CCR0 CCIFG 2 TA0CCR2 CCIFG 3 TA1CCR0 CCIFG 4 TA1CCR2 CCIFG 5 TA2CCR0 CCIFG 6 TA2CCR2 CCIFG 7 TBCCR0 CCIFG 8 TBCCR2 CCIFG

9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 UCA0RXIFG 17 UCA0TXIFG 18 UCB0RXIFG 19 UCB0TXIFG 20 UCA1RXIFG 21 UCA1TXIFG 22 UCB1RXIFG 23 UCB1TXIFG 24 ADC12IFGx 25 DAC12_0IFG 26 DAC12_1IFG 27 Reserved 28 Reserved 29 MPY ready 30 DMA5IFG DMA0IFG DMA1IFG DMA2IFG DMA3IFG DMA4IFG 31 DMAE0

(1) Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers will not

cause any DMA trigger event when selected.

(2) Only on devices with peripheral module DAC12_A. Reserved on devices without DAC.

0 1 2 3 4 5

CHANNEL

(2) (2)

(1)

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6.12.10 Universal Serial Communication Interface (USCI) (Links to User's Guide: UART

Mode, SPI Mode, I2C Mode)

The USCI modules are used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3-pin or 4-pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI module contains two portions, A and B.

The USCI_An module provides support for SPI (3-pin or 4-pin), UART, enhanced UART, or IrDA. The USCI_Bn module provides support for SPI (3-pin or 4-pin) or I2C. The MSP430F533x series includes two complete USCI modules (n = 0 to 1).

6.12.11 Timer TA0 (Link to User's Guide)

Timer TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers (see Table 6-12). TA0 can support multiple capture/compares, PWM outputs, and interval timing. TA0 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each capture/compare register.

Table 6-12. Timer TA0 Signal Connections

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INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER

PZ ZQW PZ ZQW

INPUT INPUT OUTPUT OUTPUT

SIGNAL SIGNAL SIGNAL SIGNAL

MODULE

BLOCK

34-P1.0 L5-P1.0 TA0CLK TACLK

ACLK ACLK

SMCLK SMCLK

Timer NA NA

34-P1.0 L5-P1.0 TA0CLK TACLK 35-P1.1 M5-P1.1 TA0.0 CCI0A 35-P1.1 M5-P1.1

DV DV

SS SS

CCI0B

GND

CCR0 TA0 TA0.0

36-P1.2 J6-P1.2 TA0.1 CCI1A 36-P1.2 J6-P1.2 40-P1.6 J7-P1.6 TA0.1 CCI1B 40-P1.6 J7-P1.6

GND

CCR1 TA1 TA0.1

ADC12_A (internal)

ADC12SHSx = {1}

37-P1.3 H6-P1.3 TA0.2 CCI2A 37-P1.3 H6-P1.3 41-P1.7 M7-P1.7 TA0.2 CCI2B 41-P1.7 M7-P1.7

GND

CCR2 TA2 TA0.2

38-P1.4 M6-P1.4 TA0.3 CCI3A 38-P1.4 M6-P1.4

DV DV

SS SS

CCI3B

GND

CCR3 TA3 TA0.3

39-P1.5 L6-P1.5 TA0.4 CCI4A 39-P1.5 L6-P1.5

DV DV

SS SS

CCI4B

GND

CCR4 TA4 TA0.4

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6.12.12 Timer TA1 (Link to User's Guide)

Timer TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers(see Table 6-13). TA1 supports multiple capture/compares, PWM outputs, and interval timing. TA1 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each capture/compare register.

Table 6-13. Timer TA1 Signal Connections

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INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER

PZ ZQW PZ ZQW

INPUT INPUT OUTPUT OUTPUT

SIGNAL SIGNAL SIGNAL SIGNAL

MODULE

BLOCK

42-P3.0 L7-P3.0 TA1CLK TACLK

ACLK ACLK

SMCLK SMCLK

Timer NA NA

42-P3.0 L7-P3.0 TA1CLK TACLK 43-P3.1 H7-P3.1 TA1.0 CCI0A 43-P3.1 H7-P3.1

DV DV

SS SS

CCI0B

GND

CCR0 TA0 TA1.0

44-P3.2 M8-P3.2 TA1.1 CCI1A 44-P3.2 M8-P3.2

CBOUT

(internal)

CCI1B DAC12_0, DAC12_1

CCR1 TA1 TA1.1

GND

DAC12_A

(internal)

45-P3.3 L8-P3.3 TA1.2 CCI2A 45-P3.3 L8-P3.3

ACLK

(internal)

CCI2B

GND

CCR2 TA2 TA1.2

(1) Only on devices with peripheral module DAC12_A.

(1)

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6.12.13 Timer TA2 (Link to User's Guide)

Timer TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers(see Table 6-14). TA2 supports multiple capture/compares, PWM outputs, and interval timing. TA2 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each capture/compare register.

Table 6-14. Timer TA2 Signal Connections

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INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER

PZ ZQW PZ ZQW

INPUT INPUT OUTPUT OUTPUT

SIGNAL SIGNAL SIGNAL SIGNAL

MODULE

BLOCK

46-P3.4 J8-P3.4 TA2CLK TACLK

ACLK ACLK

SMCLK SMCLK

Timer NA NA

46-P3.4 J8-P3.4 TA2CLK TACLK 47-P3.5 M9-P3.5 TA2.0 CCI0A 47-P3.5 M9-P3.5

DV DV

SS SS

CCI0B

GND

CCR0 TA0 TA2.0

48-P3.6 L9-P3.6 TA2.1 CCI1A 48-P3.6 L9-P3.6

CBOUT

(internal)

CCI1B

GND

CCR1 TA1 TA2.1

49-P3.7 M10-P3.7 TA2.2 CCI2A 49-P3.7 M10-P3.7

ACLK

(internal)

CCI2B

GND

CCR2 TA2 TA2.2

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6.12.14 Timer TB0 (Link to User's Guide)

Timer TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers(see Table 6-15). TB0 supports multiple capture/compares, PWM outputs, and interval timing. TB0 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each capture/compare register.

Table 6-15. Timer TB0 Signal Connections

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INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER

PZ ZQW PZ ZQW

58-P8.0 J11-P8.0

P2MAPx

(1)

P2MAPx

(1)

INPUT INPUT OUTPUT OUTPUT

SIGNAL SIGNAL SIGNAL SIGNAL

TB0CLK TB0CLK

ACLK ACLK

SMCLK SMCLK

58-P8.0 J11-P8.0

P2MAPx

(1)

P2MAPx

TB0CLK TB0CLK

(1)

MODULE

BLOCK

Timer NA NA

50-P4.0 J9-P4.0 TB0.0 CCI0A 50-P4.0 J9-P4.0

P2MAPx

(1)

P2MAPx

(1)

TB0.0 CCI0B P2MAPx

GND

CCR0 TB0 TB0.0

(1)

P2MAPx

ADC12 (internal)

ADC12SHSx = {2}

51-P4.1 M11-P4.1 TB0.1 CCI1A 51-P4.1 M11-P4.1

P2MAPx

(1)

P2MAPx

(1)

TB0.1 CCI1B P2MAPx

GND

CCR1 TB1 TB0.1

(1)

P2MAPx

ADC12 (internal)

ADC12SHSx = {3}

52-P4.2 L10-P4.2 TB0.2 CCI2A 52-P4.2 L10-P4.2

P2MAPx

(1)

P2MAPx

(1)

TB0.2 CCI2B P2MAPx

GND DAC12_0, DAC12_1

CCR2 TB2 TB0.2

(1)

DAC12_A

(internal)

P2MAPx

53-P4.3 M12-P4.3 TB0.3 CCI3A 53-P4.3 M12-P4.3

P2MAPx

(1)

P2MAPx

(1)

TB0.3 CCI3B P2MAPx

GND

CCR3 TB3 TB0.3

(1)

P2MAPx

54-P4.4 L12-P4.4 TB0.4 CCI4A 54-P4.4 L12-P4.4

P2MAPx

(1)

P2MAPx

(1)

TB0.4 CCI4B P2MAPx

GND

CCR4 TB4 TB0.4

(1)

P2MAPx

55-P4.5 L11-P4.5 TB0.5 CCI5A 55-P4.5 L11-P4.5

P2MAPx

(1)

P2MAPx

(1)

TB0.5 CCI5B P2MAPx

GND

CCR5 TB5 TB0.5

(1)

P2MAPx

56-P4.6 K11-P4.6 TB0.6 CCI6A 56-P4.6 K11-P4.6

P2MAPx

(1)

P2MAPx

(1)

TB0.6 CCI6B P2MAPx

GND

CCR6 TB6 TB0.6

(1)

P2MAPx

(1) Timer functions selectable by the port mapping controller. (2) Only on devices with peripheral module DAC12_A.

(1)

(2)

(1)

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6.12.15 Comparator_B (Link to User's Guide)

The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions, battery voltage supervision, and monitoring of external analog signals.

6.12.16 ADC12_A (Link to User's Guide)

The ADC12_A module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention.

6.12.17 DAC12_A (Link to User's Guide)

The DAC12_A module is a 12-bit R-ladder voltage-output DAC. The DAC12_A may be used in 8-bit or 12bit mode, and may be used with the DMA controller. When multiple DAC12_A modules are present, they may be grouped together for synchronous operation.

6.12.18 CRC16 (Link to User's Guide)

The CRC16 module produces a signature based on a sequence of entered data values and can be used for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.

6.12.19 Voltage Reference (REF) Module (Link to User's Guide)

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The REF module generates all of the critical reference voltages that can be used by the various analog peripherals in the device.

6.12.20 LDO and PU Port

The integrated 3.3-V power system incorporates an integrated 3.3-V LDO regulator that allows the entire MSP430 microcontroller to be powered from nominal 5-V LDOI when it is made available for the system. Alternatively, the power system can supply power only to other components within the system, or it can be unused altogether.

The Port U Pins (PU.0/PU.1) function as general-purpose high-current I/O pins. These pins can only be configured together as either both inputs or both outputs. Port U is supplied by the LDOO rail. If the 3.3-V LDO is not being used in the system (disabled), the LDOO pin can be supplied externally.

6.12.21 Embedded Emulation Module (EEM) (Link to User's Guide)

The EEM supports real-time in-system debugging. The L version of the EEM has the following features:

• Eight hardware triggers or breakpoints on memory access

• Two hardware triggers or breakpoints on CPU register write access

• Up to 10 hardware triggers can be combined to form complex triggers or breakpoints

• Two cycle counters

• Sequencer

• State storage

• Clock control on module level

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6.12.22 Peripheral File Map

Table 6-16 lists the register base address for all of the available peripheral modules.

Table 6-16. Peripherals

MODULE NAME BASE ADDRESS OFFSET ADDRESS RANGE

Special Functions (see Table 6-17) 0100h 000h-01Fh

PMM (see Table 6-18) 0120h 000h-010h

Flash Control (see Table 6-19) 0140h 000h-00Fh

CRC16 (see Table 6-20) 0150h 000h-007h

RAM Control (see Table 6-21) 0158h 000h-001h

Watchdog (see Table 6-22) 015Ch 000h-001h

UCS (see Table 6-23) 0160h 000h-01Fh

SYS (see Table 6-24) 0180h 000h-01Fh

Shared Reference (see Table 6-25) 01B0h 000h-001h

Port Mapping Control (see Table 6-26) 01C0h 000h-003h

Port Mapping Port P2 (see Table 6-26) 01D0h 000h-007h

Port P1, P2 (see Table 6-27) 0200h 000h-01Fh Port P3, P4 (see Table 6-28) 0220h 000h-01Fh Port P5, P6 (see Table 6-29) 0240h 000h-00Bh Port P7, P8 (see Table 6-30) 0260h 000h-00Bh

Port P9 (see Table 6-31) 0280h 000h-00Bh

Port PJ (see Table 6-32) 0320h 000h-01Fh Timer TA0 (see Table 6-33) 0340h 000h-02Eh Timer TA1 (see Table 6-34) 0380h 000h-02Eh Timer TB0 (see Table 6-35) 03C0h 000h-02Eh Timer TA2 (see Table 6-36) 0400h 000h-02Eh

Battery Backup (see Table 6-37) 0480h 000h-01Fh

RTC_B (see Table 6-38) 04A0h 000h-01Fh

32-bit Hardware Multiplier (see Table 6-39) 04C0h 000h-02Fh

DMA General Control (see Table 6-40) 0500h 000h-00Fh

DMA Channel 0 (see Table 6-40) 0510h 000h-00Ah DMA Channel 1 (see Table 6-40) 0520h 000h-00Ah DMA Channel 2 (see Table 6-40) 0530h 000h-00Ah DMA Channel 3 (see Table 6-40) 0540h 000h-00Ah DMA Channel 4 (see Table 6-40) 0550h 000h-00Ah DMA Channel 5 (see Table 6-40) 0560h 000h-00Ah

USCI_A0 (see Table 6-41) 05C0h 000h-01Fh USCI_B0 (see Table 6-42) 05E0h 000h-01Fh USCI_A1 (see Table 6-43) 0600h 000h-01Fh

USCI_B1 (see Table 6-44) 0620h 000h-01Fh ADC12_A (see Table 6-45) 0700h 000h-03Fh DAC12_A (see Table 6-46) 0780h 000h-01Fh

Comparator_B (see Table 6-47) 08C0h 000h-00Fh

LDO and Port U configuration (see Table 6-48) 0900h 000h-014h

(1) For a detailed description of the individual control register offset addresses, see the MSP430x5xx and MSP430x6xx Family User's Guide

(SLAU208).

(1)

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Table 6-17. Special Function Registers (Base Address: 0100h)

SFR interrupt enable SFRIE1 00h SFR interrupt flag SFRIFG1 02h SFR reset pin control SFRRPCR 04h

Table 6-18. PMM Registers (Base Address: 0120h)

PMM control 0 PMMCTL0 00h PMM control 1 PMMCTL1 02h SVS high-side control SVSMHCTL 04h SVS low-side control SVSMLCTL 06h PMM interrupt flags PMMIFG 0Ch PMM interrupt enable PMMIE 0Eh PMM power mode 5 control PM5CTL0 10h

Table 6-19. Flash Control Registers (Base Address: 0140h)

Flash control 1 FCTL1 00h Flash control 3 FCTL3 04h Flash control 4 FCTL4 06h

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Table 6-20. CRC16 Registers (Base Address: 0150h)

CRC data input CRC16DI 00h CRC result CRC16INIRES 04h

Table 6-21. RAM Control Registers (Base Address: 0158h)

RAM control 0 RCCTL0 00h

Table 6-22. Watchdog Registers (Base Address: 015Ch)

Watchdog timer control WDTCTL 00h

Table 6-23. UCS Registers (Base Address: 0160h)

UCS control 0 UCSCTL0 00h UCS control 1 UCSCTL1 02h UCS control 2 UCSCTL2 04h UCS control 3 UCSCTL3 06h UCS control 4 UCSCTL4 08h UCS control 5 UCSCTL5 0Ah UCS control 6 UCSCTL6 0Ch UCS control 7 UCSCTL7 0Eh UCS control 8 UCSCTL8 10h

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Table 6-24. SYS Registers (Base Address: 0180h)

System control SYSCTL 00h Bootloader configuration area SYSBSLC 02h JTAG mailbox control SYSJMBC 06h JTAG mailbox input 0 SYSJMBI0 08h JTAG mailbox input 1 SYSJMBI1 0Ah JTAG mailbox output 0 SYSJMBO0 0Ch JTAG mailbox output 1 SYSJMBO1 0Eh Bus error vector generator SYSBERRIV 18h User NMI vector generator SYSUNIV 1Ah System NMI vector generator SYSSNIV 1Ch Reset vector generator SYSRSTIV 1Eh

Table 6-25. Shared Reference Registers (Base Address: 01B0h)

Shared reference control REFCTL 00h

Table 6-26. Port Mapping Registers

(Base Address of Port Mapping Control: 01C0h, Port P2: 01D0h)

Port mapping password PMAPPWD 00h Port mapping control PMAPCTL 02h Port P2.0 mapping P2MAP0 00h Port P2.1 mapping P2MAP1 01h Port P2.2 mapping P2MAP2 02h Port P2.3 mapping P2MAP3 03h Port P2.4 mapping P2MAP4 04h Port P2.5 mapping P2MAP5 05h Port P2.6 mapping P2MAP6 06h Port P2.7 mapping P2MAP7 07h

Table 6-27. Port P1, P2 Registers (Base Address: 0200h)

Port P1 input P1IN 00h Port P1 output P1OUT 02h Port P1 direction P1DIR 04h Port P1 pullup/pulldown enable P1REN 06h Port P1 drive strength P1DS 08h Port P1 selection P1SEL 0Ah Port P1 interrupt vector word P1IV 0Eh Port P1 interrupt edge select P1IES 18h Port P1 interrupt enable P1IE 1Ah Port P1 interrupt flag P1IFG 1Ch Port P2 input P2IN 01h Port P2 output P2OUT 03h Port P2 direction P2DIR 05h Port P2 pullup/pulldown enable P2REN 07h

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Table 6-27. Port P1, P2 Registers (Base Address: 0200h) (continued)

Port P2 drive strength P2DS 09h Port P2 selection P2SEL 0Bh Port P2 interrupt vector word P2IV 1Eh Port P2 interrupt edge select P2IES 19h Port P2 interrupt enable P2IE 1Bh Port P2 interrupt flag P2IFG 1Dh

Table 6-28. Port P3, P4 Registers (Base Address: 0220h)

Port P3 input P3IN 00h Port P3 output P3OUT 02h Port P3 direction P3DIR 04h Port P3 pullup/pulldown enable P3REN 06h Port P3 drive strength P3DS 08h Port P3 selection P3SEL 0Ah Port P3 interrupt vector word P3IV 0Eh Port P3 interrupt edge select P3IES 18h Port P3 interrupt enable P3IE 1Ah Port P3 interrupt flag P3IFG 1Ch Port P4 input P4IN 01h Port P4 output P4OUT 03h Port P4 direction P4DIR 05h Port P4 pullup/pulldown enable P4REN 07h Port P4 drive strength P4DS 09h Port P4 selection P4SEL 0Bh Port P4 interrupt vector word P4IV 1Eh Port P4 interrupt edge select P4IES 19h Port P4 interrupt enable P4IE 1Bh Port P4 interrupt flag P4IFG 1Dh

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Table 6-29. Port P5, P6 Registers (Base Address: 0240h)

Port P5 input P5IN 00h Port P5 output P5OUT 02h Port P5 direction P5DIR 04h Port P5 pullup/pulldown enable P5REN 06h Port P5 drive strength P5DS 08h Port P5 selection P5SEL 0Ah Port P6 input P6IN 01h Port P6 output P6OUT 03h Port P6 direction P6DIR 05h Port P6 pullup/pulldown enable P6REN 07h Port P6 drive strength P6DS 09h Port P6 selection P6SEL 0Bh

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Table 6-30. Port P7, P8 Registers (Base Address: 0260h)

Port P7 input P7IN 00h Port P7 output P7OUT 02h Port P7 direction P7DIR 04h Port P7 pullup/pulldown enable P7REN 06h Port P7 drive strength P7DS 08h Port P7 selection P7SEL 0Ah Port P8 input P8IN 01h Port P8 output P8OUT 03h Port P8 direction P8DIR 05h Port P8 pullup/pulldown enable P8REN 07h Port P8 drive strength P8DS 09h Port P8 selection P8SEL 0Bh

Table 6-31. Port P9 Register (Base Address: 0280h)

Port P9 input P9IN 00h Port P9 output P9OUT 02h Port P9 direction P9DIR 04h Port P9 pullup/pulldown enable P9REN 06h Port P9 drive strength P9DS 08h Port P9 selection P9SEL 0Ah

Table 6-32. Port J Registers (Base Address: 0320h)

Port PJ input PJIN 00h Port PJ output PJOUT 02h Port PJ direction PJDIR 04h Port PJ pullup/pulldown enable PJREN 06h Port PJ drive strength PJDS 08h

Table 6-33. TA0 Registers (Base Address: 0340h)

TA0 control TA0CTL 00h Capture/compare control 0 TA0CCTL0 02h Capture/compare control 1 TA0CCTL1 04h Capture/compare control 2 TA0CCTL2 06h Capture/compare control 3 TA0CCTL3 08h Capture/compare control 4 TA0CCTL4 0Ah TA0 counter TA0R 10h Capture/compare 0 TA0CCR0 12h Capture/compare 1 TA0CCR1 14h Capture/compare 2 TA0CCR2 16h Capture/compare 3 TA0CCR3 18h Capture/compare 4 TA0CCR4 1Ah TA0 expansion 0 TA0EX0 20h TA0 interrupt vector TA0IV 2Eh

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Table 6-34. TA1 Registers (Base Address: 0380h)

TA1 control TA1CTL 00h Capture/compare control 0 TA1CCTL0 02h Capture/compare control 1 TA1CCTL1 04h Capture/compare control 2 TA1CCTL2 06h TA1 counter TA1R 10h Capture/compare 0 TA1CCR0 12h Capture/compare 1 TA1CCR1 14h Capture/compare 2 TA1CCR2 16h TA1 expansion 0 TA1EX0 20h TA1 interrupt vector TA1IV 2Eh

Table 6-35. TB0 Registers (Base Address: 03C0h)

TB0 control TB0CTL 00h Capture/compare control 0 TB0CCTL0 02h Capture/compare control 1 TB0CCTL1 04h Capture/compare control 2 TB0CCTL2 06h Capture/compare control 3 TB0CCTL3 08h Capture/compare control 4 TB0CCTL4 0Ah Capture/compare control 5 TB0CCTL5 0Ch Capture/compare control 6 TB0CCTL6 0Eh TB0 counter TB0R 10h Capture/compare 0 TB0CCR0 12h Capture/compare 1 TB0CCR1 14h Capture/compare 2 TB0CCR2 16h Capture/compare 3 TB0CCR3 18h Capture/compare 4 TB0CCR4 1Ah Capture/compare 5 TB0CCR5 1Ch Capture/compare 6 TB0CCR6 1Eh TB0 expansion 0 TB0EX0 20h TB0 interrupt vector TB0IV 2Eh

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Table 6-36. TA2 Registers (Base Address: 0400h)

TA2 control TA2CTL 00h Capture/compare control 0 TA2CCTL0 02h Capture/compare control 1 TA2CCTL1 04h Capture/compare control 2 TA2CCTL2 06h TA2 counter TA2R 10h Capture/compare 0 TA2CCR0 12h Capture/compare 1 TA2CCR1 14h Capture/compare 2 TA2CCR2 16h TA2 expansion 0 TA2EX0 20h TA2 interrupt vector TA2IV 2Eh

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Table 6-37. Battery Backup Registers (Base Address: 0480h)

Battery backup memory 0 BAKMEM0 00h Battery backup memory 1 BAKMEM1 02h Battery backup memory 2 BAKMEM2 04h Battery backup memory 3 BAKMEM3 06h Battery backup control BAKCTL 1Ch Battery charger control BAKCHCTL 1Eh

Table 6-38. Real-Time Clock Registers (Base Address: 04A0h)

RTC control 0 RTCCTL0 00h RTC control 1 RTCCTL1 01h RTC control 2 RTCCTL2 02h RTC control 3 RTCCTL3 03h RTC prescaler 0 control RTCPS0CTL 08h RTC prescaler 1 control RTCPS1CTL 0Ah RTC prescaler 0 RTCPS0 0Ch RTC prescaler 1 RTCPS1 0Dh RTC interrupt vector word RTCIV 0Eh RTC seconds RTCSEC 10h RTC minutes RTCMIN 11h RTC hours RTCHOUR 12h RTC day of week RTCDOW 13h RTC days RTCDAY 14h RTC month RTCMON 15h RTC year low RTCYEARL 16h RTC year high RTCYEARH 17h RTC alarm minutes RTCAMIN 18h RTC alarm hours RTCAHOUR 19h RTC alarm day of week RTCADOW 1Ah RTC alarm days RTCADAY 1Bh Binary-to-BCD conversion BIN2BCD 1Ch BCD-to-binary conversion BCD2BIN 1Eh

Table 6-39. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)

16-bit operand 1 – multiply MPY 00h 16-bit operand 1 – signed multiply MPYS 02h 16-bit operand 1 – multiply accumulate MAC 04h 16-bit operand 1 – signed multiply accumulate MACS 06h 16-bit operand 2 OP2 08h 16 × 16 result low word RESLO 0Ah 16 × 16 result high word RESHI 0Ch 16 × 16 sum extension SUMEXT 0Eh 32-bit operand 1 – multiply low word MPY32L 10h 32-bit operand 1 – multiply high word MPY32H 12h 32-bit operand 1 – signed multiply low word MPYS32L 14h 32-bit operand 1 – signed multiply high word MPYS32H 16h

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Table 6-39. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h) (continued)

32-bit operand 1 – multiply accumulate low word MAC32L 18h 32-bit operand 1 – multiply accumulate high word MAC32H 1Ah 32-bit operand 1 – signed multiply accumulate low word MACS32L 1Ch 32-bit operand 1 – signed multiply accumulate high word MACS32H 1Eh 32-bit operand 2 – low word OP2L 20h 32-bit operand 2 – high word OP2H 22h 32 × 32 result 0 – least significant word RES0 24h 32 × 32 result 1 RES1 26h 32 × 32 result 2 RES2 28h 32 × 32 result 3 – most significant word RES3 2Ah MPY32 control 0 MPY32CTL0 2Ch

Table 6-40. DMA Registers (Base Address DMA General Control: 0500h,

DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA

Channel 4: 0550h, DMA Channel 5: 0560h)

DMA general control: DMA module control 0 DMACTL0 00h DMA general control: DMA module control 1 DMACTL1 02h DMA general control: DMA module control 2 DMACTL2 04h DMA general control: DMA module control 3 DMACTL3 06h DMA general control: DMA module control 4 DMACTL4 08h DMA general control: DMA interrupt vector DMAIV 0Ah DMA channel 0 control DMA0CTL 00h DMA channel 0 source address low DMA0SAL 02h DMA channel 0 source address high DMA0SAH 04h DMA channel 0 destination address low DMA0DAL 06h DMA channel 0 destination address high DMA0DAH 08h DMA channel 0 transfer size DMA0SZ 0Ah DMA channel 1 control DMA1CTL 00h DMA channel 1 source address low DMA1SAL 02h DMA channel 1 source address high DMA1SAH 04h DMA channel 1 destination address low DMA1DAL 06h DMA channel 1 destination address high DMA1DAH 08h DMA channel 1 transfer size DMA1SZ 0Ah DMA channel 2 control DMA2CTL 00h DMA channel 2 source address low DMA2SAL 02h DMA channel 2 source address high DMA2SAH 04h DMA channel 2 destination address low DMA2DAL 06h DMA channel 2 destination address high DMA2DAH 08h DMA channel 2 transfer size DMA2SZ 0Ah DMA channel 3 control DMA3CTL 00h DMA channel 3 source address low DMA3SAL 02h DMA channel 3 source address high DMA3SAH 04h DMA channel 3 destination address low DMA3DAL 06h DMA channel 3 destination address high DMA3DAH 08h DMA channel 3 transfer size DMA3SZ 0Ah DMA channel 4 control DMA4CTL 00h

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Table 6-40. DMA Registers (Base Address DMA General Control: 0500h,

DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA

Channel 4: 0550h, DMA Channel 5: 0560h) (continued)

DMA channel 4 source address low DMA4SAL 02h DMA channel 4 source address high DMA4SAH 04h DMA channel 4 destination address low DMA4DAL 06h DMA channel 4 destination address high DMA4DAH 08h DMA channel 4 transfer size DMA4SZ 0Ah DMA channel 5 control DMA5CTL 00h DMA channel 5 source address low DMA5SAL 02h DMA channel 5 source address high DMA5SAH 04h DMA channel 5 destination address low DMA5DAL 06h DMA channel 5 destination address high DMA5DAH 08h DMA channel 5 transfer size DMA5SZ 0Ah

Table 6-41. USCI_A0 Registers (Base Address: 05C0h)

USCI control 0 UCA0CTL0 00h USCI control 1 UCA0CTL1 01h USCI baud rate 0 UCA0BR0 06h USCI baud rate 1 UCA0BR1 07h USCI modulation control UCA0MCTL 08h USCI status UCA0STAT 0Ah USCI receive buffer UCA0RXBUF 0Ch USCI transmit buffer UCA0TXBUF 0Eh USCI LIN control UCA0ABCTL 10h USCI IrDA transmit control UCA0IRTCTL 12h USCI IrDA receive control UCA0IRRCTL 13h USCI interrupt enable UCA0IE 1Ch USCI interrupt flags UCA0IFG 1Dh USCI interrupt vector word UCA0IV 1Eh

Table 6-42. USCI_B0 Registers (Base Address: 05E0h)

USCI synchronous control 0 UCB0CTL0 00h USCI synchronous control 1 UCB0CTL1 01h USCI synchronous bit rate 0 UCB0BR0 06h USCI synchronous bit rate 1 UCB0BR1 07h USCI synchronous status UCB0STAT 0Ah USCI synchronous receive buffer UCB0RXBUF 0Ch USCI synchronous transmit buffer UCB0TXBUF 0Eh USCI I2C own address UCB0I2COA 10h USCI I2C slave address UCB0I2CSA 12h USCI interrupt enable UCB0IE 1Ch USCI interrupt flags UCB0IFG 1Dh USCI interrupt vector word UCB0IV 1Eh

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Table 6-43. USCI_A1 Registers (Base Address: 0600h)

USCI control 0 UCA1CTL0 00h USCI control 1 UCA1CTL1 01h USCI baud rate 0 UCA1BR0 06h USCI baud rate 1 UCA1BR1 07h USCI modulation control UCA1MCTL 08h USCI status UCA1STAT 0Ah USCI receive buffer UCA1RXBUF 0Ch USCI transmit buffer UCA1TXBUF 0Eh USCI LIN control UCA1ABCTL 10h USCI IrDA transmit control UCA1IRTCTL 12h USCI IrDA receive control UCA1IRRCTL 13h USCI interrupt enable UCA1IE 1Ch USCI interrupt flags UCA1IFG 1Dh USCI interrupt vector word UCA1IV 1Eh

Table 6-44. USCI_B1 Registers (Base Address: 0620h)

USCI synchronous control 0 UCB1CTL0 00h USCI synchronous control 1 UCB1CTL1 01h USCI synchronous bit rate 0 UCB1BR0 06h USCI synchronous bit rate 1 UCB1BR1 07h USCI synchronous status UCB1STAT 0Ah USCI synchronous receive buffer UCB1RXBUF 0Ch USCI synchronous transmit buffer UCB1TXBUF 0Eh USCI I2C own address UCB1I2COA 10h USCI I2C slave address UCB1I2CSA 12h USCI interrupt enable UCB1IE 1Ch USCI interrupt flags UCB1IFG 1Dh USCI interrupt vector word UCB1IV 1Eh

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Table 6-45. ADC12_A Registers (Base Address: 0700h)

ADC12 control 0 ADC12CTL0 00h ADC12 control 1 ADC12CTL1 02h ADC12 control 2 ADC12CTL2 04h Interrupt flag ADC12IFG 0Ah Interrupt enable ADC12IE 0Ch Interrupt vector word ADC12IV 0Eh ADC memory control 0 ADC12MCTL0 10h ADC memory control 1 ADC12MCTL1 11h ADC memory control 2 ADC12MCTL2 12h ADC memory control 3 ADC12MCTL3 13h ADC memory control 4 ADC12MCTL4 14h ADC memory control 5 ADC12MCTL5 15h ADC memory control 6 ADC12MCTL6 16h ADC memory control 7 ADC12MCTL7 17h ADC memory control 8 ADC12MCTL8 18h

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Table 6-45. ADC12_A Registers (Base Address: 0700h) (continued)

ADC memory control 9 ADC12MCTL9 19h ADC memory control 10 ADC12MCTL10 1Ah ADC memory control 11 ADC12MCTL11 1Bh ADC memory control 12 ADC12MCTL12 1Ch ADC memory control 13 ADC12MCTL13 1Dh ADC memory control 14 ADC12MCTL14 1Eh ADC memory control 15 ADC12MCTL15 1Fh Conversion memory 0 ADC12MEM0 20h Conversion memory 1 ADC12MEM1 22h Conversion memory 2 ADC12MEM2 24h Conversion memory 3 ADC12MEM3 26h Conversion memory 4 ADC12MEM4 28h Conversion memory 5 ADC12MEM5 2Ah Conversion memory 6 ADC12MEM6 2Ch Conversion memory 7 ADC12MEM7 2Eh Conversion memory 8 ADC12MEM8 30h Conversion memory 9 ADC12MEM9 32h Conversion memory 10 ADC12MEM10 34h Conversion memory 11 ADC12MEM11 36h Conversion memory 12 ADC12MEM12 38h Conversion memory 13 ADC12MEM13 3Ah Conversion memory 14 ADC12MEM14 3Ch Conversion memory 15 ADC12MEM15 3Eh

Table 6-46. DAC12_A Registers (Base Address: 0780h)

DAC12_A channel 0 control 0 DAC12_0CTL0 00h DAC12_A channel 0 control 1 DAC12_0CTL1 02h DAC12_A channel 0 data DAC12_0DAT 04h DAC12_A channel 0 calibration control DAC12_0CALCTL 06h DAC12_A channel 0 calibration data DAC12_0CALDAT 08h DAC12_A channel 1 control 0 DAC12_1CTL0 10h DAC12_A channel 1 control 1 DAC12_1CTL1 12h DAC12_A channel 1 data DAC12_1DAT 14h DAC12_A channel 1 calibration control DAC12_1CALCTL 16h DAC12_A channel 1 calibration data DAC12_1CALDAT 18h DAC12_A interrupt vector word DAC12IV 1Eh

Table 6-47. Comparator_B Registers (Base Address: 08C0h)

Comp_B control 0 CBCTL0 00h Comp_B control 1 CBCTL1 02h Comp_B control 2 CBCTL2 04h Comp_B control 3 CBCTL3 06h Comp_B interrupt CBINT 0Ch Comp_B interrupt vector word CBIV 0Eh

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Table 6-48. LDO and Port U Configuration Registers (Base Address: 0900h)

LDO key/ID LDOKEYID 00h PU port control PUCTL 04h LDO power control LDOPWRCTL 08h

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P1.0/TA0CLK/ACLK P1.1/TA0.0 P1.2/TA0.1 P1.3/TA0.2 P1.4/TA0.3 P1.5/TA0.4 P1.6/TA0.1 P1.7/TA0.2

Direction 0:Input 1:Output

P1SEL.x

P1DIR.x

P1IN.x

P1IRQ.x

ModuleXIN

ModuleXOUT

P1OUT.x

Interrupt

Edge

Select

Set

P1SEL.x

P1IES.x

P1IFG.x

P1IE.x

P1REN.x

PadLogic

P1DS.x 0:Lowdrive 1:Highdrive

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6.13 Input/Output Schematics

6.13.1 Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger

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Figure 6-2. Port P1 (P1.0 to P1.7) Schematic

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Table 6-49. Port P1 (P1.0 to P1.7) Pin Functions

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PIN NAME (P1.x) x FUNCTION

P1.0/TA0CLK/ACLK 0 P1.0 (I/O) I: 0; O: 1 0

Timer TA0.TA0CLK 0 1 ACLK 1 1

P1.1/TA0.0 1 P1.1 (I/O) I: 0; O: 1 0

Timer TA0.CCI0A capture input 0 1 Timer TA0.0 output 1 1

P1.2/TA0.1 2 P1.2 (I/O) I: 0; O: 1 0

Timer TA0.CCI1A capture input 0 1 Timer TA0.1 output 1 1

P1.3/TA0.2 3 P1.3 (I/O) I: 0; O: 1 0

Timer TA0.CCI2A capture input 0 1 Timer TA0.2 output 1 1

P1.4/TA0.3 4 P1.4 (I/O) I: 0; O: 1 0

Timer TA0.CCI3A capture input 0 1 Timer TA0.3 output 1 1

P1.5/TA0.4 5 P1.5 (I/O) I: 0; O: 1 0

Timer TA0.CCI4A capture input 0 1 Timer TA0.4 output 1 1

P1.6/TA0.1 6 P1.6 (I/O) I: 0; O: 1 0

Timer TA0.CCI1B capture input 0 1 Timer TA0.1 output 1 1

P1.7/TA0.2 7 P1.7 (I/O) I: 0; O: 1 0

Timer TA0.CCI2B capture input 0 1 Timer TA0.2 output 1 1

CONTROL BITS OR SIGNALS

P1DIR.x P1SEL.x

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P2.0/P2MAP0 P2.1/P2MAP1 P2.2/P2MAP2 P2.3/P2MAP3 P2.4/P2MAP4 P2.5/P2MAP5 P2.6/P2MAP6 P2.7/P2MAP7

Direction 0:Input 1:Output

P2SEL.x

P2DIR.x

P2IN.x

P2IRQ.x

ToPortMapping

FromPortMapping

P2OUT.x

Interrupt

Edge

Select

Set

P2SEL.x

P2IES.x

P2IFG.x

P2IE.x

P2REN.x

PadLogic

P2DS.x 0:Lowdrive 1:Highdrive

FromPortMapping

MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333

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SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

6.13.2 Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger

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Figure 6-3. Port P2 (P2.0 to P2.7) Schematic

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Table 6-50. Port P2 (P2.0 to P2.7) Pin Functions

PIN NAME (P2.x) x FUNCTION

P2.0/P2MAP0 0 P2.0 (I/O) I: 0; O: 1 0

Mapped secondary digital function X 1 ≤ 19

P2.1/P2MAP1 1 P2.1 (I/O) I: 0; O: 1 0

Mapped secondary digital function X 1 ≤ 19

P2.2/P2MAP2 2 P2.2 (I/O) I: 0; O: 1 0

Mapped secondary digital function X 1 ≤ 19

P2.3/P2MAP3 3 P2.3 (I/O) I: 0; O: 1 0

Mapped secondary digital function X 1 ≤ 19

P2.4/P2MAP4 4 P2.4 (I/O) I: 0; O: 1 0

Mapped secondary digital function X 1 ≤ 19

P2.5/P2MAP5 5 P2.5 (I/O I: 0; O: 1 0

Mapped secondary digital function X 1 ≤ 19

P2.6/P2MAP6 6 P2.6 (I/O) I: 0; O: 1 0

Mapped secondary digital function X 1 ≤ 19

P2.7/P2MAP7 7 P2.7 (I/O) I: 0; O: 1 0

Mapped secondary digital function X 1 ≤ 19

(1) X = Don't care

CONTROL BITS OR SIGNALS

P2DIR.x P2SEL.x P2MAPx

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(1)

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P3.0/TA1CLK/CBOUT P3.1/TA1.0 P3.2/TA1.1 P3.3/TA1.2 P3.4/TA2CLK/SMCLK P3.5/TA2.0 P3.6/TA2.1 P3.7/TA2.2

Direction 0:Input 1:Output

P3SEL.x

P3DIR.x

P3IN.x

ModuleXIN

ModuleXOUT

P3OUT.x

P3REN.x

PadLogic

P3DS.x 0:Lowdrive 1:Highdrive

P3IRQ.x

Interrupt

Edge

Select

Set

P3SEL.x

P3IES.x

P3IFG.x

P3IE.x

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SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

6.13.3 Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger

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Figure 6-4. Port P3 (P3.0 to P3.7) Schematic

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SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

Table 6-51. Port P3 (P3.0 to P3.7) Pin Functions

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PIN NAME (P3.x) x FUNCTION

P3.0/TA1CLK/CBOUT 0 P3.0 (I/O) I: 0; O: 1 0

Timer TA1.TA1CLK 0 1 CBOUT 1 1

P3.1/TA1.0 1 P3.1 (I/O) I: 0; O: 1 0

Timer TA1.CCI0A capture input 0 1 Timer TA1.0 output 1 1

P3.2/TA1.1 2 P3.2 (I/O) I: 0; O: 1 0

Timer TA1.CCI1A capture input 0 1 Timer TA1.1 output 1 1

P3.3/TA1.2 3 P3.3 (I/O) I: 0; O: 1 0

Timer TA1.CCI2A capture input 0 1 Timer TA1.2 output 1 1

P3.4/TA2CLK/SMCLK 4 P3.4 (I/O) I: 0; O: 1 0

Timer TA2.TA2CLK 0 1 SMCLK 1 1

P3.5/TA2.0 5 P3.5 (I/O) I: 0; O: 1 0

Timer TA2.CCI0A capture input 0 1 Timer TA2.0 output 1 1

P3.6/TA2.1 6 P3.6 (I/O) I: 0; O: 1 0

Timer TA2.CCI1A capture input 0 1 Timer TA2.1 output 1 1

P3.7/TA2.2 7 P3.7 (I/O) I: 0; O: 1 0

Timer TA2.CCI2A capture input 0 1 Timer TA2.2 output 1 1

CONTROL BITS OR SIGNALS

P3DIR.x P3SEL.x

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P4.0/TB0.0 P4.1/TB0.1 P4.2/TB0.2 P4.3/TB0.3 P4.4/TB0.4 P4.5/TB0.5 P4.6/TB0.6 P4.7/TB0OUTH/SVMOUT

Direction 0:Input 1:Output

P4SEL.x

P4DIR.x

P4IN.x

ModuleXIN

ModuleXOUT

P4OUT.x

P4REN.x

PadLogic

P4DS.x 0:Lowdrive 1:Highdrive

P4IRQ.x

Interrupt

Edge

Select

Set

P4SEL.x

P4IES.x

P4IFG.x

P4IE.x

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SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

6.13.4 Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger

Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333

Figure 6-5. Port P4 (P4.0 to P4.7) Schematic

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SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

Table 6-52. Port P4 (P4.0 to P4.7) Pin Functions

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PIN NAME (P4.x) x FUNCTION

CONTROL BITS OR SIGNALS

P4DIR.x P4SEL.x

P4.0/TB0.0 0 P4.0 (I/O) I: 0; O: 1 0

Timer TB0.CCI0A capture input 0 1 Timer TB0.0 output

(1)

1 1

P4.1/TB0.1 1 P4.1 (I/O) I: 0; O: 1 0

Timer TB0.CCI1A capture input 0 1 Timer TB0.1 output

(1)

1 1

P4.2/TB0.2 2 P4.2 (I/O) I: 0; O: 1 0

Timer TB0.CCI2A capture input 0 1 Timer TB0.2 output

(1)

1 1

P4.3/TB0.3 3 P4.3 (I/O) I: 0; O: 1 0

Timer TB0.CCI3A capture input 0 1 Timer TB0.3 output

(1)

1 1

P4.4/TB0.4 4 P4.4 (I/O) I: 0; O: 1 0

Timer TB0.CCI4A capture input 0 1 Timer TB0.4 output

(1)

1 1

P4.5/TB0.5 5 P4.5 (I/O) I: 0; O: 1 0

Timer TB0.CCI5A capture input 0 1 Timer TB0.5 output

(1)

1 1

P4.6/TB0.6 6 P4.6 (I/O) I: 0; O: 1 0

Timer TB0.CCI6A capture input 0 1 Timer TB0.6 output

(1)

1 1

P4.7/TB0OUTH/ 7 P4.7 (I/O) I: 0; O: 1 0 SVMOUT

Timer TB0.TB0OUTH 0 1 SVMOUT 1 1

(1) Setting TB0OUTH causes all Timer_B configured outputs to be set to high impedance.

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P5.0/VREF+/VeREF+ P5.1/VREF–/VeREF–

P5SEL.x

P5DIR.x

P5IN.x

ModuleXIN

ModuleXOUT

P5OUT.x

P5REN.x

PadLogic

P5DS.x 0:Lowdrive 1:Highdrive

Bus

Keeper

To/From

Reference

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SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

6.13.5 Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger

Figure 6-6. Port P5 (P5.0 and P5.1) Schematic

Table 6-53. Port P5 (P5.0 and P5.1) Pin Functions

PIN NAME (P5.x) x FUNCTION

P5.0/VREF+/VeREF+ 0 P5.0 (I/O)

VeREF+ VREF+

P5.1/VREF-/VeREF- 1 P5.1 (I/O)

VeREFVREF-

(1) X = Don't care (2) Default condition (3) Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog

signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC12_A, Comparator_B, or DAC12_A.

(4) Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog

signals. The ADC12_A, VREF+ reference is available at the pin.

(5) Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog

signals. An external voltage can be applied to VeREF- and used as the reference for the ADC12_A, Comparator_B, or DAC12_A.

(6) Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog

signals. The ADC12_A, VREF- reference is available at the pin.

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CONTROL BITS OR SIGNALS

(1)

P5DIR.x P5SEL.x REFOUT

(2)

(3)

(4)

(2)

(5)

(6)

I: 0; O: 1 0 X

X 1 0 X 1 1

I: 0; O: 1 0 X

X 1 0 X 1 1

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P5.2 P5.3 P5.4 P5.5 P5.6/ADC12CLK/DMAE0 P5.7/RTCCLK

Direction 0:Input 1:Output

P5SEL.x

P5DIR.x

P5IN.x

ModuleXIN

ModuleXOUT

P5OUT.x

P5REN.x

PadLogic

P5DS.x 0:Lowdrive 1:Highdrive

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SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

6.13.6 Port P5, P5.2 to P5.7, Input/Output With Schmitt Trigger

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Figure 6-7. Port P5 (P5.2 to P5.7) Schematic

Table 6-54. Port P5 (P5.2 to P5.7) Pin Functions

PIN NAME (P5.x) x FUNCTION

P5.2 2 P5.2 (I/O) I: 0; O: 1 0 P5.3 3 P5.3 (I/O) I: 0; O: 1 0 P5.4 4 P5.4 (I/O) I: 0; O: 1 0 P5.5 5 P5.5 (I/O) I: 0; O: 1 0 P5.6/ADC12CLK/DMAE0 6 P5.6 (I/O) I: 0; O: 1 0

ADC12CLK 1 1 DMAE0 0 1

P5.7/RTCCLK 7 P5.7 (I/O) I: 0; O: 1 0

RTCCLK 1 1

CONTROL BITS OR SIGNALS

P5DIR.x P5SEL.x

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P6SEL.x

P6DIR.x

P6IN.x

P6OUT.x

P6REN.x

PadLogic

P6DS.x 0:Lowdrive 1:Highdrive

Bus

Keeper

To ADC12

P6.0/CB0/A0 P6.1/CB1/A1 P6.2/CB2/A2 P6.3/CB3/A3 P6.4/CB4/A4 P6.5/CB5/A5 P6.6/CB6/A6/DAC0 P6.7/CB7/A7/DAC1

INCHx=y

FromDAC12_A

ToComparator_B

FromComparator_B

CBPD.x

Dvss

0ifDAC12AMPx=0 1ifDAC12AMPx=1 2ifDAC12AMPx>1

DAC12AMPx>0

DAC12OPS

MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333

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SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

6.13.7 Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger

Figure 6-8. Port P6 (P6.0 to P6.7) Schematic

Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333

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Table 6-55. Port P6 (P6.0 to P6.7) Pin Functions

PIN NAME (P6.x) x FUNCTION

P6DIR.x P6SEL.x CBPD.x DAC12OPS DAC12AMPx

CONTROL BITS OR SIGNALS

P6.0/CB0/A0 0 P6.0 (I/O) I: 0; O: 1 0 0 n/a n/a

CB0 X X 1 n/a n/a

(2) (3)

X 1 X n/a n/a

P6.1/CB1/A1 1 P6.1 (I/O) I: 0; O: 1 0 0 n/a n/a

CB1 X X 1 n/a n/a

(2) (3)

X 1 X n/a n/a

P6.2/CB2/A2 2 P6.2 (I/O) I: 0; O: 1 0 0 n/a n/a

CB2 X X 1 n/a n/a

(2) (3)

X 1 X n/a n/a

P6.3/CB3/A3 3 P6.3 (I/O) I: 0; O: 1 0 0 n/a n/a

CB3 X X 1 n/a n/a

(2) (3)

X 1 X n/a n/a

P6.4/CB4/A4 4 P6.4 (I/O) I: 0; O: 1 0 0 n/a n/a

CB4 X X 1 n/a n/a

(2) (3)

X 1 X n/a n/a

P6.5/CB5/A5 5 P6.5 (I/O) I: 0; O: 1 0 0 n/a n/a

CB5 X X 1 n/a n/a

(2) (3)

X 1 X n/a n/a

P6.6/CB6/A6/DAC0 6 P6.6 (I/O) I: 0; O: 1 0 0 X 0

CB6 X X 1 X 0

(2) (3)

X 1 X X 0

DAC0 X X X 0 >1

P6.7/CB7/A7/DAC1 7 P6.7 (I/O) I: 0; O: 1 0 0 X 0

CB7 X X 1 X 0

(2) (3)

X 1 X X 0

DAC1 X X X 0 >1

(1) X = Don't care (2) Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog

signals.

(3) The ADC12_A channel Ax is connected internally to AVSSif not selected by the respective INCHx bits.

(1)

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P7.2/XT2IN

P7SEL.2

P7DIR.2

P7IN.2

P7OUT.2

P7REN.2

PadLogic

P7DS.2 0:Lowdrive 1:Highdrive

Bus

Keeper

ToXT2

MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333

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6.13.8 Port P7, P7.2, Input/Output With Schmitt Trigger

SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

Figure 6-9. Port P7 (P7.2) Schematic

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P7.3/XT2OUT

P7DIR.3

P7IN.3

P7OUT.3

P7REN.3

Pad Logic

P7DS.3 0: Low drive 1: High drive

Bus

Keeper

To XT2

P7SEL.2

XT2BYPASS

P7SEL.3

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SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

6.13.9 Port P7, P7.3, Input/Output With Schmitt Trigger

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Figure 6-10. Port P7 (P7.3) Schematic

Table 6-56. Port P7 (P7.2 and P7.3) Pin Functions

PIN NAME (P5.x) x FUNCTION

P7DIR.x P7SEL.2 P7SEL.3 XT2BYPASS

P7.2/XT2IN 2 P7.2 (I/O) I: 0; O: 1 0 X X

XT2IN crystal mode XT2IN bypass mode

(2)

X 1 X 0 X 1 X 1

CONTROL BITS OR SIGNALS

P7.3/XT2OUT 3 P7.3 (I/O) I: 0; O: 1 0 0 X

(3)

X 1 X 0 X 1 0 1

XT2OUT crystal mode P7.3 (I/O)

(3)

(1) X = Don't care (2) Setting P7SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P7.2 is configured for crystal

mode or bypass mode.

(3) Setting P7SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P7.3 can be used as

general-purpose I/O.

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(1)

P7SEL.x

P7DIR.x

P7IN.x

P7OUT.x

P7REN.x

PadLogic

P7DS.x 0:Lowdrive 1:Highdrive

Bus

Keeper

FromDAC12_A

P7.4/CB8/A12 P7.5/CB9/A13 P7.6/CB10/A14/DAC0 P7.7/CB11/A15/DAC1

INCHx=y

To ADC12

ToComparator_B

FromComparator_B

CBPD.x

Dvss

0ifDAC12AMPx=0 1ifDAC12AMPx=1 2ifDAC12AMPx>1

DAC12AMPx>0

DAC12OPS

MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333

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SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

6.13.10 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger

Figure 6-11. Port P7 (P7.4 to P7.7) Schematic

Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333

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Table 6-57. Port P7 (P7.4 to P7.7) Pin Functions

PIN NAME (P7.x) x FUNCTION

P7DIR.x P7SEL.x CBPD.x DAC12OPS DAC12AMPx

CONTROL BITS OR SIGNALS

P7.4/CB8/A12 4 P7.4 (I/O) I: 0; O: 1 0 0 n/a n/a

Comparator_B input CB8 X X 1 n/a n/a

(2) (3)

A12

X 1 X n/a n/a

P7.5/CB9/A13 5 P7.5 (I/O) I: 0; O: 1 0 0 n/a n/a

Comparator_B input CB9 X X 1 n/a n/a

(2) (3)

A13

X 1 X n/a n/a

P7.6/CB10/A14/DAC0 6 P7.6 (I/O) I: 0; O: 1 0 0 X 0

Comparator_B input CB10 X X 1 X 0

(2) (3)

A14

X 1 X X 0

DAC12_A output DAC0 X X X 1 >1

P7.7/CB11/A15/DAC1 7 P7.7 (I/O) I: 0; O: 1 0 0 X 0

Comparator_B input CB11 X X 1 X 0

(2) (3)

A15

X 1 X X 0

DAC12_A output DAC1 X X X 1 >1

(1) X = Don't care (2) Setting the P7SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog

signals.

(3) The ADC12_A channel Ax is connected internally to AVSSif not selected by the respective INCHx bits.

(1)

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P8.0/TB0CLK P8.1/UCB1STE/UCA1CLK P8.2/UCA1TXD/UCA1SIMO P8.3/UCA1RXD/UCA1SOMI P8.4/UCB1CLK/UCA1STE P8.5/UCB1SIMO//UCB1SDA P8.6/UCB1SOMI/UCB1SCL P8.7

Direction 0:Input 1:Output

P8SEL.x

P8DIR.x

P8IN.x

ModuleXIN

ModuleXOUT

P8OUT.x

P8REN.x

PadLogic

P8DS.x 0:Lowdrive 1:Highdrive

Frommodule

MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333

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SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

6.13.11 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger

Figure 6-12. Port P8 (P8.0 to P8.7) Schematic

Table 6-58. Port P8 (P8.0 to P8.7) Pin Functions

CONTROL BITS OR

PIN NAME (P9.x) x FUNCTION

SIGNALS

P8DIR.x P8SEL.x

P8.0/TB0CLK 0 P8.0 (I/O) I: 0; O: 1 0

Timer TB0.TB0CLK clock input 0 1

P8.1/UCB1STE/UCA1CLK 1 P8.1 (I/O) I: 0; O: 1 0

UCB1STE/UCA1CLK X 1

P8.2/UCA1TXD/UCA1SIMO 2 P8.2 (I/O) I: 0; O: 1 0

UCA1TXD/UCA1SIMO X 1

P8.3/UCA1RXD/UCA1SOMI 3 P8.3 (I/O) I: 0; O: 1 0

UCA1RXD/UCA1SOMI X 1

P8.4/UCB1CLK/UCA1STE 4 P8.4 (I/O) I: 0; O: 1 0

UCB1CLK/UCA1STE X 1

P8.5/UCB1SIMO/UCB1SDA 5 P8.5 (I/O) I: 0; O: 1 0

UCB1SIMO/UCB1SDA X 1

P8.6/UCB1SOMI/UCB1SCL 6 P8.6 (I/O) I: 0; O: 1 0

UCB1SOMI/UCB1SCL X 1

P8.7 7 P8.7 (I/O) I: 0; O: 1 0

(1) X = Don't care

(1)

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P9.0 P9.1 P9.2 P9.3 P9.4 P9.5 P9.6 P9.7

Direction 0:Input 1:Output

P9DIR.x

P9IN.x

P9OUT.x

P9REN.x

PadLogic

P9DS.x 0:Lowdrive 1:Highdrive

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SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

6.13.12 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger

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Figure 6-13. Port P9 (P9.0 to P9.7) Schematic

Table 6-59. Port P9 (P9.0 to P9.7) Pin Functions

PIN NAME (P9.x) x FUNCTION

P9.0 0 P9.0 (I/O) I: 0; O: 1 0 P9.1 1 P9.1 (I/O) I: 0; O: 1 0 P9.2 2 P9.2 (I/O) I: 0; O: 1 0 P9.3 3 P9.3 (I/O) I: 0; O: 1 0 P9.4 4 P9.4 (I/O) I: 0; O: 1 0 P9.5 5 P9.5 (I/O) I: 0; O: 1 0 P9.6 6 P9.6 (I/O) I: 0; O: 1 0 P9.7 7 P9.7 (I/O) I: 0; O: 1 0

CONTROL BITS OR SIGNALS

P9DIR.x P9SEL.x

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PUOPE

PUOUT0

PadLogic

PU.0

LDOO VSSU

PU.1

PUOUT1

PUIN1

PUIN0

PUIPE

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6.13.13 Port PU.0, PU.1 Ports

MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333

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Figure 6-14. Port U (PU.0 and PU.1) Schematic

Table 6-60. Port PU.0, PU.1 Functions

PUIPE PUOPE PUOUT1 PUOUT0 PU.1 PU.0 PORT U FUNCTION

0 1 0 0 Output low Output low Outputs enabled 0 1 0 1 Output low Output high Outputs enabled 0 1 1 0 Output high Output low Outputs enabled 0 1 1 1 Output high Output high Outputs enabled 1 0 X X Input enabled Input enabled Inputs enabled 0 0 X X Hi-Z Hi-Z Outputs and inputs disabled

(1) PU.1 and PU.0 inputs and outputs are supplied from LDOO. LDOO can be generated by the device using the integrated 3.3-V LDO

when enabled. LDOO can also be supplied externally when the 3.3-V LDO is not being used and is disabled.

(1)

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PJ.1/TDI/TCLK PJ.2/TMS PJ.3/TCK

From JTAG

PJDIR.x

PJIN.x

From JTAG

PJOUT.x

PJREN.x

Pad Logic

PJDS.x 0: Low drive 1: High drive

DVSS

To JTAG

PJ.0/TDO

From JTAG

PJDIR.0

PJIN.0

From JTAG

PJOUT.0

PJREN.0

Pad Logic

PJDS.0 0: Low drive 1: High drive

DVCC

MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333

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6.13.14 Port J, J.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output

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Figure 6-15. Port J (PJ.0) Schematic

6.13.15 Port J, J.1 to J.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output

Figure 6-16. Port PJ (PJ.1 to PJ.3) Schematic

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Table 6-61. Port PJ (PJ.0 to PJ.3) Pin Functions

PIN NAME (PJ.x) x FUNCTION

PJ.0/TDO 0 PJ.0 (I/O)

TDO

PJ.1/TDI/TCLK 1 PJ.1 (I/O)

TDI/TCLK

PJ.2/TMS 2 PJ.2 (I/O)

TMS

PJ.3/TCK 3 PJ.3 (I/O)

TCK

(2)

(3)

(2) (3) (4) (2)

(3) (4)

(2)

(3) (4)

(1) X = Don't care (2) Default condition (3) The pin direction is controlled by the JTAG module. (4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.

CONTROL BITS OR

SIGNALS

(1)

PJDIR.x

I: 0; O: 1

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6.14 Device Descriptors

Table 6-62 list the complete contents of the device descriptor tag-length-value (TLV) structure for each

device type.

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DESCRIPTION ADDRESS

Info Block

Die Record

ADC12 Calibration

(1) NA = Not applicable

Table 6-62. MSP430F533x Device Descriptor Table

SIZE

(bytes)

Info length 01A00h 1 06h 06h 06h 06h

CRC length 01A01h 1 06h 06h 06h 06h

CRC value 01A02h 2 per unit per unit per unit per unit

Device ID 01A04h 2 812Ah 8128h 8127h 8125h

Hardware revision 01A06h 1 per unit per unit per unit per unit

Firmware revision 01A07h 1 per unit per unit per unit per unit

Die record tag 01A08h 1 08h 08h 08h 08h

Die record length 01A09h 1 0Ah 0Ah 0Ah 0Ah

Lot/wafer ID 01A0Ah 4 per unit per unit per unit per unit Die X position 01A0Eh 2 per unit per unit per unit per unit Die Y position 01A10h 2 per unit per unit per unit per unit

Test results 01A12h 2 per unit per unit per unit per unit

ADC12 calibration tag 01A14h 1 11h 11h 11h 11h

ADC12 calibration length 01A15h 1 10h 10h 10h 10h

ADC gain factor 01A16h 2 per unit per unit per unit per unit

ADC offset 01A18h 2 per unit per unit per unit per unit

ADC 1.5-V reference

temperature sensor 30°C

ADC 1.5-V reference

temperature sensor 85°C

ADC 2.0-V reference

temperature sensor 30°C

ADC 2.0-V reference

temperature sensor 85°C

ADC 2.5-V reference

temperature sensor 30°C

ADC 2.5-V reference

temperature sensor 85°C

01A1Ah 2 per unit per unit per unit per unit

01A1Ch 2 per unit per unit per unit per unit

01A1Eh 2 per unit per unit per unit per unit

01A20h 2 per unit per unit per unit per unit

01A22h 2 per unit per unit per unit per unit

01A24h 2 per unit per unit per unit per unit

F5338 F5336 F5335 F5333

(1)

VALUE

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Texas Instruments MSP430F533x, MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual