Texas Instruments MSP430F533x, MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333 User Manual

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MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333

SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

MSP430F533x Mixed-Signal Microcontrollers

1 Device Overview

1.1 Features

1

• Low Supply Voltage Range: 1.8 V to 3.6 V • Four 16-Bit Timers With 3, 5, or 7

• Ultra-Low Power Consumption
– Active Mode (AM):

All System Clocks Active:
270 µA/MHz at 8 MHz, 3.0 V, Flash Program – USCI_A0 and USCI_A1 Each Support:
Execution (Typical)

– Standby Mode (LPM3):

Watchdog With Crystal and Supply Supervisor
Operational, Full RAM Retention, Fast Wakeup:

1.8 µA at 2.2 V, 2.1 µA at 3.0 V (Typical)

– Shutdown Real-Time Clock (RTC) Mode

(LPM3.5):
Shutdown Mode, Active RTC With Crystal:

1.1 µA at 3.0 V (Typical)

– Shutdown Mode (LPM4.5):

0.3 µA at 3.0 V (Typical)

• Wake up From Standby Mode in 3 µs (Typical)

• 16-Bit RISC Architecture, Extended Memory, up to
20-MHz System Clock

• Flexible Power-Management System
– Fully Integrated LDO With Programmable

Regulated Core Supply Voltage

– Supply Voltage Supervision, Monitoring, and

Brownout

• Unified Clock System
– FLL Control Loop for Frequency Stabilization
– Low-Power Low-Frequency Internal Clock

Source (VLO)

– Low-Frequency Trimmed Internal Reference

Source (REFO)
– 32-kHz Crystals (XT1)
– High-Frequency Crystals up to 32 MHz (XT2)

Capture/Compare Registers

• Two Universal Serial Communication Interfaces
(USCIs)

• Enhanced UART Supports Automatic Baud­Rate Detection

• IrDA Encoder and Decoder

• Synchronous SPI

– USCI_B0 and USCI_B1 Each Support:

• I2C

• Synchronous SPI

• Integrated 3.3-V Power System

• 12-Bit Analog-to-Digital Converter (ADC) With
Internal Shared Reference, Sample-and-Hold, and
Autoscan Feature

• Dual 12-Bit Digital-to-Analog Converters (DACs)
With Synchronization

• Voltage Comparator

• Hardware Multiplier Supports 32-Bit Operations

• Serial Onboard Programming, No External
Programming Voltage Needed

• Six-Channel Internal DMA

• RTC Module With Supply Voltage Backup Switch

• Table 3-1 Summarizes the Available Family
Members

• For Complete Module Descriptions, See the

MSP430x5xx and MSP430x6xx Family User's
Guide (SLAU208)

1.2 Applications

• Analog and Digital Sensor Systems • Thermostats

• Digital Motor Control • Digital Timers

• Remote Controls • Hand-Held Meters

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333

SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

1.3 Description

The TI MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring different
sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device
features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to
maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from low­power modes to active mode in 3 µs (typical).

The MSP430F533x devices are microcontrollers with an integrated 3.3-V LDO, a high-performance 12-bit
ADC, a comparator, two USCIs, a hardware multiplier, DMA, four 16-bit timers, an RTC module with alarm
capabilities, and up to 74 I/O pins.

www.ti.com

Device Information

PART NUMBER PACKAGE BODY SIZE

MSP430F5338IPZ LQFP (100) 14 mm × 14 mm
MSP430F5338IZQW BGA (113) 7 mm × 7 mm

(1) For the most current device, package, and ordering information, see the Package Option Addendum in

Section 8, or see the TI website at www.ti.com.

(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the

Mechanical Data in Section 8.

(1)

(2)

2 Device Overview Copyright © 2010–2015, Texas Instruments Incorporated

Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333

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Unified

Clock

System

256KB
128KB

Flash

18KB/

10KB

RAM

+8B Backup

RAM

MCLK

ACLK

SMCLK

I/O Ports

P1/P2

2×8 I/Os

Interrupt

Capability

PA

1×16 I/Os

CPUXV2

and

Working

Registers

EEM

(L: 8+2)

XIN

XOUT

JTAG/

SBW

Interface/

Port PJ

PA PB PC PD

DMA

6 Channel

XT2IN

XT2OUT

Power

Management

LDO
SVM/SVS
Brownout

SYS

Watchdog

P2 Port

Mapping

Controller

I/O Ports

P3/P4

2×8 I/Os

Interrupt

Capability

PB

1×16 I/Os

I/O Ports

P5/P6

2×8 I/Os

PC

1×16 I/Os

I/O Ports

P7/P8

1×6 I/Os

PD

1×14 I/Os

1×8 I/Os

I/O Ports

P9

1×8 I/Os

PE

1×8 I/Os

MPY32

TA0

Timer_A

5 CC

Registers

TA1 and

TA2

2 Timer_A

each with

3 CC

Registers

TB0

Timer_B

7 CC

Registers

CRC16

USCI0,1

Ax: UART,

IrDA, SPI

Bx: SPI, I2C

ADC12_A

200 KSPS

16 Channels
(12 ext/4 int)

Autoscan

12 Bit

DVCCDVSSAVCCAV

SS

P1.x P2.x

P3.x

P4.x

P5.x P6.x

P7.x

P8.x P9.x

RST/NMI

REF

Reference

1.5V, 2.0V,

2.5V

Comp_B

PJ.x

RTC_B

Battery
Backup
System

PU Port

LDO

PU.0
PU.1

LDOO

LDOI

Unified

Clock

System

256KB
128KB

Flash

MCLK

ACLK

SMCLK

I/O Ports

P1/P2

2×8 I/Os

Interrupt

Capability

PA

1×16 I/Os

CPUXV2

and

Working

Registers

EEM

(L: 8+2)

XIN

XOUT

JTAG/

SBW

Interface/

Port PJ

PA PB PC PD

DMA

6 Channel

XT2IN

XT2OUT

Power

Management

LDO
SVM/SVS
Brownout

SYS

Watchdog

P2 Port

Mapping

Controller

I/O Ports

P3/P4

2×8 I/Os

Interrupt

Capability

PB

1×16 I/Os

I/O Ports

P5/P6

2×8 I/Os

PC

1×16 I/Os

I/O Ports

P7/P8

1×6 I/Os

PD

1×14 I/Os

1×8 I/Os

I/O Ports

P9

1×8 I/Os

PE

1×8 I/Os

MPY32

TA0

Timer_A

5 CC

Registers

TA1 and

TA2

2 Timer_A

each with

3 CC

Registers

TB0

Timer_B

7 CC

Registers

RTC_B

Battery
Backup
System

CRC16

USCI0,1

Ax: UART,

IrDA, SPI

Bx: SPI, I2C

ADC12_A

200 KSPS

16 Channels
(12 ext/4 int)

Autoscan

12 Bit

DVCCDVSSAVCCAV

SS

P1.x P2.x

P3.x

P4.x

P5.x P6.x

P7.x

P8.x P9.x

RST/NMI

REF

Reference

1.5V, 2.0V,

2.5V

DAC12_A

12 bit
2 channels
voltage out

Comp_B

PJ.x

18KB

RAM

+8B Backup

RAM

PU Port

LDO

PU.0
PU.1

LDOO

LDOI

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1.4 Functional Block Diagrams

Figure 1-1 shows the functional block diagram for the MSP430F5338 and MSP430F5336 devices.

MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333

SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

Figure 1-1. Functional Block Diagram – MSP430F5338, MSP430F5336

Figure 1-2 shows the functional block diagram for the MSP430F5335 and MSP430F5333 devices.

Figure 1-2. Functional Block Diagram – MSP430F5335, MSP430F5333

Copyright © 2010–2015, Texas Instruments Incorporated Device Overview 3

Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333

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MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333

SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

www.ti.com

Table of Contents

1 Device Overview ......................................... 1 5.30 USCI (UART Mode) ................................. 31

1.1 Features .............................................. 1 5.31 USCI (SPI Master Mode)............................ 31

1.2 Applications........................................... 1 5.32 USCI (SPI Slave Mode)............................. 33

1.3 Description............................................ 2 5.33 USCI (I2C Mode) .................................... 35

1.4 Functional Block Diagrams........................... 3

2 Revision History ......................................... 5

3 Device Comparison ..................................... 6

4 Terminal Configuration and Functions.............. 7

4.1 Pin Designation – MSP430F5338IPZ,

MSP430F5336IPZ.................................... 7

4.2 Pin Designation – MSP430F5335IPZ,

MSP430F5333IPZ.................................... 8

4.3 Pin Designation – MSP430F5338IZQW,
MSP430F5336IZQW, MSP430F5335IZQW,

MSP430F5333IZQW ................................. 9 5.40 REF, External Reference ........................... 39

4.4 Signal Descriptions.................................. 10 5.41 REF, Built-In Reference............................. 40

5 Specifications........................................... 15 5.42 12-Bit DAC, Supply Specifications.................. 41

5.1 Absolute Maximum Ratings......................... 15 5.43 12-Bit DAC, Linearity Specifications ................ 41

5.2 ESD Ratings ........................................ 15 5.44 12-Bit DAC, Output Specifications .................. 43

5.3 Recommended Operating Conditions............... 15 5.45 12-Bit DAC, Reference Input Specifications ........ 44

5.4 Active Mode Supply Current Into VCCExcluding

External Current..................................... 17

5.5 Low-Power Mode Supply Currents (Into VCC)

Excluding External Current.......................... 17

5.6 Thermal Resistance Characteristics ................ 18

5.7 Schmitt-Trigger Inputs – General-Purpose I/O...... 19

5.8 Inputs – Ports P1, P2, P3, and P4.................. 19

5.9 Leakage Current – General-Purpose I/O ........... 19

5.10 Outputs – General-Purpose I/O (Full Drive

Strength) ............................................ 19

5.11 Outputs – General-Purpose I/O (Reduced Drive

Strength) ............................................ 20

5.12 Output Frequency – Ports P1, P2, and P3.......... 20

5.13 Typical Characteristics – Outputs, Reduced Drive

Strength (PxDS.y = 0)............................... 21

5.14 Typical Characteristics – Outputs, Full Drive

Strength (PxDS.y = 1)............................... 22

5.15 Crystal Oscillator, XT1, Low-Frequency Mode ..... 23

5.16 Crystal Oscillator, XT2 .............................. 24

5.17 Internal Very-Low-Power Low-Frequency Oscillator

(VLO)................................................ 25

5.18 Internal Reference, Low-Frequency Oscillator 6.12 Peripherals .......................................... 57

(REFO) .............................................. 25

5.19 DCO Frequency..................................... 26

5.20 PMM, Brownout Reset (BOR)....................... 27

5.21 PMM, Core Voltage ................................. 27

5.22 PMM, SVS High Side ............................... 28

5.23 PMM, SVM High Side............................... 28

5.24 PMM, SVS Low Side................................ 29

5.25 PMM, SVM Low Side ............................... 29

5.26 Wake-up Times From Low-Power Modes and

Reset ................................................ 29

5.27 Timer_A, Timers TA0, TA1, and TA2............... 30

5.28 Timer_B, Timer TB0 ................................ 30

5.29 Battery Backup ...................................... 30

5.34 12-Bit ADC, Power Supply and Input Range

Conditions ........................................... 36

5.35 12-Bit ADC, Timing Parameters .................... 36

5.36 12-Bit ADC, Linearity Parameters Using an External

Reference Voltage .................................. 37

5.37 12-Bit ADC, Linearity Parameters Using AVCC as

Reference Voltage .................................. 37

5.38 12-Bit ADC, Linearity Parameters Using the Internal

Reference Voltage .................................. 37

5.39 12-Bit ADC, Temperature Sensor and Built-In V

5.46 12-Bit DAC, Dynamic Specifications................ 44

5.47 12-Bit DAC, Dynamic Specifications (Continued)... 45

5.48 Comparator_B....................................... 46

5.49 Ports PU.0 and PU.1................................ 47

5.50 LDO-PWR (LDO Power System) ................... 48

5.51 Flash Memory ....................................... 49

5.52 JTAG and Spy-Bi-Wire Interface.................... 49

MID

38

6 Detailed Description ................................... 50

6.1 Overview ............................................ 50

6.2 CPU ................................................. 50

6.3 Instruction Set....................................... 51

6.4 Operating Modes.................................... 52

6.5 Interrupt Vector Addresses.......................... 53

6.6 Memory.............................................. 54

6.7 Bootloader (BSL).................................... 55

6.8 JTAG Operation ..................................... 55

6.9 Flash Memory (Link to User's Guide)............... 56

6.10 RAM (Link to User's Guide)......................... 57

6.11 Backup RAM ........................................ 57

6.13 Input/Output Schematics ............................ 79

6.14 Device Descriptors................................. 100

7 Device and Documentation Support.............. 101

7.1 Device Support..................................... 101

7.2 Documentation Support............................ 104

7.3 Related Links ...................................... 104

7.4 Community Resources............................. 105

7.5 Trademarks ........................................ 105

7.6 Electrostatic Discharge Caution ................... 105

7.7 Export Control Notice .............................. 105

7.8 Glossary............................................ 105

8 Mechanical, Packaging, and Orderable

4 Table of Contents Copyright © 2010–2015, Texas Instruments Incorporated

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www.ti.com

Information............................................. 105

SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from August 5, 2013 to December 8, 2015 Page

• Document format and organization changes throughout, including addition of section numbering........................ 1

• Moved all functional block diagrams to Section 1.4, Functional Block Diagrams ............................................ 3

• Added USB column to Table 3-1, Family Members ............................................................................. 6

• Added Section 3, Device Comparison, and moved Table 3-1, Family Members to it ....................................... 6

• Added "Port U is supplied by the LDOO rail" to the PU.0 and PU.1 descriptions in Table 4-1, Signal Descriptions .. 13

• Moved all electrical specifications to Section 5 ................................................................................. 15

• Added Section 5.2, ESD Ratings.................................................................................................. 15

• Added note to C

• Added Section 5.6, Thermal Characteristics .................................................................................... 18

• Added note to R

• Changed TYP value of C

• In V

parameter description, changed from "V

BAT3

• Changed from f

crosstalk" parameter ................................................................................................................ 45

• Changed the value of DAC12_xDAT from 7F7h to F7Fh and changed the x-axis label from f

Figure 5-22, Crosstalk Test Conditions .......................................................................................... 45

• Corrected the spelling of the MRG bits in the f

• Removed RTC_B from LPM4.5 wake-up options............................................................................... 52

• Throughout document, changed all instances of "bootstrap loader" to "bootloader"....................................... 55

• Added the paragraph that starts "The application report Using the MSP430 RTC_B..." .................................. 59

• Corrected names of interrupt events PMMSWBOR (BOR) and PMMSWPOR (POR) in Table 6-10, System

Module Interrupt Vector Registers ................................................................................................ 60

• Corrected spelling of NMIIFG (added missing "I") in Table 6-10, System Module Interrupt Vector Registers.......... 60

• Added P7SEL.2 and XT2BYPASS inputs with AND and OR gates in Figure 6-10, Port P7 (P7.3) Schematic ........ 92

• Changed P7SEL.3 column from X to 0 for "P7.3 (I/O)" rows.................................................................. 92

• Changed Table 6-60, Port PU.0, PU.1 Functions............................................................................... 97

• Added Section 7 and moved Development Tools Support, Device and Development Tool Nomenclature,

Trademarks, and Electrostatic Discharge Caution sections to it ............................................................ 101

• Added Section 8, Mechanical, Packaging, and Orderable Information..................................................... 105

............................................................................................................... 15

VCORE

.................................................................................................................. 19

Pull

DAC12_0OUT

with Test Conditions of "XTS = 0, XCAPx = 0" from 2 pF to 1 pF ......................... 23

L,eff

to f

DAC12_1OUT

in the first row of the Test Conditions for the "Channel-to-channel

BAT3

MCLK,MRG

≠ V

/3" to "V

BAT

BAT3

= V

/3" ........................................ 30

BAT

to 1/f

Toggle

Toggle

in

parameter........................................................... 49

Copyright © 2010–2015, Texas Instruments Incorporated Revision History 5

Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333

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MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333

SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

3 Device Comparison

Table 3-1 summarizes the available family members.

www.ti.com

Table 3-1. Family Members

USCI

DEVICE Timer_A

MSP430F5338 256 18 5, 3, 3 7 2 2 2 12 No 74

MSP430F5336 128 18 5, 3, 3 7 2 2 2 12 No 74

MSP430F5335 256 18 5, 3, 3 7 2 2 - 12 No 74

MSP430F5333 128 10 5, 3, 3 7 2 2 - 12 No 74

FLASH SRAM ADC12_A DAC12_A Comp_B

(KB) (KB) (Ch) (Ch) (Ch)

(3)

Timer_B

CHANNEL CHANNEL

(4)

A: B:

UART,

IrDA, SPI

SPI, I2C

(1)(2)

USB I/O PACKAGE

12 ext, 100 PZ,

4 int 113 ZQW

12 ext, 100 PZ,

4 int 113 ZQW

12 ext, 100 PZ,

4 int 113 ZQW

12 ext, 100 PZ,

4 int 113 ZQW

(1) For the most current package and ordering information, see the Package Option Addendum in Section 8, or see the TI website at

www.ti.com.

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/packaging.

(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM

output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.

(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM

output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.

6 Device Comparison Copyright © 2010–2015, Texas Instruments Incorporated

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P6.4/CB4/A4

P6.5/CB5/A5
P6.6/CB6/A6/DAC0
P6.7/CB7/A7/DAC1

P7.4/CB8/A12
P7.5/CB9/A13

P7.6/CB10/A14/DAC0

P7.7/CB11/A15/DAC1

P5.0/VREF+/VeREF+
P5.1/VREF−/VeREF−

AVCC1
AVSS1

XIN

XOUT

DVCC1

DVSS1

VCORE

P5.2

DVSS

DNC

P5.3

P9.7

P9.6
P9.5
P9.4
P9.3
P9.2
P9.1
P9.0
P8.7
P8.6/UCB1SOMI/UCB1SCL
P8.5/UCB1SIMO/UCB1SDA
DVCC2
DVSS2

P2.0/P2MAP0

MSP430F5338
MSP430F5336

PZ PACKAGE

(TOP VIEW)

P6.3/CB3/A3

P6.2/CB2/A2

P6.1/CB1/A1

P6.0/CB0/A0

RST/NMI/SBWTDIO

PJ.3/TCK

PJ.2/TMS

PJ.1/TDI/TCLK

PJ.0/TDO

TEST/SBWTCK

P7.3/XT2OUT

P7.2/XT2IN

LDOI

LDOO

PU.1

NC

PU.0

VSSU

NC

AVSS3

P1.3/TA0.2

P1.4/TA0.3

AVSS2

P5.6/ADC12CLK/DMAE0

P5.4

P5.5

P1.0/TA0CLK/ACLK

P3.0/TA1CLK/CBOUT

P3.1/TA1.0

P3.2/TA1.1

P1.6/TA0.1

P1.7/TA0.2

P1.1/TA0.0

P1.2/TA0.1

P1.5/TA0.4

P3.3/TA1.2

P3.4/TA2CLK/SMCLK

P3.5/TA2.0

P3.6/TA2.1

P3.7/TA2.2

P4.0/TB0.0

P4.2/TB0.2
P4.1/TB0.1

P4.4/TB0.4
P4.3/TB0.3

P4.6/TB0.6
P4.5/TB0.5

P8.0/TB0CLK
P4.7/TB0OUTH/SVMOUT

P8.4/UCB1CLK/UCA1STE

VBAK

P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
P2.6/P2MAP6
P2.7/P2MAP7

DVCC3

DVSS3

VBAT

P5.7/RTCCLK

P8.1/UCB1STE/UCA1CLK

P8.2/UCA1TXD/UCA1SIMO

P8.3/UCA1RXD/UCA1SOMI

MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333

www.ti.com

4 Terminal Configuration and Functions

4.1 Pin Designation – MSP430F5338IPZ, MSP430F5336IPZ

Figure 4-1 shows the pinout for the MSP430F5338 and MSP430F5336 devices in the PZ package.

SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

NOTE: DNC = Do not connect

Figure 4-1. 100-Pin PZ Package (Top View) – MSP430F5338, MSP430F5336

Copyright © 2010–2015, Texas Instruments Incorporated Terminal Configuration and Functions 7

Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333

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P6.4/CB4/A4

P6.5/CB5/A5

P6.6/CB6/A6

P6.7/CB7/A7

P7.4/CB8/A12
P7.5/CB9/A13

P7.6/CB10/A14

P7.7/CB11/A15
P5.0/VREF+/VeREF+
P5.1/VREF−/VeREF−

AVCC1
AVSS1

XIN

XOUT

DVCC1

DVSS1

VCORE

P5.2

DVSS

DNC

P5.3

P9.7

P9.6
P9.5
P9.4
P9.3
P9.2
P9.1
P9.0
P8.7
P8.6/UCB1SOMI/UCB1SCL
P8.5/UCB1SIMO/UCB1SDA
DVCC2
DVSS2

P2.0/P2MAP0

MSP430F5335
MSP430F5333

PZ PACKAGE

(TOP VIEW)

P6.3/CB3/A3

P6.2/CB2/A2

P6.1/CB1/A1

P6.0/CB0/A0

RST/NMI/SBWTDIO

PJ.3/TCK

PJ.2/TMS

PJ.1/TDI/TCLK

PJ.0/TDO

TEST/SBWTCK

P7.3/XT2OUT

P7.2/XT2IN

LDOI

LDOO

PU.1

NC

PU.0

VSSU

NC

AVSS3

P1.3/TA0.2

P1.4/TA0.3

AVSS2

P5.6/ADC12CLK/DMAE0

P5.4

P5.5

P1.0/TA0CLK/ACLK

P3.0/TA1CLK/CBOUT

P3.1/TA1.0

P3.2/TA1.1

P1.6/TA0.1

P1.7/TA0.2

P1.1/TA0.0

P1.2/TA0.1

P1.5/TA0.4

P3.3/TA1.2

P3.4/TA2CLK/SMCLK

P3.5/TA2.0

P3.6/TA2.1

P3.7/TA2.2

P4.0/TB0.0

P4.2/TB0.2
P4.1/TB0.1

P4.4/TB0.4
P4.3/TB0.3

P4.6/TB0.6
P4.5/TB0.5

P8.0/TB0CLK
P4.7/TB0OUTH/SVMOUT

P8.4/UCB1CLK/UCA1STE

VBAK

P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
P2.6/P2MAP6
P2.7/P2MAP7

DVCC3

DVSS3

VBAT

P5.7/RTCCLK

P8.1/UCB1STE/UCA1CLK

P8.2/UCA1TXD/UCA1SIMO

P8.3/UCA1RXD/UCA1SOMI

MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333

SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

4.2 Pin Designation – MSP430F5335IPZ, MSP430F5333IPZ

Figure 4-2 shows the pinout for the MSP430F5335 and MSP430F5333 devices in the PZ package.

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NOTE: DNC = Do not connect

Figure 4-2. 100-Pin PZ Package (Top View) – MSP430F5335, MSP430F5333

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A1 A2

A3

A4

A5 A6

A7

A8 A9 A10

A11 A12

B1 B2

B3

B4

B5 B6

B7

B8 B9 B10

B11 B12

C1 C2 C3 C11 C12

D1 D2 D4

D5 D6

D7

D8 D9

D11 D12

E1 E2 E4

E5 E6

E7

E8 E9

E11 E12

F1 F2 F4

F5 F8 F9

F11 F12

G1 G2 G4

G5 G8 G9

G11 G12

J1 J2 J4

J5 J6

J7

J8 J9

J11 J12

H1 H2 H4

H5 H6

H7

H8 H9

H11 H12

K1 K2 K11 K12

L1 L2

L3

L4

L5 L6

L7

L8 L9 L10

L11 L12

M1 M2

M3 M5 M6

M7

M8 M9 M10

M11 M12

M4

ZQW PACKAGE

(TOP VIEW)

MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333

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SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

4.3 Pin Designation – MSP430F5338IZQW, MSP430F5336IZQW, MSP430F5335IZQW,
MSP430F5333IZQW

Figure 4-3 shows the pin diagram for all devices in the ZQW package. See Section 4.4 for pin

assignments and descriptions.

NOTE: For terminal assignments, see Table 4-1

Figure 4-3. 113-Pin ZQW Package (Top View) – MSP430F5338, MSP430F5336, MSP430F5335,

MSP430F5333

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4.4 Signal Descriptions

Table 4-1 describes the signals for all device variants and packages.

Table 4-1. Signal Descriptions

TERMINAL

NAME

P6.4/CB4/A4 1 A1 I/O Comparator_B input CB4

P6.5/CB5/A5 2 B2 I/O Comparator_B input CB5

P6.6/CB6/A6/DAC0 3 B1 I/O

P6.7/CB7/A7/DAC1 4 C2 I/O

P7.4/CB8/A12 5 C1 I/O Comparator_B input CB8

P7.5/CB9/A13 6 C3 I/O Comparator_B input CB9

P7.6/CB10/A14/DAC0 7 D2 I/O

P7.7/CB11/A15/DAC1 8 D1 I/O

P5.0/VREF+/VeREF+ 9 D4 I/O Output of reference voltage to the ADC

P5.1/VREF-/VeREF- 10 E4 I/O

AVCC1 11 Analog power supply
AVSS1 12 F2 Analog ground supply

XIN 13 F1 I Input terminal for crystal oscillator XT1
XOUT 14 G1 O Output terminal of crystal oscillator XT1

NO. I/O

PZ ZQW

E1,

E2

(1)

General-purpose digital I/O

Analog input A4 – ADC
General-purpose digital I/O

Analog input A5 – ADC
General-purpose digital I/O

Comparator_B input CB6
Analog input A6 – ADC
DAC12.0 output (not available on F5335 and F5333 devices)

General-purpose digital I/O
Comparator_B input CB7
Analog input A7 – ADC
DAC12.1 output (not available on F5335 and F5333 devices)

General-purpose digital I/O

Analog input A12 –ADC
General-purpose digital I/O

Analog input A13 – ADC
General-purpose digital I/O

Comparator_B input CB10
Analog input A14 – ADC
DAC12.0 output (not available on F5335 and F5333 devices)

General-purpose digital I/O
Comparator_B input CB11
Analog input A15 – ADC
DAC12.1 output (not available on F5335 and F5333 devices)

General-purpose digital I/O

Input for an external reference voltage to the ADC
General-purpose digital I/O

Negative terminal for the reference voltage of the ADC for both sources, the
internal reference voltage, or an external applied reference voltage

DESCRIPTION

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(1) I = input, O = output, N/A = not available on this package offering
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Table 4-1. Signal Descriptions (continued)

TERMINAL

NAME

NO. I/O

PZ ZQW

AVSS2 15 G2 Analog ground supply

P5.6/ADC12CLK/DMAE0 16 H1 I/O Conversion clock output ADC

P2.0/P2MAP0 17 G4 I/O

P2.1/P2MAP1 18 H2 I/O

P2.2/P2MAP2 19 J1 I/O

P2.3/P2MAP3 20 H4 I/O

P2.4/P2MAP4 21 J2 I/O

P2.5/P2MAP5 22 K1 I/O

P2.6/P2MAP6 23 K2 I/O

P2.7/P2MAP7 24 L2 I/O

DVCC1 25 L1 Digital power supply
DVSS1 26 M1 Digital ground supply

(2)

VCORE

27 M2 Regulated core power supply (internal use only, no external current loading)
P5.2 28 L3 I/O General-purpose digital I/O
DVSS 29 M3 Digital ground supply
DNC 30 J4 Do not connect. It is strongly recommended to leave this terminal open.
P5.3 31 L4 I/O General-purpose digital I/O
P5.4 32 M4 I/O General-purpose digital I/O
P5.5 33 J5 I/O General-purpose digital I/O

P1.0/TA0CLK/ACLK 34 L5 I/O Timer TA0 clock signal TACLK input

P1.1/TA0.0 35 M5 I/O Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output

P1.2/TA0.1 36 J6 I/O Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output

P1.3/TA0.2 37 H6 I/O

(1)

DESCRIPTION

General-purpose digital I/O

DMA external trigger input
General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_B0 SPI slave transmit enable; USCI_A0 clock input/output
General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_B0 SPI slave in/master out; USCI_B0 I2C data
General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_B0 SPI slave out/master in; USCI_B0 I2C clock
General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable
General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in/master out
General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: USCI_A0 UART receive data; USCI_A0 slave out/master in
General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: no secondary function
General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: no secondary function

General-purpose digital I/O with port interrupt

ACLK output (divided by 1, 2, 4, 8, 16, or 32)
General-purpose digital I/O with port interrupt

BSL transmit output
General-purpose digital I/O with port interrupt

BSL receive input
General-purpose digital I/O with port interrupt

Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output

(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended

capacitor value, C

Copyright © 2010–2015, Texas Instruments Incorporated Terminal Configuration and Functions 11

VCORE

.

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Table 4-1. Signal Descriptions (continued)

TERMINAL

NAME

P1.4/TA0.3 38 M6 I/O

P1.5/TA0.4 39 L6 I/O

P1.6/TA0.1 40 J7 I/O

P1.7/TA0.2 41 M7 I/O

P3.0/TA1CLK/CBOUT 42 L7 I/O Timer TA1 clock input

P3.1/TA1.0 43 H7 I/O

P3.2/TA1.1 44 M8 I/O

P3.3/TA1.2 45 L8 I/O

P3.4/TA2CLK/SMCLK 46 J8 I/O Timer TA2 clock input

P3.5/TA2.0 47 M9 I/O

P3.6/TA2.1 48 L9 I/O

P3.7/TA2.2 49 M10 I/O

P4.0/TB0.0 50 J9 I/O

P4.1/TB0.1 51 M11 I/O

P4.2/TB0.2 52 L10 I/O

P4.3/TB0.3 53 M12 I/O

P4.4/TB0.4 54 L12 I/O

P4.5/TB0.5 55 L11 I/O

P4.6/TB0.6 56 K11 I/O

NO. I/O

PZ ZQW

(1)

General-purpose digital I/O with port interrupt
Timer TA0 CCR3 capture: CCI3A input compare: Out3 output

General-purpose digital I/O with port interrupt
Timer TA0 CCR4 capture: CCI4A input, compare: Out4 output

General-purpose digital I/O with port interrupt
Timer TA0 CCR1 capture: CCI1B input, compare: Out1 output

General-purpose digital I/O with port interrupt
Timer TA0 CCR2 capture: CCI2B input, compare: Out2 output

General-purpose digital I/O with port interrupt

Comparator_B output
General-purpose digital I/O with port interrupt

Timer TA1 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
General-purpose digital I/O with port interrupt

Timer TA1 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
General-purpose digital I/O with port interrupt

Timer TA1 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
General-purpose digital I/O with port interrupt

SMCLK output
General-purpose digital I/O with port interrupt

Timer TA2 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
General-purpose digital I/O with port interrupt

Timer TA2 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
General-purpose digital I/O with port interrupt

Timer TA2 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
General-purpose digital I/O with port interrupt

Timer TB0 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
General-purpose digital I/O with port interrupt

Timer TB0 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
General-purpose digital I/O with port interrupt

Timer TB0 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
General-purpose digital I/O with port interrupt

Timer TB0 capture CCR3: CCI3A/CCI3B input, compare: Out3 output
General-purpose digital I/O with port interrupt

Timer TB0 capture CCR4: CCI4A/CCI4B input, compare: Out4 output
General-purpose digital I/O with port interrupt

Timer TB0 capture CCR5: CCI5A/CCI5B input, compare: Out5 output
General-purpose digital I/O with port interrupt

Timer TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output

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DESCRIPTION

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Table 4-1. Signal Descriptions (continued)

TERMINAL

NAME

NO. I/O

PZ ZQW

P4.7/TB0OUTH/SVMOUT 57 K12 I/O Timer TB0: Switch all PWM outputs high impedance

P8.0/TB0CLK 58 J11 I/O

P8.1/UCB1STE/UCA1CLK 59 J12 I/O

P8.2/UCA1TXD/UCA1SIMO 60 H11 I/O

(1)

DESCRIPTION

General-purpose digital I/O with port interrupt

SVM output
General-purpose digital I/O

Timer TB0 clock input
General-purpose digital I/O

USCI_B1 SPI slave transmit enable; USCI_A1 clock input/output
General-purpose digital I/O

USCI_A1 UART transmit data; USCI_A1 SPI slave in/master out

P8.3/UCA1RXD/UCA1SOMI 61 H12 I/O

General-purpose digital I/O
USCI_A1 UART receive data; USCI_A1 SPI slave out/master in

P8.4/UCB1CLK/UCA1STE 62 G11 I/O

General-purpose digital I/O

USCI_B1 clock input/output; USCI_A1 SPI slave transmit enable
DVSS2 63 G12 Digital ground supply
DVCC2 64 F12 Digital power supply

P8.5/UCB1SIMO/UCB1SDA 65 F11 I/O

P8.6/UCB1SOMI/UCB1SCL 66 G9 I/O

General-purpose digital I/O

USCI_B1 SPI slave in/master out; USCI_B1 I2C data

General-purpose digital I/O

USCI_B1 SPI slave out/master in; USCI_B1 I2C clock
P8.7 67 E12 I/O General-purpose digital I/O
P9.0 68 E11 I/O General-purpose digital I/O
P9.1 69 F9 I/O General-purpose digital I/O
P9.2 70 D12 I/O General-purpose digital I/O

P9.3 71 D11 I/O

General-purpose digital I/O
P9.4 72 E9 I/O General-purpose digital I/O
P9.5 73 C12 I/O General-purpose digital I/O
P9.6 74 C11 I/O General-purpose digital I/O
P9.7 75 D9 I/O General-purpose digital I/O

VSSU 76 PU ground supply

PU.0 77 A12 I/O

B11,

B12

General-purpose digital I/O, controlled by PU control register. Port U is supplied by

the LDOO rail.
NC 78 B10 No connect

PU.1 79 A11 I/O

General-purpose digital I/O, controlled by PU control register. Port U is supplied by

the LDOO rail.
LDOI 80 A10 LDO input
LDOO 81 A9 LDO output
NC 82 B9 No connect
AVSS3 83 A8 Analog ground supply

P7.2/XT2IN 84 B8 I/O

P7.3/XT2OUT 85 B7 I/O

General-purpose digital I/O

Input terminal for crystal oscillator XT2

General-purpose digital I/O

Output terminal of crystal oscillator XT2

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Table 4-1. Signal Descriptions (continued)

TERMINAL

NAME

NO. I/O

PZ ZQW

VBAK 86 A7

VBAT 87 D8

P5.7/RTCCLK 88 D7 I/O

DVCC3 89 A6 Digital power supply
DVSS3 90 A5 Digital ground supply

TEST/SBWTCK 91 B6 I

PJ.0/TDO 92 B5 I/O

PJ.1/TDI/TCLK 93 A4 I/O

PJ.2/TMS 94 E7 I/O

PJ.3/TCK 95 D6 I/O

RST/NMI/SBWTDIO 96 A3 I/O Nonmaskable interrupt input

P6.0/CB0/A0 97 B4 I/O Comparator_B input CB0

P6.1/CB1/A1 98 B3 I/O Comparator_B input CB1

P6.2/CB2/A2 99 A2 I/O Comparator_B input CB2

P6.3/CB3/A3 100 D5 I/O Comparator_B input CB3

E5,
E6,
E8,
F4,
F5,

Reserved N/A F8, Reserved. TI recommends connecting to ground (DVSS, AVSS).

G5,
G8,
H5,
H8,

H9

(3) When this pin is configured as reset, the internal pullup resistor is enabled by default.

(1)

DESCRIPTION

Capacitor for backup subsystem. Do not load this pin externally. For capacitor

values, see C

in Recommended Operating Conditions.

BAK

Backup or secondary supply voltage. If backup voltage is not supplied, connect to

DVCC externally.

General-purpose digital I/O

RTCCLK output

Test mode pin; selects digital I/O on JTAG pins

Spy-Bi-Wire input clock

General-purpose digital I/O

Test data output port

General-purpose digital I/O

Test data input or test clock input

General-purpose digital I/O

Test mode select

General-purpose digital I/O

Test clock

Reset input (active low)

(3)

Spy-Bi-Wire data input/output

General-purpose digital I/O

Analog input A0 – ADC

General-purpose digital I/O

Analog input A1 – ADC

General-purpose digital I/O

Analog input A2 – ADC

General-purpose digital I/O

Analog input A3 – ADC

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5 Specifications

MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333

SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

5.1 Absolute Maximum Ratings

(1)

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

Voltage applied at VCCto V

SS

Voltage applied to any pin (excluding VCORE, VBUS, V18)

(2)

–0.3 4.1 V

–0.3 VCC+ 0.3 V
Diode current at any device pin ±2 mA
Maximum junction temperature, T
Storage temperature, T

(3)

stg

J

–55 150 °C

95 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

5.2 ESD Ratings

VALUE UNIT

V

Electrostatic discharge V

(ESD)

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
Charged-device model (CDM), per JEDEC specification JESD22-C101

(1)

(2)

±1000

±250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as

±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V

may actually have higher performance.

5.3 Recommended Operating Conditions

MIN NOM MAX UNIT

PMMCOREVx = 0 1.8 3.6

V

CC

V

SS

V

BAT,RTC

V

BAT,MEM

T

A

T

J

C

BAK

C

VCORE

C

DVCC

C

VCORE

Supply voltage during program execution and flash
programming (AVCC1 = DVCC1 = DVCC2 = DVCC3 = V
DVCC= VCC)

(1)(2)

Supply voltage (AVSS1 = AVSS2 = AVSS3 = DVSS1 =
DVSS2 = DVSS3 = VSS)

Backup-supply voltage with RTC operational V

Backup-supply voltage with backup memory retained TA= –40°C to +85°C 1.20 3.6 V
Operating free-air temperature I version –40 85 °C
Operating junction temperature I version –40 85 °C
Capacitance at pin VBAK 1 4.7 10 nF
Capacitor at VCORE

/

Capacitor ratio of DVCC to VCORE 10

(3)

PMMCOREVx = 0, 1 2.0 3.6
PMMCOREVx = 0, 1, 2 2.2 3.6
PMMCOREVx = 0, 1, 2, 3 2.4 3.6

0 V

TA= 0°C to 85°C 1.55 3.6
TA= –40°C to +85°C 1.70 3.6

470 nF

(1) TI recommends powering AVCCand DVCCfrom the same source. A maximum difference of 0.3 V between AVCCand DVCCcan be

tolerated during power up and operation.
(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the threshold parameters in Section 5.22

for the exact values and further details.
(3) A capacitor tolerance of ±20% or better is required.

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2.01.8

8

0

12

20

25

SystemFrequency-MHz

SupplyVoltage-V

ThenumberswithinthefieldsdenotethesupportedPMMCOREVxsettings.

2.2 2.4 3.6

0,1,2,30,1,20,10

1,2,3

1,2

1

2,3

3

2

16

MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333

SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

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Recommended Operating Conditions (continued)

MIN NOM MAX UNIT

PMMCOREVx = 0,

1.8 V ≤ VCC≤ 3.6 V 0 8.0
(default condition)

f

SYSTEM

(4) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the

specified maximum frequency.
(5) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.

Processor frequency (maximum MCLK frequency)
(see Figure 5-1)

(4)(5)

PMMCOREVx = 1,
2 V ≤ VCC≤ 3.6 V

PMMCOREVx = 2,

2.2 V ≤ VCC≤ 3.6 V
PMMCOREVx = 3,

2.4 V ≤ VCC≤ 3.6 V

0 12.0

0 16.0

0 20.0

MHz

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Figure 5-1. Frequency vs Supply Voltage

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5.4 Active Mode Supply Current Into VCCExcluding External Current

over recommended operating free-air temperature (unless otherwise noted)

PARAMETER V

I

AM, Flash

I

AM, RAM

(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load

capacitance are chosen to closely match the required 12.5 pF.
(3) Characterized with program executing typical data processing. LDO disabled (LDOEN = 0).

f

ACLK

XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.

EXECUTION

MEMORY

= 32786 Hz, f

PMMCOREVx 1 MHz 8 MHz 12 MHz 20 MHz UNIT

CC

TYP MAX TYP MAX TYP MAX TYP MAX

0 0.32 0.36 2.1 2.4

Flash 3 V mA

1 0.36 2.4 3.6 4.0
2 0.37 2.5 3.8
3 0.39 2.7 4.0 6.6
0 0.18 0.21 1.0 1.2

RAM 3 V mA

1 0.20 1.2 1.7 1.9
2 0.22 1.3 2.0
3 0.23 1.4 2.1 3.6

= f

DCO

MCLK

= f

at specified frequency.

SMCLK

(1)(2)(3)

FREQUENCY (f

DCO

= f

MCLK

= f

SMCLK

)

5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

–40°C 25°C 60°C 85°C

TYP MAX TYP MAX TYP MAX TYP MAX

I

LPM0,1MHz

I

LPM2

I

LPM3,XT1LF

PARAMETER V

2.2 V 0 71 75 87 81 85 99

Low-power mode 0

Low-power mode 2

(3)(4)

2.2 V 0 6.3 6.7 9.9 9.0 11 16

(5)(4)

2.2 V 1 1.6 1.9 4.8 6.6

Low-power mode 3,
crystal mode

(6)(4)

PMMCOREVx UNIT

CC

3 V 3 78 83 98 89 94 108

3 V 3 6.6 7.0 11 10 12 18

0 1.6 1.8 2.4 4.7 6.5 10.5

2 1.7 2.0 4.9 6.7
0 1.9 2.1 2.7 5.0 6.8 10.8 µA

3 V

1 1.9 2.1 5.1 7.0
2 2.0 2.2 5.2 7.1
3 2.0 2.2 2.9 5.4 7.3 12.6

(1)(2)

µA

µA

(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external

load capacitance are chosen to closely match the required 9 pF.
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), f

LDO disabled (LDOEN = 0).
(4) Current for brownout included. Low-side supervisor and monitors disabled (SVSL, SVML). High-side supervisor and monitor disabled

(SVSH, SVMH). RAM retention enabled.
(5) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low-frequency crystal operation

(XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), f

setting = 1 MHz operation, DCO bias generator enabled.

LDO disabled (LDOEN = 0).
(6) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low-frequency crystal operation

(XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), f

LDO disabled (LDOEN = 0).

Copyright © 2010–2015, Texas Instruments Incorporated Specifications 17

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= 32768 Hz, f

ACLK

= 32768 Hz, f

ACLK

= 32768 Hz, f

ACLK

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MCLK

MCLK

MCLK

= 0 MHz, f

= 0 MHz, f

= f

SMCLK

SMCLK

SMCLK

= f

DCO

= f

DCO

= f

DCO

= 0 MHz

= 1 MHz

= 0 MHz; DCO

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SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

Low-Power Mode Supply Currents (Into VCC) Excluding External Current (continued)

= f

(1)(2)

SMCLK

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER V

PMMCOREVx UNIT

CC

0 0.9 1.2 1.9 4.0 5.9 10.3

I

LPM3,

VLO,WDT

Low-power mode 3,
VLO mode, Watchdog 3 V µA

(7)(4)

enabled

1 0.9 1.2 4.1 6.0
2 1.0 1.3 4.2 6.1
3 1.0 1.3 2.2 4.3 6.3 11.3
0 0.9 1.1 1.8 3.9 5.8 10

I

LPM4

Low-power mode 4

(8)(4)

3 V µA

1 0.9 1.1 4.0 5.9
2 1.0 1.2 4.1 6.1
3 1.0 1.2 2.1 4.2 6.2 11

Low-power mode 3.5

I

LPM3.5,

RTC,VCC

(LPM3.5) current with
active RTC into primary
supply pin DV

CC

(9)

3 V 0.5 0.8 1.4 µA

Low-power mode 3.5

I

LPM3.5,

RTC,VBAT

I

LPM3.5,

RTC,TOT

I

LPM4.5

(LPM3.5) current with
active RTC into backup
supply pin VBAT

(10)

3 V 0.6 0.8 1.4 µA

Total low-power mode

3.5 (LPM3.5) current 3 V 1.0 1.1 1.3 1.6 2.8 µA
with active RTC

Low-power mode 4.5
(LPM4.5)

(12)

(11)

3 V 0.2 0.3 0.6 0.7 0.9 1.4 µA

(7) Current for watchdog timer clocked by VLO included.

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), f

LDO disabled (LDOEN = 0).
(8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), f

LDO disabled (LDOEN = 0).
(9) V
(10) V

(11) f
(12) Internal regulator disabled. No data retention.

= VCC- 0.2 V, f

VBAT

= VCC- 0.2 V, f

VBAT

current drawn on VBAK

DCO

= f

MCLK

= f

SMCLK

= f

DCO

= f

DCO

= 0 MHz, f

MCLK

MCLK

= f
= f

ACLK

= 0 MHz, f

SMCLK

= 0 MHz, f

SMCLK

= 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no current drawn on VBAK

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), f

–40°C 25°C 60°C 85°C

TYP MAX TYP MAX TYP MAX TYP MAX

= f

ACLK

= f

DCO

= 32768 Hz, PMMREGOFF = 1, RTC in backup domain active

ACLK

= 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no

ACLK

MCLK

ACLK

= f

= f

MCLK

SMCLK

= f

DCO

= f

DCO

SMCLK

= f

= 0 MHz

= 0 MHz

ACLK

= f

MCLK

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= 0 MHz

5.6 Thermal Resistance Characteristics

PARAMETER VALUE UNIT

θ

JA

θ

JC(TOP)

θ

JB

Junction-to-ambient thermal resistance, still air

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

(3)

(1)

(2)

(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

18 Specifications Copyright © 2010–2015, Texas Instruments Incorporated

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QFP (PZ) 122
BGA (ZQW) 108
QFP (PZ) 83
BGA (ZQW) 72
QFP (PZ) 98
BGA (ZQW) 76

°C/W

°C/W

°C/W

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MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333

SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

5.7 Schmitt-Trigger Inputs – General-Purpose I/O

(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

V

Positive-going input threshold voltage V

IT+

V

Negative-going input threshold voltage V

IT–

V

Input voltage hysteresis (V

hys

R

Pullup or pulldown resistor

Pull

C

Input capacitance VIN= VSSor V

I

IT+

(2)

– V

) V

IT–

For pullup: VIN= V
For pulldown: VIN= V

SS

CC

CC

CC

1.8 V 0.80 1.40
3 V 1.50 2.10

1.8 V 0.45 1.00
3 V 0.75 1.65

1.8 V 0.3 0.8
3 V 0.4 1.0

(1) Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).
(2) Also applies to RST pin when pullup or pulldown resistor is enabled.

5.8 Inputs – Ports P1, P2, P3, and P4

(1)

MIN TYP MAX UNIT

20 35 50 kΩ

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

t

External interrupt timing

(int)

(2)

Port P1, P2, P3, P4: P1.x to P4.x,
External trigger pulse duration to set interrupt flag

(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
(2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t

shorter than t

(int)

.

is met. It may be set by trigger signals

(int)

CC

2.2 V, 3 V 20 ns

5 pF

MIN MAX UNIT

5.9 Leakage Current – General-Purpose I/O

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

I

lkg(Px.x)

PARAMETER TEST CONDITIONS V

High-impedance leakage current

(1)(2)

CC

1.8 V, 3 V ±50 nA

(1) The leakage current is measured with VSSor VCCapplied to the corresponding pin(s), unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is

disabled.

MIN MAX UNIT

5.10 Outputs – General-Purpose I/O (Full Drive Strength)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

V

V

High-level output voltage V

OH

Low-level output voltage V

OL

(1) The maximum total current, I

specified.

(2) The maximum total current, I

drop specified.

(OHmax)

(OHmax)

and I
and I

I

= –3 mA

(OHmax)

I

= –10 mA

(OHmax)

I

= –5 mA

(OHmax)

I

= –15 mA

(OHmax)

I

= 3 mA

(OLmax)

I

= 10 mA

(OLmax)

I

= 5 mA

(OLmax)

I

= 15 mA

(OLmax)

, for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop

(OLmax)

, for all outputs combined should not exceed ±100 mA to hold the maximum voltage

(OLmax)

(1)

(2)

(1)

(2)

(1)

(2)

(1)

(2)

CC

1.8 V

3 V

1.8 V

3 V

MIN MAX UNIT

VCC– 0.25 V
VCC– 0.60 V
VCC– 0.25 V
VCC– 0.60 V

VSSVSS+ 0.25
VSSVSS+ 0.60
VSSVSS+ 0.25
VSSVSS+ 0.60

CC
CC
CC
CC

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5.11 Outputs – General-Purpose I/O (Reduced Drive Strength)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

I

(OHmax)

I

V

V

High-level output voltage V

OH

Low-level output voltage V

OL

(OHmax)

I

(OHmax)

I

(OHmax)

I

(OLmax)

I

(OLmax)

I

(OLmax)

I

(OLmax)

(1) Selecting reduced drive strength may reduce EMI.
(2) The maximum total current, I

specified.

(3) The maximum total current, I

drop specified.

(OHmax)

(OHmax)

and I
and I

, for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop

(OLmax)

, for all outputs combined, should not exceed ±100 mA to hold the maximum voltage

(OLmax)

= –1 mA
= –3 mA
= –2 mA

= –6 mA
= 1 mA
= 3 mA
= 2 mA
= 6 mA

(2)
(3)
(2)

(3)
(2)
(3)
(2)
(3)

CC

1.8 V

3 V

1.8 V

3 V

VCC– 0.25 V
VCC– 0.60 V
VCC– 0.25 V
VCC– 0.60 V

(1)

MIN MAX UNIT

CC
CC
CC
CC

VSSVSS+ 0.25
VSSVSS+ 0.60
VSSVSS+ 0.25
VSSVSS+ 0.60

5.12 Output Frequency – Ports P1, P2, and P3

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

VCC= 1.8 V,

f

Px.y

Port output frequency P3.4/TA2CLK/SMCLK/S27,
(with load) CL= 20 pF, RL= 1 kΩ

(1)

or 3.2 kΩ

(2)(3)

PMMCOREVx = 0
VCC= 3 V,

PMMCOREVx = 3
VCC= 1.8 V,

PMMCOREVx = 0
VCC= 3 V,

PMMCOREVx = 3

f

Port_CLK

P1.0/TA0CLK/ACLK/S39,

Clock output frequency MHz

P3.4/TA2CLK/SMCLK/S27,
P2.0/P2MAP0 (P2MAP0 = PM_MCLK ),
CL= 20 pF

(3)

(1) Full drive strength of port: A resistive divider with 2 × 0.5 kΩ between VCCand VSSis used as load. The output is connected to the

center tap of the divider.

(2) Reduced drive strength of port: A resistive divider with 2 × 1.6 kΩ between VCCand VSSis used as load. The output is connected to the

center tap of the divider.

(3) The output voltage reaches at least 10% and 90% VCCat the specified toggle frequency.

8

MHz

20

8

20

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−25.0

−20.0

−15.0

−10.0

−5.0

0.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

T = 25°C

A

T = 85°C

A

V = 3.0 V
P3.2

CC

V – High-Level Output Voltage – V

OH

I – Typical High-Level Output Current – mA

OH

−8.0

−7.0

−6.0

−5.0

−4.0

−3.0

−2.0

−1.0

0.0

0.0 0.5 1.0 1.5 2.0

T = 25°C

A

T = 85°C

A

V = 1.8 V
P3.2

CC

V – High-Level Output Voltage – V

OH

I – Typical High-Level Output Current – mA

OH

0.0

5.0

10.0

15.0

20.0

25.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

T = 25°C

A

T = 85°C

A

V = 3.0 V
P3.2

CC

V – Low-Level Output Voltage – V

OL

I – Typical Low-Level Output Current – mA

OL

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

0.0 0.5 1.0 1.5 2.0

T = 25°C

A

T = 85°C

A

V = 1.8 V
P3.2

CC

V – Low-Level Output Voltage – V

OL

I – Typical Low-Level Output Current – mA

OL

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SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

Figure 5-2. Typical Low-Level Output Current vs Low-Level

Figure 5-4. Typical High-Level Output Current vs High-Level

Output Voltage

Output Voltage

Figure 5-3. Typical Low-Level Output Current vs Low-Level

Figure 5-5. Typical High-Level Output Current vs High-Level

Output Voltage

Output Voltage

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−20

−16

−12

−8

−4

0

0.0 0.5 1.0 1.5 2.0

T = 25°C

A

T = 85°C

A

V = 1.8 V
P3.2

CC

V – High-Level Output Voltage – V

OH

I – Typical High-Level Output Current – mA

OH

−60.0

−55.0

−50.0

−45.0

−40.0

−35.0

−30.0

−25.0

−20.0

−15.0

−10.0

−5.0

0.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

T = 25°C

A

T = 85°C

A

V = 3.0 V
P3.2

CC

V – High-Level Output Voltage – V

OH

I – Typical High-Level Output Current – mA

OH

0.0

5.0

10.0

15.0

20.0

25.0

30.0

35.0

40.0

45.0

50.0

55.0

60.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

T = 25°C

A

T = 85°C

A

V = 3.0 V
P3.2

CC

V – Low-Level Output Voltage – V

OL

I – Typical Low-Level Output Current – mA

OL

0

4

8

12

16

20

24

0.0 0.5 1.0 1.5 2.0

T = 25°C

A

T = 85°C

A

V = 1.8 V
P3.2

CC

V – Low-Level Output Voltage – V

OL

I – Typical Low-Level Output Current – mA

OL

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SLAS721D –AUGUST 2010–REVISED DECEMBER 2015

5.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

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Figure 5-6. Typical Low-Level Output Current vs Low-Level

Figure 5-8. Typical High-Level Output Current vs High-Level

22 Specifications Copyright © 2010–2015, Texas Instruments Incorporated

Output Voltage

Output Voltage

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Figure 5-7. Typical Low-Level Output Current vs Low-Level

Figure 5-9. Typical High-Level Output Current vs High-Level

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Output Voltage

Output Voltage

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5.15 Crystal Oscillator, XT1, Low-Frequency Mode

(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

f

= 32768 Hz, XTS = 0,

OSC

XT1BYPASS = 0, XT1DRIVEx = 1, 0.075

CC

TA= 25°C

ΔI

DVCC,LF

Differential XT1 oscillator crystal f
current consumption from lowest XT1BYPASS = 0, XT1DRIVEx = 2, 3 V 0.170 µA
drive setting, LF mode TA= 25°C

= 32768 Hz, XTS = 0,

OSC

f

= 32768 Hz, XTS = 0,

OSC

XT1BYPASS = 0, XT1DRIVEx = 3, 0.290
TA= 25°C

f

XT1,LF0

f

XT1,LF,SW

XT1 oscillator crystal frequency,
LF mode

XT1 oscillator logic-level square­wave input frequency, LF mode

XTS = 0, XT1BYPASS = 0 32768 Hz

XTS = 0, XT1BYPASS = 1

(2) (3)

XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0, 210

OA

= 32768 Hz, C

LF

Oscillation allowance for
LF crystals

(4)

XT1,LF

XTS = 0,

L,eff

= 6 pF

f

XT1BYPASS = 0, XT1DRIVEx = 1, 300
f

= 32768 Hz, C

XT1,LF

XTS = 0, XCAPx = 0

C

L,eff

Integrated effective load
capacitance, LF mode

(5)

XTS = 0, XCAPx = 1 5.5
XTS = 0, XCAPx = 2 8.5

= 12 pF

L,eff

(6)

XTS = 0, XCAPx = 3 12.0
XTS = 0, Measured at ACLK,

f

= 32768 Hz

XT1,LF

XTS = 0
f

XT1BYPASS = 0, XT1DRIVEx = 0,

(8)

= 32768 Hz, XTS = 0,

OSC

f

Fault,LF

Duty cycle, LF mode 30% 70%
Oscillator fault frequency,

LF mode

(7)

TA= 25°C,
C

= 6 pF

t

START,LF

Start-up time, LF mode 3 V ms

L,eff

f

= 32768 Hz, XTS = 0,

OSC

XT1BYPASS = 0, XT1DRIVEx = 3,
TA= 25°C,
C

= 12 pF

L,eff

(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.

• Keep the trace between the device and the crystal as short as possible.

• Design a good ground plane around the oscillator pins.

• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.

• If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.

(2) When XT1BYPASS is set, XT1 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined in

the Schmitt-trigger Inputs section of this datasheet.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the

XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following

guidelines, but should be evaluated based on the actual crystal selected for the application:

• For XT1DRIVEx = 0, C

• For XT1DRIVEx = 1, 6 pF ≤ C

• For XT1DRIVEx = 2, 6 pF ≤ C

• For XT1DRIVEx = 3, C

(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

L,eff

L,eff

≤ 6 pF.

L,eff
L,eff

≥ 6 pF.

≤ 9 pF.
≤ 10 pF.

Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a

correct setup, the effective load capacitance should always match the specification of the used crystal.
(6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies in between might set the flag.
(8) Measured with logic-level input frequency but also applies to operation with crystals.

MIN TYP MAX UNIT

10 32.768 50 kHz

kΩ

1

pF

10 10000 Hz

1000

500

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5.16 Crystal Oscillator, XT2

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

f

= 4 MHz, XT2OFF = 0,

OSC

XT2BYPASS = 0, XT2DRIVEx = 0, 200
TA= 25°C

f

= 12 MHz, XT2OFF = 0,

OSC

XT2BYPASS = 0, XT2DRIVEx = 1, 260

I

DVCC,XT2

XT2 oscillator crystal current
consumption

TA= 25°C
f

= 20 MHz, XT2OFF = 0,

OSC

XT2BYPASS = 0, XT2DRIVEx = 2, 325
TA= 25°C

f

= 32 MHz, XT2OFF = 0,

OSC

XT2BYPASS = 0, XT2DRIVEx = 3, 450
TA= 25°C

f

XT2,HF0

f

XT2,HF1

f

XT2,HF2

f

XT2,HF3

f

XT2,HF,SW

XT2 oscillator crystal frequency,
mode 0

XT2 oscillator crystal frequency,
mode 1

XT2 oscillator crystal frequency,
mode 2

XT2 oscillator crystal frequency,
mode 3

XT2 oscillator logic-level square­wave input frequency

XT2DRIVEx = 0, XT2BYPASS = 0

XT2DRIVEx = 1, XT2BYPASS = 0

XT2DRIVEx = 2, XT2BYPASS = 0

XT2DRIVEx = 3, XT2BYPASS = 0

XT2BYPASS = 1

(4) (3)

(3)

(3)

(3)

(3)

XT2DRIVEx = 0, XT2BYPASS = 0,
f

XT2,HF0

= 6 MHz, C

L,eff

= 15 pF

XT2DRIVEx = 1, XT2BYPASS = 0,

OA

HF

Oscillation allowance for
HF crystals

(5)

f
XT2DRIVEx = 2, XT2BYPASS = 0,

f

XT2,HF1

XT2,HF2

= 12 MHz, C

= 20 MHz, C

L,eff

L,eff

= 15 pF

= 15 pF

XT2DRIVEx = 3, XT2BYPASS = 0,

t

START,HF

C

L,eff

f

Fault,HF

f
f

XT2BYPASS = 0, XT2DRIVEx = 0, 0.5

Start-up time 3 V ms

TA= 25°C, C
f

XT2BYPASS = 0, XT2DRIVEx = 3, 0.3
TA= 25°C, C

Integrated effective load
capacitance, HF mode

(6) (1)

Duty cycle Measured at ACLK, f
Oscillator fault frequency

(7)

XT2BYPASS = 1

XT2,HF3

= 6 MHz

OSC

= 20 MHz

OSC

= 32 MHz, C

= 15 pF

L,eff

= 15 pF

L,eff

(8)

= 15 pF

L,eff

= 20 MHz 40% 50% 60%

XT2,HF2

(1) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(2) To improve EMI on the XT2 oscillator the following guidelines should be observed.

• Keep the traces between the device and the crystal as short as possible.

• Design a good ground plane around the oscillator pins.

• Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.

• Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.

• Use assembly materials and processes that avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.

• If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) When XT2BYPASS is set, the XT2 circuit is automatically powered down.
(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.
(6) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.

(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies in between might set the flag.

(8) Measured with logic-level input frequency but also applies to operation with crystals.

CC

3 V µA

(1) (2)

MIN TYP MAX UNIT

4 8 MHz

8 16 MHz

16 24 MHz

24 32 MHz

0.7 32 MHz

450

320

200

200

1 pF

30 300 kHz

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5.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

f

VLO

df

VLO/dT

df

VLO

VLO frequency Measured at ACLK 1.8 V to 3.6 V 6 9.4 14 kHz
VLO frequency temperature drift Measured at ACLK

/dVCCVLO frequency supply voltage drift Measured at ACLK

(1)
(2)

CC

1.8 V to 3.6 V 0.5 %/°C

1.8 V to 3.6 V 4 %/V

Duty cycle Measured at ACLK 1.8 V to 3.6 V 40% 50% 60%

(1) Calculated using the box method: (MAX(–40°C to +85°C) – MIN(–40°C to +85°C)) / MIN(–40°C to +85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

MIN TYP MAX UNIT

5.18 Internal Reference, Low-Frequency Oscillator (REFO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

I

REFO

PARAMETER TEST CONDITIONS V

REFO oscillator current
consumption

TA= 25°C 1.8 V to 3.6 V 3 µA

CC

REFO frequency calibrated Measured at ACLK 1.8 V to 3.6 V 32768 Hz

f

REFO

df

REFO/dT

df

REFO

/dV

REFO absolute tolerance
calibrated

REFO frequency temperature drift Measured at ACLK
REFO frequency supply voltage

CC

drift

Full temperature range 1.8 V to 3.6 V ±3.5%
TA= 25°C 3 V ±1.5%

Measured at ACLK

(1)

(2)

1.8 V to 3.6 V 0.01 %/°C

1.8 V to 3.6 V 1.0 %/V

Duty cycle Measured at ACLK 1.8 V to 3.6 V 40% 50% 60%

t

START

REFO start-up time 40%/60% duty cycle 1.8 V to 3.6 V 25 µs

(1) Calculated using the box method: (MAX(–40°C to +85°C) – MIN(–40°C to +85°C)) / MIN(–40°C to +85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

MIN TYP MAX UNIT

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0

1 2

3

4

5

6

7

Typical DCO Frequency,V = 3.0 V,T = 25°C

CC A

DCORSEL

100

10

1

0.1

f – MHz

DCO

DCOx = 31

DCOx = 0

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5.19 DCO Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

DCO(0,0)

f

DCO(0,31)

f

DCO(1,0)

f

DCO(1,31)

f

DCO(2,0)

f

DCO(2,31)

f

DCO(3,0)

f

DCO(3,31)

f

DCO(4,0)

f

DCO(4,31)

f

DCO(5,0)

f

DCO(5,31)

f

DCO(6,0)

f

DCO(6,31)

f

DCO(7,0)

f

DCO(7,31)

S

DCORSEL

S

DCO

df

/dT DCO frequency temperature drift f

DCO

df

/dV

DCO

CC

DCO frequency (0, 0) DCORSELx = 0, DCOx = 0, MODx = 0 0.07 0.20 MHz
DCO frequency (0, 31) DCORSELx = 0, DCOx = 31, MODx = 0 0.70 1.70 MHz
DCO frequency (1, 0) DCORSELx = 1, DCOx = 0, MODx = 0 0.15 0.36 MHz
DCO frequency (1, 31) DCORSELx = 1, DCOx = 31, MODx = 0 1.47 3.45 MHz
DCO frequency (2, 0) DCORSELx = 2, DCOx = 0, MODx = 0 0.32 0.75 MHz
DCO frequency (2, 31) DCORSELx = 2, DCOx = 31, MODx = 0 3.17 7.38 MHz
DCO frequency (3, 0) DCORSELx = 3, DCOx = 0, MODx = 0 0.64 1.51 MHz
DCO frequency (3, 31) DCORSELx = 3, DCOx = 31, MODx = 0 6.07 14.0 MHz
DCO frequency (4, 0) DCORSELx = 4, DCOx = 0, MODx = 0 1.3 3.2 MHz
DCO frequency (4, 31) DCORSELx = 4, DCOx = 31, MODx = 0 12.3 28.2 MHz
DCO frequency (5, 0) DCORSELx = 5, DCOx = 0, MODx = 0 2.5 6.0 MHz
DCO frequency (5, 31) DCORSELx = 5, DCOx = 31, MODx = 0 23.7 54.1 MHz
DCO frequency (6, 0) DCORSELx = 6, DCOx = 0, MODx = 0 4.6 10.7 MHz
DCO frequency (6, 31) DCORSELx = 6, DCOx = 31, MODx = 0 39.0 88.0 MHz
DCO frequency (7, 0) DCORSELx = 7, DCOx = 0, MODx = 0 8.5 19.6 MHz
DCO frequency (7, 31) DCORSELx = 7, DCOx = 31, MODx = 0 60 135 MHz
Frequency step between range

DCORSEL and DCORSEL + 1
Frequency step between tap

DCO and DCO + 1

S

S

= f

RSEL

DCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)

= f

DCO

DCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)

1.2 2.3 ratio

1.02 1.12 ratio

Duty cycle Measured at SMCLK 40% 50% 60%

= 1 MHz 0.1 %/°C

DCO

DCO frequency voltage drift f

= 1 MHz 1.9 %/V

DCO

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Figure 5-10. Typical DCO frequency

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5.20 PMM, Brownout Reset (BOR)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V(DVCC_BOR_IT–) | dDVCC/dt| < 3 V/s 1.45 V

V(DVCC_BOR_IT+) | dDVCC/dt| < 3 V/s 0.80 1.30 1.50 V
V(DVCC_BOR_hys) BORHhysteresis 60 250 mV

t

RESET

BORHon voltage,
DVCCfalling level

BORHoff voltage,
DVCCrising level

Pulse length required at
RST/NMI pin to accept a 2 µs
reset

5.21 PMM, Core Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

(AM) 2.4 V ≤ DVCC≤ 3.6 V, 0 mA ≤ I(V

CORE3

V

(AM) 2.2 V ≤ DVCC≤ 3.6 V, 0 mA ≤ I(V

CORE2

V

(AM) 2 V ≤ DVCC≤ 3.6 V, 0 mA ≤ I(V

CORE1

V

(AM) 1.8 V ≤ DVCC≤ 3.6 V, 0 mA ≤ I(V

CORE0

V

(LPM) 2.4 V ≤ DVCC≤ 3.6 V, 0 µA ≤ I(V

CORE3

V

(LPM) 2.2 V ≤ DVCC≤ 3.6 V, 0 µA ≤ I(V

CORE2

V

(LPM) 2 V ≤ DVCC≤ 3.6 V, 0 µA ≤ I(V

CORE1

V

(LPM) 1.8 V ≤ DVCC≤ 3.6 V, 0 µA ≤ I(V

CORE0

Core voltage, active
mode, PMMCOREV = 3

Core voltage, active
mode, PMMCOREV = 2

Core voltage, active
mode, PMMCOREV = 1

Core voltage, active
mode, PMMCOREV = 0

Core voltage, low-current
mode, PMMCOREV = 3

Core voltage, low-current
mode, PMMCOREV = 2

Core voltage, low-current
mode, PMMCOREV = 1

Core voltage, low-current
mode, PMMCOREV = 0

) ≤ 21 mA 1.90 V

CORE

) ≤ 21 mA 1.80 V

CORE

) ≤ 17 mA 1.60 V

CORE

) ≤ 13 mA 1.40 V

CORE

) ≤ 30 µA 1.94 V

CORE

) ≤ 30 µA 1.84 V

CORE

) ≤ 30 µA 1.64 V

CORE

) ≤ 30 µA 1.44 V

CORE

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5.22 PMM, SVS High Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SVSHE = 0, DVCC= 3.6 V 0

I

(SVSH)

SVS current consumption SVSHE = 1, DVCC= 3.6 V, SVSHFP = 0 200

SVSHE = 1, DVCC= 3.6 V, SVSHFP = 1 2.0 µA
SVSHE = 1, SVSHRVL = 0 1.59 1.64 1.69

V

(SVSH_IT–)

SVSHon voltage level

(1)

SVSHE = 1, SVSHRVL = 1 1.79 1.84 1.91
SVSHE = 1, SVSHRVL = 2 1.98 2.04 2.11
SVSHE = 1, SVSHRVL = 3 2.10 2.16 2.23
SVSHE = 1, SVSMHRRL = 0 1.62 1.74 1.81
SVSHE = 1, SVSMHRRL = 1 1.88 1.94 2.01
SVSHE = 1, SVSMHRRL = 2 2.07 2.14 2.21

V

(SVSH_IT+)

SVSHoff voltage level

(1)

SVSHE = 1, SVSMHRRL = 3 2.20 2.26 2.33
SVSHE = 1, SVSMHRRL = 4 2.32 2.40 2.48
SVSHE = 1, SVSMHRRL = 5 2.56 2.70 2.84
SVSHE = 1, SVSMHRRL = 6 2.85 3.00 3.15
SVSHE = 1, SVSMHRRL = 7 2.85 3.00 3.15

t

pd(SVSH)

t

(SVSH)

dV

DVCC

SVSHpropagation delay µs

SVSHon or off delay time µs

/dt DVCCrise time 0 1000 V/s

SVSHE = 1, dV
SVSHE = 1, dV
SVSHE = 0→1, SVSHFP = 1 12.5
SVSHE = 0→1, SVSHFP = 0 100

/dt = 10 mV/µs, SVSHFP = 1 2.5

DVCC

/dt = 1 mV/µs, SVSHFP = 0 20

DVCC

(1) The SVSHsettings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage

Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and usage.

nA

V

V

5.23 PMM, SVM High Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SVMHE = 0, DVCC = 3.6 V 0

I

(SVMH)

SVMHcurrent consumption SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0 200

SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1 2.0 µA
SVMHE = 1, SVSMHRRL = 0 1.65 1.74 1.86
SVMHE = 1, SVSMHRRL = 1 1.85 1.94 2.02
SVMHE = 1, SVSMHRRL = 2 2.02 2.14 2.22
SVMHE = 1, SVSMHRRL = 3 2.18 2.26 2.35

V

(SVMH)

SVMHon or off voltage level

(1)

SVMHE = 1, SVSMHRRL = 4 2.32 2.40 2.48 V
SVMHE = 1, SVSMHRRL = 5 2.56 2.70 2.84
SVMHE = 1, SVSMHRRL = 6 2.85 3.00 3.15
SVMHE = 1, SVSMHRRL = 7 2.85 3.00 3.15
SVMHE = 1, SVMHOVPE = 1 3.75

t

pd(SVMH)

t

(SVMH)

SVMHpropagation delay µs

SVMHon or off delay time µs

SVMHE = 1, dV
SVMHE = 1, dV
SVMHE = 0→1, SVSMFP = 1 12.5
SVMHE = 0→1, SVMHFP = 0 100

/dt = 10 mV/µs, SVMHFP = 1 2.5

DVCC

/dt = 1 mV/µs, SVMHFP = 0 20

DVCC

(1) The SVMHsettings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage

Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and usage.

nA

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5.24 PMM, SVS Low Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SVSLE = 0, PMMCOREV = 2 0

I

(SVSL)

t

pd(SVSL)

t

(SVSL)

SVSLcurrent consumption SVSLE = 1, PMMCOREV = 2, SVSLFP = 0 200

SVSLE = 1, PMMCOREV = 2, SVSLFP = 1 2.0 µA

SVSLpropagation delay µs

SVSLon/off delay time µs

SVSLE = 1, dV
SVSLE = 1, dV
SVSLE = 0→1, SVSLFP = 1 12.5
SVSLE = 0→1, SVSLFP = 0 100

/dt = 10 mV/µs, SVSLFP = 1 2.5

CORE

/dt = 1 mV/µs, SVSLFP = 0 20

CORE

5.25 PMM, SVM Low Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SVMLE = 0, PMMCOREV = 2 0

I

(SVML)

t

pd(SVML)

t

(SVML)

SVMLcurrent consumption SVMLE = 1, PMMCOREV = 2, SVMLFP = 0 200

SVMLE = 1, PMMCOREV = 2, SVMLFP = 1 2.0 µA

SVMLpropagation delay µs

SVMLon or off delay time µs

SVMLE = 1, dV
SVMLE = 1, dV
SVMLE = 0→1, SVMLFP = 1 12.5
SVMLE = 0→1, SVMLFP = 0 100

/dt = 10 mV/µs, SVMLFP = 1 2.5

CORE

/dt = 1 mV/µs, SVMLFP = 0 20

CORE

nA

nA

5.26 Wake-up Times From Low-Power Modes and Reset

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

≥ 4 MHz 3 6.5

t

WAKE-UP-FAST

LPM3, or LPM4 to active (where n = 0, 1, 2, or 3), µs

(1)

mode

SVSLFP = 1

Wake-up time from LPM2, PMMCOREV = SVSMLRRL = n

Wake-up time from LPM2, PMMCOREV = SVSMLRRL = n

t

WAKE-UP-SLOW

t

WAKE-UP-LPM5

t

WAKE-UP-RESET

LPM3 or LPM4 to active (where n = 0, 1, 2, or 3), 150 165 µs

(2)

mode
Wake-up time from LPM3.5 or

LPM4.5 to active mode

(3)

Wake-up time from RST or
BOR event to active mode

SVSLFP = 0

(3)

(1) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance

mode of the low-side supervisor (SVSL) and low-side monitor (SVML). Fastest wake-up times are possible with SVSLand SVMLin full
performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVMLwhile
operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx
and MSP430x6xx Family User's Guide (SLAU208).

(2) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance

mode of the low-side supervisor (SVSL) and low-side monitor (SVML). In this case, the SVSLand SVMLare in normal mode (low
current) mode when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVMLwhile operating in LPM2,
LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx
Family User's Guide (SLAU208).

(3) This value represents the time from the wake-up event to the reset vector execution.

MCLK

1 MHz < f
4 MHz

MCLK

<

4 8.0

2 3 ms

2 3 ms

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5.27 Timer_A, Timers TA0, TA1, and TA2

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

f

TA

t

TA,cap

PARAMETER TEST CONDITIONS V

Internal: SMCLK, ACLK

Timer_A input clock frequency External: TACLK 1.8 V, 3 V 20 MHz

Duty cycle = 50% ±10%
All capture inputs,

Timer_A capture timing Minimum pulse duration required for 1.8 V, 3 V 20 ns

capture

CC

5.28 Timer_B, Timer TB0

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

f

TB

t

TB,cap

PARAMETER TEST CONDITIONS V

Internal: SMCLK, ACLK

Timer_B input clock frequency External: TBCLK 1.8 V, 3 V 20 MHz

Duty cycle = 50% ±10%
All capture inputs,

Timer_B capture timing Minimum pulse duration required for 1.8 V, 3 V 20 ns

capture

CC

5.29 Battery Backup

over operating free-air temperature range (unless otherwise noted)

I

VBAT

V

SWITCH

R

ON_VBAT

V

BAT3

t

Sample,

VBAT3

V

CHVx

R

CHARGE

PARAMETER TEST CONDITIONS V

CC

TA= –40°C 0.43

VBAT = 1.7 V,
DVCC not connected,
RTC running

TA= 25°C 0.52
TA= 60°C 0.58
TA= 85°C 0.64
TA= –40°C 0.50

Current into VBAT terminal if no
primary battery is connected

VBAT = 2.2 V,
DVCC not connected, µA
RTC running

TA= 25°C 0.59
TA= 60°C 0.64
TA= 85°C 0.71
TA= –40°C 0.68

VBAT = 3 V,
DVCC not connected,
RTC running

TA= 25°C 0.75
TA= 60°C 0.79
TA= 85°C 0.86
General V
SVSHRL = 0 1.59 1.69

Switch-over level (VCCto VBAT) C

= 4.7 µF SVSHRL = 1 1.79 1.91 V

VCC

SVSHRL = 2 1.98 2.11
SVSHRL = 3 2.10 2.23

ON-resistance of switch
between VBAT and VBAK

V

= 1.8 V 0 V 0.35 1 kΩ

BAT

1.8 V 0.6 ±5%
VBAT to ADC input channel 12:
V

BAT

divided, V

BAT3

= V

BAT

/3

3 V 1.0 ±5% V

3.6 V 1.2 ±5%
VBAT to ADC: Sampling time ADC12ON = 1,

required if VBAT3 selected Error of conversion result ≤ 1 LSB
Charger end voltage CHVx = 2 2.65 2.7 2.9 V

CHCx = 1 5

Charge limiting resistor CHCx = 2 10 kΩ

CHCx = 3 20

MIN TYP MAX UNIT

1000 ns

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MIN MAX UNIT

MIN MAX UNIT

SVSH_IT-

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