TEXAS INSTRUMENTS MSP430F42xA Technical data

MSP430F42xA

MIXED SIGNAL MICROCONTROLLER

SLAS587 -- FEBRUARY 2008

D Low Supply-Voltage Range, 1.8 V to 3.6 V
D Ultra-Low Power Consumption:

-- Active Mode: 400 μAat1MHz,3.0V

-- Standby Mode: 1.6 μA

-- Off Mode (RAM Retention): 0.1 μA

D Five Power-Saving Modes
D Wake-Up From Standby Mode in Less

Than 6 μs

D Frequency-Locked Loop, FLL+
D 16-Bit RISC Architecture, 125-ns

Instruction Cycle Time

D Three Independent 16-bit Sigma-Delta A/D

Converters With Differential PGA Inputs

D 16-Bit Timer_A With Three

Capture/Compare Registers

D Integrated LCD Driver for 128 Segments
D Serial Communication Interface (USART),

Asynchronous UART, or Synchronous SPI
Selectable by Software

D Brownout Detector

description

D Supply Voltage Supervisor/Monitor With

Programmable Level Detection

D Serial Onboard Programming,

No External Programming Voltage Needed,
Programmable Code Protection by Security
Fuse

D Bootstrap Loader in Flash Devices
D Family Members Include:

-- MSP430F423A:
8KB + 256B Flash Memory,
256B RAM

-- MSP430F425A:
16KB + 256B Flash Memory,
512B RAM

-- MSP430F427A:
32KB + 256B Flash Memory,
1KB RAM

D Availablein64-PinQuadFlatPack(QFP)
D For Complete Module Descriptions, Refer

to the MSP430x4xx Family User’s Guide,
Literature Number SLAU056

The Texas Instruments MSP430family ofultra-low power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. Thedigitally controlled oscillator (DCO) allows wake-up from low-power modesto activemode in less
than 6 μs.

The MSP430F42xA series are microcontroller configurations with three independent 16-bit sigma-delta A/D
converters, each with an integrated differential programmable gain amplifier input stage. Also included are a
built-in 16-bit timer, 128 LCD segment drive capability, hardware multiplier, and 14 I/O pins.

Typical applications include high-resolution applications such as handheld metering equipment, weigh scales,
and energy meters.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures cancause damage. ESD damagecan range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

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Copyright © 2008 Texas Instruments Incorporated

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MSP430F42xA

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MIXED SIGNAL MICROCONTROLLER

SLAS587 -- FEBRUARY 2008

T

A

-- 4 0 °Cto85°C

AVAILABLE OPTIONS

PACKAGED DEVICES

PLASTIC 64-PIN QFP

(PM)

MSP430F423AIPM
MSP430F425AIPM
MSP430F427AIPM

pin designation

†

DV

CC

A0.0+
A0.0-­A1.0+
A1.0-­A2.0+
A2.0--

XIN

XOUT

V

REF

P2.2/STE0

S0
S1
S2
S3
S4

SS

SS

CC

DV

AV

AV

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1
2
3
4
5

6
7
8

9
10
11

12
13
14
15
16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

P2.3/SVSIN

P2.4/UTXD0

P2.5/URXD0

RST/NMI

MSP430F42xA

TCK

TMS

TDI/TCLK

TDO/TDI

P1.0/TA0

P1.1/TA0/MCLK

P1.2/TA1/S31

P1.3/SVSOUT/S3

P1.4/S29

P1.5/TACLK/ACLK/S28

48

P1.6/SIMO0/S27

47

P1.7/SOMI0/S26

46

P2.0/TA2/S25

45

P2.1/UCLK0/S24

44

R33

43

R23

42

R13

41

R03

40

COM3

39

COM2

38

COM1

37

COM0

36

S23

35

S22

34

S21

33

S5S6S7S8S9

†

It is recommended to short unused analog input pairs and connect them to analog ground.

2

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S10

S11

S12

S13

S14

S15

S16

S17

S18

S19

S20

functional block diagram

MSP430F42xA

MIXED SIGNAL MICROCONTROLLER

SLAS587 -- FEBRUARY 2008

XOUT

XIN

Oscillators

FLL+

MCLK

8MHz

CPU

incl. 16

Registers

Emulation

Module

JTAG

Interface

ACLK

SMCLK

MAB

MDB

Hardware

Multiplier

MPY, MPYS
MAC,MACS

DV

Flash

32KB
16KB

8KB

DV

CC

SS

RAM

1KB
512B
256B

POR/
SVS/

Brownout

RST/NMI

AV

CC

AV

Timer_A3

3CCReg

Watchdog

WDT+

15/16-Bit

SS

P1

8

Port 1

8 I/O

Interrupt

Capability

SD16

Three 16-bit
Sigma-Delta

A/D

Converters

P2

6

Port 2

6 I/O

Interrupt

Capability

Basic

Timer 1

1 Interrupt

Vector

USART0

UART or

Function

Segments

1,2,3,4 MUX

f

LCD

SPI

LCD

128

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MSP430F42xA

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MIXED SIGNAL MICROCONTROLLER

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Terminal Functions

TERMINAL

NAME NO.

DV

CC

A0.0+ 2 I Internal connection to SD16 Channel 0, input 0 +. (see Note 1)

A0.0-- 3 I Internal connection to SD16 Channel 0, input 0 --. (see Note 1)

A1.0+ 4 I Internal connection to SD16 Channel 1, input 0 +. (see Note 1)

A1.0-- 5 I Internal connection to SD16 Channel 1, input 0 --. (see Note 1)

A2.0+ 6 I Internal connection to SD16 Channel 2, input 0 +. (see Note 1)

A2.0-- 7 I Internal connection to SD16 Channel 2, input 0 --. (see Note 1)

XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.

XOUT 9 O Output terminal of crystal oscillator XT1

V

REF

P2.2/STE0 11 I/O General-purpose digital I/O / slave transmit enable—USART0/SPI mode

S0 12 O LCD segment output 0

S1 13 O LCD segment output 1

S2 14 O LCD segment output 2

S3 15 O LCD segment output 3

S4 16 O LCD segment output 4

S5 17 O LCD segment output 5

S6 18 O LCD segment output 6

S7 19 O LCD segment output 7

S8 20 O LCD segment output 8

S9 21 O LCD segment output 9

S10 22 O LCD segment output 10

S11 23 O LCD segment output 11

S12 24 O LCD segment output 12

S13 25 O LCD segment output 13

S14 26 O LCD segment output 14

S15 27 O LCD segment output 15

S16 28 O LCD segment output 16

S17 29 O LCD segment output 17

S18 30 O LCD segment output 18

S19 31 O LCD segment output 19

S20 32 O LCD segment output 20

S21 33 O LCD segment output 21

S22 34 O LCD segment output 22

S23 35 O LCD segment output 23

COM0 36 O Common output, COM0--3 are used for LCD backplanes.

COM1 37 O Common output, COM0--3 are used for LCD backplanes.

COM2 38 O Common output, COM0--3 are used for LCD backplanes.

COM3 39 O Common output, COM0--3 are used for LCD backplanes.

R03 40 I Input port of fourth positive (lowest) analog LCD level (V5)

I

O DESCRIPTION

1 Digital supply voltage, positive terminal.

10 I/O Input for an external reference voltage / internal reference voltage output (can be used as mid-voltage)

NOTE 1: It is recommended to short unused analog input pairs and connect them to analog ground.

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/

Terminal Functions (Continued)

MSP430F42xA

SLAS587 -- FEBRUARY 2008

TERMINAL

NAME NO.

R13 41 I Input port of third most positive analog LCD level (V4 or V3)

R23 42 I Input port of second most positive analog LCD level (V2)

R33 43 O Output port of most positive analog LCD level (V1)

P2.1/UCLK0/S24 44 I/O

P2.0/TA2/S25 45 I/O

P1.7/SOMI0/S26 46 I/O

P1.6/SIMO0/S27 47 I/O

P1.5/TACLK/
ACLK/S28

P1.4/S29 49 I/O General-purpose digital I/O / LCD segment output 29 (See Note 1)

P1.3/SVSOUT/
S30

P1.2/TA1/S31 51 I/O

P1.1/TA0/MCLK 52 I/O

P1.0/TA0 53 I/O General-purpose digital I/O / Timer_A, Capture: CCI0A input, Compare: Out0 output / BSL transmit

TDO/TDI 54 I/O Test data output port. TDO/TDI data output or programming data input terminal.

TDI/TCLK 55 I Test data input or test clock input. The device protection fuse is connected to TDI.

TMS 56 I Test mode select. TMS is used as an input port for device programming and test.

TCK 57 I Test clock. TCK is the clock input port for device programming and test.

RST/NMI 58 I Reset input or nonmaskable interrupt input port

P2.5/URXD0 59 I/O General-purpose digital I/O / receive data in—USART0/UART mode

P2.4/UTXD0 60 I/O General-purpose digital I/O / transmit data out—USART0/UART mode

P2.3/SVSIN 61 I/O General-purpose digital I/O / Analog input to brownout, supply voltage supervisor

AV

SS

DV

SS

AV

CC

I

O DESCRIPTION

General-purpose digital I/O/ external clock input-USART0/UART orSPI mode, clock output—USART0/SPI
mode / LCD segment output 24 (See Note 1)

General-purpose digital I/O / Timer_A Capture: CCI2A input, Compare: Out2 output / LCD segment output
25 (See Note 1)

General-purpose digital I/O / slave out/master in of USART0/SPI mode / LCD segment output 26
(See Note 1)

General-purpose digital I/O / slave in/master out of USART0/SPI mode / LCD segment output 27
(See Note 1)

48 I/O

50 I/O General-purpose digital I/O / SVS: output of SVS comparator / LCD segment output 30 (See Note 1)

62

63 Digital supply voltage, negative terminal

64

General-purpose digital I/O / Timer_A and SD16 clock signal TACLK input / ACLK output (divided by 1,
2, 4, or 8) / LCD segment output 28 (See Note 1)

General-purpose digital I/O/ Timer_A, Capture: CCI1A, CCI1B input, Compare: Out1 output / LCD segment
output 31 (See Note 1)

General-purpose digital I/O / Timer_A, Capture: CCI0B input / MCLK output.
Note: TA0 is only an input on this pin / BSL receive

Analog supply voltage, negative terminal. Supplies SD16, SVS, brownout, oscillator, and LCD resistive
divider circuitry.

Analog supply voltage, positive terminal. Supplies SD16, SVS, brownout, oscillator, and LCD resistive
divider circuitry; must not power up prior to DV

CC

.

NOTE 1: LCD function is selected automatically when applicable LCD module control bits are set, not with PxSEL bits.

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MSP430F42xA
MIXED SIGNAL MICROCONTROLLER

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short-form description

CPU

The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for the
source operand and four addressing modes for
the destination operand.

The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator, respectively. The
remaining registers are general-purpose
registers.

Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.

instruction set

The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.

Program Counter

Stack Pointer

Status Register

Constant Generator

General-Purpose Register

General-Purpose Register

General-Purpose Register

General-Purpose Register

General-Purpose Register

General-Purpose Register

General-Purpose Register

General-Purpose Register

General-Purpose Register

General-Purpose Register

General-Purpose Register

General-Purpose Register

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R4

R5

R6

R7

R8

R9

R10

R11

R12

R13

R14

R15

Table 1. Instruction Word Formats

Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 ------> R5

Single operands, destination only e.g., CALL R8 PC -- -->(TOS), R8----> PC

Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0

Table 2. Address Mode Descriptions

ADDRESS MODE S D SYNTAX EXAMPLE OPERATION

Register D
Indexed D D MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)-- --> M(6+R6)

Symbolic (PC relative) D D MOV EDE,TONI M(EDE) ----> M(TONI)

Absolute D D MOV &MEM,&TCDAT M(MEM) -- --> M(TCDAT)

Indirect D MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) -- --> M(Tab+R6)

Indirect

autoincrement

Immediate D MOV #X,TONI MOV #45,TONI #45 ----> M(TONI)

NOTE: S = source D = destination

D

D MOV @Rn+,Rm MOV @R10+,R11

MOV Rs,Rd MOV R10,R11 R10 ----> R11

M(R10) -- --> R11
R10 + 2----> R10

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MSP430F42xA

MIXED SIGNAL MICROCONTROLLER

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operating modes

The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

D Active mode (AM)

-- All clocks are active.

D Low-power mode 0 (LPM0)

-- CPU is disabled.
ACLK and SMCLK remain active, MCLK is available to modules.
FLL+ loop control remains active.

D Low-power mode 1 (LPM1)

-- CPU is disabled.
ACLK and SMCLK remain active, MCLK is available to modules.
FLL+ loop control is disabled.

D Low-power mode 2 (LPM2)

-- CPU is disabled.
MCLK, FLL+ loop control, and DCOCLK are disabled.
DCO dc generator remains enabled.
ACLK remains active.

D Low-power mode 3 (LPM3)

-- CPU is disabled.
MCLK, FLL+ loop control, and DCOCLK are disabled.
DCO dc generator is disabled.
ACLK remains active.

D Low-power mode 4 (LPM4)

-- CPU is disabled.
ACLK is disabled.
MCLK, FLL+ loop control, and DCOCLK are disabled.
DCO dc generator is disabled.
Crystal oscillator is stopped.

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MSP430F42xA
MIXED SIGNAL MICROCONTROLLER

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interrupt vector addresses

The interrupt vectors andthe power-upstarting address are located in the address range of0FFFFh to0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY

Power-up

External reset

Watchdog

Flash memory

PC out-of-range (see Note 4)

NMI

Oscillator fault

Flash memory access violation

SD16

Watchdog timer WDTIFG Maskable 0FFF4h 10

USART0 receive URXIFG0 Maskable 0FFF2h 9

USART0 transmit UTXIFG0 Maskable 0FFF0h 8

Timer_A3 TACCR0 CCIFG (see Note 2) Maskable 0FFECh 6

Timer_A3

I/O port P1 (eight flags)

I/O port P2 (eight flags)

Basic Timer1 BTIFG Maskable 0FFE0h 0, lowest

NOTES: 1. Multiple source flags

2. Interrupt flags are located in the module.

3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt-enable cannot.

4. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or
from within unused address ranges (from 0600h to 0BFFh).

NMIIFG (see Notes 1 and 3)

OFIFG (see Notes 1 and 3)

ACCVIFG (see Notes 1 and 3)

SD16CCTLx SD16OVIFG,

CCIFGs, and TACTL TAIFG

WDTIFG

KEYV

(see Note 1)

SD16CCTLx SD16IFG

(see Notes 1 and 2)

TACCR1 and TACCR2

(see Notes 1 and 2)

P1IFG.0toP1IFG.7
(see Notes 1 and 2)

P2IFG.0toP2IFG.7
(see Notes 1 and 2)

Reset 0FFFEh 15, highest

(Non)maskable
(Non)maskable
(Non)maskable

Maskable 0FFF8h 12

Maskable 0FFEAh 5

Maskable 0FFE8h 4

Maskable 0FFE2h 1

0FFFCh 14

0FFFAh 13

0FFF6h 11

0FFEEh 7

0FFE6h 3

0FFE4h 2

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MIXED SIGNAL MICROCONTROLLER

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special function registers

Most interruptand module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple software access
is provided with this arrangement.

interrupt enable 1 and 2

Address

0h URXIE0 ACCVIE NMIIE

7654 0

UTXIE0 OFIE WDTIE

rw–0 rw–0 rw–0

rw–0 rw–0 rw–0

32 1

WDTIE: Watchdog timer interruptenable. Inactive if watchdog modeis selected. Active if watchdogtimer

is configured in interval timer mode.

OFIE: Oscillator fault interrupt enable
NMIIE: Nonmaskable interrupt enable
ACCVIE: Flash access violation interrupt enable
URXIE0: USART0: UART and SPI receive-interrupt enable
UTXIE0: USART0: UART and SPI transmit-interrupt enable

Address

1h BTIE

BTIE: Basic Timer1 interrupt enable

7654 0321

rw-0

interrupt flag register 1 and 2

Address

02h URXIFG0 NMIIFG

7654 0

UTXIFG0 OFIFG WDTIFG

rw–1 rw–0

rw–0 rw–1 rw–(0)

32 1

WDTIFG: Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on V

power up or a reset condition at the RST/NMI pin in reset mode.

OFIFG: Flag set on oscillator fault
NMIIFG: Set via RST

/NMI pin
URXIFG0: USART0: UART and SPI receive flag
UTXIFG0: USART0: UART and SPI transmit flag

Address

3h BTIFG

BTIFG: Basic Timer1 interrupt flag

7654 0321

rw-0

CC

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MSP430F42xA
MIXED SIGNAL MICROCONTROLLER

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module enable registers 1 and 2

Address

04h

7654 0

UTXE0

rw–0 rw–0

URXE0
USPIE0

URXE0: USART0: UART mode receive enable
UTXE0: USART0: UART mode transmit enable
USPIE0: USART0: SPI mode transmit and receive enable

Address

05h

Legend: rw--0,1: Bit can be read and written. It Is reset or set by PUC.

7654 0321

rw--(0,1): Bit can be read and written. It Is reset or set by POR.

SFR Bit Not Present in Device.

memory organization

MSP430F423A MSP430F425A MSP430F427A

Memory

Interrupt vector
Code memory

Information memory Size 256 Byte

Boot memory Size 1kB

RAM Size 256 Byte

Peripherals 16 bit

Size
Flash
Flash

8bit

8-bit SFR

8KB
0FFFFh to 0FFE0h
0FFFFh to 0E000h

010FFh to 01000h

0FFFh to 0C00h

02FFh to 0200h

01FFh to 0100h

0FFh to 010h

0Fh to 00h

32 1

16KB
0FFFFh to 0FFE0h
0FFFFh to 0C000h

256 Byte

010FFh to 01000h

1kB

0FFFh to 0C00h

512 Byte

03FFh to 0200h

01FFh to 0100h

0FFh to 010h

0Fh to 00h

0FFFFh to 0FFE0h

0FFFFh to 08000h

256 Byte

010FFh to 01000h

0FFFh to 0C00h

05FFh to 0200h

01FFh to 0100h

0FFh to 010h

0Fh to 00h

32KB

1kB

1KB

bootstrap loader (BSL)

The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSLand itsimplementation, see the application report Features of the MSP430
Bootstrap Loader, literature number SLAA089.

BSL FUNCTION PM PACKAGE PINS

Data transmit 53 - P1.0

Data receive 52 - P1.1

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MSP430F42xA

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MIXED SIGNAL MICROCONTROLLER

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flash memory

The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU c an perform single-byteand single-wordwrites tothe flash memory.Features ofthe flash memory include:

D Flash memory has n segments of main memory and two segments of information memory (A and B) of

128 bytes each. Each segment in main memory is 512 bytes in size.

D Segments 0 to n may be erased in one step, or each segment may be individually erased.

D Segments A and B can be erased individually, or as a group with segments 0 to n.

Segments A and B are also called information memory.

D New devices may have some bytes programmed in the information memory (needed for test during

manufacturing). The user should perform an erase of the information memory prior to the first use.

8KB

0FFFFh

0FE00h

0FDFFh

0FC00h
0FBFFh

0FA00h
0F9FFh

0E400h

0E3FFh

0E200h

0E1FFh

0E000h
010FFh

01080h

0107Fh

01000h

16KB

0FFFFh

0FE00h
0FDFFh

0FC00h
0FBFFh

0FA00h
0F9FFh

0C400h

0C3FFh

0C200h
0C1FFh

0C000h

010FFh

01080h
0107Fh

01000h

B

32

0FFFFh

0FE00h

0FDFFh

0FC00h

0FBFFh

0FA00h
0F9FFh

08400h

083FFh

08200h

081FFh

08000h

010FFh

01080h

0107Fh

01000h

Segment 0

With Interrupt Vectors

Segment 1

Segment 2

Main Memory

Segment n--1

Segment n

Segment A

Information Memory

Segment B

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peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide, literature number
SLAU056.

oscillator and system clock

The clock system in the MSP430F42xA family of devices is supported by the FLL+ module, which includes
support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO), and a
high-frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low
system cost and low power consumption. The FLL+ features digital frequency locked loop (FLL) hardware that,
in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch
crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 μs. The
FLL+ module provides the following clock signals:

D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal.
D Main clock (MCLK), the system clock used by the CPU.
D Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules.
D ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.

brownout, supply voltage supervisor (SVS)

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The SVS circuitry detects if the supply voltage drops below a user-selectable level and supports
both supply-voltage supervision (the device is automatically reset) and supply-voltage monitoring (SVM) (the
device is not automatically reset).

The CPU begins code execution after the brownout circuit releases the device reset. However, V
have ramped to V
reaches V

CC(min)

CC(min)

. If desired, the SVS circuit can be used to determine when VCCreaches V

at that time. The user must ensure the default FLL+ settings are not changed until V

CC(min)

digital I/O

There are two 8-bit I/O ports implemented—ports P1 and P2 (only six P2 I/O signals are available on external
pins):

D All individual I/O bits are independently programmable.
D Any combination of input, output, and interrupt conditions is possible.
D Edge-selectable interrupt input capability for all the eight bits of port P1 and six bits of P2.
D Read/write access to port-control registers is supported by all instructions.

NOTE:

Six bits of port P2 (P2.0 to P2.5) are available on external pins, but all control and data bits for port
P2 are implemented.

Basic Timer1

CC

.

may not

CC

The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and
clock for the LCD module.

LCD drive

The LCD driver generates the segment and common signals required to drive an LCD display. The LCD
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.

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MSP430F42xA

A

MIXED SIGNAL MICROCONTROLLER

SLAS587 -- FEBRUARY 2008

watchdog timer (WDT+)

The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in anapplication, the module can be configured asan interval timer and can generate interruptsat selected time
intervals.

Timer_A3

Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.

TIMER_A3 SIGNAL CONNECTIONS

INPUT PIN

NUMBER

48 - P1.5 TACL K TACLK

48 - P1.5 TACLK INCLK

53 - P1.0 TA0 CCI0A

52 - P1.1 TA0 CCI0B

51 - P1.2 TA1 CCI1A

51 - P1.2 TA1 CCI1B

45 - P2.0 TA2 CCI2A

DEVICE INPUT

SIGNAL

ACLK ACLK

SMCLK SMCLK

DV

SS

DV

CC

DV

SS

DV

CC

ACLK (internal) CCI2B

DV

SS

DV

CC

MODULE INPUT

NAME

GND

V

CC

GND

V

CC

GND

V

CC

MODULE BLOCK

Timer N

CCR0 TA0

CCR1 TA1

CCR2 TA2

MODULE OUTPUT

SIGNAL

OUTPUT PIN

NUMBER

53 - P1.0

51 - P1.2

45 - P2.0

universal synchronous/asynchronous receive transmit (USART)

The MSP430F42xA devices have one hardware USART peripheral module (USART0) that is used for serial
data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART
communication protocols, using double-buffered transmit and receive channels.

hardware multiplier

The multiplication operation is supported by a dedicated peripheral module. The module performs 16×16,
16×8, 8×16, and 8×8 bit operations. The module is capable of supporting signed and unsigned multiplication,
as well as signed and unsigned multiply and accumulateoperations. Theresult of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.

SD16

The SD16 moduleintegrates three independent16-bit sigma-delta A/Dconverters, internal temperaturesensor,
and built-in voltage reference. Each channel is designed with a fully differential analog input pair and
programmable gain amplifier input stage.

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