Texas Instruments MSP430F4152IPM, MSP430F4132IRGZ, MSP430F4152IRGZ, MSP430F4132IPM User Manual

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

D Low Supply-Voltage Range, 1.8 V to 3.6 V D Ultralow Power Consumption

Active Mode: 220 Aat1MHz,2.2V Standby Mode: 0.9 A Off Mode (RAM Retention): 0.1 A

D Five Power-Saving Modes D Wake-Up From Standby Mode in Less

Than 6 s

-- Internal Very Low Power, Low-Frequency Oscillator

D 16-Bit RISC Architecture,

125-ns Instruction Cycle Time

D 16-Bit Timer_A With Three

Capture/Compare Registers

D 16-Bit Timer_A With Five Capture/Compare

Registers

D Two Universal Serial Communication

Interfaces (USCIs) USCI_A0

-- Enhanced UART Supporting Auto-Baudrate Detection

-- IrDA Encoder and Decoder

-- Synchronous SPI

USCI_B0

-- I 2 C

-- Synchronous SPI

D Supply Voltage Supervisor/Monitor With

Programmable Level Detection

D Integrated LCD Driver With Contrast

Control for Up to 144 Segments

D Basic Timer With Real Time Clock Feature D Brownout detector D On-Chip Comparator for Analog Signal

Compare Function or Slope A/D

D 10-Bit 200-ksps Analog-to-Digital (A/D)

Converter With Internal Reference, Sample-and-Hold, Autoscan, and Data Transfer Controller

D Serial Onboard Programming,

No External Programming Voltage Needed Programmable Code Protection by Security Fuse

D Bootstrap Loader D On-Chip Emulation Module D Family Members Include:

MSP430F4152: 16KB+256B Flash Memory

512B RAM

MSP430F4132: 8KB+256B Flash Memory

512B RAM

D Available in 64-Pin QFP Package and

48-Pin QFN Package (See Available Options)

D For Complete Module Descriptions, See

The MSP430x4xx Family User’s Guide, Literature Number SLAU056

description

The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generator that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 s.

The MSP430F41x2 is a microcontroller configuration with two 16-bit timers, a basic timer with a real--time clock, a 10-bit A/D converter, a versatile analog comparator, two universal serial communication interfaces, up to 48 I/O pins, and a liquid crystal display driver.

Typical applications for this device include analog and digital sensor systems, remote controls, thermostats, digital timers, hand-held meters, etc.

This integrated circuit can be damaged by ESD. Texas Instrum ents recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. These devices have limited built-in ESD protection.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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MSP430F41x2 MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

AVAILABLE OPTIONS

-- 4 0 Cto85C

†

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.

‡

Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

PLASTIC 64-PIN QFP (PM) PLASTIC 48-PIN QFN (RGZ)

MSP430F4152IPM MSP430F4132IPM

PACKAGED DEVICES

DEVELOPMENT TOOL SUPPORT

All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging and programming through easy to use development tools. Recommended hardware options include the following:

D Debugging and Programming Interface

-- MSP-FET430UIF (USB)

-- MSP-FET430PIF (Parallel Port)

D Debugging and Programming Interface with Target Board

†

‡

MSP430F4152IRGZ MSP430F4132IRGZ

-- MSP-FET430U64A (PM package)

D Production Programmer

-- MSP-GANG430

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

pin designation, MSP430F41x2IPM (QFP)

P6.1/UCB0SOMI/UCB0SCL

P6.2/UCB0SIMO/UCB0SDA

P6.3/UCB0STE/UCA0CLK/A3/CA5/Ve

P6.4/UCB0CLK/UCA0STE/A4/CA6/Ve

P6.5/UCA0RXD/UCA0SOMI/A5

P6.6/UCA0TXD/UCA0SIMO/A6

P6.7/A7/CA7/SVSIN P4.7/ADC10CLK/S0

REF-/VREF-

REF+/VREF+

XIN

XOUT

P4.6/S1 P4.5/S2 P4.4/S3 P4.3/S4

1 2 3 4 5 6 7

8 9 10

11 12 13 14 15 16

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

P6.0/TA1.2/A2/CA4

P7.5/TA1.3/A1/CA3

64 63

62 61 60 59 58 57 56 55 54 53 52 51 50 49

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

RST/NMI/SBWTDIO

P7.4/TA1.4/A0/CA2

TEST/SBWTCLK

P7.3/TCK/S35

64-pin

PM PACKAGE

(TOP VIEW)

P7.2/TMS/S34

P7.1/TDI/TCLK/S33

P7.0/TDO/TDI/S32

P1.0/TA0.0/S31

P1.1/TA0.0/MCLK/S30

P1.2/TA0.1/S29

P1.3/TA1.0/SVSOUT/S28

P1.4/TA1.0/S27

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

MSP430F41x2

P1.5/TA0CLK/CAOUT/S26 P1.6/ACLK/CA0 P1.7/TA0CLK/CAOUT/CA1 P7.6/TA0.2/S25 P5.0/TA1.1/S24 R33/LCDCAP P5.1/R23 P5.2/R13/LCDREF P5.3/R03 P5.4/COM3 P5.5/COM2 P5.6/COM1 P5.7/COM0 P3.0/TA1.2/S23 P3.1/TA1.3/S22 P3.2/TA1.4/S21

P4.2/S5

P4.1/S6

P4.0/S7

P2.7/S8

P2.6/S9

P2.5/S10

P2.4/S11

P2.3/TA1.4/S12

P2.2/TA1.3/S13

P2.1/TA1.2/S14

P2.0/TA1.1/S15

P3.7/S16

P3.6/S17

P3.5/S18

P3.4/CAOUT/S19

P3.3/TA0.0/TA1CLK/S20

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MSP430F41x2 MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

pin designation, MSP430F41x2IRGZ (QFN)

P6.0/TA1.2/A2/CA4

48 47 46 45 44 43 42 41 40 39 38 37

XIN

13 14 15 16 17 18 19 20 21 22 23 24

RGZ PACKAGE

P6.1

P6.2

XOUT

P6.7/A7/CA7/SVSIN

P4.7/ADC10CLK/S0

P4.6/S1

P4.5/S2

P4.4/S3

P4.3/S4

†

TEST/SBWTCLK

P7.5/TA1.3/A1/CA3

P7.4/TA1.4/A0/CA2

48-pin

(TOP VIEW)

RST/NMI/SBWTDIO

P7.3/TCK/S35

P7.2/TMS/S34

P7.1/TDI/TCLK/S33

P7.0/TDO/TDI/S32

P1.0/TA0.0/S31

P1.1/TA0.0/MCLK/S30

P1.5/TA0CLK/CAOUT/S26

P1.6/ACLK/CA0

P1.7/TA0CLK/CAOUT/CA1

R33/LCDCAP

P5.1/R23

P5.2/R13/LCDREF

P5.3/R03

P5.4/COM3

P5.5/COM2

P5.6/COM1

P5.7/COM0

P4.2/S5

P4.1/S6

P4.0/S7

P2.7/S8

P2.6/S9

P2.5/S10

P2.4/S11

P2.3/TA1.4/S12

P2.2/TA1.3/S13

†

“Not available” pins in the 48-pin package should be initialized to output direction.

P2.1/TA1.2/S14

P2.0/TA1.1/S15

P3.4/CAOUT/S19

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functional block diagram

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

XIN XOUT

Oscillators

FLL+

VLO

MCLK

CPU 64kB

incl. 16

Registers

EEM

JTAG

Interface

S p y --B i --

Wire

ACLK

SMCLK

DVCC DVSS

Flash

16kB

8kB

MAB

MDB

Brownout

Protection

SVS, SVM

RST/NMI

RAM

512B 512B

LCD_A

144

Segments

1,2,3,4

Mux

AVC C AVSS P1.x/P2.x

ADC10

10--bit

8 Channels

Autoscan

DTC

Comparator

_A+

USCI A0

UART/

LIN,

IrDA, SPI

USCI B 0 SPI, I2C

Watchdog

WDT+

15--Bit

capability

Timer _A3

Registers

Ports

P1/P2

2x8 I/O

Interrupt

3CC

NOTE: The USCI A0 and USCI B0 cannot be used in the 48-pin package options (RGZ).

2x8

P3.x/P4.x

2x8

Ports

P3/P4

2x8 I/O

Timer _A5

5CC

Registers

P5.x/P6.x

2x8

Ports

P5/P6

2x8 I/O

Basic

Timer &

Real--

Time

Clock

P7.x

1x7

Port

1x7 I/O

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MSP430F41x2

I/ODESCRIPTIO

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

TERMINAL

NO.

NAME

P1.0/TA0.0/S31 53 37 I/O

P1.1/TA0.0/ MCLK/S30

P1.2/TA0.1/S29 51 -- I/O

P1.3/TA1.0/ SVSOUT/S28

P1.4/TA1.0/S27 49 -- I/O

P1.5/TA0CLK/ CAOUT/S26

P1.6/ACLK/CA0 47 34 I/O

P1.7/TA0CLK CAOUT/CA1

P2.0/TA1.1/S15 27 23 I/O

P2.1/TA1.2/S14 26 22 I/O

P2.2/TA1.3/S13 25 21 I/O

P2.3/TA1.4/S12 24 20 I/O

P2.4/S11 23 19 I/O

P2.5/S10 22 18 I/O

P2.6/S9 21 17 I/O

P2.7/S8 20 16 I/O

PIN48PIN

52 36 I/O

50 -- I/O

48 35 I/O

46 33 I/O

General-purpose digital I/O pin Timer0_A3, capture: CCI0A input, compare: Out0 output LCD segment output

General-purpose digital I/O pin Timer0_A3, capture: CCI0B input MCLK signal output LCD segment output

General-purpose digital I/O pin Timer0_A3, capture: CCI1A input, compare: Out1 output LCD segment output

General-purpose digital I/O pin Timer1_A5, capture: CCI0B input SVS comparator output LCD segment output

General-purpose digital I/O pin/ Timer1_A5, capture: CCI0A input, compare: Out0 output LCD segment output

General-purpose digital I/O pin Timer0_A3, clock signal TACLK input Comparator_A output LCD segment output

General-purpose digital I/O pin Comparator_A input 0 ACLK signal output

General-purpose digital I/O pin Timer0_A3, clock signal TACLK input Comparator_A output Comparator_A input 1

General-purpose digital I/O pin Timer1_A5, compare: Out1 Output LCD segment output

General-purpose digital I/O pin Timer1_A5, compare: Out2 Output LCD segment output

General-purpose digital I/O pin Timer1_A5, compare: Out3 Output LCD segment output

General-purpose digital I/O pin Timer1_A5, compare: Out4 output LCD segment output

General-purpose digital I/O pin LCD segment output

Terminal Functions

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TERMINAL

I/ODESCRIPTIO

NO.

NAME

P3.0/TA1.2/S23 35 -- I/O

P3.1/TA1.3/S22 34 -- I/O

P3.2/TA1.4/S21 33 -- I/O

P3.3/TA0.0/ TA1CLK/S20

P3.4/CAOUT/S19 31 24 I/O

P3.5/S18 30 -- I/O

P3.6/S17 29 -- I/O

P3.7/S16 28 -- I/O

P4.0/S7 19 15 I/O

P4.1/S6 18 14 I/O

P4.2/S5 17 13 I/O

P4.3/S4 16 12 I/O

P4.4/S3 15 11 I/O

P4.5/S2 14 10 I/O

P4.6/S1 13 9 I/O

P4.7/ADC10CLK/ S0

P5.0/TA1.1/S24 44 -- I/O

LCDCAP/R33 43 32 I/O

P5.1/R23 42 31 I/O

P5.2/LCDREF/ R13

PIN48PIN

32 -- I/O

12 8 I/O

41 30 I/O

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

Terminal Functions (continued)

General-purpose digital I/O pin Timer1_A5, capture: CCI2A input, compare: Out2 output LCD segment output

General-purpose digital I/O pin Timer1_A5, capture: CCI3A input, compare: Out3 output LCD segment output

General-purpose digital I/O pin Timer1_A5, capture: CCI4A input, compare: Out4 output LCD segment output

General-purpose digital I/O pin Timer0_A3, compare: Out0 output Timer1_A5, clock signal TACLK input LCD segment output

General-purpose digital I/O pin Comparator_A output LCD segment output

General-purpose digital I/O pin LCD segment output

General-purpose digital I/O pin ADC10, conversion clock LCD segment output

General-purpose digital I/O pin Timer1_A5, capture: CCI1A input, compare: Out1 output LCD segment output

Capacitor connection for LCD charge pump input port of the most positive analog LCD level (V4)

General-purpose digital I/O pin input port of the second most positive analog LCD level (V3)

General-purpose digital I/O pin External LCD reference voltage input input port of the third most positive analog LCD level (V3 or V2)

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MSP430F41x2

I/ODESCRIPTIO

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

Terminal Functions (continued)

TERMINAL

NO.

NAME

P5.3/R03 40 29 I/O

P5.4/COM3 39 28 I/O

P5.5/COM2 38 27 I/O

P5.6/COM1 37 26 I/O

P5.7/COM0 36 25 I/O

P6.0/TA1.2/A2†/ CA4

P6.1/ UCB0SOMI UCB0SCL

P6.2/ UCB0SIMO UCB0SDA

†

P6.3/UCB0STE/ UCA0CLK/A3/ CA5/V

eref--/Vref--

P6.4/UCB0CLK/ UCA0STE/A4/ CA6/V

eref+/Vref+

P6.5/UCA0RXD/ UCA0SOMI/A5

P6.6/UCA0TXD/ UCA0SIMO/A6

P6.7/A7/CA7/ SVSIN

P7.0/TDO/TDI/ S32

P7.1/TDI/TCLK/ S33

P7.2/TMS/S34 56 40 I/O General-purpose digital I/O pin

†

64-pin package devices only

PIN48PIN

General-purpose digital I/O pin input port of the fourth most positive analog LCD level (V1)

General-purpose digital I/O pin common output, COM0--3 are used for LCD backplanes

General-purpose digital I/O pin

63 47 I/O

Timer1_A5, compare: Out2 output ADC10 analog input A2

†

Comparator_A input 4

1 1 I/O

2 2 I/O

General-purpose digital I/O pin USCI B0 slave out/master in in SPI mode, SCL I

General-purpose digital I/O pin USCI B0 slave in/master out in SPI mode, SDA I

General-purpose digital I/O pin

3 -- I/O

USCI B0 slave transmit enable/USCI A0 clock input/output ADC10 analog input A3 / negative reference Comparator_A input 5

General-purpose digital I/O pin

4 -- I/O

USCI B0 clock input/output, USCI A0 slave transmit enable ADC10 analog input A4/ positive reference Comparator_A input 6

General-purpose digital I/O pin

5 -- I/O

USCI A0 receive data input in UART mode, slave data out/master in in SPI mode ADC10 analog input A5

General-purpose digital I/O pin

6 -- I/O

USCI A0 transmit data output in UART mode, slave data i n/master out SPI mode ADC10 analog input A6

General-purpose digital I/O pin

11 7 I/O

ADC10 analog input A7 Comparator_A input 7 SVS input

54 38 I/O General-purpose digital I/O pin

JTAG test data output terminal or test data input in programming an test LCD segment output

55 39 I/O General-purpose digital I/O pin

JTAG test data input or test clock input in programming an test LCD segment output

JTAG test mode select, input terminal for device programming and test LCD segment output

C clock in I2C mode

CdatainI2C mode

†

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MSP430F41x2

I/ODESCRIPTIO

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

Terminal Functions (continued)

TERMINAL

NO.

NAME

P7.3/TCK/S35 57 41 I/O General-purpose digital I/O pin

P7.4/TA1.4/ A0/CA2

P7.5/TA1.3/ A1/CA3

P7.6/TA0.2/S25 45 -- I/O

XOUT 9 5 O Output port for crystal oscillator XT1. Standard or watch crystals can be connected.

XIN 8 4 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.

RST/NMI/ SBWTDIO

TEST/SBWTCLK 59 43 I Selects test mode for JTAG pins on Port7. The device protection fuse is connected to TEST.

Thermal Pad NA NA NA QFN package pad (RGZ package only). Connection to DVSSis recommended.

PIN48PIN

Test clock input for device programming and test LCD segment output

General-purpose digital I/O pin

60 44 I/O

61 45 I/O

64 48 Analog supply voltage, positive terminal

62 46 Analog supply voltage, negative terminal

7 3 Digital supply voltage, positive terminal. Supplies all digital parts.

10 6 Digital supply voltage, negative terminal. Supplies all digital parts.

58 42 I Reset or nonmaskable interrupt input

Timer1_A5, capture: CCI4B input, compare: Out4 output ADC10 analog input A0 Comparator_A input 2

General-purpose digital I/O pin Timer1_A5, capture: CCI3B input, compare: Out3 output ADC10 analog input A1 Comparator_A input 3

General-purpose digital I/O pin Timer0_A3, capture: CCI2A input, compare: Out2 output LCD segment output

Spy-Bi-Wire test data input/output during programming and test

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MSP430F41x2 MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

short-form description

CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses and can be handled with all instructions.

instruction set

The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 1 shows examples of the three types of instruction formats; Table 2 shows the address modes.

Program Counter

Stack Pointer

Status Register

Constant Generator

General-Purpose Register

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R10

R11

R12

R13

R14

R15

Table 1. Instruction Word Formats

Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 ------> R5

Single operands, destination only e.g., CALL R8 PC ---->(TOS), R8----> PC

Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0

Table 2. Address Mode Descriptions

ADDRESS MODE S D SYNTAX EXAMPLE OPERATION

Indexed F F MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) —> M(6+R6)

Symbolic (PC relative) F F MOV EDE,TONI M(EDE) —> M(TONI)

Absolute F F MOV&MEM,&TCDAT M(MEM) —> M(TCDAT)

Indirect F MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) —> M(Tab+R6)

Indirect

autoincrement

Immediate F MOV #X,TONI MOV #45,TONI #45 —> M(TONI)

NOTE: S = source, D = destination

F MOV @Rn+,Rm MOV @R10+,R11

MOV Rs,Rd MOV R10,R11 R10 —> R11

M(R10) —> R11

R10+2—>R10

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

operating modes

The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

D Active mode (AM)

-- All clocks are active

D Low-power mode 0 (LPM0)

-- CPU is disabled

-- ACLK and SMCLK remain active

-- FLL+ loop control remains active

D Low-power mode 1 (LPM1)

-- CPU is disabled

-- ACLK and SMCLK remain active

-- FLL+ loop control is disabled

D Low-power mode 2 (LPM2)

-- CPU is disabled

-- MCLK, FLL+ loop control, and DCOCLK are disabled

-- DCO’s dc generator remains enabled

-- ACLK remains active

D Low-power mode 3 (LPM3)

-- CPU is disabled

-- MCLK, FLL+ loop control, and DCOCLK are disabled

-- DCO’s dc generator is disabled

-- ACLK remains active

D Low-power mode 4 (LPM4)

-- CPU is disabled

-- ACLK is disabled

-- MCLK, FLL+ loop control, and DCOCLK are disabled

-- DCO’s dc generator is disabled

-- Crystal oscillator is stopped

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MSP430F41x2 MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the address range 0xFFFF to 0xFFC0. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

If the reset vector (located at address 0xFFFE) contains 0xFFFF (e.g., flash is not programmed), the CPU goes into LPM4 immediately after power-up.

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT

Power-Up

External Reset

Watchdog

PC Out--of --Range (see Note 4)

Flash Memory Access Violation

NOTES: 1. Multiple source flags

Flash Memory

NMI

Oscillator Fault

Timer_A5 TA1CCR0 CCIFG0 (see Note 2) Maskable 0xFFFA 13

Timer_A5

Comparator_A+ CAIFG Maskable 0xFFF6 11

Watchdog Timer+ WDTIFG Maskable 0xFFF4 10

USCI_A0/B0 Receive

USCI_A0/B0 Transmit

ADC10 ADC10IFG (see Note 2) Maskable 0xFFEE 7

Timer_A3 TACCR0 CCIFG0 (see Note 2) Maskable 0xFFEC 6

Timer_A3

I/O Port P1 (Eight Flags) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) Maskable 0xFFE8 4

I/O Port P2 (Eight Flags) P2IFG.0 to P2IFG.7 (see Notes 1 and 2) Maskable 0xFFE2 1

Basic Timer1/RTC BTIFG Maskable 0xFFE0 0, lowest

2. Interrupt flags are located in the module.

3. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh). (Non)maskable: the individual interrupt -enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

4. Access and key violations, KEYV and ACCVIFG.

UCB0STAT UCALIFG, UCNACKIFG, UCSTTIFG,

NMIIFG (see Notes 1 and 3)

OFIFG (see Notes 1 and 3)

ACCVIFG (see Notes 1, 2, and 4)

TA1CCR1 to TACCR4 CCIFGs, and TAIFG (see Notes 1 and 2)

UCA0RXIFG (see Note 1),

UCB0RXIFG (SPI mode), or

UCA0TXIFG (see Note 1),

UCB0TXIFG (SPI mode), or

UCB0RXIFG and UCB0TXIFG (I2C mode)

TACCR1 CCIFG1 and TACCR2 CCIFG2,

TAIFG (see Notes 1 and 2)

PORIFG RSTIFG WDTIFG

KEYV

(see Note 1)

UCSTPIFG (I2C mode)

(see Note 1)

Reset 0xFFFE 15, highest

(Non)maskable (Non)maskable (Non)maskable

Maskable 0xFFF8 12

Maskable 0xFFF2 9

Maskable 0xFFF0 8

Maskable 0xFFEA 5

WORD

ADDRESS

0xFFFC 14

0xFFE6 3

0xFFE4 2

PRIORITY

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

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special function registers

Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access.

interrupt enable 1 and 2

Address76543210

00h

WDTIE Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog

timer is configured in interval timer mode.

OFIE Oscillator fault enable

NMIIE (Non)maskable interrupt enable

ACCVIE Flash access violation interrupt enable

Address76543210

01h

BTIE

rw--0 rw--0 rw--0 rw--0 rw --0

ACCVIE NMIIE OFIE WDTIE

rw--0 rw--0 rw--0 rw --0

UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE

UCA0RXIE USCI_A0 receive interrupt enable

UCA0TXIE USCI_A0 transmit interrupt enable

UCB0RXIE USCI_B0 receive interrupt enable

UCB0TXIE USCI_B0 transmit interrupt enable

BTIE Basic timer interrupt enable

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interrupt flag register 1 and 2

Address76543210

02h

WDTIFG Set on watchdog timer overflow (in watchdog mode) or security key violation.

Reset on V

power-up or a reset condition at RST/NMI pin in reset mode.

OFIFG Flag set on oscillator fault

RSTIFG External reset interrupt flag. Set on a reset condition at RST

on V

power-up.

PORIFG Power-on interrupt flag. Set on V

NMIIFG Set via RST

Address76543210

03h

BTIFG

rw--0 rw--1 rw--0 rw--1 rw --0

/NMI-pin

NMIIFG RSTIFG PORIFG OFIFG WDTIFG

rw--0 rw-- (0) rw--(1) rw--1 rw--(0)

/NMI pin in reset mode. Reset

power--up.

UCB0

TXIFG

UCB0

RXIFG

UCA0

TXIFG

UCA0

RXIFG

UCA0RXIFG USCI_A0 receive interrupt flag

UCA0TXIFG USCI_A0 transmit interrupt flag

UCB0RXIFG USCI_B0 receive interrupt flag

UCB0TXIFG USCI_B0 transmit interrupt flag

BTIFG Basic Timer1 interrupt flag

Legend rw:

rw-0,1: rw-(0,1):

Bit can be read and written. Bit can be read and written. It is Reset or set by PUC. Bit can be read and written. It is Reset or set by POR.

SFR bit is not present in device

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MSP430F41x2

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memory organization

MSP430F4152 MSP430F4132

Memory Main: interrupt vector Main: code memory

Information memory Size

Boot memory Size

RAM Size 512B

Peripherals 16-bit

bootstrap loader (BSL)

The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the MSP430 Memory Programming User’s Guide, literature number SLAU265.

Size Flash Flash

Flash

ROM

8-bit

8-bit SFR

16KB 0FFFFh -- 0FFE0h 0FFFFh -- 0C000h

256 Byte

010FFh -- 01000h

1KB

0FFFh -- 0C00h

03FFh -- 0200h

01FFh -- 0100h

0FFh -- 010h

0Fh -- 00h

8KB 0FFFFh -- 0FFE0h 0FFFFh -- 0E000h

256 Byte

010FFh -- 01000h

1KB

0FFFh -- 0C00h

512B

03FFh -- 0200h

01FFh -- 0100h

0FFh -- 010h

0Fh -- 00h

BSL FUNCTION PM PACKAGE PINS RGZ PACKAGE PINS

Data transmit 53 -- P1.0 37 -- P1.0

Data receive 52 -- P1.1 36 -- P1.1

flash memory (Flash)

The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

D Flash memory has n segments of main memory and four segments of information memory (A to D) of

64 bytes each. Each segment in main memory is 512 bytes in size.

D Segments 0 to n may be erased in one step, or each segment may be individually erased.

D Segments A to D can be erased individually, or as a group with segments 0 to n.

Segments A to D are also called information memory.

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MSP430F41x2 MIXED SIGNAL MICROCONTROLLER

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peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide, literature number SLAU056.

oscillator and system clock

The clock system in the MSP430F41x2 is supported by the FLL+ module that includes support for a 32768-Hz watch crystal oscillator, an internal very low-power low--frequency oscillator, an internal digitally-controlled oscillator (DCO), and an 8-MHz high-frequency crystal oscillator (XT1). The FLL+ clock module is designed to meet the requirements of both low system cost and low power consumption. The FLL+ features a digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator,stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 s. The FLL+ module provides the following clock signals:

D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, or a very

low-power LF oscillator

D Main clock (MCLK), the system clock used by the CPU D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules D ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8

brownout, supply voltage supervisor

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset).

The CPU begins code execution after the brownout circuit releases the device reset. However, V have ramped to V reaches V

CC(min)

. If desired, the SVS circuit can be used to determine when VCCreaches V

at that time. The user must insure the default FLL+ settings are not changed until V

CC(min)

digital I/O

There are seven 8-bit I/O ports implemented—ports P1 through P7. Port P7 is a 7-bit I/O port.

D All individual I/O bits are independently programmable. D Any combination of input, output, and interrupt conditions is possible. D Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2. D Read/write access to port-control registers is supported by all instructions.

may not

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MSP430F41x2

DEVICEINPUT

MODUL

TimerNA

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

watchdog timer (WDT+)

The primary function of the WDT+ module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.

Basic Timer1 and Real-Time Clock (RTC)

The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. The Basic Timer1 is extended to provide an integrated real-time clock (RTC). An internal calendar compensates for month with less than 31 days and includes leap year correction.

LCD_A driver with regulated charge pump

The LCD_A driver generates the segment and common signals required to drive an LCD display. The LCD_A controller has dedicated data memory to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2--MUX, 3--MUX, and 4--MUX LCDs are supported by this peripheral. The module can provide a LCD voltage independent of the supply voltage via an integrated charge pump. Furthermore it is possible to control the level of the LCD voltage and thus contrast in software.

Timer0_A3

Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

TIMER_A3 SIGNAL CONNECTIONS

INPUT PIN NUMBER

PM RGZ

48 -- P1.5

46 -- P1.7

48 -- P1.5 35 -- P1.5 TA0CLK TACLK

53 -- P1.0 37 -- P1.0 TA0.0 CCI0A 53 -- P1.0 37 -- P1.0

52 -- P1.1 36 -- P1.1 TA0.0 CCI0B

51 -- P1.2 -- TA0 . 1 CCI1A 51 -- P1.2

45 -- P7.6 -- TA0 . 2 CCI2A 45 -- P7.6 --

35 -- P1.5

33 -- P1.7

DEVICE INPUT MODULE MODULE

SIGNAL

TA0CLK TA C LK

ACLK ACLK

SMCLK SMCLK

CAOUT (internal) CCI1B

ACLK (internal) CCI2B

INPUT NAME

GND

BLOCK

Timer N

CCR0 TA0

CCR1 TA1

CCR2 TA2

MODULE

OUTPUT

SIGNAL

OUTPUT PIN NUMBER

PM RGZ

32 -- P3.3 --

ADC10 (internal) ADC10 (internal)

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MSP430F41x2

DEVICEINPUT

MODUL

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

Timer1_A5

Timer_A5 is a 16-bit timer/counter with five capture/compare registers. Timer_A5 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A5 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

TIMER_A5 SIGNAL CONNECTIONS

INPUT PIN NUMBER

PM RGZ

32 -- P3.3 -- TA1CLK TA C LK

32 -- P3.3 -- TA1CLK TACLK

49 -- P1.4 -- TA1 . 0 CCI0A 49 -- P1.4 --

50 -- P1.3 -- TA1 . 0 CCI0B

44 -- P5.0 -- TA1 . 1 CCI1A 44 -- P5.0 --

35 -- P3.0 -- TA1 . 2 CCI2A 35 -- P3.0 --

34 -- P3.1 -- TA1 . 3 CCI3A 34 -- P3.1 --

61 -- P7.5 45 -- P7.5 TA1.3 CCI3B

33 -- P3.2 -- TA1 . 4 CCI4A 33 -- P3.2 --

60 -- P7.4 44 -- P7.4 TA1.4 CCI4B

DEVICE INPUT MODULE MODULE

SIGNAL

ACLK ACLK

SMCLK SMCLK

CAOUT (internal) CCI1B

ACLK (internal) CCI2B

INPUT NAME

GND

BLOCK

Timer N

CCR0 TA0

CCR1 TA1

CCR2 TA2

CCR3 TA3

CCR4 TA4

MODULE

OUTPUT

SIGNAL

OUTPUT PIN NUMBER

PM RGZ

ADC10 (internal) ADC10 (internal)

27 -- P2.0 23 -- P2.0

ADC10 (internal) ADC10 (internal)

26 -- P2.1 22 -- P2.1

63 -- P6.0 47 -- P6.0

25 -- P2.2 21 -- P2.2

61 -- P7.5 45 -- P7.5

24 -- P2.3 20 -- P2.3

60 -- P7.4 44 -- P7.4

universal serial communication interface (USCI) (USCI_A0, USCI_B0)

The USCI module is used for serial data communication. The USCI module supports synchronous communication protocols like SPI (3 or 4 pin), I2C and asynchronous communication protocols like UART, enhanced UART with automatic baudrate detection (LIN), and IrDA.

USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.

USCI_B0 provides support for SPI (3 or 4 pin) and I2C.

Comparator_A+

The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals.

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MSP430F41x2

Timer0_A3Capture/compareregister2

TA0CCR2

0176h

Capture/compareregister

TA0CCR1

0174h

p/p

Capture/compareregister

TA1CCR2

0196h

Timer_Aregister

TA1

0190h

Capt

TA1CCTL

0186h

p/p

FlashFlashcontrol

FCTL3

012Ch

Flashcontrol2

FCTL2

012Ah

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

ADC10

The ADC10 module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator, and data transfer controller (DTC) for automatic conversion result handling, allowing ADC samples to be converted and stored without any CPU intervention.

peripheral file map

PERIPHERALS WITH W ORD ACCESS

Watchdog Watchdog timer control WDTCTL 0120h

Timer0_A3 Capture/compare register 2 TA0CCR2 0176h

Capture/compare register 1

Capture/compare register 0

Timer_A register TA0 R 0170h

Capture/compare control 2 TA0CCTL2 0166h

Capture/compare control 1 TA0CCTL1 0164h

Capture/compare control 0 TA0CCTL0 0162h

Timer_A control TA0 C T L 0160h

Timer_A interrupt vector TA0 I V 012Eh

Timer1_A5 Capture/compare register 4

Capture/compare register 3

ture/compare register 2

Capture/compare register 1

Capture/compare register 0

TA0CCR1

TA0CCR0

TA1CCR4

TA1CCR3

1CCR2

TA1CCR1

TA1CCR0

0174h

0172h

019A

0198

0196h

0194h

0192h

Capture/compare control 4

Capture/compare control 3

ure/compare contro

Capture/compare control 1

Capture/compare control 0

Timer

Timer_A interrupt vector

Flash Flash control 3 FCTL3 012Ch

Flash control 2

Flash control 1

ADC10 ADC data transfer start address

ADC memory

ADC control register 1

ADC control register 0

ADC analog enable 0

ADC analog enable 1

ADC data transfer control register 1

ADC data transfer control register 0

control

TA1CCTL4

TA1CCTL3

TA1CCTL1

TA1CCTL0

TA1CTL

TA1 I V

FCTL2

FCTL1

ADC10SA

ADC10MEM

ADC10CTL1

ADC10CTL0

ADC10AE0

ADC10AE1

ADC10DTC1

ADC10DTC0

018A

0188

0184h

0182h

0180h

011Eh

012Ah

0128h

01BCh

01B4h

01B2h

01B0h

004Ah

004Bh

0049h

0048h

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MSP430F41x2

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peripheral file map (continued)

PERIPHERALS WITH BYTE ACCESS

LCD_A LCD Voltage Control 1

LCD Voltage Control 0

LCD Voltage Port Control 1

LCD Voltage Port Control 0

LCD memory 20

LCD memory 16

LCD memory 15

LCD memory 1

LCD control and mode

USCI A0/B0

Comparator_A+

Brownout, SVS SVS control register (Reset by brownout signal) SVSCTL 056h

FLL+ Clock FLL+ Control 2

USCI A0 auto baud rate control UCA0ABCTL 0x005D

USCI A0 transmit buffer UCA0TXBUF 0x0067

USCI A0 receive buffer UCA0RXBUF 0x0066

USCI A0 status UCA0STAT 0x0065

USCI A0 modulation control UCA0MCTL 0x0064

USCI A0 baud rate control 1 UCA0BR1 0x0063

USCI A0 baud rate control 0 UCA0BR0 0x0062

USCI A0 control 1 UCA0CTL1 0x0061

USCI A0 control 0 UCA0CTL0 0x0060

USCI A0 IrDA receive control UCA0IRRCTL 0x005F

USCI A0 IrDA transmit control UCA0IRTCTL 0x005E

USCI B0 transmit buffer UCB0TXBUF 0x006F

USCI B0 receive buffer UCB0RXBUF 0x006E

USCI B0 status UCB0STAT 0x006D

USCI B0 I2C Interrupt enable UCB0CIE 0x006C

USCI B0 baud rate control 1 UCB0BR1 0x006B

USCI B0 baud rate control 0 UCB0BR0 0x006A

USCI B0 control 1 UCB0CTL1 0x0069

USCI B0 control 0 UCB0CTL0 0x0068

USCI B0 I2C slave address UCB0SA 0x011A

USCI B0 I2C own address UCB0OA 0x0118

Comparator_A port disable CAPD 05Bh

Comparator_A control2 CACTL2 05Ah

Comparator_A control1 CACTL1 059h

FLL+ Control 1

FLL+ Control 0 FLL_CTL0 053h

System clock frequency control SCFQCTL 052h

System clock frequency integrator SCFI1 051h

System clock frequency integrator SCFI0 050h

LCDAVCTL1

LCDAVCTL0

LCDAPCTL1

LCDAPCTL0

LCDM20

LCDM16

LCDM15

LCDM1

LCDACTL

FLL_CTL2

FLL_CTL1

0AFh

0AEh

0ADh

0ACh

0A4h

0A0h

09Fh

091h

090h

055h

054h

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peripheral file map (continued)

RTC (Basic Timer1)

Port P7

Port P6

Port P5

Port P4

Port P3

Port P2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

PERIPHERALS WITH BYTE ACCESS

Real Time Clock Year High Byte

Real Time Clock Year Low Byte

Real Time Clock Month

Real Time Clock Day of Month

Basic Timer1 Counter

Real Time Counter 4

(Real Time Clock Day of Week)

Real Time Counter 3

(Real Time Clock Hour)

Real Time Counter 2

(Real Time Clock Minute)

Real Time Counter 1

(Real Time Clock Second)

Real Time Clock Control

Basic Timer1 Control

Port P7 selection P7SEL 03Bh

Port P7 direction P7DIR 03Ah

Port P7 output P7OUT 039h

Port P7 input P7IN 038h

Port P6 selection P6SEL 037h

Port P6 direction P6DIR 036h

Port P6 output P6OUT 035h

Port P6 input P6IN 034h

Port P5 selection P5SEL 033h

Port P5 direction P5DIR 032h

Port P5 output P5OUT 031h

Port P5 input P5IN 030h

Port P4 selection P4SEL 01Fh

Port P4 direction P4DIR 01Eh

Port P4 output P4OUT 01Dh

Port P4 input P4IN 01Ch

Port P3 selection P3SEL 01Bh

Port P3 direction P3DIR 01Ah

Port P3 output P3OUT 019h

Port P3 input P3IN 018h

Port P2 selection P2SEL 02Eh

Port P2 interrupt enable P2IE 02Dh

Port P2 interrupt -edge select P2IES 02Ch

Port P2 interrupt flag P2IFG 02Bh

Port P2 direction P2DIR 02Ah

Port P2 output P2OUT 029h

Port P2 input P2IN 028h

RTCYEARH

RTCYEARL

RTCMON

RTCDAY

BTCNT2

BTCNT1

RTCNT4

(RTCDOW)

RTCNT3

(RTCHOUR)

RTCNT2

(RTCMIN)

RTCNT1

(RTCSEC)

RTCCTL

BTCTL

04Fh

04Eh

04Dh

04Ch

047h

046h

045h

044h

043h

042h

041h

040h

MSP430F41x2

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MSP430F41x2

SFR

int

tflag2IFG2003h

SFRinterruptenable2IE2001hS

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

peripheral file map (continued)

PERIPHERALS WITH BYTE ACCESS (CONTINUED)

Port P1

pecia

unc

Port P1 selection register P1SEL 026h

Port P1 interrupt enable P1IE 025h

Port P1 interrupt -edge select P1IES 024h

Port P1 interrupt flag P1IFG 023h

Port P1 direction P1DIR 022h

Port P1 output P1OUT 021h

Port P1 input P1IN 020h

ons

errup

SFR interrupt flag 1 IFG1 002h

SFR interrupt enable 2 IE2 001h

FR interrupt enable 1 IE1 000h

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MSP430F41x2

(seeNote1

)

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Voltage applied at VCCto V Voltage applied to any pin (see Note 1) --0.3 V to V

†

--0.3 V to 4.1 V......................................................

+0.3V.......................................

Diode current at any device terminal . 2mA......................................................

Storage temperature, T

: Unprogrammed device --55C to 150C................................

stg

Programmed device --55Cto85C....................................

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltages referenced to V

applied to the TEST pin when blowing the JTAG fuse.

The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is

SS.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage during program execution, VCC(AVCC=DVCC=VCC) 1.8 3.6 V

Supply voltage during flash memory programming, VCC(AVCC=DVCC=VCC) 2.2 3.6 V

Supply voltage, VSS(AVSS=DVSS=VSS) 0 0 V

Operating free-air temperature range, T

LFXT1 crystal frequency, f (see Note 1)

Processorfrequency (signal MCLK),

NOTES: 1. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.

(LFXT1)

(System)

LF selected, XTS_FLL = 0

XT1 selected, XTS_FLL = 1

Watch crystal 32.768 kHz

Ceramic resonator 0.45 6 MHz

Crystal 1 6 MHz

VCC=1.8V dc 4.15

VCC=3.0V dc 8

-- 4 0 85 C

MHz

System

8 MHz

4.15 MHz

(MHz)

Supply voltage range , MSP430F41x2, during program execution

1.8 Supply Voltage - V

2.2 3.0 3.6

Supply voltage range , MSP430F41x2, during flash memory programming

Figure 1. Frequency vs Supply Voltage

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MSP430F41x2

f=f

(MCLK

)

(SMCLK)

=1MHz

Low-powermode3(LPM3

)

(MCLK

)f(SMCLK)

0MHz,

ALCD_Aenabled,LCDCPEN=0

(

LCD(ACLK)

)

Low-powermode3(LPM3

)

(MCLK

)f(SMCLK)

0MHz,

2.2

ALCD_Aenabled,LCDCPEN=0

(

LCD(ACLK)

)

0Hz,SCG

0=1(seeNote2)

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted)

supply current into AVCC+DVCCexcluding external current

PARAMETER T

Active mode (see Note 1),

(AM)

(ACLK)

= 32768 Hz,

=1MHz,

XTS=0, SELM=(0,1)

(LPM0)

Low-power mode 0 (LPM0) (see Note 1) --40Cto85C

Low-power mode 2 (LPM2),

(LPM2)

(MCLK) =f(SMCLK) = 0 MHz,

f(ACLK) = 32768 Hz, SCG0 = 0 (see Note 2)

(LPM3)

(MCLK)=f(SMCLK)

= 32768 Hz, SCG0 = 1,

(ACLK)

Basic Timer1 enabled ,ACLK selected, LCD

enabled,LCDCPEN = 0

(static mode, f

=0MHz,

LCD=f(ACLK)

(see Notes 2 and 3)

(LPM3)

(MCLK)=f(SMCLK)

= 32768 Hz, SCG0 = 1,

(ACLK)

Basic Timer1 enabled ,ACLK selected, LCD

enabled,LCDCPEN = 0

(4-mux mode, f

=0MHz,

LCD=f(ACLK)

(see Notes 2 and 3)

Low-power mode 4 (LPM4),

(LPM4)

(MCLK)

(ACLK)

=0MHz,

(SMCLK)

NOTES: 1. Timer_Aisclockedbyf

2. All inputs are tied to 0 V or to V

3. The LPM3 currents are characterized with a Micro Crystal CC4V--T1A (9 pF) crystal and OSCCAPx = 01h.

/32)

=0MHz,

(DCOCLK)

-- 4 0 Cto85C

-- 4 0 C 0.85 1.4

25C

60C

85C 2.15 3.0

-- 4 0 C 1.0 1.5

25C

60C

85C 2.5 3.5

-- 4 0 C 1.8 3.3

25C

85C

-- 4 0 C 2.1 3.6

25C

85C

-- 4 0 C 0.1 0.5

25C

60C

85C 1.1 2.5

-- 4 0 C 0.1 0.8

25C

60C

85C 1.9 3.5

= 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.

. Outputs do not source or sink any current.

MIN TYP MAX UNIT

2.2 V 220 295

3V 350 398

2.2 V 33 60

3V 50 92

2.2 V 6 13

3V 7 15

2.2

2.2 V

0.90 1.2

1.15 1.4

1.1 1.5

1.4 1.9

2.1 3.2

3.6 5.0

2.3 3.6

4.1 5.5

2.2

0.1 0.5

0.35 0.9

0.1 0.8

0.8 1.2



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typical characteristics -- LPM4 current

ILPM4 -- Low-- power mode current -- uA

ILPM4 -- Low-- power mode current --

3.0

2.5

2.0

1.5

1.0

0.5

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

Vcc = 3.6V

Vcc = 3.0V

Vcc = 2.2V

0.0

Figure 2. I

Vcc = 1.8V

--40.0 --20.0 0.0 20.0 40.0 60.0 80.0 100.0

TA-- Temperature -- C

-- LPM4 Current vs Temperature

LPM4

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MSP430F41x2

PortP1,P2:P1.xtoP2.x,externaltriggersigna

Timer_Aclockfrequencyexternally

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

Schmitt-trigger inputs -- ports P1, P2, P3, P4, P5, P6, and P7, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)

PARAMETER V

IT+

IT--

hys

Positive-going input threshold voltage

Negative-going input threshold voltage

Input voltage hysteresis (V

IT+

-- V

IT--

)

2.2 V 1.1 1.55

2.2 V 0.4 0.9

2.2 V 0.3 1.1

3V 0.5 1

inputs Px.y, TAx

PARAMETER TEST CONDITIONS V

(int)

(cap)

(TAext)

(TAint)

External interrupt timing

Timer

capture timing TA0, TA1, TA2

clockfrequencyexternall

applied to pin

Timer

,clockfrequency SMCLK orACLK signal selected

Port P1, P2: P1.x to P2.x, external trigger signal for the interrupt flag (see Note 1)

CLK, INCLK: t

(H)=t(L)

NOTES: 1. The external signal sets the interrupt flag every time the minimum t

shorter than t

(int)

parameters are met. It may be set even with trigger signals

(int)

2.2 V 62

3V 50

2.2 V 62

3V 50

2.2 V 8

3V 10

2.2 V 8

3V 10

leakage current -- ports P1, P2, P3, P4, P5, P6, and P7 (see Note 1)

PARAMETER TEST CONDITIONS V

lkg(Px.y)

Leakage current Port Px V

(see Note 2) 2.2 V/3 V 50 nA

(Px.y)

NOTES: 1. The leakage current is measured with VSSor VCCapplied to the corresponding pin(s), unless otherwise noted.

2. The port pin must be selected as input.

MIN MAX UNIT

1.5 1.98

0.9 1.3

MIN MAX UNIT

MHz

MIN MAX UNIT

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MSP430F41x2

1.1/TA0.0/MCLK/S3

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

outputs -- ports P1, P2, P3, P4, P5, P6, and P7

PARAMETER TEST CONDITIONS MIN MAX UNIT

High-level output voltage

Low-level output voltage

NOTES: 1. The maximum total current, I

specified voltage drop.

2. The maximum total current, I specified voltage drop.

output frequency

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(Px.y)

(MCLK)

(Xdc)

(x=1,2,3,4,5,6,7,0 y  7) CL=20pF,IL= 1.5 mA VCC=2.2V/3V dc f

P1.1/TA0.0/MCLK/S30 CL=20pF f

Duty cycle of output frequency

and I

OH(max)

P1.1/TA0.0/MCLK/S30 C

=--1.5mA, VCC=2.2V (see Note 1) VCC--0.25 V

OH(max)

=--6mA, VCC=2.2V (see Note 2) VCC-- 0 . 6 V

OH(max)

=--1.5mA, VCC=3V (see Note 1) VCC--0.25 V

OH(max)

=--6mA, VCC=3V (see Note 2) VCC-- 0 . 6 V

OH(max)

=1.5mA, VCC=2.2V (see Note 1) VSSVSS+0.25

OL(max)

=6mA, VCC=2.2V (see Note 2) V

OL(max)

=1.5mA, VCC=3V (see Note 1) VSSVSS+0.25

OL(max)

=6mA, VCC=3V (see Note 2) V

OL(max)

for all outputs combined, should not exceed 12 mA to satisfy the maximum

OL(max),

and I

=20pF,

=2.2V/3V

for all outputs combined, should not exceed 48 mA to satisfy the maximum

OL(max),

(MCLK)=f(XT1)

(MCLK)=f(DCOCLK)

40% 60%

50%-15 ns

50%

VSS+0.6

System

50%+

15 ns

MHz

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

outputs -- ports Px (continued)

TYPICAL LOW-LEVEL OUTPUT CURRENT

LOW-LEVEL OUTPUT VOLTAGE

VCC=2.2V P1.0

-- Typical Low-level Output Current -- mA

0.0 0.5 1.0 1.5 2.0 2.5

VOL-- Low-Level Output Voltage -- V

TA=--40C

TA=25C

TA=85C

Figure 3

TYPICAL LOW-LEVEL OUTPUT CURRENT

LOW-LEVEL OUTPUT VOLTAGE

VCC=3V

P1.0

-- Typical Low-level Output Current -- mA 5

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

VOL-- Low-Level Output Voltage -- V

TA=--40C

TA=25C

TA=85C

Figure 4

TYPICAL HIGH-LEVEL OUTPUT CURRENT

HIGH-LEVEL OUTPUT VOLTAGE

0.0 VCC=2.2V P1.0

-- 5 . 0

--10.0

--15.0

--20.0

TA=85C

TA=--40C

0.0 0.5 1.0 1.5 2.0 2.5

VOH-- High-Level Output Voltage -- V

-- Typical High-level Output Current -- m

--25.0

--30.0

--35.0

Figure 5

TA=25C

TYPICAL HIGH-LEVEL OUTPUT CURRENT

HIGH-LEVEL OUTPUT VOLTAGE

0.0 VCC=3V P1.0

TA=25CTA=85C

TA=--40C

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

VOH-- High-Level Output Voltage -- V

-- Typical High-level Output Current -- mA

-- 5 . 0

--10.0

--15.0

--20.0

--25.0

--30.0

--35.0

--40.0

--45.0

--50.0

--55.0

--60.0

--65.0

Figure 6

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MSP430F41x2

)

d(LPM3)

Delaytime

2.2V/3V



MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

wake-up LPM3

PARAMETER TEST CONDITIONS MIN MAX UNIT

f=1MHz 6

d(LPM3

Delay time

f=2MHz

VCC=2.2V/3V

f=3MHz

POR/brownout reset (BOR) (see Note 1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

d(BOR)

CC(start)

(B_IT--)

hys(B_IT--)

(reset)

Brownout

(see Note 2)

dVCC/dt  3 V/s (see Figure 7) 0.7  V

(B_IT--)

dVCC/dt  3 V/s (see Figure 7) 1.71 V

dVCC/dt  3 V/s (see Figure 7) mV

Pulse length needed at RST/NMI pin to accepted reset internally, V

=2.2V/3V

2 s

NOTES: 1. The current consumption of the brownout module is already included in the ICCcurrent consumption data.

The voltage level V

(B_IT--)+Vhys(B_IT--)

2. During power up, the CPU begins code execution following a period of t settings must not be changed until V

is  1.8V.

 V

CC(min)

, where V

after VCC=V

d(BOR)

is the minimum supply voltage for the desired operating frequency.

CC(min)

(B_IT--)+Vhys(B_IT--)

See the MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout.

typical characteristics

s

2000 s

. The default FLL+

CC(start)

(B_IT--)

hys(B_IT--)

d(BOR)

Figure 7. POR/Brownout Reset (BOR) vs Supply Voltage

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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

typical characteristics (continued)

1.5

-- V

=3V

Typical Conditions

CC(min)

0.5

0.001 1 1000

tpw-- Pulse Width -- s

Figure 8. V

Typical Conditions

1.5

-- V

CC(min)

0.5

0.001 1 1000

Figure 9. V

(CC)min

=3V

CC(min)

Level With a Square Voltage Drop to Generate a POR/Brownout Signal

-- Pulse Width -- s

Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal

CC(min)

1ns 1ns

tpw-- Pulse Width -- s

tf=t

tpw-- Pulse Width -- s

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MSP430F41x2

)

hys(SVS_I

T--)

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted)

SVS (supply voltage supervisor/monitor)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(SVSR)

d(SVSon)

settle

(SVSstart)

hys(SVSIT--

(SVS_IT--)

CC(SVS)

(see Note 1)

†

The recommended operating voltage range is limited to 3.6 V.

‡

is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD  0 to a different VLD value somewhere

settle

between 2 and 15. The overdrive is assumed to be > 50 mV.

NOTE 1: The current consumption of the SVS module is not included in the I

dVCC/dt > 30 V/ms (see Figure 10) 5 150 s

dVCC/dt  30 V/ms 2000 s

SVSON, switch from VLD = 0 to VLD  0, VCC=3V 150 300 s

‡

VLD  0

12 s

VLD  0, VCC/dt  3 V/s (see Figure 10) 1.55 1.7 V

VLD = 1 70 120 210 mV

VCC/dt  3 V/s (see Figure 10)

VCC/dt  3 V/s (see Figure 10), External voltage applied on A7

VLD=2to14

VLD = 15 4.4 20 mV

(SVS_IT--)

0.001



(SVS_IT--)

0.016



VLD = 1 1.8 1.9 2.05

VLD = 2 1.94 2.1 2.25

VLD = 3 2.05 2.2 2.37

VLD = 4 2.14 2.3 2.48

VLD = 5 2.24 2.4 2.6

VLD = 6 2.33 2.5 2.71

dt  3V/s (see Figure 10 and Figure 11)

VLD = 7 2.46 2.65 2.86

VLD = 8 2.58 2.8 3

VLD = 9 2.69 2.9 3.13

VLD = 10 2.83 3.05 3.29

VLD = 11 2.94 3.2 3.42

3.99

†

VCC/dt  3 V/s (see Figure 10 and Figure 11), External voltage applied on A7

VLD = 12 3.11 3.35 3.61

VLD = 13 3.24 3.5 3.76

VLD = 14 3.43 3.7

†

VLD = 15 1.1 1.2 1.3

VLD  0, VCC=2.2V/3V 10 15 A

current consumption data.

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MSP430F41x2 MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

typical characteristics

(SVS_IT--)

(SVSstart)

(B_IT--)

CC(start)

Brownout

SVS out

hys(SVS_IT--)

hys(B_IT--)

Brownout

Region

d(BOR)

Software sets VLD > 0:

SVS is active

SVS Circuit is Active From VLD > to VCC<V(

B_IT--)

Brown-

out

Region

d(BOR)

Set POR

1.5

-- V

CC(min)

0.5

undefined

d(SVSon)

Figure 10. SVS Reset (SVSR) vs Supply Voltage

Rectangular Drop

Triangular Drop

1 10 1000

-- Pulse Width -- s

100

CC(min)

d(SVSR)

1ns 1ns

Figure 11. V

CC(min)

: Square Voltage Drop and Triangle Voltage Drop to Generate an SVS Signal (VLD = 1)

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tf=t

t -- Pulse Width -- s

MSP430F41x2

StepsizebetweenadjacentDCOtaps:

Temperaturedrif

t,N

(DCO)

=01E0

h,FN_8=FN_4=FN_3=FN_2=0

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted)

DCO

PARAMETER TEST CONDITIONS V

= 01E0h, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2,

(DCOCLK)

(DCO2)

(DCO27)

(DCO2)

(DCO27)

(DCO2)

(DCO27)

(DCO2)

(DCO27)

(DCO2)

(DCO27)

(DCO)

DCOPLUS = 0

FN_8=FN_4=FN_3=FN_2 = 0, DCOPLUS = 1

FN_8=FN_4=FN_3=FN_2 = 0, DCOPLUS = 1 (see Note 1)

FN_8=FN_4=FN_3=0,FN_2 = 1, DCOPLUS = 1

FN_8=FN_4=FN_3=0,FN_2 = 1, DCOPLUS = 1 (see Note 1)

FN_8=FN_4=0,FN_3=1,FN_2=x, DCOPLUS = 1

FN_8=FN_4=0,FN_3=1,FN_2=x, DCOPLUS = 1 (see Note 1)

FN_8=0,FN_4=1,FN_3=FN_2=x, DCOPLUS = 1

FN_8=0,FN_4=1,FN_3=FN_2=x, DCOPLUS = 1 (see Note 1)

FN_8=1,FN_4=FN_3=FN_2=x, DCOPLUS = 1

FN_8=1,FN_4=FN_3=FN_2=x, DCOPLUS = 1 (see Note 1)

Stepsize between adjacent DCO taps: Sn=f

DCO(Tap n+1)/fDCO(Tap n)

Temperature drift, N

, (see Figure 13 for taps 21 to 27)

= 01E0h, FN_8=FN_4=FN_3=FN_2=0,

D = 2, DCOPLUS = 0

Drift with VCCvariation, N

(DCO)

= 01E0h,

FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0

1<TAP 20 1.06 1.11

NOTES: 1. Do not exceed the maximum system frequency.

2.2 V/3 V 1 MHz

2.2 V 0.3 0.65 1.25

3V 0.3 0.7 1.3

2.2 V 2.5 5.6 10.5

3V 2.7 6.1 11 . 3

2.2 V 0.7 1.3 2.3

3V 0.8 1.5 2.5

2.2 V 5.7 10.8 18

3V 6.5 12.1 20

2.2 V 1.2 2 3

3V 1.3 2.2 3.5

2.2 V 9 15.5 25

3V 10.3 17.9 28.5

2.2 V 1.8 2.8 4.2

3V 2.1 3.4 5.2

2.2 V 13.5 21.5 33

3V 16 26.6 41

2.2 V 2.8 4.2 6.2

3V 4.2 6.3 9.2

2.2 V 21 32 46

3V 30 46 70

TAP = 27 1.07 1.17

2.2 V –0.2 –0.4 -- 0 . 6

3V –0.2 –0.4 -- 0 . 6

MIN TYP MAX UNIT

MHz

%_C

0 5 15 %/V

(DCO)

(DCO3V)

1.0

1.8 3.02.4 3.6

Figure 12. DCO Frequency vs Supply Voltage VCCand vs Ambient Temperature

(DCO)

(DCO20C)

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1.0

20 6040 85

0-- 2 0-- 4 00

-- CVCC-- V

MSP430F41x2 MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

1.17

(DCO)

- Stepsize Ratio between DCO Taps S

1.11

1.07

1.06 Min

12720

DCO Tap

Max

Figure 13. DCO Tap Step Size

Legend

Tolerance at Tap 27

DCO Frequency Adjusted by Bits

to 25in SCFI1 {N

Tol e r a nce at Tap 2

{DCO}

}

FN_2=0 FN_3=0 FN_4=0 FN_8=0

FN_2=1 FN_3=0 FN_4=0 FN_8=0

Figure 14. Five Overlapping DCO Ranges Controlled by FN_x Bits

FN_2=x FN_3=1 FN_4=0 FN_8=0

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FN_2=x FN_3=x FN_4=1 FN_8=0

Overlapping DCO Ranges: Uninterrupted Frequency Range

FN_2=x FN_3=x FN_4=x

FN_8=1

MSP430F41x2

ALFOscillationallowancefor

(seeNote1

)

MIXED SIGNAL MICROCONTROLLER

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electrical characteristics over recommended operating free-air temperature (unless otherwise noted)

crystal oscillator, LFXT1, low-frequency modes (see Note 4)

PARAMETER TEST CONDITIONS V

LFXT1,LF

L,eff

Duty cycle LF mode

Fault,LF

NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).

LFXT1 oscillator crystal frequency, LF mode 0, 1

Oscillation allowancefor LF crystals

Integrated effective load capacitance, LF mode

Oscillator fault frequency, LF mode (see Note 3)

Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should always match the specification of the used crystal.

2. Measured with logic level input frequency but also applies to operation with crystals.

3. Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and frequencies in between might set the flag.

4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.

XTS = 0, LFXT1Sx = 0 or 1 1.8 V to 3.6 V 32768 Hz

XTS = 0, LFXT1Sx = 0, f

LFXT1,LF

XTS = 0, LFXT1Sx = 0, f

LFXT1,LF

XTS = 0, XCAPx = 0 1

XTS = 0, XCAPx = 1 5.5

XTS = 0, XCAPx = 2 8.5

XTS = 0, XCAPx = 3 11

XTS = 0, Measured at P1.6/ACLK, f

LFXT1,LF

XTS = 0, XCAPx = 0. LFXT1Sx = 3 (see Note 2)

L,eff

= 32768 kHz,

=6pF

= 32768 kHz,

=12pF

2.2 V/3 V 30 50 70 %

= 32768Hz

2.2 V/3 V 10 10000 Hz

-- Keep the trace between the device and the crystal as short as possible.

-- Design a good ground plane around the oscillator pins.

-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

-- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

-- Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.

-- If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.

-- Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other

documentation. This signal is no longer required for the serial programming adapter.

MIN TYP MAX UNIT

500

kΩ

200

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MSP430F41x2

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SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted)

crystal oscillator, LFXT1, high frequency modes

PARAMETER TEST CONDITIONS V

LFXT1

L,eff

Duty cycle Measured at P1.6/ACLK 2.2 V/3 V 40 50 60 %

NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).

LFXT1 oscillator crystalfrequency

Integrated effective load capacitance, HF mode (see Note 1)

2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

Ceramic resonator 1.8 V to 3.6 V 0.45 6

Crystal resonator

SeeNote2 1 pF

1.8 V to 3.6 V 1 6

internal very low power, low-frequency oscillator (VLO)

PARAMETER TEST CONDITIONS V

VLO

/dT VLO frequency temperature drift See Note 2.2 V/3 V 0.5 %/C

VLO

/dV

VLO

NOTES: 1. Calculated using the box method:

VLO frequency TA=--40Cto85C 2.2 V/3 V 4 12 20 kHz

VLO frequency supply voltage drift SeeNote2 1.8V to 3.6V 4 %/V

I Version: (MAX(--40_Cto85_C) -- MIN(--40_Cto85_C))/MIN(--40_Cto85_C)/(85_C--(--40_C))

2. Calculated using the box method: (MAX(1.8 V to 3.6 V ) -- MIN(1.8 V to 3.6 V))/MIN(1.8 V to 3.6 V)/(3.6 V -- 1.8 V)

MIN TYP MAX UNIT

MHz

MIN TYP MAX UNIT

RAM

PARAMETER TEST CONDITIONS MIN MAX UNIT

VRAMh SeeNote1 CPU halted 1.6 V

NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution

should take place during this supply voltage condition.

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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

LCD_A

CC(LCD)

LCD

CC(LCD)

LCD

PARAMETER TEST CONDITIONS V

Supply voltage range

Capacitor on LCDCAP (see Note 1)

Average supply current (see Note 2)

Charge pump enabled (LCDCPEN = 1, VLCDx > 0000)

V VLCDx= 1000, all segments on f no LCD connected (see Note 3) T

=3V, LCDCPEN = 1,

LCD(typ)

LCD=fACLK

=25C

/32

LCD frequency 1.1 kHz

LCD voltage VLCDx = 0000 V

LCD voltage VLCDx = 0001 2.60 V

LCD voltage VLCDx = 0010 2.66 V

LCD voltage VLCDx = 0011 2.72 V

LCD voltage VLCDx = 0100 2.78 V

LCD voltage VLCDx = 0101 2.84 V

LCD voltage VLCDx = 0110 2.90 V

LCD voltage VLCDx = 0111 2.96 V

LCD voltage VLCDx = 1000 3.02 V

LCD voltage VLCDx = 1001 3.08 V

LCD voltage VLCDx = 1010 3.14 V

LCD voltage VLCDx = 1011 3.20 V

LCD voltage VLCDx = 1100 3.26 V

LCD voltage VLCDx = 1101 3.32 V

LCD voltage VLCDx = 1110 3.38 V

LCD voltage VLCDx = 1111 3.44 3.60 V

=3V,LCDCPEN=1,

LCD driver output impedance

LCD

VLCDx = 1000, I

LOAD

= 10 A

2.2 V 3.8 A

2.2 V 10 k

NOTES: 1. Enabling the internal charge pump with an external capacitor smaller than the minimum specified might damage the device.

2. Refer to the supply current specifications I

for additional current specifications with the LCD_A module active.

(LPM3)

3. Connecting an actual display will increase the current consumption depending on the size of the LCD.

MIN TYP MAX UNIT

2.2 3.6 V

4.7 F

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MSP430F41x2

CAON=

1,CARSEL=

0,CAREF=1/2/3

SeeFigure15an

/CA

TA=25

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

Comparator_A+ (see Note 1)

PARAMETER TEST CONDITIONS V

(CC)

(Refladder/RefDiode)

(Ref025)

(Ref050)

(RefVT)

Vp-- V

hys

Voltage @ 0.25 VCCnode

Voltage @ 0.5 VCCnode

See Figure 15 and Figure 16

Common-mode input voltage range

Offset voltage SeeNote2 2.2 V / 3 V -- 3 0 30 mV

Input hysteresis CAON = 1 2.2 V / 3 V 0 0.7 1.4 mV

CAON = 1, CARSEL = 0, CAREF = 0

CAON = 1, CARSEL = 0, CAREF = 1/2/3, No load at P1.6/CA0 and P1.7/CA1

PCA0 = 1, CARSEL = 1, CAREF = 1, No load at P1.6/CA0 and P1.7/CA1

PCA0 = 1, CARSEL = 1, CAREF = 2, No load at P1.6/CA0 and P1.7/CA1

PCA0 = 1, CARSEL = 1, CAREF = 3, No load at P1.6 T

=85C

0 and P1.7/CA1,

CAON = 1 2.2 V / 3 V 0 VCC-- 1 V

=25C,

Overdrive 10 mV, without filter: CAF = 0

(response LH and HL)

(see Note 3)

=25C

Overdrive 10 mV, with filter: CAF = 1

NOTES: 1. The leakage current for the Comparator_A terminals is identical to I

2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The two successive measurements are then summed together.

3. The response time is measured at P1.6/CA0 with an input voltage step and the Comparator_A already enabled (CAON=1). If CAON is set at the same time, a settling time of up to 300ns is added to the response time.

lkg(Px.x)

2.2 V 25 40

3V 45 60

2.2 V 30 50

3V 45 80

2.2 V / 3 V 0.23 0.24 0.25

2.2V / 3 V 0.47 0.48 0.5

2.2 V 390 480 540

3V 400 490 550

2.2 V 80 165 300

3V 70 120 240

2.2 V 1.4 1.9 2.8

3V 0.9 1.5 2.2

specification.

MIN TYP MAX UNIT



s

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430F41x2

(

)

(

)

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

typical characteristics

REFERENCE VOLTAGE

FREE-AIR TEMPERATURE

650

VCC=3V

600

Typical

550

500

-- Reference Voltage -- mV

REF

450

400

-- 4 5 -- 2 5 -- 5 1 5 3 5 5 5 7 5 9 5

TA-- Free-Air Temperature -- C

Figure 15. V

V+

V--

vs Temperature

RefVT

+ _

CAON

REFERENCE VOLTAGE

FREE-AIR TEMPERATURE

650

VCC=2.2V

600

Typical

550

500

-- Reference Voltage -- mV

REF

450

400

-- 4 5 -- 2 5 -- 5 1 5 3 5 5 5 7 5 9 5

TA-- Free-Air Temperature -- C

Figure 16. V

CAF

Low-Pass Filter

vs Temperature

RefVT

To I n t ernal Modules

CAOUT

Figure 17. Block Diagram of Comparator_A Module

Overdrive

V--

400 mV

V+

(response)

Figure 18. Overdrive Definition

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2 s

CAOUT

Set CAIFG Flag

MSP430F41x2

ply

ADC10supplycurren

currentwith

_5V

currentwith

REFON=1

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

10-bit ADC, power supply and input range conditions (see Note )

PARAMETER TEST CONDITIONS V

ADC10

REF+

Analog supply voltage range

Analog input voltage range (see Note 2)

DC10 su

current

(see Note 3)

Reference supply current, reference bu disabled (see Note 4)

VSS=0V 2.2 3.6 V

All Ax terminals, Analog inputs selected in ADC10AE register

ADC10CLK =

5MHz,

DC10ON = 1, REFON = 0

ADC10SHT0 = 1, ADC10SHT1 = 0, ADC10DIV = 0

ADC10CLK =

5MHz, ADC10ON = 0, REF2_5V = 0, REFON = 1, REFOUT = 0

ADC10CLK =

5MHz, ADC10ON = 0, REF2_5V = 1, REFON = 1, REFOUT = 0

REFB,0

REFB,1

Reference buffer supply current with ADC10SR = 0 (see Note 4)

Reference buffer supply current with ADC10SR = 1 (see Note 4)

ADC10CLK =

ADC10ON = 0, REFON = 1, REF2 REFOUT = 1, ADC10SR = 0

ADC10CLK =

ADC10ON = 0, REFON = 1 REF2_5V = 0, REFOUT = 1,

5MHz,

=0,

5MHz,

ADC10SR = 1

Input capacitance Only one terminal Ax selected at a time 27 pF

Input MUX ON resistance

0V  VAx V

NOTES: 1. The leakage current is defined in the leakage current table with Px.x/Ax parameter.

2. The analog input voltage range must be within the selected reference voltage range V

3. The internal reference supply current is not included in current consumption parameter I

4. The internal reference current is supplied via terminal V

. Consumption is independent of the ADC10ON control bit, unless a

conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.

2.2 V 0.52 1.05

3V 0.6 1.2

2.2 V/3 V

2.2 V/3 V 1.1 1.4 mA

2.2 V/3 V 1.8 mA

2.2 V/3 V 0.5 0.7 mA

2.2 V/3 V 0.8 mA

2.2 V/3 V 2000 

R+

MIN TYP MAX UNIT

0 V

0.25 0.4

to V

for valid conversion results.

R--

ADC10

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430F41x2

C,REF

REF

Positivebuiltinreferencevoltage

REF

loadregulationrespons

REF2_5V=0

Settlingtimeofreferencebuffer

REF2_5V=1

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

10-bit ADC, built-in voltage reference

PARAMETER TEST CONDITIONS V

 1 mA, REF2_5V = 0 2.2

VREF+

 0.5 mA, REF2_5V = 1 2.8

VREF+

 1 mA, REF2_5V = 1 2.9

VREF+

 I

VREF+

 I

VREF+

VREF+ =

Analog input voltage V

max, REF2_5V = 0

VREF+

max, REF2_5V = 1 3V 2.35 2.5 2.65 V

VREF+

500 A  100 A,

 0.75 V,

REF2_5V = 0

I Analog input voltage V

VREF+ =

500 A  100 A,

 1.25 V,

2.2 V/ 3V

2.2 V 0.5

3V 1

2.2 V/ 3V

3V 2 LSB

CC,REF+

LD,VREF+

Positive built-in reference analog supplyvo

age range

Positive built-in reference voltage

Maximum V

load regulation

REF+

load current

REF2_5V = 1

VREF+

REF+

REFON

REFBURST

load regulation response

time

Max. capacitance at pin V

REF+

(see Note 1)

Temperature coefficient

Settling time of internal reference voltage (see Note 2)

Settlingtime ofreference bu

(see Note 2)

= 100 A900 A,

VREF+

 0.5

REF+,

Error o

conversion result  1LSB

1mA,

VREF+

REFON = 1, REFOUT = 1

const. with 0 mA  I

VREF+ =

(see Note 3)

0.5 mA, REF2_5V = 0,

VREF+ =

REFON = 0  1

I REF2 5

VREF+ =

0.5 mA, =0,

, REFON = 1, REFBURST = 1

VREF+ =

0.5 mA, =1,

I REF2 5 REFON = 1, REFBURST = 1

ADC10SR = 0 3V 400

ADC10SR = 1 3V 2000

2.2 V/ 3V

VREF+

 1mA

2.2 V/ 3V

3.6 V 30 s

ADC10SR = 0 2.2 V 1

ADC10SR = 1 2.2 V 2.5

ADC10SR = 0 3V 2

ADC10SR = 1 3V 4.5

NOTES: 1. The capacitance applied to the internal buffer operational amplifier, if switched to terminal

P6.4/UCB0CLK/UCA0STE/A4/CA6/V

eref+/Vref+

(REFOUT = 1), must be limited; the reference buffer m ay become unstable,

otherwise.

2. The condition is that the error in a conversion started after t

3. Calculated using the box method: ((MAX(V

(T)) -- MIN(V

REF

REFON

(T))) / MIN(V

REF

or t

is less than 0.5 LSB.

RefBuf

REF

(T)) / (T

MAX

MIN TYP MAX UNIT

1.41 1.5 1.59 V

-- T

)

MIN

2 LSB

100 pF

100 ppm/C

s

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MSP430F41x2

Positiveexternalreferenceinpu

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

10-bit ADC, external reference (see Note 1)

eREF+

PARAMETER TEST CONDITIONS V

Positive external reference input voltage range (see Note 2)

eREF+>VeREF--

SREF1 = 1, SREF0 = 0

 V

eREF--

 (VCC-- 0.15 V)

eREF+

SREF1=1,SREF0=1(seeNote3)

eREF--

Negative external reference input voltage range (see Note 4)

eREF+>VeREF--

Differential external reference input

V

eREF

VeREF+

VeREF --

voltage range V

eREF=VeREF+

-- V

eREF--

Static input current into V

eREF+

eREF--

eREF+>VeREF--

0V  V

eREF+

(see Note 5) 1.4 V

 VCC,

SREF1 = 1, SREF0 = 0

0V  V

 (VCC-- 0.15 V)  3V,

eREF+

SREF1=1,SREF0=1(seeNote3)

0V  V

eREF--

 V

2.2 V/3 V 1

2.2 V/3 V 0

2.2 V/3 V 1 A

NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI,isalso

the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.

2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements.

3. Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply current I

. The current consumption can be limited to the sample and conversion period with REBURST = 1.

REFB

4. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements.

5. The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements.

MIN TYP MAX UNIT

1.4 V

1.4 3.0

0 1.2 V



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MSP430F41x2

perf

performanceof

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

10-bit ADC, timing parameters

PARAMETER TEST CONDITIONS V

For specified

ADC10CLK

DC10 input clockfrequency

ormance o ADC10 linearity parameters

ADC10OSC

ADC10 built-in oscillator frequency

ADC10DIVx = 0, ADC10SSELx = 0 f

ADC10CLK =fADC10OSC

ADC10 built-in oscillator, ADC10SSELx = 0 f

CONVERT

Conversion time

ADC10CLK =fADC10OSC

ADC10CLK

SMCLK: ADC10SSELx  0

ADC10ON

Turn on settling time of the ADC SeeNote1 100 ns

NOTE 1: The condition is that the error in a conversion started after t

settled.

ADC10SR = 0 2.2 V/3 V 0.45 6.3

ADC10SR = 1 2.2 V/3 V 0.45 1.5

from ACLK, MCLK or

ADC10ON

is less than 0.5 LSB. The reference and input signals are already

2.2 V/3 V 3.7 6.3 MHz

2.2 V/3 V 2.06 3.51 s

MIN TYP MAX UNIT

MHz

13 ADC10DIV 1/f

ADC10CLK

s

10-bit ADC, linearity parameters

PARAMETER TEST CONDITIONS V

EIIntegral linearity error 2.2 V/3 V 1 LSB

EDDifferential linearity error 2.2 V/3 V 1 LSB

Offset error

Gain error

Total unadjusted error

Source impedance RS< 100  2.2 V/3 V 1 LSB

SREFx = 010, Unbuffered external reference, V

SREFx = 011, Buffered external reference (see Note 2), V

eREF+ =

1.5 V

SREFx = 011, Buffered external reference (see Note 2), V

eREF+ =

2.5 V

SREFx = 010, Unbuffered external reference, V

SREFx = 011, Buffered external reference (see Note 2), V

eREF+ =

1.5 V

SREFx = 011, Buffered external reference (see Note 2), V

eREF+ =

2.5 V

1.5 V 2.2 V 1.1 2 LSB

eREF+ =

2.5 V 3V 1.1 2 LSB

eREF+ =

2.2 V 1.1 4 LSB

3V 1.1 3 LSB

1.5 V 2.2 V 2 5 LSB

eREF+ =

2.5 V 3V 2 5 LSB

eREF+ =

2.2 V 2 7 LSB

3V 2 6 LSB

NOTE 1: The reference buffer’s offset adds to the gain and total unadjusted error.

MIN TYP MAX UNIT

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430F41x2

ply

Temperaturesensorsupply

REFON=0,INCHx=0Ah

(

)

Currentintodividera

ADC10ON=1,INCHx=0Bh

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

10-bit ADC, temperature sensor and built-in V

PARAMETER

SENSOR

Offset,Sensor

Sensor

Temperature sensor su current (see Note )

Sensor offset voltage

Sensor output voltage (see Note 3)

Sample time required if

Sensor(sample)

VMID

MID

channel 10 is selected (see Note 4)

Current into divider at channel11 (see Note 5)

VCCdivider at channel 11

Sample time required if

VMID(sample)

channel 11 is selected (see Note 6)

NOTES: 1. The sensor current I

is high). When REFON = 1, I sensor input (INCH = 0Ah).

2. The following formula can be used to calculate the temperature sensor output voltage: V

Sensor,typ

=TC =TC

Sensor

3. Results based on characterization and/or production test, not TC

4. The typical equivalent impedance of the sensor is 51 k. The sample time required includes the sensor-on time t

5. No additional current is needed. The V

6. The on-time t

VMID(on)

is consumed if (ADC10ON = 1 and REFON = 1), or (ADC10ON = 1 and INCH = 0Ah and sample signal

SENSOR

( 273 + T [C] ) + V T[C] + V

is included in the sampling time t

REFON = 0, INCHx=0Ah, ADC10ON = 1, T

ADC10ON = 1, INCHx = 0Ah (see Note 2)

Temperature sensor voltage at T

=85C

Temperature sensor voltage at T

=25C

Temperature sensor voltage at T

=0C

ADC10ON = 1, INCHx = 0Ah, Error of conversion result  1LSB

DC10ON = 1, INCHx=0Bh

DC10ON = 1, INCHx=0Bh,

is 0.5 x V

MID

DC10ON = 1, INCHx=0Bh,

Error of conversion result  1LSB

is included in I

Offset,sensor

Sensor(TA

=0C) [mV]

is used during sampling.

MID

TEST CONDITIONS V

=25_C

2.2 V/3 V 3.55 mV/C

2.2 V/3 V 1195 1295 1395 mV

2.2 V/3 V 985 1085 1185

2.2 V/3 V 895 995 1095

2.2 V/3 V 30 s

. When REFON = 0, I

REF+

SENSOR

[mV] or

or V

VMID(sample)

Sensor

; no additional on time is needed.

Offset,sensor

MIN TYP MAX UNIT

2.2 V 40 120

3V 60 160

--100 100 mV

2.2 V NA

3V NA

2.2 V 1.06 1.1 1.14

3V 1.46 1.5 1.54

2.2 V 1400

3V 1220

applies during conversion of the temperature

SENSOR(on)



Timer0_A3, Timer1_A5

PARAMETER TEST CONDITIONS V

TA, cap

Timer

Timer_A, capture timing TA0 , TA1, TA 2 2.2 V/3 V 20 ns

clockfrequency

Internal: SMCLK, ACLK, E

ternal: TACLK, INCLK,

Duty cycle = 50% 10%

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MIN MAX UNIT

2.2 V 8

3V 10

MHz

MSP430F41x2

UARTreceivedeglitchtime

UCLKedgetoSIMOvalid

UCLKedgetoSOMIvalid

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

USCI (UART mode)

PARAMETER TEST CONDITIONS V

Internal: SMCLK, ACLK

USCI

USCI input clock frequency

External: UCLK Duty cycle = 50%  10%

Maximum BITCLK clock frequency

fmax,

BITCLK

(equals baudrate i n MBaud) (see Note 1)



UART receive deglitch time (see Note 2)

NOTES: 1. The DCO wake-up time must be considered in LPM3/4 for baudrates above 1 MHz.

2. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed.

USCI (SPI master mode) (see Figure 19 and Figure 20)

PARAMETER TEST CONDITIONS V

USCI

SU,MI

HD,MI

VAL ID, M O

NOTE: f

USCI input clock frequency

SOMI input data setup time

SOMI input data hold time

SIMO output data valid time

UCxCLK

For the slave’s parameters t

LO∕HI

with t

≥ max(t

LO∕HI

SU,SI(Slave)

and t

SMCLK, ACLK Duty cycle = 50%  10%

UCLK edgetoSIMOvalid, C

=20pF

VALID,MO(USCI)

VALID,SO(Slave)

+ t

refer to the SPI parameters of the attached slave.

SU,SI(Slave),tSU,MI(USCI)

+ t

2.2V /3 V 2 MHz

2.2 V 50 150

3V 50 100

VALID,SO(Slave)

MIN TYP MAX UNIT

SYSTEM

MIN MAX UNIT

SYSTEM

2.2 V 110

3V 75

2.2 V 0

3V 0

2.2 V 30

3V 20

MHz

USCI (SPI slave mode) (see Figure 21 a nd Figure 22)

PARAMETER TEST CONDITIONS V

STE,LEAD

STE,LAG

STE,ACC

STE,DIS

SU,SI

HD,SI

VAL ID, S O

NOTE: f

For the master’s parameters t

STE lead time STE low to clock

STE lag time Last clock to STE high

STE access time STE low to SOMI data out

STE disable time STE high to SOMI high impedance

SIMO input data setup time

SIMO input data hold time

SOMI output data valid time

UCxCLK

LO∕HI

with t

LO∕HI

≥ max(t

SU,MI(Master)

UCLK edgetoSOMIvalid, C

=20pF

VALID,MO(Master)

and t

VALID,MO(Master)

+ t

MIN TYP MAX UNIT

2.2 V/3 V 50 ns

2.2 V/3 V 10 ns

2.2 V/3 V 50 ns

2.2 V 20

3V 15

2.2 V 10

3V 10

2.2 V 75 11 0

3V 50 75

SU,SI(USCI),tSU,MI(Master)

+ t

VALID,SO(USCI)

refer to the SPI parameters of the attached master.

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MSP430F41x2 MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

1/f

UCxCLK

CKPL=0

UCLK

CKPL=1

SOMI

SIMO

UCLK

SOMI

CKPL=0

CKPL=1

LO/HItLO/HI

VAL I D, MO

SU,MI

HD,MI

Figure 19. SPI Master Mode, CKPH = 0

1/f

UCxCLK

LO/HItLO/HI

SU,MI

VAL I D,MO

HD,MI

SIMO

Figure 20. SPI Master Mode, CKPH = 1

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

STE

UCLK

SIMO

SOMI

STE

CKPL=0

CKPL=1

STE,ACC

STE,LEAD

1/f

UCxCLK

LO/HItLO/HI

VAL I D,SO

Figure 21. SPI Slave Mode, CKPH = 0

STE,LEAD

SU,SI

HD,SI

STE,LAG

STE,DIS

UCLK

SIMO

SOMI

CKPL=0

CKPL=1

STE,ACC

1/f

UCxCLK

LO/HItLO/HI

SU,SI

VAL I D, SO

Figure 22. SPI Slave Mode, CKPH = 1

HD,SI

STE,DIS

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MSP430F41x2

Pulsewidthofspikessuppressedb

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

USCI (I2C mode) (see Figure 23)

USCI

SCL

HD,STA

SU,STA

HD,DAT

SU,DAT

SU,STO

PARAMETER TEST CONDITIONS V

Internal: SMCLK, ACLK

USCI input clock frequency

External: UCLK Duty cycle = 50%  10%

SCL clock frequency 2.2 V/3 V 0 400 kHz

 100kHz 2.2 V/3 V 4.0 us

Hold time (repeated) START

Setup timefor a repeated START

SCL

> 100kHz 2.2 V/3 V 0.6 us

SCL

 100kHz 2.2 V/3 V 4.7 us

SCL

> 100kHz 2.2 V/3 V 0.6 us

SCL

Data hold time 2.2 V/3 V 0 ns

Data set--up time 2.2 V/3 V 250 ns

SetuptimeforSTOP 2.2 V/3 V 4.0 us

Pulse width ofspikes su input filter

ressed b

2.2 V 50 150 600 ns

3V 50 100 600 ns

MIN TYP MAX UNIT

SYSTEM

MHz

SDA

SCL

HD,STA

1/f

SCL

HD,DAT

SU,STAtHD,STA

SU,DAT

Figure 23. I2C Mode Timing

SU,STO

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

flash memory

TEST

CONDITIONS

MIN NOM MAX UNIT

CC(PGM/

ERASE)

PARAMETER

Program and Erase supply voltage 2.2 3.6 V

FTG

PGM

ERASE

CPT

CMErase

Retention

Word

Block, 0

Block, 1-63

Block, End

Mass Erase

Seg Erase

Flash Timing Generator frequency 257 476 kHz

Supply current from DVCCduring program 2.5V/3.6V 3 5 mA

Supply current from DVCCduring erase 2.5V/3.6V 3 7 mA

Cumulative program time seeNote1 2.5V/3.6V 10 ms

Cumulative mass erase time seeNote2 2.5V/3.6V 200 ms

Program/Erase endurance 10

cycles

Data retention duration TJ=25C 100 years

Word or byte program time 35

Block program time for 1stbyte or word 30

Block program time for each additional byte or word

Block program end-sequence wait time

seeNote3

FTG

Mass erase time 5297

Segment erase time 4819

NOTES: 1. The cumulative program time must not be exceeded when writing to a 64--byte flash block. This parameter applies to all programming

methods: individual word/byte write and block write modes.

2. The mass erase duration generated by the flash timing generator is at least 11.1 ms ( = 5297x1 / f

, max = 5297 x 1 / 476 kHz).

FTG

To achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met. (A worst case minimum of 19 cycles is required.)

3. These values are hardwired into the Flash Controller’s state machine (t

FTG

=1/f

FTG

JTAG and Spy-Bi-Wire interface

PARAMETER

SBW

SBW,Low

Spy-Bi-Wire input frequency 2.2 V/3 V 0 8 MHz

Spy-Bi-Wire l ow clock pulse length 2.2 V/3 V 0.025 15 us

Spy-Bi-Wire enable time,

SBW,En

TEST high to acceptance of first clock edge (see Note 1)

SBW,Ret

TCK

Internal

Spy-Bi-Wire return to normal operation time 2.2 V /3 V 15 100 us

TCK inputfrequency (see Note 2)

Internal pulldown resistance on TEST 2.2 V/3 V 25 60 90 k

NOTES: 1. Tools accessing the Spy-Bi-Wire interface need to wait for the maximum t

before applying the first SBWCLK clock edge.

2. f

may be restricted to meet the timing requirements of the module selected.

TCK

TEST

CONDITIONS

MIN TYP MAX UNIT

2.2 V/3 V 1 us

2.2 V 0 5 MHz

3V 0 10 MHz

time after pulling the TEST/SBWCLK pin high

SBW,En

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430F41x2 MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

JTAG fuse (see Note 1)

PARAMETER

CC(FB)

NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched

Supply voltage during fuse-blow condition TA=25C 2.5 V

Voltage level on TDI/TCLK for fuse-blow 6 7 V

Supply current into TDI/TCLK during fuse blow 100 mA

Time to blow fuse 1 ms

to bypass mode.

TEST

CONDITIONS

MIN MAX UNIT

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MIXED SIGNAL MICROCONTROLLER

APPLICATION INFORMATION

Port P1 pin schematic: P1.0 to P1.4, input/output with Schmitt trigger

MSP430F41x2

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

LCDS24/28

Segment Sy

P1DIR.x

P1OUT.x

Module X OUT

P1SEL.x

P1IN.x

Module X IN

P1IRQ.x

P1IFG.x

P1SEL.x

P1IES.x

P1IE.x

Set

Interrupt

Edge Select

Direction 0: Input 1: Output

Bus

Keeper

Pad Logic

P1.0/TA0.0/S31 P1.1/TA0.0/MCLK/S30 P1.2/TA0.1/S29 P1.3/TA1.0/SVSOUT/S28 P1.4/TA1.0/S27

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430F41x2

///

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

Port P1 (P1.0 to P1.4) pin functions

PIN NAME (P1.X)

P1.0/TA0.0/S31 0

P1.1/TA0.0/MCLK/S30 1

P1.2/TA0.1/S29 2

P1.3/TA1.0/SVSOUT/S28 3

P1.4/TA1.0/S27 4

NOTES: 1. x: Don’t care

X FUNCTION

P1.x (I/O) I: 0, O: 1 0 0

Timer0_A3.CCI0A 0 1 0

Timer0_A3.TA0 1 1 0

S31 x x 1 (LCDS28)

P1.x (I/O) I: 0, O: 1 0 0

Timer0_A3.CCI0B 0 1 0

MCLK 1 1 0

S30 x x 1 (LCDS28)

P1.x (I/O) I: 0, O: 1 0 0

Timer0_A3.CCI1A 0 1 0

Timer0_A3.TA1 1 1 0

S29 x x 1 (LCDS28)

P1.x (I/O) I: 0, O: 1 0 0

Timer1_A5.CCI0B 0 1 0

SVSOUT 1 1 0

S28 x x 1 (LCDS28)

P1.x (I/O) I: 0, O: 1 0 0

Timer1_A5.CCI0A 0 1 0

Timer1_A5.TA0 1 1 0

S27 x x 1 (LCDS24)

CONTROL BITS / SIGNALS

P1DIR.x P1SEL.x

LCDS24 LCDS28

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

APPLICATION INFORMATION

///

Port P1 pin schematic: P1.5, input/output with Schmitt trigger

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

LCDS24

Segment Sy

P1DIR.x

P1OUT.x

Module X OUT

P1SEL.x

P1IN.x

from TA0CLK of P1.7

TA0CLK

P1IRQ.x

P1IFG.x

P1SEL.x

P1IES.x

P1IE.x

Interrupt

Edge Select

Set

Direction 0: Input 1: Output

Bus

Keeper

Pad Logic

P1.5/TA0CLK/ CAOUT/S26

Port P1 (P1.5) pin functions

PIN NAME (P1.X)

P1.5/TA0CLK/CAOUT/S26 5

NOTES: 1. x: Don’t care

2. The input TA0CLK of P1.5 and P1.7 are logically ORed. Therefore only one of them should be enabled at a time to feed in TA0CLK.

X FUNCTION

CONTROL BITS / SIGNALS

P1DIR.x P1SEL.x

LCDS24 LCDS28

P1.x (I/O) I: 0, O: 1 0 0

Timer0_A3.TACLK 0 1 0

CAOUT 1 1 0

S26 x x 1 (LCDS24)

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

APPLICATION INFORMATION

Port P1 pin schematic: P1.6, input/output with Schmitt trigger

To Comparator_A

From Comparator_A

CAPD.y

P1DIR.x

P1OUT.x

Module Out

P1SEL.x

P1IN.x

Module X IN

P1IRQ.x

Pad Logic

P1IE.x

P1IFG.x

Direction 0: Input 1: Output

P1.6/ACLK/CA0

Bus

Keeper

Set

P1SEL.x

P1IES.x

Port P1 (P1.6) pin functions

PIN NAME (P1.X)

P1.6/ACLK/CA0 6

NOTES: 1. x: Don’t care

P1.x (I/O) 0 I: 0, O: 1 0

ACLK 0 1 1

CA0 1 (CAPD.0) x x

Interrupt

Edge Select

FUNCTION

CONTROL BITS / SIGNALS

CAPD P1DIR.x P1SEL.x

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

APPLICATION INFORMATION

///

Port P1 pin schematic: P1.7, input/output with Schmitt trigger

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

To Comparator_A

From Comparator_A

CAPD.y

P1DIR.x

P1OUT.x

Module Out

P1SEL.x

P1IN.x

TA0CLK

to P1.5

P1IRQ.x

Pad Logic

P1IE.x

P1IFG.x

Direction 0: Input 1: Output

Set

Bus

Keeper

P1.7/TA0CLK/ CAOUT/CA1

P1SEL.x

P1IES.x

Port P1 (P1.7) pin functions

PIN NAME (P1.X)

P1.7/TA0CLK/CAOUT/CA1 7

NOTES: 1. x: Don’t care

2. The input TA0CLK of P1.5 and P1.7 are c ombined by a logical OR. Therefore, only one of them should be enabled at a time to feed in TA0CLK.

Interrupt

Edge Select

FUNCTION

CONTROL BITS / SIGNALS

CAPD P1DIR.x P1SEL.x

P1.x (I/O) 0 I: 0, O: 1 0

Timer0_A3.TACLK 0 0 1

CAOUT 0 1 1

CA1 1 (CAPD.1) x x

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430F41x2 MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

APPLICATION INFORMATION

Port P2 pin schematic: P2.0 to P2.7 input/output with Schmitt trigger

LCDS8/12

Segment Sy

P2DIR.x

P2OUT.x

Module X OUT

P2SEL.x

P2IN.x

Module X IN

P2IRQ.x

P2SEL.x

P2IES.x

P2IE.x

P2IFG.x

Set

Interrupt

Edge Select

Direction 0: Input 1: Output

Bus

Keeper

Pad Logic

P2.0/TA1.1/S15 P2.1/TA1.2/S14 P2.2/TA1.3/S13 P2.3/TA1.4/S12 P2.4/S11 P2.5/S10 P2.6/S9 P2.7/S8

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

Port P2 (P2.0 to P2.7) pin functions

PIN NAME (P2.X)

P2.0/TA1.1/S15 0

P2.1/TA1.2/S14 1

P2.2/TA1.3/S13 2

P2.3/TA1.4/S12 3

P2.4/S11 4

P2.5/S10 5

P2.6/S9 6

P2.7/S8 7

NOTES: 1. x: Don’t care

X FUNCTION

P2.x (I/O) I: 0, O: 1 0 0

Timer1_A5.TA1 1 1 0

S15 x x 1 (LCDS12)

P2.x (I/O) I: 0, O: 1 0 0

Timer1_A5.TA2 1 1 0

S14 x x 1 (LCDS12)

P2.x (I/O) I: 0, O: 1 0 0

Timer1_A5.TA3 1 1 0

S13 x x 1 (LCDS12)

P2.x (I/O) I: 0, O: 1 0 0

Timer1_A5.TA4 1 1 0

S12 x x 1 (LCDS12)

P2.x (I/O) I: 0, O: 1 0 0

S11 x x 1 (LCDS8)

P2.x (I/O) I: 0, O: 1 0 0

S10 x x 1 (LCDS8)

P2.x (I/O) I: 0, O: 1 0 0

S9 x x 1 (LCDS8)

P2.x (I/O) I: 0, O: 1 0 0

S8 x x 1 (LCDS8)

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

CONTROL BITS / SIGNALS

P2DIR.x P2SEL.x

LCDS8

LCDS12

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430F41x2 MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

APPLICATION INFORMATION

Port P3 pin schematic: P3.0 to P3.7 input/output with Schmitt trigger

LCDS16/20

Segment Sy

P3DIR.x

P3OUT.x

Module X OUT

P3SEL.x

P3IN.x

Module X IN

Pad Logic

Direction 0: Input 1: Output

Bus

Keeper

P3.0/TA1.2/S23 P3.1/TA1.3/S22 P3.2/TA1.4/S21 P3.3/TA0.0/TA1CLK/S20 P3.4/CAOUT/S19 P3.5/S18 P3.6/S17 P3.7/S16

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

Port P3 (P3.0 to P3.7) pin functions

///

PIN NAME (P3.X)

P3.0/TA1.2/S23 0

P3.1/TA1.3/S22 1

P3.2/TA1.4/S21 2

P3.3/TA0.0/TA1CLK/S20 3

P3.4/CAOUT/S19 4

P3.5/S18 5

P3.6/S17 6

P3.7/S16 7

NOTES: 1. x: Don’t care

X FUNCTION

P3.x (I/O) I: 0, O: 1 0 0

Timer1_A5.CCI2A 0 1 0

Timer1_A5.TA2 1 1 0

S23 x x 1 (LCDS20)

P3.x (I/O) I: 0, O: 1 0 0

Timer1_A5.CCI3A 0 1 0

Timer1_A5.TA3 1 1 0

S22 x x 1 (LCDS20)

P3.x (I/O) I: 0, O: 1 0 0

Timer1_A5.CCI4A 0 1 0

Timer1_A5.TA4 1 1 0

S21 x x 1 (LCDS20)

P3.x (I/O) I: 0, O: 1 0 0

Timer1_A5.TACLK 0 1 0

Timer0_A3.TA0 1 1 0

S20 x x 1 (LCDS20)

P3.x (I/O) I: 0, O: 1 0 0

CAOUT 1 1 0

S19 x x 1 (LCDS16)

P3.x (I/O) I: 0, O: 1 0 0

S18 x x 1 (LCDS16)

P3.x (I/O) I: 0, O: 1 0 0

S17 x x 1 (LCDS16)

P3.x (I/O) I: 0, O: 1 0 0

S16 x x 1 (LCDS16)

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

CONTROL BITS / SIGNALS

P3DIR.x P3SEL.x

LCDS16 LCDS20

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

APPLICATION INFORMATION

Port P4 pin schematic: P4.0 to P4.7 input/output with Schmitt trigger

LCDS0/4

Segment Sy

P4DIR.x

P4OUT.x

Module X Out

P4SEL.x

P4IN.x

Direction 0: Input 1: Output

Port P4 (P4.0 to P4.7) pin functions

PIN NAME (P4.X)

P4.0/S7 0

P4.1/S6 1

P4.2/S5 2

P4.3/S4 3

P4.4/S3 4

P4.5/S2 5

P4.6/S1 6

P4.7/ADC10CLK/S0 7

NOTES: 1. x: Don’t care

X FUNCTION

P4.x (I/O) I: 0, O: 1 0 0

S7 x x 1 (LCDS4)

P4.x (I/O) I: 0, O: 1 0 0

S6 x x 1 (LCDS4)

P4.x (I/O) I: 0, O: 1 0 0

S5 x x 1 (LCDS4)

P4.x (I/O) I: 0, O: 1 0 0

S4 x x 1 (LCDS4)

P4.x (I/O) I: 0, O: 1 0 0

S3 x x 1 (LCDS0)

P4.x (I/O) I: 0, O: 1 0 0

S2 x x 1 (LCDS0)

P4.x (I/O) I: 0, O: 1 0 0

S1 x x 1 (LCDS0)

P4.x (I/O) I: 0, O: 1 0 0

ADC10CLK 1 1 0

S0 x x 1 (LCDS0)

Bus

Keeper

Pad Logic

P4.0/S7 P4.1/S6 P4.2/S5 P4.3/S4 P4.4/S3 P4.5/S2 P4.6/S1 P4.7/ADC10CLK/S0

CONTROL BITS / SIGNALS

P4DIR.x P4SEL.x

LCDS4 LCDS0

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

APPLICATION INFORMATION

Port P5 pin schematic: P5.0, input/output with Schmitt trigger

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

LCDS24

Segment Sy

P5DIR.x

P5OUT.x

Module X OUT

P5SEL.x

P5IN.x

Module X IN

Port P5 (P5.0) pin functions

PIN NAME (P5.X)

P5.0/TA1.1/S24 0

NOTES: 1. x: Don’t care

P5.x (I/O) I: 0, O: 1 0 0

Timer1_A5.CCI1A 0 1 0

Timer1_A5.TA1 1 1 0

S24 x x 1

Pad Logic

Direction 0: Input 1: Output

FUNCTION

P5.0/TA1.1/S24

Bus

Keeper

CONTROL BITS / SIGNALS

P5DIR.x P5SEL.x LCDS24

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

APPLICATION INFORMATION

Port P5 pin schematic: P5.1 to P5.7, input/output with Schmitt trigger

LCD Signal

P5DIR.x

P5OUT.x

0/1

P5SEL.x

P5IN.x

Direction 0: Input

1: Output

Bus

Keeper

Pad Logic

P5.1/R23 P5.2/R13LCDREF P5.3/R03 P5.4/COM3 P5.5/COM2 P5.6/COM1 P5.7/COM0

Port P5 (P5.1 to P5.7) pin functions

PIN NAME (P5.X)

FUNCTION

P5.1/R23 1 P5.x (I/O) I: 0, O: 1 0

R23 x 1

P5.2/LCDREF/R13 2

P5.x (I/O) I: 0, O: 1 0

R13 or LCDREF x 1

P5.3/R03 3

P5.x (I/O) I: 0, O: 1 0

R03 x 1

P5.4/COM3 4

P5.x (I/O) I: 0, O: 1 0

COM3 x 1

P5.5/COM2 5

P5.x (I/O) I: 0, O: 1 0

COM2 x 1

P5.6/COM1 6

P5.x (I/O) I: 0, O: 1 0

COM1 x 1

P5.7/COM0 7

P5.x (I/O) I: 0, O: 1 0

COM0 x 1

NOTES: 1. x: Don’t care

CONTROL BITS / SIGNALS

P5DIR.x P5SEL.x

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

APPLICATION INFORMATION

///

Port P6 pin schematic: P6.0, input/output with Schmitt trigger

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

To Comparator_A

From Comparator_A

CAPD.4

ADC10AE0.2

INCH=2

To ADC10

P6DIR.x

P6OUT.x

Module Out

P6SEL.x

P6IN.x

Module X IN

Pad Logic

Direction 0: Input 1: Output

P6.0/TA1.2/A2/CA4

Bus

Keeper

Port P6 (P6.0) pin functions

PIN NAME (P6.X)

P6.0/TA1.2/A2/CA4 0

NOTES: 1. x: Don’t care

P6.x (I/O) 0 0 I: 0, O: 1 0

Timer1_A5.TA2 0 0 1 1

A2 x 1(y=2) x x

CA4 1 (CAPD.4) x x x

FUNCTION

CONTROL BITS / SIGNALS

CAPD ADC10AE0.y P6DIR.x P6SEL.x

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

APPLICATION INFORMATION

Port P6 pin schematic: P6.1 and P6.2, inpututput with Schmitt trigger

P6DIR.x

Module

direction

P6OUT.x

Module X OUT

P6SEL.x

P6IN.x

Module X IN

Direction 0: Input 1: Output

Port P6 (P6.1 and P6.2) pin functions

PIN NAME (P6.X)

P6.1/UCB0SOMI/UCB0SCL 1

P6.2/UCB0SIMO/UCB0SDA 2

NOTES: 1. x: Don’t care

2. The pin direction is controlled by the USCI module.

P6.x (I/O) I: 0, O: 1 0

UCB0SOMI/UCB0SCL (see Note 2) x 1

P6.x (I/O) I: 0, O: 1 0

UCB0SIMO/UCB0SDA (see Note 2) x 1

FUNCTION

Pad Logic

P6.1/UCB0SOMI/UCB0SCL P6.2/UCB0SIMO/UCB0SDA

CONTROL BITS / SIGNALS

P6DIR.x P6SEL.x

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MIXED SIGNAL MICROCONTROLLER

APPLICATION INFORMATION

Port P6 pin schematic: P6.3 and P6.4, input/output with Schmitt trigger

MSP430F41x2

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

To Comparator_A

From Comparator_A

CAPD.5/6

ADC10AE0.3/4

INCH=3/4

To ADC10

P6DIR.x

from Module

P6OUT.x

Module Out

P6SEL.x

P6IN.x

Module X IN

Pad Logic

Direction 0: Input 1: Output

Bus

Keeper

P6.3/UCB0STE/ UCA0CLK/A3/CA5/ V

eref-/Vref-

P6.4/UCB0CLK/ UCA0STE/A4/CA6/ V

eref+/Vref+

Port P6 (P6.3 and P6.4) pin functions

PIN NAME (P6.X)

P6.3/UCB0STE/ 3 UCA0CLK/A3/CA5/

eref--

ref--

P6.4/UCB0CLK/ 4 UCA0STE/A4/CA6/

eref+

ref+

NOTES: 1. x: Don’t care

2. The pin direction is controlled by the USCI module.

P6.x (I/O) 0 0 I: 0, O: 1 0

UCB0STE/UCA0CLK (see Note 2) 0 0 x 1

A3/V

eref--/Vref--

CA5 1 (CAPD.5) x x x

P6.x (I/O) 0 0 I: 0, O: 1 0

UCB0CLK/UCA0STE (see Note 2) 0 0 x 1

A4/V

eref+/Vref+

CA6 1 (CAPD.6) x x x

FUNCTION

CONTROL BITS / SIGNALS

CAPD ADC10AE0.y P6DIR.x P6SEL.x

x 1(y=3) x x

x 1(y=4) x x

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

APPLICATION INFORMATION

Port P6 pin schematic: P6.5 and P6.6, input/output with Schmitt trigger

INCHx = 5/6

To ADC10

ADC10AE0.5/6

P6DIR.x

Module

direction

P6OUT.x

Module X OUT

P6SEL.x

P6IN.x

Module X IN

Direction 0: Input 1: Output

Port P6 (P6.5 and P6.6) pin functions

PIN NAME (P6.X)

P6.5/UCA0RXD/ 5 UCA0SOMI/A5

P6.6/UCA0TXD/ 6 UCA0SIMO/A6

NOTES: 1. x: Don’t care

2. The pin direction is controlled by the USCI module.

P6.x (I/O) 0 I: 0, O: 1 0

UCA0RXD/UCA0SOMI (see Note 2) 0 x 1

A5 1(y=5) x x

P6.x (I/O) 0 I: 0, O: 1 0

UCA0TXD/UCA0SIMO (see Note 2) 0 x 1

A6 1(y=6) x x

FUNCTION

Bus

Keeper

Pad Logic

P6.5/UCA0RXD/ UCA0SOMI/A5 P6.6/UCA0TXD/ UCA0SIMO/A6

CONTROL BITS / SIGNALS

ADC10AE0.y P6DIR.x P6SEL.x

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

APPLICATION INFORMATION

///

Port P6 pin schematic: P6.7, input/output with Schmitt trigger

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

to SVS Mux

VLD = 15

To Comparator_A

From Comparator_A

CAPD.7

ADC10AE0.7

INCH=7

To ADC10

P6DIR.x

P6OUT.x

0/1

P6SEL.x

P6IN.x

Pad Logic

Direction 0: Input 1: Output

P6.7/A7/CA7/SVSIN

Bus

Keeper

Port P6 (P6.7) pin functions

PIN NAME (P6.X)

P6.7/A7/CA7/SVSIN 7

NOTES: 1. x: Don’t care

P7.x (I/O) 0 0 0 I: 0, O: 1 0

A7 0 x 1(y=7) x x

CA7 0 1 (CAPD.7) x x x

SVSIN 1 0 0 x x

FUNCTION

CONTROL BITS / SIGNALS

VLDx = 15 CAPD ADC10AE0 P6DIR.x P6SEL.x

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430F41x2

///

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

/APPLICATION INFORMATION

Port P7 pin schematic: P7.0 to P7.3, input/output with Schmitt trigger

LCDS32

Pad Logic

P7DIR.x

P7OUT.x

0/1

P7SEL.x

P7IN.x

To JTAG

From JTAG

Direction 0: Input 1: Output

Bus

Keeper

Port P7 (P7.0 to P7.3) pin functions

PIN NAME (P7.X)

P7.0/TDO/TDI/S32 0

P7.x (I/O) 0 I: 0, O: 1 0 0

TDO/TDI (see Note 1) 1 x x x

S32 0 x x 1

P7.1/TDI/TCLK/S33 1

P7.x (I/O) 0 I: 0, O: 1 0 0

TDI/TCLK(seeNote1) 1 x x x

S33 0 x x 1

P7.2/TMS/S34 2

P7.x (I/O) 0 I: 0, O: 1 0 0

TMS(seeNote1) 1 x x x

S34 0 x x 1

P7.3/TCK/S35 3

P7.3 (I/O) 0 I: 0, O: 1 0 0

TCK(seeNote1) 1 x x x

S35 0 x x 1

NOTES: 1. In JTAG Mode the internal pullup/pulldown resistors are disabled.

2. X: Don’t care.

FUNCTION

JTAG Mode P7DIR.x P7SEL.x LCDS32

P7.0/TDO/TDI/S32 P7.1/TDI/TCLK/S33 P7.2/TMS/S34 P7.3/TCK/S35

CONTROL BITS / SIGNALS

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MIXED SIGNAL MICROCONTROLLER

///

APPLICATION INFORMATION

Port P7 pin schematic: P7.4 and P7.5, input/output with Schmitt trigger

MSP430F41x2

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

To Comparator_A

From Comparator_A

CAPD.2/3

ADC10AE0.0/1

INCH=0/1

To ADC10

P7DIR.x

P7OUT.x

Module Out

P7SEL.x

P7IN.x

Module X IN

Pad Logic

Direction 0: Input 1: Output

Bus

Keeper

P7.4/TA1.4/A0/CA2 P7.5/TA1.3/A1/CA3

Port P7 (P7.4 and P7.5) pin functions

PIN NAME (P7.X)

P7.4/TA1.4/A0/CA2 4

P7.5/TA1.3/A1/CA3 5

NOTES: 1. x: Don’t care

P7.x (I/O) 0 0 I: 0, O: 1 0

Timer1_A5.TA4 0 0 1 1

Timer1_A5.CCI4B 0 0 0 1

A0 x 1(y=0) x x

CA2 1 (CAPD.2) x x x

P7.x (I/O) 0 0 I: 0, O: 1 0

Timer1_A5.TA3 0 0 1 1

Timer1_A5.CCI3B 0 0 0 1

A1 x 1(y=1) x x

CA3 1 (CAPD.3) x x x

FUNCTION

CONTROL BITS / SIGNALS

CAPD ADC10AE0.y P7DIR.x P7SEL.x

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

APPLICATION INFORMATION

Port P7 pin schematic: P7.6, input/output with Schmitt trigger

LCDS24

Segment Sy

P7DIR.x

P7OUT.x

Module X OUT

P7SEL.x

P7IN.x

Module X IN

Port P7 (P7.6) pin functions

PIN NAME (P7.X)

P7.6/TA0.2/S25 6

NOTES: 1. x: Don’t care

P7.x (I/O) I: 0, O: 1 0 0

Timer0_A3.CCI2A 0 1 0

Timer0_A3.TA2 1 1 0

S25 x x 1

Pad Logic

Direction 0: Input 1: Output

FUNCTION

P7.6/TA0.2/S25

Bus

Keeper

CONTROL BITS / SIGNALS

P7DIR.x P7SEL.x LCDS24

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

APPLICATION INFORMATION

JTAG pins: TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger

TDO

Controlled by JTAG

MSP430F41x2

JTAG

Test

and

Emulation

Module

Controlled by JTAG

TDI

TMS

TCK

Fuse

Burn & Test

Fuse

TDO/TDI

TDI/TCLK

TMS

During Programming Activity and During Blowing of the Fuse, Pin TDO/TDI Is Used to Apply the Test Input Data for JTAG Circuitry

TCK

JTAG fuse check mode

For details on the JTAG fuse check mode, see the MSP430 Memory Programming User’s Guide (SLAU265) chapter ”Fuse Check and Reset of the JTAG State Machine (TAP Controller)”.

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430F41x2 MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

Data Sheet Revision History

LITERATURE

NUMBER

SLAS648 Production Data release

Changed TDI/TCLK to TEST in Note 1 of “absolute maximum ratings” table (page 23)

SLAS648A

SLAS648B

SLAS648C Added note to functional block diagram (page 5)

SLAS648D

SLAS648E Changed limits on t

Changed lower limit of Storage temperature, Programmed device from --40Cto--55C i n “absolute maximum ratings”

table (page 23) Corrected Timer_A3 Signal Connections and Timer_A5 Signal Connections tables (pages 17, 18) Removed bullet indicating that Segment A contains calibration data (page 15)

In “absolute maximum ratings” table, changed LFXT1 crystal frequency, f ceramic resonator) and from 1000 to 1 MHz (with crystal) (page 23) In “crystal oscillator, LFXT1, high frequency modes” table, changed f crystal resonator (page 36)t

d(SVSon)

parameter (page 31)

SUMMARY

MIN from 450 to 0.45 MHz (with

(LFXT1)

MAX from 8 to 6 MHz for both ceramic and

LFXT1

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

30-Aug-2018

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

MSP430F4132IPM ACTIVE LQFP PM 64 160 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 M430F4132

MSP430F4132IPMR ACTIVE LQFP PM 64 1000 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 M430F4132

MSP430F4132IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 M430

F4132

MSP430F4132IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 M430

F4132

MSP430F4152IPM ACTIVE LQFP PM 64 160 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 M430F4152

MSP430F4152IPMR ACTIVE LQFP PM 64 1000 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 M430F4152

MSP430F4152IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 M430

F4152

MSP430F4152IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR M430

F4152

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

PACKAGE OPTION ADDENDUM

www.ti.com

30-Aug-2018

Addendum-Page 2

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

PACKAGE MATERIALS INFORMATION

www.ti.com 1-Nov-2018

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

MSP430F4132IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2

MSP430F4132IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2

MSP430F4132IRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2

MSP430F4152IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2

MSP430F4152IRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2

Type

Package

Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 1-Nov-2018

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

MSP430F4132IPMR LQFP PM 64 1000 367.0 367.0 45.0 MSP430F4132IRGZR VQFN RGZ 48 2500 367.0 367.0 38.0 MSP430F4132IRGZT VQFN RGZ 48 250 210.0 185.0 35.0

MSP430F4152IPMR LQFP PM 64 1000 350.0 350.0 43.0 MSP430F4152IRGZT VQFN RGZ 48 250 210.0 185.0 35.0

Pack Materials-Page 2

GENERIC PACKAGE VIEW

VQFN - 1 mm max heightRGZ 48

7 x 7, 0.5 mm pitch

PLASTIC QUADFLAT PACK- NO LEAD

Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details.

4224671/A

www.ti.com

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

PACKAGE OUTLINE

4219044/A 05/2018

www.ti.com

VQFN - 1 mm max height

PLASTIC QUADFLAT PACK- NO LEAD

RGZ0048A

0.08

0.1 C A B

0.05 C

SYMM

PIN 1 INDEX AREA

7.1

6.9

7.1

6.9

1 MAX

0.05

0.00

SEATING PLANE

5.15±0.1

2X 5.5

5.5

44X 0.5

48X

0.5

0.3

48X

0.30

0.18

PIN1 ID

(OPTIONAL)

(0.2) TYP

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

EXAMPLE BOARD LAYOUT

4219044/A 05/2018

www.ti.com

VQFN - 1 mm max height

RGZ0048A

PLASTIC QUADFLAT PACK- NO LEAD

SYMM

LAND PATTERN EXAMPLE

SCALE: 15X

( 5.15)

2X (6.8)

(6.8)

48X (0.6)

48X (0.24)

44X (0.5)

2X (5.5)

(5.5)

21X (Ø0.2) VIA

TYP

(R0.05)

TYP

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

METAL

SOLDER MASK

OPENING

EXPOSED METAL

SOLDER MASK DETAILS

SOLDER MASK OPENING

METAL UNDER SOLDER MASK

EXPOSED METAL

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

(1.26)

2X (1.26)

2X (1.065)

(1.065)

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

EXAMPLE STENCIL DESIGN

4219044/A 05/2018

www.ti.com

VQFN - 1 mm max height

RGZ0048A

PLASTIC QUADFLAT PACK- NO LEAD

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

67% PRINTED COVERAGE BY AREA

SCALE: 15X

SYMM

( 1.06)

2X (6.8)

(6.8)

48X (0.6)

48X (0.24)

44X (0.5)

2X (5.5)

(5.5)

(R0.05)

TYP

(0.63)

2X (0.63)

(1.26)

MECHANICAL DATA

MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996

PM (S-PQFP-G64) PLASTIC QUAD FLATPACK

0,50

0,27 0,17

7,50 TYP

10,20

9,80

12,20

11,80

0,08

0,05 MIN

0,13 NOM

Gage Plane

0,25

0°–7°

1,45 1,35

1,60 MAX

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 D. May also be thermally enhanced plastic with leads connected to the die pads.

0,75 0,45

Seating Plane

0,08

4040152/C 11/96

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Texas Instruments MSP430F4152IPM, MSP430F4132IRGZ, MSP430F4152IRGZ, MSP430F4132IPM User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual