Texas Instruments MSP430F4152IPM, MSP430F4132IRGZ, MSP430F4152IRGZ, MSP430F4132IPM User Manual

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

D Low Supply-Voltage Range, 1.8 V to 3.6 V D Ultralow Power Consumption

Active Mode: 220 Aat1MHz,2.2V Standby Mode: 0.9 A Off Mode (RAM Retention): 0.1 A

D Five Power-Saving Modes D Wake-Up From Standby Mode in Less

Than 6 s

-- Internal Very Low Power, Low-Frequency Oscillator

D 16-Bit RISC Architecture,

125-ns Instruction Cycle Time

D 16-Bit Timer_A With Three

Capture/Compare Registers

D 16-Bit Timer_A With Five Capture/Compare

Registers

D Two Universal Serial Communication

Interfaces (USCIs) USCI_A0

-- Enhanced UART Supporting Auto-Baudrate Detection

-- IrDA Encoder and Decoder

-- Synchronous SPI

USCI_B0

-- I 2 C

-- Synchronous SPI

D Supply Voltage Supervisor/Monitor With

Programmable Level Detection

D Integrated LCD Driver With Contrast

Control for Up to 144 Segments

D Basic Timer With Real Time Clock Feature D Brownout detector D On-Chip Comparator for Analog Signal

Compare Function or Slope A/D

D 10-Bit 200-ksps Analog-to-Digital (A/D)

Converter With Internal Reference, Sample-and-Hold, Autoscan, and Data Transfer Controller

D Serial Onboard Programming,

No External Programming Voltage Needed Programmable Code Protection by Security Fuse

D Bootstrap Loader D On-Chip Emulation Module D Family Members Include:

MSP430F4152: 16KB+256B Flash Memory

512B RAM

MSP430F4132: 8KB+256B Flash Memory

512B RAM

D Available in 64-Pin QFP Package and

48-Pin QFN Package (See Available Options)

D For Complete Module Descriptions, See

The MSP430x4xx Family User’s Guide, Literature Number SLAU056

description

The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generator that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 s.

The MSP430F41x2 is a microcontroller configuration with two 16-bit timers, a basic timer with a real--time clock, a 10-bit A/D converter, a versatile analog comparator, two universal serial communication interfaces, up to 48 I/O pins, and a liquid crystal display driver.

Typical applications for this device include analog and digital sensor systems, remote controls, thermostats, digital timers, hand-held meters, etc.

This integrated circuit can be damaged by ESD. Texas Instrum ents recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. These devices have limited built-in ESD protection.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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MSP430F41x2 MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

AVAILABLE OPTIONS

-- 4 0 Cto85C

†

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.

‡

Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

PLASTIC 64-PIN QFP (PM) PLASTIC 48-PIN QFN (RGZ)

MSP430F4152IPM MSP430F4132IPM

PACKAGED DEVICES

DEVELOPMENT TOOL SUPPORT

All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging and programming through easy to use development tools. Recommended hardware options include the following:

D Debugging and Programming Interface

-- MSP-FET430UIF (USB)

-- MSP-FET430PIF (Parallel Port)

D Debugging and Programming Interface with Target Board

†

‡

MSP430F4152IRGZ MSP430F4132IRGZ

-- MSP-FET430U64A (PM package)

D Production Programmer

-- MSP-GANG430

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pin designation, MSP430F41x2IPM (QFP)

P6.1/UCB0SOMI/UCB0SCL

P6.2/UCB0SIMO/UCB0SDA

P6.3/UCB0STE/UCA0CLK/A3/CA5/Ve

P6.4/UCB0CLK/UCA0STE/A4/CA6/Ve

P6.5/UCA0RXD/UCA0SOMI/A5

P6.6/UCA0TXD/UCA0SIMO/A6

P6.7/A7/CA7/SVSIN P4.7/ADC10CLK/S0

REF-/VREF-

REF+/VREF+

XIN

XOUT

P4.6/S1 P4.5/S2 P4.4/S3 P4.3/S4

1 2 3 4 5 6 7

8 9 10

11 12 13 14 15 16

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

P6.0/TA1.2/A2/CA4

P7.5/TA1.3/A1/CA3

64 63

62 61 60 59 58 57 56 55 54 53 52 51 50 49

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

RST/NMI/SBWTDIO

P7.4/TA1.4/A0/CA2

TEST/SBWTCLK

P7.3/TCK/S35

64-pin

PM PACKAGE

(TOP VIEW)

P7.2/TMS/S34

P7.1/TDI/TCLK/S33

P7.0/TDO/TDI/S32

P1.0/TA0.0/S31

P1.1/TA0.0/MCLK/S30

P1.2/TA0.1/S29

P1.3/TA1.0/SVSOUT/S28

P1.4/TA1.0/S27

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

MSP430F41x2

P1.5/TA0CLK/CAOUT/S26 P1.6/ACLK/CA0 P1.7/TA0CLK/CAOUT/CA1 P7.6/TA0.2/S25 P5.0/TA1.1/S24 R33/LCDCAP P5.1/R23 P5.2/R13/LCDREF P5.3/R03 P5.4/COM3 P5.5/COM2 P5.6/COM1 P5.7/COM0 P3.0/TA1.2/S23 P3.1/TA1.3/S22 P3.2/TA1.4/S21

P4.2/S5

P4.1/S6

P4.0/S7

P2.7/S8

P2.6/S9

P2.5/S10

P2.4/S11

P2.3/TA1.4/S12

P2.2/TA1.3/S13

P2.1/TA1.2/S14

P2.0/TA1.1/S15

P3.7/S16

P3.6/S17

P3.5/S18

P3.4/CAOUT/S19

P3.3/TA0.0/TA1CLK/S20

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MSP430F41x2 MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

pin designation, MSP430F41x2IRGZ (QFN)

P6.0/TA1.2/A2/CA4

48 47 46 45 44 43 42 41 40 39 38 37

XIN

13 14 15 16 17 18 19 20 21 22 23 24

RGZ PACKAGE

P6.1

P6.2

XOUT

P6.7/A7/CA7/SVSIN

P4.7/ADC10CLK/S0

P4.6/S1

P4.5/S2

P4.4/S3

P4.3/S4

†

TEST/SBWTCLK

P7.5/TA1.3/A1/CA3

P7.4/TA1.4/A0/CA2

48-pin

(TOP VIEW)

RST/NMI/SBWTDIO

P7.3/TCK/S35

P7.2/TMS/S34

P7.1/TDI/TCLK/S33

P7.0/TDO/TDI/S32

P1.0/TA0.0/S31

P1.1/TA0.0/MCLK/S30

P1.5/TA0CLK/CAOUT/S26

P1.6/ACLK/CA0

P1.7/TA0CLK/CAOUT/CA1

R33/LCDCAP

P5.1/R23

P5.2/R13/LCDREF

P5.3/R03

P5.4/COM3

P5.5/COM2

P5.6/COM1

P5.7/COM0

P4.2/S5

P4.1/S6

P4.0/S7

P2.7/S8

P2.6/S9

P2.5/S10

P2.4/S11

P2.3/TA1.4/S12

P2.2/TA1.3/S13

†

“Not available” pins in the 48-pin package should be initialized to output direction.

P2.1/TA1.2/S14

P2.0/TA1.1/S15

P3.4/CAOUT/S19

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functional block diagram

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

XIN XOUT

Oscillators

FLL+

VLO

MCLK

CPU 64kB

incl. 16

Registers

EEM

JTAG

Interface

S p y --B i --

Wire

ACLK

SMCLK

DVCC DVSS

Flash

16kB

8kB

MAB

MDB

Brownout

Protection

SVS, SVM

RST/NMI

RAM

512B 512B

LCD_A

144

Segments

1,2,3,4

Mux

AVC C AVSS P1.x/P2.x

ADC10

10--bit

8 Channels

Autoscan

DTC

Comparator

_A+

USCI A0

UART/

LIN,

IrDA, SPI

USCI B 0 SPI, I2C

Watchdog

WDT+

15--Bit

capability

Timer _A3

Registers

Ports

P1/P2

2x8 I/O

Interrupt

3CC

NOTE: The USCI A0 and USCI B0 cannot be used in the 48-pin package options (RGZ).

2x8

P3.x/P4.x

2x8

Ports

P3/P4

2x8 I/O

Timer _A5

5CC

Registers

P5.x/P6.x

2x8

Ports

P5/P6

2x8 I/O

Basic

Timer &

Real--

Time

Clock

P7.x

1x7

Port

1x7 I/O

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MSP430F41x2

I/ODESCRIPTIO

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

TERMINAL

NO.

NAME

P1.0/TA0.0/S31 53 37 I/O

P1.1/TA0.0/ MCLK/S30

P1.2/TA0.1/S29 51 -- I/O

P1.3/TA1.0/ SVSOUT/S28

P1.4/TA1.0/S27 49 -- I/O

P1.5/TA0CLK/ CAOUT/S26

P1.6/ACLK/CA0 47 34 I/O

P1.7/TA0CLK CAOUT/CA1

P2.0/TA1.1/S15 27 23 I/O

P2.1/TA1.2/S14 26 22 I/O

P2.2/TA1.3/S13 25 21 I/O

P2.3/TA1.4/S12 24 20 I/O

P2.4/S11 23 19 I/O

P2.5/S10 22 18 I/O

P2.6/S9 21 17 I/O

P2.7/S8 20 16 I/O

PIN48PIN

52 36 I/O

50 -- I/O

48 35 I/O

46 33 I/O

General-purpose digital I/O pin Timer0_A3, capture: CCI0A input, compare: Out0 output LCD segment output

General-purpose digital I/O pin Timer0_A3, capture: CCI0B input MCLK signal output LCD segment output

General-purpose digital I/O pin Timer0_A3, capture: CCI1A input, compare: Out1 output LCD segment output

General-purpose digital I/O pin Timer1_A5, capture: CCI0B input SVS comparator output LCD segment output

General-purpose digital I/O pin/ Timer1_A5, capture: CCI0A input, compare: Out0 output LCD segment output

General-purpose digital I/O pin Timer0_A3, clock signal TACLK input Comparator_A output LCD segment output

General-purpose digital I/O pin Comparator_A input 0 ACLK signal output

General-purpose digital I/O pin Timer0_A3, clock signal TACLK input Comparator_A output Comparator_A input 1

General-purpose digital I/O pin Timer1_A5, compare: Out1 Output LCD segment output

General-purpose digital I/O pin Timer1_A5, compare: Out2 Output LCD segment output

General-purpose digital I/O pin Timer1_A5, compare: Out3 Output LCD segment output

General-purpose digital I/O pin Timer1_A5, compare: Out4 output LCD segment output

General-purpose digital I/O pin LCD segment output

Terminal Functions

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TERMINAL

I/ODESCRIPTIO

NO.

NAME

P3.0/TA1.2/S23 35 -- I/O

P3.1/TA1.3/S22 34 -- I/O

P3.2/TA1.4/S21 33 -- I/O

P3.3/TA0.0/ TA1CLK/S20

P3.4/CAOUT/S19 31 24 I/O

P3.5/S18 30 -- I/O

P3.6/S17 29 -- I/O

P3.7/S16 28 -- I/O

P4.0/S7 19 15 I/O

P4.1/S6 18 14 I/O

P4.2/S5 17 13 I/O

P4.3/S4 16 12 I/O

P4.4/S3 15 11 I/O

P4.5/S2 14 10 I/O

P4.6/S1 13 9 I/O

P4.7/ADC10CLK/ S0

P5.0/TA1.1/S24 44 -- I/O

LCDCAP/R33 43 32 I/O

P5.1/R23 42 31 I/O

P5.2/LCDREF/ R13

PIN48PIN

32 -- I/O

12 8 I/O

41 30 I/O

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

Terminal Functions (continued)

General-purpose digital I/O pin Timer1_A5, capture: CCI2A input, compare: Out2 output LCD segment output

General-purpose digital I/O pin Timer1_A5, capture: CCI3A input, compare: Out3 output LCD segment output

General-purpose digital I/O pin Timer1_A5, capture: CCI4A input, compare: Out4 output LCD segment output

General-purpose digital I/O pin Timer0_A3, compare: Out0 output Timer1_A5, clock signal TACLK input LCD segment output

General-purpose digital I/O pin Comparator_A output LCD segment output

General-purpose digital I/O pin LCD segment output

General-purpose digital I/O pin ADC10, conversion clock LCD segment output

General-purpose digital I/O pin Timer1_A5, capture: CCI1A input, compare: Out1 output LCD segment output

Capacitor connection for LCD charge pump input port of the most positive analog LCD level (V4)

General-purpose digital I/O pin input port of the second most positive analog LCD level (V3)

General-purpose digital I/O pin External LCD reference voltage input input port of the third most positive analog LCD level (V3 or V2)

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MSP430F41x2

I/ODESCRIPTIO

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

Terminal Functions (continued)

TERMINAL

NO.

NAME

P5.3/R03 40 29 I/O

P5.4/COM3 39 28 I/O

P5.5/COM2 38 27 I/O

P5.6/COM1 37 26 I/O

P5.7/COM0 36 25 I/O

P6.0/TA1.2/A2†/ CA4

P6.1/ UCB0SOMI UCB0SCL

P6.2/ UCB0SIMO UCB0SDA

†

P6.3/UCB0STE/ UCA0CLK/A3/ CA5/V

eref--/Vref--

P6.4/UCB0CLK/ UCA0STE/A4/ CA6/V

eref+/Vref+

P6.5/UCA0RXD/ UCA0SOMI/A5

P6.6/UCA0TXD/ UCA0SIMO/A6

P6.7/A7/CA7/ SVSIN

P7.0/TDO/TDI/ S32

P7.1/TDI/TCLK/ S33

P7.2/TMS/S34 56 40 I/O General-purpose digital I/O pin

†

64-pin package devices only

PIN48PIN

General-purpose digital I/O pin input port of the fourth most positive analog LCD level (V1)

General-purpose digital I/O pin common output, COM0--3 are used for LCD backplanes

General-purpose digital I/O pin

63 47 I/O

Timer1_A5, compare: Out2 output ADC10 analog input A2

†

Comparator_A input 4

1 1 I/O

2 2 I/O

General-purpose digital I/O pin USCI B0 slave out/master in in SPI mode, SCL I

General-purpose digital I/O pin USCI B0 slave in/master out in SPI mode, SDA I

General-purpose digital I/O pin

3 -- I/O

USCI B0 slave transmit enable/USCI A0 clock input/output ADC10 analog input A3 / negative reference Comparator_A input 5

General-purpose digital I/O pin

4 -- I/O

USCI B0 clock input/output, USCI A0 slave transmit enable ADC10 analog input A4/ positive reference Comparator_A input 6

General-purpose digital I/O pin

5 -- I/O

USCI A0 receive data input in UART mode, slave data out/master in in SPI mode ADC10 analog input A5

General-purpose digital I/O pin

6 -- I/O

USCI A0 transmit data output in UART mode, slave data i n/master out SPI mode ADC10 analog input A6

General-purpose digital I/O pin

11 7 I/O

ADC10 analog input A7 Comparator_A input 7 SVS input

54 38 I/O General-purpose digital I/O pin

JTAG test data output terminal or test data input in programming an test LCD segment output

55 39 I/O General-purpose digital I/O pin

JTAG test data input or test clock input in programming an test LCD segment output

JTAG test mode select, input terminal for device programming and test LCD segment output

C clock in I2C mode

CdatainI2C mode

†

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MSP430F41x2

I/ODESCRIPTIO

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

Terminal Functions (continued)

TERMINAL

NO.

NAME

P7.3/TCK/S35 57 41 I/O General-purpose digital I/O pin

P7.4/TA1.4/ A0/CA2

P7.5/TA1.3/ A1/CA3

P7.6/TA0.2/S25 45 -- I/O

XOUT 9 5 O Output port for crystal oscillator XT1. Standard or watch crystals can be connected.

XIN 8 4 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.

RST/NMI/ SBWTDIO

TEST/SBWTCLK 59 43 I Selects test mode for JTAG pins on Port7. The device protection fuse is connected to TEST.

Thermal Pad NA NA NA QFN package pad (RGZ package only). Connection to DVSSis recommended.

PIN48PIN

Test clock input for device programming and test LCD segment output

General-purpose digital I/O pin

60 44 I/O

61 45 I/O

64 48 Analog supply voltage, positive terminal

62 46 Analog supply voltage, negative terminal

7 3 Digital supply voltage, positive terminal. Supplies all digital parts.

10 6 Digital supply voltage, negative terminal. Supplies all digital parts.

58 42 I Reset or nonmaskable interrupt input

Timer1_A5, capture: CCI4B input, compare: Out4 output ADC10 analog input A0 Comparator_A input 2

General-purpose digital I/O pin Timer1_A5, capture: CCI3B input, compare: Out3 output ADC10 analog input A1 Comparator_A input 3

General-purpose digital I/O pin Timer0_A3, capture: CCI2A input, compare: Out2 output LCD segment output

Spy-Bi-Wire test data input/output during programming and test

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MSP430F41x2 MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

short-form description

CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses and can be handled with all instructions.

instruction set

The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 1 shows examples of the three types of instruction formats; Table 2 shows the address modes.

Program Counter

Stack Pointer

Status Register

Constant Generator

General-Purpose Register

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R10

R11

R12

R13

R14

R15

Table 1. Instruction Word Formats

Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 ------> R5

Single operands, destination only e.g., CALL R8 PC ---->(TOS), R8----> PC

Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0

Table 2. Address Mode Descriptions

ADDRESS MODE S D SYNTAX EXAMPLE OPERATION

Indexed F F MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) —> M(6+R6)

Symbolic (PC relative) F F MOV EDE,TONI M(EDE) —> M(TONI)

Absolute F F MOV&MEM,&TCDAT M(MEM) —> M(TCDAT)

Indirect F MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) —> M(Tab+R6)

Indirect

autoincrement

Immediate F MOV #X,TONI MOV #45,TONI #45 —> M(TONI)

NOTE: S = source, D = destination

F MOV @Rn+,Rm MOV @R10+,R11

MOV Rs,Rd MOV R10,R11 R10 —> R11

M(R10) —> R11

R10+2—>R10

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

operating modes

The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

D Active mode (AM)

-- All clocks are active

D Low-power mode 0 (LPM0)

-- CPU is disabled

-- ACLK and SMCLK remain active

-- FLL+ loop control remains active

D Low-power mode 1 (LPM1)

-- CPU is disabled

-- ACLK and SMCLK remain active

-- FLL+ loop control is disabled

D Low-power mode 2 (LPM2)

-- CPU is disabled

-- MCLK, FLL+ loop control, and DCOCLK are disabled

-- DCO’s dc generator remains enabled

-- ACLK remains active

D Low-power mode 3 (LPM3)

-- CPU is disabled

-- MCLK, FLL+ loop control, and DCOCLK are disabled

-- DCO’s dc generator is disabled

-- ACLK remains active

D Low-power mode 4 (LPM4)

-- CPU is disabled

-- ACLK is disabled

-- MCLK, FLL+ loop control, and DCOCLK are disabled

-- DCO’s dc generator is disabled

-- Crystal oscillator is stopped

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MSP430F41x2 MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the address range 0xFFFF to 0xFFC0. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

If the reset vector (located at address 0xFFFE) contains 0xFFFF (e.g., flash is not programmed), the CPU goes into LPM4 immediately after power-up.

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT

Power-Up

External Reset

Watchdog

PC Out--of --Range (see Note 4)

Flash Memory Access Violation

NOTES: 1. Multiple source flags

Flash Memory

NMI

Oscillator Fault

Timer_A5 TA1CCR0 CCIFG0 (see Note 2) Maskable 0xFFFA 13

Timer_A5

Comparator_A+ CAIFG Maskable 0xFFF6 11

Watchdog Timer+ WDTIFG Maskable 0xFFF4 10

USCI_A0/B0 Receive

USCI_A0/B0 Transmit

ADC10 ADC10IFG (see Note 2) Maskable 0xFFEE 7

Timer_A3 TACCR0 CCIFG0 (see Note 2) Maskable 0xFFEC 6

Timer_A3

I/O Port P1 (Eight Flags) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) Maskable 0xFFE8 4

I/O Port P2 (Eight Flags) P2IFG.0 to P2IFG.7 (see Notes 1 and 2) Maskable 0xFFE2 1

Basic Timer1/RTC BTIFG Maskable 0xFFE0 0, lowest

2. Interrupt flags are located in the module.

3. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh). (Non)maskable: the individual interrupt -enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

4. Access and key violations, KEYV and ACCVIFG.

UCB0STAT UCALIFG, UCNACKIFG, UCSTTIFG,

NMIIFG (see Notes 1 and 3)

OFIFG (see Notes 1 and 3)

ACCVIFG (see Notes 1, 2, and 4)

TA1CCR1 to TACCR4 CCIFGs, and TAIFG (see Notes 1 and 2)

UCA0RXIFG (see Note 1),

UCB0RXIFG (SPI mode), or

UCA0TXIFG (see Note 1),

UCB0TXIFG (SPI mode), or

UCB0RXIFG and UCB0TXIFG (I2C mode)

TACCR1 CCIFG1 and TACCR2 CCIFG2,

TAIFG (see Notes 1 and 2)

PORIFG RSTIFG WDTIFG

KEYV

(see Note 1)

UCSTPIFG (I2C mode)

(see Note 1)

Reset 0xFFFE 15, highest

(Non)maskable (Non)maskable (Non)maskable

Maskable 0xFFF8 12

Maskable 0xFFF2 9

Maskable 0xFFF0 8

Maskable 0xFFEA 5

WORD

ADDRESS

0xFFFC 14

0xFFE6 3

0xFFE4 2

PRIORITY

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

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special function registers

Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access.

interrupt enable 1 and 2

Address76543210

00h

WDTIE Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog

timer is configured in interval timer mode.

OFIE Oscillator fault enable

NMIIE (Non)maskable interrupt enable

ACCVIE Flash access violation interrupt enable

Address76543210

01h

BTIE

rw--0 rw--0 rw--0 rw--0 rw --0

ACCVIE NMIIE OFIE WDTIE

rw--0 rw--0 rw--0 rw --0

UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE

UCA0RXIE USCI_A0 receive interrupt enable

UCA0TXIE USCI_A0 transmit interrupt enable

UCB0RXIE USCI_B0 receive interrupt enable

UCB0TXIE USCI_B0 transmit interrupt enable

BTIE Basic timer interrupt enable

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SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

interrupt flag register 1 and 2

Address76543210

02h

WDTIFG Set on watchdog timer overflow (in watchdog mode) or security key violation.

Reset on V

power-up or a reset condition at RST/NMI pin in reset mode.

OFIFG Flag set on oscillator fault

RSTIFG External reset interrupt flag. Set on a reset condition at RST

on V

power-up.

PORIFG Power-on interrupt flag. Set on V

NMIIFG Set via RST

Address76543210

03h

BTIFG

rw--0 rw--1 rw--0 rw--1 rw --0

/NMI-pin

NMIIFG RSTIFG PORIFG OFIFG WDTIFG

rw--0 rw-- (0) rw--(1) rw--1 rw--(0)

/NMI pin in reset mode. Reset

power--up.

UCB0

TXIFG

UCB0

RXIFG

UCA0

TXIFG

UCA0

RXIFG

UCA0RXIFG USCI_A0 receive interrupt flag

UCA0TXIFG USCI_A0 transmit interrupt flag

UCB0RXIFG USCI_B0 receive interrupt flag

UCB0TXIFG USCI_B0 transmit interrupt flag

BTIFG Basic Timer1 interrupt flag

Legend rw:

rw-0,1: rw-(0,1):

Bit can be read and written. Bit can be read and written. It is Reset or set by PUC. Bit can be read and written. It is Reset or set by POR.

SFR bit is not present in device

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

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memory organization

MSP430F4152 MSP430F4132

Memory Main: interrupt vector Main: code memory

Information memory Size

Boot memory Size

RAM Size 512B

Peripherals 16-bit

bootstrap loader (BSL)

The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the MSP430 Memory Programming User’s Guide, literature number SLAU265.

Size Flash Flash

Flash

ROM

8-bit

8-bit SFR

16KB 0FFFFh -- 0FFE0h 0FFFFh -- 0C000h

256 Byte

010FFh -- 01000h

1KB

0FFFh -- 0C00h

03FFh -- 0200h

01FFh -- 0100h

0FFh -- 010h

0Fh -- 00h

8KB 0FFFFh -- 0FFE0h 0FFFFh -- 0E000h

256 Byte

010FFh -- 01000h

1KB

0FFFh -- 0C00h

512B

03FFh -- 0200h

01FFh -- 0100h

0FFh -- 010h

0Fh -- 00h

BSL FUNCTION PM PACKAGE PINS RGZ PACKAGE PINS

Data transmit 53 -- P1.0 37 -- P1.0

Data receive 52 -- P1.1 36 -- P1.1

flash memory (Flash)

The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

D Flash memory has n segments of main memory and four segments of information memory (A to D) of

64 bytes each. Each segment in main memory is 512 bytes in size.

D Segments 0 to n may be erased in one step, or each segment may be individually erased.

D Segments A to D can be erased individually, or as a group with segments 0 to n.

Segments A to D are also called information memory.

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MSP430F41x2 MIXED SIGNAL MICROCONTROLLER

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peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide, literature number SLAU056.

oscillator and system clock

The clock system in the MSP430F41x2 is supported by the FLL+ module that includes support for a 32768-Hz watch crystal oscillator, an internal very low-power low--frequency oscillator, an internal digitally-controlled oscillator (DCO), and an 8-MHz high-frequency crystal oscillator (XT1). The FLL+ clock module is designed to meet the requirements of both low system cost and low power consumption. The FLL+ features a digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator,stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 s. The FLL+ module provides the following clock signals:

D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, or a very

low-power LF oscillator

D Main clock (MCLK), the system clock used by the CPU D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules D ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8

brownout, supply voltage supervisor

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset).

The CPU begins code execution after the brownout circuit releases the device reset. However, V have ramped to V reaches V

CC(min)

. If desired, the SVS circuit can be used to determine when VCCreaches V

at that time. The user must insure the default FLL+ settings are not changed until V

CC(min)

digital I/O

There are seven 8-bit I/O ports implemented—ports P1 through P7. Port P7 is a 7-bit I/O port.

D All individual I/O bits are independently programmable. D Any combination of input, output, and interrupt conditions is possible. D Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2. D Read/write access to port-control registers is supported by all instructions.

may not

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MSP430F41x2

DEVICEINPUT

MODUL

TimerNA

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

watchdog timer (WDT+)

The primary function of the WDT+ module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.

Basic Timer1 and Real-Time Clock (RTC)

The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. The Basic Timer1 is extended to provide an integrated real-time clock (RTC). An internal calendar compensates for month with less than 31 days and includes leap year correction.

LCD_A driver with regulated charge pump

The LCD_A driver generates the segment and common signals required to drive an LCD display. The LCD_A controller has dedicated data memory to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2--MUX, 3--MUX, and 4--MUX LCDs are supported by this peripheral. The module can provide a LCD voltage independent of the supply voltage via an integrated charge pump. Furthermore it is possible to control the level of the LCD voltage and thus contrast in software.

Timer0_A3

Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

TIMER_A3 SIGNAL CONNECTIONS

INPUT PIN NUMBER

PM RGZ

48 -- P1.5

46 -- P1.7

48 -- P1.5 35 -- P1.5 TA0CLK TACLK

53 -- P1.0 37 -- P1.0 TA0.0 CCI0A 53 -- P1.0 37 -- P1.0

52 -- P1.1 36 -- P1.1 TA0.0 CCI0B

51 -- P1.2 -- TA0 . 1 CCI1A 51 -- P1.2

45 -- P7.6 -- TA0 . 2 CCI2A 45 -- P7.6 --

35 -- P1.5

33 -- P1.7

DEVICE INPUT MODULE MODULE

SIGNAL

TA0CLK TA C LK

ACLK ACLK

SMCLK SMCLK

CAOUT (internal) CCI1B

ACLK (internal) CCI2B

INPUT NAME

GND

BLOCK

Timer N

CCR0 TA0

CCR1 TA1

CCR2 TA2

MODULE

OUTPUT

SIGNAL

OUTPUT PIN NUMBER

PM RGZ

32 -- P3.3 --

ADC10 (internal) ADC10 (internal)

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MSP430F41x2

DEVICEINPUT

MODUL

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

Timer1_A5

Timer_A5 is a 16-bit timer/counter with five capture/compare registers. Timer_A5 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A5 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

TIMER_A5 SIGNAL CONNECTIONS

INPUT PIN NUMBER

PM RGZ

32 -- P3.3 -- TA1CLK TA C LK

32 -- P3.3 -- TA1CLK TACLK

49 -- P1.4 -- TA1 . 0 CCI0A 49 -- P1.4 --

50 -- P1.3 -- TA1 . 0 CCI0B

44 -- P5.0 -- TA1 . 1 CCI1A 44 -- P5.0 --

35 -- P3.0 -- TA1 . 2 CCI2A 35 -- P3.0 --

34 -- P3.1 -- TA1 . 3 CCI3A 34 -- P3.1 --

61 -- P7.5 45 -- P7.5 TA1.3 CCI3B

33 -- P3.2 -- TA1 . 4 CCI4A 33 -- P3.2 --

60 -- P7.4 44 -- P7.4 TA1.4 CCI4B

DEVICE INPUT MODULE MODULE

SIGNAL

ACLK ACLK

SMCLK SMCLK

CAOUT (internal) CCI1B

ACLK (internal) CCI2B

INPUT NAME

GND

BLOCK

Timer N

CCR0 TA0

CCR1 TA1

CCR2 TA2

CCR3 TA3

CCR4 TA4

MODULE

OUTPUT

SIGNAL

OUTPUT PIN NUMBER

PM RGZ

ADC10 (internal) ADC10 (internal)

27 -- P2.0 23 -- P2.0

ADC10 (internal) ADC10 (internal)

26 -- P2.1 22 -- P2.1

63 -- P6.0 47 -- P6.0

25 -- P2.2 21 -- P2.2

61 -- P7.5 45 -- P7.5

24 -- P2.3 20 -- P2.3

60 -- P7.4 44 -- P7.4

universal serial communication interface (USCI) (USCI_A0, USCI_B0)

The USCI module is used for serial data communication. The USCI module supports synchronous communication protocols like SPI (3 or 4 pin), I2C and asynchronous communication protocols like UART, enhanced UART with automatic baudrate detection (LIN), and IrDA.

USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.

USCI_B0 provides support for SPI (3 or 4 pin) and I2C.

Comparator_A+

The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals.

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MSP430F41x2

Timer0_A3Capture/compareregister2

TA0CCR2

0176h

Capture/compareregister

TA0CCR1

0174h

p/p

Capture/compareregister

TA1CCR2

0196h

Timer_Aregister

TA1

0190h

Capt

TA1CCTL

0186h

p/p

FlashFlashcontrol

FCTL3

012Ch

Flashcontrol2

FCTL2

012Ah

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

ADC10

The ADC10 module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator, and data transfer controller (DTC) for automatic conversion result handling, allowing ADC samples to be converted and stored without any CPU intervention.

peripheral file map

PERIPHERALS WITH W ORD ACCESS

Watchdog Watchdog timer control WDTCTL 0120h

Timer0_A3 Capture/compare register 2 TA0CCR2 0176h

Capture/compare register 1

Capture/compare register 0

Timer_A register TA0 R 0170h

Capture/compare control 2 TA0CCTL2 0166h

Capture/compare control 1 TA0CCTL1 0164h

Capture/compare control 0 TA0CCTL0 0162h

Timer_A control TA0 C T L 0160h

Timer_A interrupt vector TA0 I V 012Eh

Timer1_A5 Capture/compare register 4

Capture/compare register 3

ture/compare register 2

Capture/compare register 1

Capture/compare register 0

TA0CCR1

TA0CCR0

TA1CCR4

TA1CCR3

1CCR2

TA1CCR1

TA1CCR0

0174h

0172h

019A

0198

0196h

0194h

0192h

Capture/compare control 4

Capture/compare control 3

ure/compare contro

Capture/compare control 1

Capture/compare control 0

Timer

Timer_A interrupt vector

Flash Flash control 3 FCTL3 012Ch

Flash control 2

Flash control 1

ADC10 ADC data transfer start address

ADC memory

ADC control register 1

ADC control register 0

ADC analog enable 0

ADC analog enable 1

ADC data transfer control register 1

ADC data transfer control register 0

control

TA1CCTL4

TA1CCTL3

TA1CCTL1

TA1CCTL0

TA1CTL

TA1 I V

FCTL2

FCTL1

ADC10SA

ADC10MEM

ADC10CTL1

ADC10CTL0

ADC10AE0

ADC10AE1

ADC10DTC1

ADC10DTC0

018A

0188

0184h

0182h

0180h

011Eh

012Ah

0128h

01BCh

01B4h

01B2h

01B0h

004Ah

004Bh

0049h

0048h

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MSP430F41x2

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peripheral file map (continued)

PERIPHERALS WITH BYTE ACCESS

LCD_A LCD Voltage Control 1

LCD Voltage Control 0

LCD Voltage Port Control 1

LCD Voltage Port Control 0

LCD memory 20

LCD memory 16

LCD memory 15

LCD memory 1

LCD control and mode

USCI A0/B0

Comparator_A+

Brownout, SVS SVS control register (Reset by brownout signal) SVSCTL 056h

FLL+ Clock FLL+ Control 2

USCI A0 auto baud rate control UCA0ABCTL 0x005D

USCI A0 transmit buffer UCA0TXBUF 0x0067

USCI A0 receive buffer UCA0RXBUF 0x0066

USCI A0 status UCA0STAT 0x0065

USCI A0 modulation control UCA0MCTL 0x0064

USCI A0 baud rate control 1 UCA0BR1 0x0063

USCI A0 baud rate control 0 UCA0BR0 0x0062

USCI A0 control 1 UCA0CTL1 0x0061

USCI A0 control 0 UCA0CTL0 0x0060

USCI A0 IrDA receive control UCA0IRRCTL 0x005F

USCI A0 IrDA transmit control UCA0IRTCTL 0x005E

USCI B0 transmit buffer UCB0TXBUF 0x006F

USCI B0 receive buffer UCB0RXBUF 0x006E

USCI B0 status UCB0STAT 0x006D

USCI B0 I2C Interrupt enable UCB0CIE 0x006C

USCI B0 baud rate control 1 UCB0BR1 0x006B

USCI B0 baud rate control 0 UCB0BR0 0x006A

USCI B0 control 1 UCB0CTL1 0x0069

USCI B0 control 0 UCB0CTL0 0x0068

USCI B0 I2C slave address UCB0SA 0x011A

USCI B0 I2C own address UCB0OA 0x0118

Comparator_A port disable CAPD 05Bh

Comparator_A control2 CACTL2 05Ah

Comparator_A control1 CACTL1 059h

FLL+ Control 1

FLL+ Control 0 FLL_CTL0 053h

System clock frequency control SCFQCTL 052h

System clock frequency integrator SCFI1 051h

System clock frequency integrator SCFI0 050h

LCDAVCTL1

LCDAVCTL0

LCDAPCTL1

LCDAPCTL0

LCDM20

LCDM16

LCDM15

LCDM1

LCDACTL

FLL_CTL2

FLL_CTL1

0AFh

0AEh

0ADh

0ACh

0A4h

0A0h

09Fh

091h

090h

055h

054h

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peripheral file map (continued)

RTC (Basic Timer1)

Port P7

Port P6

Port P5

Port P4

Port P3

Port P2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

PERIPHERALS WITH BYTE ACCESS

Real Time Clock Year High Byte

Real Time Clock Year Low Byte

Real Time Clock Month

Real Time Clock Day of Month

Basic Timer1 Counter

Real Time Counter 4

(Real Time Clock Day of Week)

Real Time Counter 3

(Real Time Clock Hour)

Real Time Counter 2

(Real Time Clock Minute)

Real Time Counter 1

(Real Time Clock Second)

Real Time Clock Control

Basic Timer1 Control

Port P7 selection P7SEL 03Bh

Port P7 direction P7DIR 03Ah

Port P7 output P7OUT 039h

Port P7 input P7IN 038h

Port P6 selection P6SEL 037h

Port P6 direction P6DIR 036h

Port P6 output P6OUT 035h

Port P6 input P6IN 034h

Port P5 selection P5SEL 033h

Port P5 direction P5DIR 032h

Port P5 output P5OUT 031h

Port P5 input P5IN 030h

Port P4 selection P4SEL 01Fh

Port P4 direction P4DIR 01Eh

Port P4 output P4OUT 01Dh

Port P4 input P4IN 01Ch

Port P3 selection P3SEL 01Bh

Port P3 direction P3DIR 01Ah

Port P3 output P3OUT 019h

Port P3 input P3IN 018h

Port P2 selection P2SEL 02Eh

Port P2 interrupt enable P2IE 02Dh

Port P2 interrupt -edge select P2IES 02Ch

Port P2 interrupt flag P2IFG 02Bh

Port P2 direction P2DIR 02Ah

Port P2 output P2OUT 029h

Port P2 input P2IN 028h

RTCYEARH

RTCYEARL

RTCMON

RTCDAY

BTCNT2

BTCNT1

RTCNT4

(RTCDOW)

RTCNT3

(RTCHOUR)

RTCNT2

(RTCMIN)

RTCNT1

(RTCSEC)

RTCCTL

BTCTL

04Fh

04Eh

04Dh

04Ch

047h

046h

045h

044h

043h

042h

041h

040h

MSP430F41x2

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MSP430F41x2

SFR

int

tflag2IFG2003h

SFRinterruptenable2IE2001hS

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

peripheral file map (continued)

PERIPHERALS WITH BYTE ACCESS (CONTINUED)

Port P1

pecia

unc

Port P1 selection register P1SEL 026h

Port P1 interrupt enable P1IE 025h

Port P1 interrupt -edge select P1IES 024h

Port P1 interrupt flag P1IFG 023h

Port P1 direction P1DIR 022h

Port P1 output P1OUT 021h

Port P1 input P1IN 020h

ons

errup

SFR interrupt flag 1 IFG1 002h

SFR interrupt enable 2 IE2 001h

FR interrupt enable 1 IE1 000h

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MSP430F41x2

(seeNote1

)

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Voltage applied at VCCto V Voltage applied to any pin (see Note 1) --0.3 V to V

†

--0.3 V to 4.1 V......................................................

+0.3V.......................................

Diode current at any device terminal . 2mA......................................................

Storage temperature, T

: Unprogrammed device --55C to 150C................................

stg

Programmed device --55Cto85C....................................

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltages referenced to V

applied to the TEST pin when blowing the JTAG fuse.

The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is

SS.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage during program execution, VCC(AVCC=DVCC=VCC) 1.8 3.6 V

Supply voltage during flash memory programming, VCC(AVCC=DVCC=VCC) 2.2 3.6 V

Supply voltage, VSS(AVSS=DVSS=VSS) 0 0 V

Operating free-air temperature range, T

LFXT1 crystal frequency, f (see Note 1)

Processorfrequency (signal MCLK),

NOTES: 1. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.

(LFXT1)

(System)

LF selected, XTS_FLL = 0

XT1 selected, XTS_FLL = 1

Watch crystal 32.768 kHz

Ceramic resonator 0.45 6 MHz

Crystal 1 6 MHz

VCC=1.8V dc 4.15

VCC=3.0V dc 8

-- 4 0 85 C

MHz

System

8 MHz

4.15 MHz

(MHz)

Supply voltage range , MSP430F41x2, during program execution

1.8 Supply Voltage - V

2.2 3.0 3.6

Supply voltage range , MSP430F41x2, during flash memory programming

Figure 1. Frequency vs Supply Voltage

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MSP430F41x2

f=f

(MCLK

)

(SMCLK)

=1MHz

Low-powermode3(LPM3

)

(MCLK

)f(SMCLK)

0MHz,

ALCD_Aenabled,LCDCPEN=0

(

LCD(ACLK)

)

Low-powermode3(LPM3

)

(MCLK

)f(SMCLK)

0MHz,

2.2

ALCD_Aenabled,LCDCPEN=0

(

LCD(ACLK)

)

0Hz,SCG

0=1(seeNote2)

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted)

supply current into AVCC+DVCCexcluding external current

PARAMETER T

Active mode (see Note 1),

(AM)

(ACLK)

= 32768 Hz,

=1MHz,

XTS=0, SELM=(0,1)

(LPM0)

Low-power mode 0 (LPM0) (see Note 1) --40Cto85C

Low-power mode 2 (LPM2),

(LPM2)

(MCLK) =f(SMCLK) = 0 MHz,

f(ACLK) = 32768 Hz, SCG0 = 0 (see Note 2)

(LPM3)

(MCLK)=f(SMCLK)

= 32768 Hz, SCG0 = 1,

(ACLK)

Basic Timer1 enabled ,ACLK selected, LCD

enabled,LCDCPEN = 0

(static mode, f

=0MHz,

LCD=f(ACLK)

(see Notes 2 and 3)

(LPM3)

(MCLK)=f(SMCLK)

= 32768 Hz, SCG0 = 1,

(ACLK)

Basic Timer1 enabled ,ACLK selected, LCD

enabled,LCDCPEN = 0

(4-mux mode, f

=0MHz,

LCD=f(ACLK)

(see Notes 2 and 3)

Low-power mode 4 (LPM4),

(LPM4)

(MCLK)

(ACLK)

=0MHz,

(SMCLK)

NOTES: 1. Timer_Aisclockedbyf

2. All inputs are tied to 0 V or to V

3. The LPM3 currents are characterized with a Micro Crystal CC4V--T1A (9 pF) crystal and OSCCAPx = 01h.

/32)

=0MHz,

(DCOCLK)

-- 4 0 Cto85C

-- 4 0 C 0.85 1.4

25C

60C

85C 2.15 3.0

-- 4 0 C 1.0 1.5

25C

60C

85C 2.5 3.5

-- 4 0 C 1.8 3.3

25C

85C

-- 4 0 C 2.1 3.6

25C

85C

-- 4 0 C 0.1 0.5

25C

60C

85C 1.1 2.5

-- 4 0 C 0.1 0.8

25C

60C

85C 1.9 3.5

= 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.

. Outputs do not source or sink any current.

MIN TYP MAX UNIT

2.2 V 220 295

3V 350 398

2.2 V 33 60

3V 50 92

2.2 V 6 13

3V 7 15

2.2

2.2 V

0.90 1.2

1.15 1.4

1.1 1.5

1.4 1.9

2.1 3.2

3.6 5.0

2.3 3.6

4.1 5.5

2.2

0.1 0.5

0.35 0.9

0.1 0.8

0.8 1.2



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typical characteristics -- LPM4 current

ILPM4 -- Low-- power mode current -- uA

ILPM4 -- Low-- power mode current --

3.0

2.5

2.0

1.5

1.0

0.5

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

Vcc = 3.6V

Vcc = 3.0V

Vcc = 2.2V

0.0

Figure 2. I

Vcc = 1.8V

--40.0 --20.0 0.0 20.0 40.0 60.0 80.0 100.0

TA-- Temperature -- C

-- LPM4 Current vs Temperature

LPM4

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