Texas Instruments LP2996-N, LP2996A Datasheet

Copyright © 2016, Texas Instruments Incorporated

220 PF

36 

V

TT

LP2996A

PV

IN

V

DDQ

V

REF

AV

IN

V

REF =

0.75 V

V

SENSE

GND

47 PF

+

+

V

DDQ =

1.5 V

V

DD =

2.5 V

V

TT =

0.75 V

SDSD

0.01PF

Product
Folder

Sample &
Buy

Technical
Documents

Tools &
Software

Support &
Community

Reference
Design

SNOSA40K –NOVEMBER 2002–REVISED DECEMBER 2016

LP2996-N, LP2996A DDR Termination Regulator

LP2996-N,LP2996A

1 Features

1

• Minimum V

DDQ

:
– 1.8 V (LP2996-N)
– 1.35 V (LP2996A)

• Source and Sink Current

• Low Output Voltage Offset

• No External Resistors Required for Setting Output
Voltage

• Linear Topology

• Suspend to Ram (STR) Functionality

• Stable With Ceramic Capacitors With Appropriate
ESR

• Low External Component Count

• Thermal Shutdown

2 Applications

• LP2996-N: DDR1 and DDR2 Termination Voltage

• LP2996A: DDR1, DDR2, DDR3, and DDR3L
Termination Voltage

• FPGA

• Industrial and Medical PC

• SSTL-2 and SSTL-3 Termination

• HSTL Termination

An additional feature found on the LP2996-N and
LP2996A is an active-low shutdown (SD) pin that
provides Suspend To RAM (STR) functionality. When
SD is pulled low the VTT output will tri-state providing
a high impedance output, but VREF remains active. A
power savings advantage can be obtained in this
mode through lower quiescent current.

TI recommends the LP2998 and LP2998-Q1 devices
for automotive applications and DDR applications that
require operating at temperatures below zero.

WEBENCH®design tools can be used by application

designers to generate, optimize, and simlulate
applications using the LP2998 and LP2998-Q1.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)

LP2996-N SOIC (8) 4.90 mm x 3.90 mm
LP2996-N, LP2996A WSON (8) 4.90 mm x 3.90 mm
LP2996-N WQFN (16) 4.00 mm x 4.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

(1)

Simplified Schematic

3 Description

The LP2996-N and LP2996A linear regulators are
designed to meet the JEDEC SSTL-2 specifications
for termination of DDR-SDRAM. The device also
supports DDR2, while LP2996A supports DDR3 and
DDR3L VTT bus termination with V

1.35 V. The device contains a high-speed operational

amplifier to provide excellent response to load
transients. The output stage prevents shoot through
while delivering 1.5-A continuous current and
transient peaks up to 3 A in the application as
required for DDR-SDRAM termination. The LP2996-N
and LP2996A also incorporate a VSENSE pin to
provide superior load regulation and a VREF output
as a reference for the chipset and DIMMs.

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

minimum of

DDQ

LP2996-N,LP2996A

SNOSA40K –NOVEMBER 2002–REVISED DECEMBER 2016

www.ti.com

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 6

6.6 Typical Characteristics.............................................. 7

7 Detailed Description............................................ 10

7.1 Overview................................................................. 10

7.2 Functional Block Diagram ...................................... 10

7.3 Feature Description................................................. 11

7.4 Device Functional Modes........................................ 11

8 Applications and Implementation ...................... 12

8.1 Application Information............................................ 12

8.2 Typical Applications ................................................ 12

9 Power Supply Recommendations...................... 18

10 Layout................................................................... 19

10.1 Layout Guidelines ................................................. 19

10.2 Layout Examples................................................... 19

10.3 Thermal Considerations........................................ 20

11 Device and Documentation Support ................. 23

11.1 Documentation Support ........................................ 23

11.2 Related Links ........................................................ 23

11.3 Receiving Notification of Documentation Updates 23

11.4 Community Resources.......................................... 23

11.5 Trademarks........................................................... 23

11.6 Electrostatic Discharge Caution............................ 23

11.7 Glossary................................................................ 23

12 Mechanical, Packaging, and Orderable

Information........................................................... 23

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision J (March 2013) to Revision K Page

• Added Device Information table, Specifications section, ESD Ratings table, Thermal Information table, Feature
Description section, Device Functional Modes section, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,

Packaging, and Orderable Information section ...................................................................................................................... 1

• Added LP2996A throughout data sheet ................................................................................................................................. 1

• Added DDR3 support throughout data sheet ......................................................................................................................... 1

• Deleted Lead temperature (260°C maximum) from Absolute Maximum Ratings .................................................................. 5

• Changed Thermal Resistance, R

151°C/W To: 56.5°C/W (SO), and From: 151°C/W To: 52.7°C/W (WQFN)........................................................................... 5

, values in Thermal Information From: 151°C/W To: 119.5°C/W (SOIC), From:

θJA

Changes from Revision I (March 2013) to Revision J Page

• Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 1

• Added V

2

Submit Documentation Feedback Copyright © 2002–2016, Texas Instruments Incorporated

Range................................................................................................................................................................. 1

DDQ

Product Folder Links: LP2996-N LP2996A

16 NC5VSENSE

1NC 12 PVIN

15 VTT6NC

2GND 11 PVIN

14 VTT7VREF

3NC 10 AVIN

13 NC8VDDQ

4SD 9 NC

Not to scale

Thermal Pad

1GND 8 VTT

2SD 7 PVIN

3VSENSE 6 AVIN

4VREF 5 VDDQ

Not to scale

PowerPAD

1GND 8 VTT

2SD 7 PVIN

3VSENSE 6 AVIN

4VREF 5 VDDQ

Not to scale

www.ti.com

5 Pin Configuration and Functions

LP2996-N,LP2996A

SNOSA40K –NOVEMBER 2002–REVISED DECEMBER 2016

D Package
8-Pin SOIC

Top View

DDA Package

8-Pin SO With PowerPAD

Top View

NHP Package
16-Pin WQFN

Top View

PIN

I/O DESCRIPTION

NAME

AVIN 6 6 10 I

GND 1 1 2 — Ground

PVIN 7 7 11, 12 I

PowerPAD

SO

SOIC WQFN

Product Folder Links: LP2996-N LP2996A

Pin Functions

Analog input pin. AVIN is used to supply all the internal control circuitry. This pin has the capability
to work from a supply separate from PVIN depending on the application. For SSTL-2 applications, a
good compromise would be to connect the AVIN and PVIN directly together at 2.5 V. This
eliminates the requirement for bypassing the two supply pins separately. The only limitation on input
voltage selection is that PVINmust be equal to or lower than AVIN.

Power input pin. PVIN is used exclusively to provide the rail voltage for the output stage used to
create VTT. This pin has the capability to work from a supply separate from PVIN depending on the
application. Higher voltages on PVIN increases the maximum continuous output current because of
output R
the internal power loss also increases, thermally limiting the design. For SSTL-2 applications, a
good compromise would be to connect the AVIN and PVIN directly together at 2.5 V. This
eliminates the requirement for bypassing the two supply pins separately. The only limitation on input
voltage selection is that PVINmust be equal to or lower than AVIN. TI recommends connecting PVIN
to voltage rails equal to or less than 3.3 V to prevent the thermal limit from tripping because of
excessive internal power dissipation. If the junction temperature exceeds the thermal shutdown then
the part enters a shutdown state identical to the manual shutdown where VTT is tri-stated and
VREF remains active.

limitations at voltages close to VTT. The disadvantage of high values of PVINis that

DS(ON)

Submit Documentation FeedbackCopyright © 2002–2016, Texas Instruments Incorporated

3

LP2996-N,LP2996A

SNOSA40K –NOVEMBER 2002–REVISED DECEMBER 2016

PIN

NAME

SO

PowerPAD

SOIC WQFN

SD 2 2 4 I

VDDQ 5 5 8 I

VREF 4 4 7 O

VSENSE 3 3 5 I

VTT 8 8 14, 15 O

NC — —
Thermal

Pad

PowerPAD —

1, 3, 6,

9, 13, 16

Thermal

Pad

I/O DESCRIPTION

— No internal connection

— Exposed pad thermal connection. Connect to Ground.

www.ti.com

Pin Functions (continued)

Shutdown. The LP2996-N and LP2996A contain an active low shutdown pin that can be used to tri­state VTT. During shutdown VTT must not be exposed to voltages that exceed AVIN. With the
shutdown pin asserted low the quiescent current of the LP2996-N and LP2996A drops, however,
VDDQ always maintains its constant impedance of 100 kΩ for generating the internal reference.
Therefore, to calculate the total power loss in shutdown, both currents must be considered. See

Thermal Considerations for more information. The shutdown pin also has an internal pullup current,

therefore to turn the part on, the shutdown pin can either be connected to AVIN or left open.
Input for internal reference equal to V

reference voltage for regulating VTT. The reference voltage is generated from a resistor divider of
two internal 50-kΩ resistors. This ensures that VTTtracks V
implementation of VDDQ is as a remote sense. This can be achieved by connecting VDDQ directly
to the 2.5-V rail at the DIMM instead of AVIN and PVIN. This ensures that the reference voltage
tracks the DDR memory rails precisely without a large voltage drop from the power lines. For SSTL­2 applications V

Electrical Characteristics for exact values of VTTover temperature.

is a 2.5-V signal, which creates a 1.25-V termination voltage at VTT. See

DDQ

Buffered internal reference voltage of V
reference voltage V
Northbridge chipset and memory. Because these inputs are typically an extremely high impedance,

/ 2. This output must be used to provide the reference voltage for the

DDQ

there must be little current drawn from VREF. For improved performance, an output bypass
capacitor can be placed close to the pin to help reduce noise. TI recommends a ceramic capacitor
from 0.1 µF to 0.01 µF. This output remains active during the shutdown state and thermal shutdown
events for the suspend to RAM functionality.

Feedback pin for regulating VTT. The purpose of the sense pin is to provide improved remote load
regulation. In most motherboard applications the termination resistors connect to VTT in a long
plane. If the output voltage was regulated only at the output of the device then the long trace
causes a significant IR drop resulting in a termination voltage lower at one end of the bus than the
other. The VSENSE pin can be used to improve this performance by connecting it to the middle of
the bus. This provides a better distribution across the entire termination bus. If remote load
regulation is not used then the VSENSE pin must still be connected to VTT. Take care when a long
VSENSE trace is implemented in close proximity to the memory. Noise pickup in the VSENSE trace
can cause problems with precise regulation of VTT. A small 0.1-µF ceramic capacitor placed next to
the VSENSE pin can help filter any high frequency signals and preventing errors.

Output voltage for connection to termination resistors. VTT is the regulated output that is used to
terminate the bus resistors. It is capable of sinking and sourcing current while regulating the output
precisely to V
of up to ±3 A with a fast transient response. The maximum continuous current is a function of V

/ 2. The LP2996-N and LP2996A are designed to handle peak transient currents

DDQ

and can be seen in Typical Characteristics. If a transient above the maximum continuous current
rating is expected to last for a significant amount of time then the output capacitor must be large
enough to prevent an excessive voltage drop. Despite the fact that the device is designed to handle
large transient output currents it is not capable of handling these for long durations under all
conditions. The reason for this is the standard packages are not able to thermally dissipate the heat
as a result of the internal power loss. If large currents are required for longer durations, then ensure
that the maximum junction temperature is not exceeded. Proper thermal derating must always be
used (see Thermal Considerations). If the junction temperature exceeds the thermal shutdown point
then VTT tri-states until the part returns below the hysteretic trip-point.

/ 2. VDDQ is the input used to create the internal

DDQ

/ 2 precisely. The optimal

DDQ

/ 2. VREF provides the buffered output of the internal

DDQ

DD

4

Submit Documentation Feedback Copyright © 2002–2016, Texas Instruments Incorporated

Product Folder Links: LP2996-N LP2996A

LP2996-N,LP2996A

www.ti.com

SNOSA40K –NOVEMBER 2002–REVISED DECEMBER 2016

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

AVIN to GND −0.3 6 V
PVIN to GND –0.3 AV
Input voltage (VDDQ)
Junction temperature, T
Storage temperature, T

(3)

J

stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(3) VDDQ voltage must be less than 2 × (AVIN – 1) or 6 V, whichever is smaller.

6.2 ESD Ratings

V

(ESD)

(1) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.

Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001

(1)(2)

MIN MAX UNIT

IN

−0.3 6 V
150 °C

–65 150 °C

VALUE UNIT

(1)

±1000 V

V

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

AVIN to GND 2.2 5.5 V
PVIN supply voltage 0 AV
SD input voltage 0 AV

T

J

Junction temperature

(1) At elevated temperatures, devices must be derated based on thermal resistance.

(1)

6.4 Thermal Information

THERMAL METRIC

8 PINS 8 PINS 16 PINS

R

θJA

R

θJC(top)

R

θJB

ψ

JT

ψ

JB

R

θJC(bot)

Junction-to-ambient thermal resistance 119.5 56.5 52.7 °C/W
Junction-to-case (top) thermal resistance 65.3 65.1 50.1 °C/W
Junction-to-board thermal resistance 59.8 36.5 30.1 °C/W
Junction-to-top characterization parameter 16.7 15.9 0.7 °C/W
Junction-to-board characterization parameter 59.3 36.5 30.2 °C/W
Junction-to-case (bottom) thermal resistance — 8.4 9.8 °C/W

LP2996-N, LP2996A

MIN MAX UNIT

V

IN

V

IN

0 125 °C

UNITD (SOIC) DDA (SO) NHP (WQFN)

Product Folder Links: LP2996-N LP2996A

Submit Documentation FeedbackCopyright © 2002–2016, Texas Instruments Incorporated

5

LP2996-N,LP2996A

SNOSA40K –NOVEMBER 2002–REVISED DECEMBER 2016

www.ti.com

6.5 Electrical Characteristics

Minimum and maximum limits apply over the full operating temperature range (TJ= 0°C to 125°C) and are specified through
test, design, or statistical correlation. Typical values represent the most likely parametric norm (TJ= 25°C), and are provided
for reference purposes only. Unless otherwise specified, AVIN= PVIN= 2.5 V and V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

REF

Z

VREF

V

TT

VOS

I

Q

V

voltage (DDR I)

REF

V

voltage (DDR II)

REF

V

voltage (DDR III)

REF

V

output impedance I

REF

VTToutput voltage (DDR I)

VTToutput voltage (DDR II)

VTToutput voltage (DDR III)

VTToutput voltage offset
(V

– VTT) for DDR I

REF

VTToutput voltage offset
(V

– VTT) for DDR II

Vtt

REF

VTToutput voltage offset
(V

– VTT) for DDR III

REF

Quiescent current

VDD= V

VDD= V
PVIN= V

PVIN= V
PVIN= V

PVIN= V

REF

I

OUT

(2)

I

OUT

I

OUT

(2)

I

OUT

I

OUT

I

OUT

(2)

I

OUT

I

OUT

I

OUT

I

OUT

I

OUT

I

OUT

(2)

(2)

(2)

(3)

I
I

I
I
I
I
I
I

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

= 2.3 V 1.135 1.158 1.185

DDQ

= 2.5 V 1.235 1.258 1.285

DDQ

= 2.7 V 1.335 1.358 1.385

DDQ

= 1.7 V 0.837 0.86 0.887

DDQ

= 1.8 V 0.887 0.91 0.937

DDQ

= 1.9 V 0.936 0.959 0.986

DDQ

= 1.35 V 0.669 0.684 0.699

DDQ

= 1.5 V 0.743 0.758 0.773

DDQ

= 1.6 V 0.793 0.808 0.823

DDQ

= –30 to 30 µA 2.5 kΩ

VDD= V

= 0 A

VDD= V
VDD= V
VDD= V

= ±1.5 A

VDD= V
VDD= V
PVIN= V

= 0 A, AVIN= 2.5 V

PVIN= V
PVIN= V
PVIN= V

= ±0.5 A, AVIN= 2.5 V

PVIN= V
PVIN= V
PVIN= V

= 0 A, AVIN= 2.5 V

PVIN= V

PVIN= V
= 0.2 A, AVIN= 2.5 V, PVIN= V
= –0.2 A, AVIN= 2.5 V, PVIN= V
= 0.4 A, AVIN= 2.5 V, PVIN= V
= –0.4 A, AVIN= 2.5 V, PVIN= V
= 0.5 A, AVIN= 2.5 V, PVIN= V
= –0.5 A, AVIN= 2.5 V, PVIN= V

= 2.3 V 1.12 1.159 1.19

DDQ

= 2.5 V 1.21 1.259 1.29

DDQ

= 2.7 V 1.32 1.359 1.39

DDQ

= 2.3 V 1.125 1.159 1.19

DDQ

= 2.5 V 1.225 1.259 1.29

DDQ

= 2.7 V 1.325 1.359 1.39

DDQ

DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ

= 1.35 V 0.667 0.688 0.71

DDQ

= 1.35 V 0.641 0.673 0.694

DDQ

= 1.5 V 0.74 0.763 0.786

DDQ

= 1.5 V 0.731 0.752 0.773

DDQ

= 1.6 V 0.79 0.813 0.836

DDQ

= 1.6 V 0.781 0.802 0.823

DDQ

= 0 A –30 0 30
= –1.5 A –30 0 30
= 1.5 A –30 0 30
= 0 A –30 0 30
= –0.5 A –30 0 30
= 0.5 A –30 0 30
= 0 A –30 0 30
= ±0.2 A –30 0 30
= ±0.4 A –30 0 30
= ±0.5 A –30 0 30
= 0 A 320 500 µA

= 2.5 V.

DDQ

= 1.7 V 0.822 0.856 0.887
= 1.8 V 0.874 0.908 0.939
= 1.9 V 0.923 0.957 0.988
= 1.7 V 0.82 0.856 0.89
= 1.8 V 0.87 0.908 0.94
= 1.9 V 0.92 0.957 0.99
= 1.35 V 0.656 0.677 0.698
= 1.5 V 0.731 0.752 0.773
= 1.6 V 0.781 0.802 0.823

(1)

VVDD= V

VPVIN= V

VPVIN= V

V

V

V

mVI

mVI

mV

(1) VDDis defined as VDD= AVIN= PVIN.
(2) VTTload regulation is tested by using a 10-ms current pulse and measuring VTT.
(3) Quiescent current defined as the current flow into AVIN.

6

Submit Documentation Feedback Copyright © 2002–2016, Texas Instruments Incorporated

Product Folder Links: LP2996-N LP2996A

2 2.5 3 3.5 4 4.5 5 5.5

AVIN (V)

0.5

1

1.5

2

2.5

3

3.5

4

V

SD

(V)

-30 -20 -10 0 10 20 30

I

REF

(uA)

1.10

1.15

1.20

1.25

1.30

1.35

1.40

V

REF

(V)

2 2.5 3 3.5 4 4.5 5 5.5

AVIN (V)

50

100

150

200

250

300

350

400

I

Q

(uA)

2 2.5 3 3.5 4 4.5 5 5.5

AVIN (V)

0

150

300

450

600

750

900

1050

I

Q

(uA)

LP2996-N,LP2996A

www.ti.com

SNOSA40K –NOVEMBER 2002–REVISED DECEMBER 2016

Electrical Characteristics (continued)

Minimum and maximum limits apply over the full operating temperature range (TJ= 0°C to 125°C) and are specified through
test, design, or statistical correlation. Typical values represent the most likely parametric norm (TJ= 25°C), and are provided
for reference purposes only. Unless otherwise specified, AVIN= PVIN= 2.5 V and V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Z

VDDQ

I

SD

I

Q_SD

V

IH

V

IL

I

V

I

SENSE

T

SD

T

SD_HYS

VDDQ input impedance 100 kΩ
Quiescent current in shutdown

(3)

SD is low 115 150 µA
Shutdown leakage current SD is low 2 5 µA
Minimum shutdown, high level 1.9 V
Maximum shutdown, low level 0.8 V
VTTleakage current in shutdown SD is low, VTT= 1.25 V 1 10 µA
V

input current 13 nA

SENSE

Thermal shutdown 165 °C
Thermal shutdown hysteresis 10 °C

DDQ

= 2.5 V.

(1)

6.6 Typical Characteristics

Unless otherwise specified, AVIN= PVIN= 2.5 V.

Figure 1. IQvs AVINIn Shutdown Figure 2. IQvs AV

Figure 3. VIHand V

IL

Figure 4. V

REF

vs I

Submit Documentation FeedbackCopyright © 2002–2016, Texas Instruments Incorporated

Product Folder Links: LP2996-N LP2996A

IN

REF

7

2 2.5 3 3.5 4 4.5 5 5.5

AVIN (V)

0

150

300

450

600

750

900

1050

I

Q

(uA)

0oC

25oC

85oC

2 2.5 3 3.5 4 4.5 5 5.5

AVIN (V)

0

0.2

0.4

0.6

0.8

1

1.2

1.4

OUTPUT CURRENT (A)

0 1 2 3 4 5 6

V

DDQ

(V)

0

0.5

1

1.5

2

2.5

3

V

TT

(V)

2 2.5 3 3.5 4 4.5 5 5.5

AVIN(V)

50

100

150

200

250

300

350

400

I

Q

(uA)

0oC

125oC

0 1 2 3 4 5 6

V

DDQ

(V)

0

0.5

1

1.5

2

2.5

3

V

REF

(V)

-100 -75 -50 -25 0 25 50 75 100

I

OUT

(mA)

1.245

1.250

1.255

1.260

1.265

1.270

1.275

V

TT

(V)

LP2996-N,LP2996A

SNOSA40K –NOVEMBER 2002–REVISED DECEMBER 2016

Typical Characteristics (continued)

Unless otherwise specified, AVIN= PVIN= 2.5 V.

www.ti.com

Figure 5. V

REF

vs V

Figure 7. VTTvs V

DDQ

DDQ

Figure 6. VTTvs I

OUT

Figure 8. IQvs AVINin Shutdown Temperature

8

Submit Documentation Feedback Copyright © 2002–2016, Texas Instruments Incorporated

Figure 9. IQvs AVINTemperature

V

= 2.5 V PVIN= 1.8 V

DDQ

Figure 10. Maximum Sourcing Current vs AV

Product Folder Links: LP2996-N LP2996A

IN

2 2.5 3 3.5 4 4.5 5 5.5

AVIN (V)

1

1.2

1.4

1.6

1.8

2

2.2

2.4

OUTPUT CURRENT (A)

3 3.5 4 4.5 5 5.5

2

2.2

2.4

2.6

2.8

3

OUTPUT CURRENT (A)

AVIN (V)

2 2.5 3 3.5 4 4.5 5 5.5

AVIN (V)

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

OUTPUT CURRENT (A)

2 2.5 3 3.5 4 4.5 5 5.5

AVIN (V)

0

0.2

0.4

0.6

0.8

1

1.2

1.4

OUTPUT CURRENT (A)

2 2.5 3 3.5 4 4.5 5 5.5

AVIN (V)

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

OUTPUT CURRENT (A)

3 3.5 4 4.5 5 5.5

2

2.2

2.4

2.6

2.8

3

OUTPUT CURRENT (A)

AVIN (V)

www.ti.com

Typical Characteristics (continued)

Unless otherwise specified, AVIN= PVIN= 2.5 V.

V

= 2.5 V PVIN= 2.5 V

DDQ

Figure 11. Maximum Sourcing Current vs AV

LP2996-N,LP2996A

SNOSA40K –NOVEMBER 2002–REVISED DECEMBER 2016

V

= 2.5 V PVIN= 3.3 V

DDQ

IN

Figure 12. Maximum Sourcing Current vs AV

IN

V

= 2.5 V

DDQ

Figure 13. Maximum Sinking Current vs AV

V

= 1.8 V

DDQ

Figure 15. Maximum Sinking Current vs AV

Product Folder Links: LP2996-N LP2996A

V

= 1.8 V PVIN= 1.8 V

DDQ

IN

IN

Figure 14. Maximum Sourcing Current vs AV

V

= 1.8 V PVIN= 3.3 V

DDQ

Figure 16. Maximum Sourcing Current vs AV

Submit Documentation FeedbackCopyright © 2002–2016, Texas Instruments Incorporated

IN

IN

9

-

+

V

TT

PV

IN

V

DDQ

SD

GND

AV

IN

V

SENSE

50k

50k

+

-

V

REF

Copyright © 2016, Texas Instruments Incorporated

V

TT

V

REF

V

DD

R

S

R

T

CHIPSET

MEMORY

LP2996-N,LP2996A

SNOSA40K –NOVEMBER 2002–REVISED DECEMBER 2016

www.ti.com

7 Detailed Description

7.1 Overview

The LP2996-N and LP2996A devices can be used to provide a termination voltage for additional logic schemes
such as SSTL-3 or HSTL.

Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data transmission across the
memory bus. This termination scheme is essential to prevent data error from signal reflections while transmitting
at high frequencies encountered with DDR-SDRAM. The most common form of termination is Class II single
parallel termination. This involves one RSseries resistor from the chipset to the memory and one RTtermination
resistor. Typical values for RSand RTare 25 Ω, although these can be changed to scale the current
requirements from the LP2996-N or LP2996A. This implementation is shown in Figure 17.

7.2 Functional Block Diagram

Figure 17. SSTL-Termination Scheme

10

Submit Documentation Feedback Copyright © 2002–2016, Texas Instruments Incorporated

Product Folder Links: LP2996-N LP2996A

LP2996-N,LP2996A

www.ti.com

SNOSA40K –NOVEMBER 2002–REVISED DECEMBER 2016

7.3 Feature Description

The LP2996-N and LP2996A are linear bus termination regulators designed to meet the JEDEC requirements of
SSTL-2. The output (VTT) is capable of sinking and sourcing current while regulating the output voltage equal to
V

/ 2. The output stage is designed to maintain excellent load regulation while preventing shoot through. The

DDQ

LP2996-N and LP2996A also incorporate two distinct power rails that separates the analog circuitry from the
power output stage. This allows a split rail approach to be used to decrease internal power dissipation. It also
permits the LP2996-N to provide a termination solution for DDR2-SDRAM, while the LP2996A supports DDR3­SDRAM and DDR3L-SDRAM memory. TI recommends the LP2998 and LP2998-Q1 for all DDR applications that
require operation at below-zero temperatures.

7.4 Device Functional Modes

7.4.1 Start-Up

During start up when VDDQ is enabled, the error amplifier senses the output voltage is low and drives the pass
element hard causing a large inrush current. If this inrush current is too large, the device shuts down and restarts
due to the internal current limit. Two solutions to prevent large inrush current during start up:

1. Slow down the slew rate of VDDQ. When the slew rate of VDDQ is fast (approximately 60 µs), the input
current can reach over 5 A which exceeds the device’s current limit thus causing a restart. If VDDQ start-up
slew rate is ≥300 µs, the inrush current can be reduced by 90% limiting the input rush current to less than
500mA.

2. In some cases the system designers have very little to no control over the VDDQ voltage supply slew rate,
whether using linear or switching regulators. Some step down voltage regulators do not have soft-start
feature. VDDQ voltage source requires only 18 µA current to enable the DDRII termination voltage.
Therefore placing an RC filter at VDDQ pin can conveniently increase the output voltage slew rate, allowing
a slow rise in capacitor charge current. To keep the VDDQ voltage losses minimum, the resistor value must
be chosen carefully. Using a 100-Ω resistor keeps the VDDQ supply voltage losses down to 1.8 mV,
because the current through VDDQ is only 18 µA for DDRIII configuration.

See Limiting DDR Termination Regulators’ Inrush Current (SNVA758) for more information relating to the inrush
current during start up.

7.4.2 Normal Operation

The device contains a high-speed operational amplifier to provide excellent response to load transients. The
output stage prevents shoot through while delivering 1.5-A continuous current and transient peaks up to 3 A in
the application as required for DDR-SDRAM termination. The LP2996-N and LP2996A also incorporate a
VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.
See Electrical Characteristics and Application Information.

7.4.3 Shutdown

The LP2996-N and LP2996A feature an active-low shutdown (SD) pin that provides Suspend To RAM (STR)
functionality. When SD is pulled low, the VTT output tri-states providing a high impedance output, but VREF
remains active. A power savings advantage can be obtained in this mode through lower quiescent current.
During shutdown, VTT must not be exposed to voltages that exceed AVIN. With the shutdown pin asserted low
the quiescent current of the LP2996-N and LP2996A drops, however, VDDQ always maintains its constant
impedance of 100 kΩ for generating the internal reference. Therefore, to calculate the total power loss in
shutdown, both currents must be considered. The shutdown pin also has an internal pullup current, therefore to
turn the part on, the shutdown pin can either be connected to AVIN or left open.

Product Folder Links: LP2996-N LP2996A

Submit Documentation FeedbackCopyright © 2002–2016, Texas Instruments Incorporated

11

Copyright © 2016, Texas Instruments Incorporated

220 PF

36 

V

TT

LP2996A

PV

IN

V

DDQ

V

REF

AV

IN

V

REF =

0.75 V

V

SENSE

GND

47 PF

+

+

V

DDQ =

1.5 V

V

DD =

2.5 V

V

TT =

0.75 V

SDSD

0.01PF

LP2996-N,LP2996A

SNOSA40K –NOVEMBER 2002–REVISED DECEMBER 2016

www.ti.com

8 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LP2996 has split rails to allow flexibility in powering the device. It has a control circuitry rail (AVIN) and an
output power stage rail (PVIN), both separate from the reference voltage input (VDDQ). This allows for different
setups which cater to specific requirements such as high current capabilities, lower thermal dissipation, or
minimum component count. Because the output is always V
necessary external components are bypass capacitors.

8.2 Typical Applications

8.2.1 Typical SSTL-2 Application Circuit

This circuit permits termination in a minimum amount of board space and component count. Capacitor selection
can be varied depending on the number of lines terminated and the maximum load transient. However, with
motherboards and other applications where VTTis distributed across a long plane, it is advisable to use multiple
bulk capacitors and addition to high frequency decoupling.

/ 2 due to two internal 50-kΩ resistors, the only

DDQ

Figure 18. Typical SSTL-2 Application Circuit Diagram

8.2.1.1 Design Requirements

For this design example, use the parameters listed in Table 1 as the input parameters.

Table 1. Design Parameters

PARAMETER VALUE

Input to AVIN and PVIN, V

12

Submit Documentation Feedback Copyright © 2002–2016, Texas Instruments Incorporated

Input bypass capacitor, C

Output bypass capacitor, C

V

DDQ

DD

V

REF

V

TT

IN
OUT

Product Folder Links: LP2996-N LP2996A

1.5 V

2.5 V

0.75 V

0.75 V
47 µF

220 µF