Texas instruments LMK04828, LMK04826 User Manual

SNAU145B–MAY 2013–Revised March 2018

LMK04826 and LMK04828 User’s Guide

This user’s guide describes how to set up and operate the LMK04826/8 evaluation module (EVM). The LMK04826/8 is the industry’s highest performance clock conditioner with JEDEC JESD204B support.

Contents

1 Evaluation Board Kit Contents ............................................................................................. 2

2 Quick Start.................................................................................................................... 3

3 PLL Loop Filters and Loop Parameters................................................................................... 9

4 Default TICS Pro Modes for the LMK0482x ............................................................................ 10

5 Using TICS Pro to Program the LMK0482x ............................................................................ 11

6 Evaluation Board Inputs and Outputs ................................................................................... 16

7 Recommended Test Equipment.......................................................................................... 19

Appendix A TICS Pro Usage................................................................................................... 20

Appendix B Typical Phase Noise Performance Plots....................................................................... 29

Appendix C Schematics......................................................................................................... 39

Appendix D Bill of Materials .................................................................................................... 45

User's Guide

List of Figures

1 Quick Start Diagram......................................................................................................... 3

2 CLKout Page Description Diagram........................................................................................ 4

3 Continuous SYSREF Output............................................................................................... 6

4 Pulsed SYSREF Output .................................................................................................... 7

5 Clock Outputs Page Setup for SYSREF Output on SDCLKout7...................................................... 8

6 Selecting a Default Mode for the LMK04828 Device.................................................................. 10

7 Selecting the LMK04828B ................................................................................................ 12

8 Loading the Device ........................................................................................................ 12

9 Setting the Default Mode for LMK04828 ................................................................................ 14

10 Setting Digital Delay, Clock Divider, Analog Delay and Output Format............................................. 15

11 TICS Pro - User Controls Page .......................................................................................... 21

12 TICS Pro - Raw Registers Page ......................................................................................... 22

13 TICS Pro - Set Modes Page.............................................................................................. 23

14 TICS Pro - CLKinX Control Page ........................................................................................ 24

15 TICS Pro - SYNC / SYSREF Page ...................................................................................... 25

16 TICS Pro - Clock Outputs Page.......................................................................................... 26

17 TICS Pro - Other Page .................................................................................................... 27

18 TICS Pro - Burst Page..................................................................................................... 28

19 Crystek CVHD-950-122.88 MHz VCXO Phase Noise at 122.88 MHz.............................................. 30

20 LMK04826 DCLKout2, VCO0, 245.76 MHz, Div8, LVPECL20 /w 240-Ω Emitter Resistor,

DCLKoutX_MUX=Divider, IDL=1, ODL=0, Balun = Prodyn BIB-100G.............................................. 31

21 LMK04826 DCLKout2, VCO0, 245.76 MHz, Div8, LVPECL20 /w 240-Ω Emitter Resistor,

DCLKoutX_MUX=Divider, IDL=1, ODL=0, Single Ended............................................................. 32

22 LMK04826 DCLKout2, VCO1, 245.76 MHz, Div10, LVPECL20 /w 240 ohm emitter resistor,

DCLKoutX_MUX=Divider, IDL=1, ODL=0, Balun = Prodyn BIB-100G.............................................. 33

23 LMK04826 DCLKout2, VCO1, 245.76 MHz, Div10 , LVPECL20 /w 240-Ω Emitter Resistor,

DCLKoutX_MUX=Divider, IDL=1, ODL=0, Single Ended............................................................. 34

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Evaluation Board Kit Contents

24 LMK04828 DCLKout2, VCO0, 245.76 MHz, Div10, LVPECL20 /w 240-Ω Emitter Resistor,

DCLKoutX_MUX=Divider, IDL=1, ODL=0, Balun = ADT2-1T........................................................ 35

25 LMK04828 DCLKout2, VCO0, 245.76 MHz, Div10, LVPECL20 /w 240-Ω Emitter Resistor,

DCLKoutX_MUX=Divider, IDL=1, ODL=0, Single Ended............................................................. 36

26 LMK04828 DCLKout2, VCO1, 245.76 MHz, Div12, LVPECL20 /w 240-Ω Emitter Resistor,

DCLKoutX_MUX=Divider, IDL=1, ODL=0, Balun = ADT2-1T........................................................ 37

27 LMK04828 DCLKout2, VCO1, 245.76 MHz, Div12, LVPECL20 /w 240-Ω Emitter Resistor,

DCLKoutX_MUX=Divider, IDL=1, ODL=0, Single Ended............................................................. 38

1 EVM Contents................................................................................................................ 2

2 PLL1 Loop Filter Parameters for Crystek 122.88 MHz VCXO ........................................................ 9

3 Integrated VCO PLL ........................................................................................................ 9

4 Default TICS Pro Modes for the LMK0482x............................................................................ 10

5 Description of Evaluation Board Inputs and Outputs.................................................................. 16

6 LMK0482x Test Conditions ............................................................................................... 29

7 VCXO Phase Noise and Jitter............................................................................................ 30

8 Bill of Materials LMK0482x Evaluation Boards......................................................................... 45

Trademarks

All trademarks are the property of their respective owners.

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List of Tables

1 Evaluation Board Kit Contents

The evaluation board kit includes what is shown in Table 1. Note that -002 and -003 are currently available.

SV600788 -002 -003

Evaluation Board (1) LMK04828B Evaluation Board (1) LMK04826B Evaluation Board USB Communications (1) USB2ANY

Table 1. EVM Contents

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4 to 5 V

CLKin

Reference clock from

signal generator or other

external source.

122.88 MHz (Default)

LMK0482x

DCLKout

SDCLKout

DCLKout3*

DCLKout3

OSCout

OSCout*

CLKin0

CLKin0*

OSCin

OSCin*

These SMAs not used by default.

With PCB change, can be used for reference

input for single PLL mode.

SDCLKout1*

SDCLKout1

DCLKout0*

DCLKout0

DCLKout

Default is

LDO to IC

PLL1 Digital Lock Detect LED

PLL2 Digital

Lock Detect LED

Reference

VCC

GND

VCC

Power

Laptop or PC

USB cable

USB2ANY

USB2ANY Texas Instruments

HPA665

Å BSL Button

Program with TICS Pro

%HVXUHWRSUHVV³&WUO+/´RU USB communications Æ Write All Registers

10-Pin Ribbon Cable

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2 Quick Start

Quick Start

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Figure 1. Quick Start Diagram

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1 2 4

5 6 7 8 13 14 15 16 17

9 11 12

23 24 2625 27 2820

3 10 18 19

Quick Start

2.1 Quick Start Description

The LMK04828/6 EVM allows full verification of the device functionality and performance specifications. To quickly set up and operate the board with basic equipment, refer to the quick start procedure below and test setup shown in Figure 1.

1. Connect a voltage of 4.5 volts to the VCCSMA connector or terminal block. Device operates at 3.3 V using onboard LP3878-ADJ LDO. VCXO operates at 3.3 V using onboard LP5900 LDO.

2. Connect a reference clock to the CLKin1* port from a signal generator or other source. Use 122.88 MHz for default. Exact frequency and input port (CLKin0/CLKin1*) depends on programming.

3. Connect USB2ANY to PC and EVM.

4. Program the device with TICS Pro. TICS Pro is available for download at:

http://www.ti.com/tool/ticspro-sw.

a. Select LMK04828B or LMK04826B from the “Select Device” Menu. Click “Select Device” → “Clock

Generator/ Jitter Cleaner (Dual Loop)” → “LMK0482x”.

b. Select USB2ANY mode from the Communication Setup window. To access this, select “USB

communications” → “Interface”. Confirm PC to USB communications by clicking “Identify” to see blinking green LED on USB2ANY.

c. Select a default mode from the “Default configuration” Menu. For the quick start use, “CLKin1

122,88 MHz, OSCin 122.88 MHz”.

d. Ctrl+L must be pressed at least once to load all registers. Alternatively click “USB

communications” → “Write All Registers” or the “Write All Registers” button on the Raw Registers page.

5. Measurements may be made at an active CLKout port through its SMA connector.

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2.1.1 CLKout Page Description

Figure 2. CLKout Page Description Diagram

1. SYNC_DISX: Prevent the divider from being reset by SYNC/SYSREF path.

2. DCLKX_DIV: Divide value for the device clock. If set to 1 then #11 on list must = 1 and #12 must be Divider+DCC+HS.

3. DDLYdX_EN: Enable dynamic digital delay for this divider.

4. DCLKX_HSg_PD: If clear, glitchless half-step adjustments are enabled.

5. DCLKX_HS: Set half step for this divider. #12 must be Divider+DCC+HS.

6. DCLKX_DDLY_PD: If clear, the digital delay value is assured when a SYNC occurs.

7. DCLKoutX_DDLY_CNTL/CNTH: for controlling the digital delay value.

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8. DCLKoutX_ADLYg_PD: If set, power down device clock glitchless analog delay feature.

9. DCLKoutX_ADLY_PD: If set, power down device clock analog delay.

10. DCLKoutX_ADLY: Analog delay (if enabled with #12).

11. DCLKoutX_ADLY_MUX: Enable duty cycle correct and half-step for this device clock divider.

12. DCLKoutX_MUX: Select source for CLKoutX. Can be Divider only, Divider+DCC+HS, Bypass, or

13. SDCLKoutY_POL: If set, polarity of SYSREF output clock is inverted.

14. DCLKoutX_POL: If set, polarity of device clock is inverted.

15. SYSREF_GBL_PD: Set the conditional for SDCLKoutY_DIS_MODE registers.

16. CLKoutX_Y_IDL: Increase input drive level to improve noise floor at cost of power.

17. CLKoutX_Y_ODL: Increase output drive level to improve noise floor at cost of power. No effect for

18. DCLKoutX_FMT: Set the clock output format for CLKoutX.

19. CLKoutX_Y_PD: Power down the entire CLKoutX_Y clock pair.

20. SDCLKoutY_DDLY: The SYSREF clock digital delay setting.

21. SDCLKoutY_HS: Set half step for the SYSREF output.

22. SDCLKoutY_ADLY_EN: Enable analog delay for the SYSREF clock path.

23. SDCLKoutY_ADLY: If enabled, set the analog delay for the SYSREF clock path.

24. SDCLKoutY_MUX: Select device clock or SYSREF clock path for CLKoutY.

25. SDCLKoutY_DIS_MODE: Set the output state of output clock drivers for the SYSREF clock. For

26. SDCLKoutY_FMT: Set the clock output format for CLKoutY.

27. SDCLKoutY_PD: Power down the SYSREF clock path.

28. Clock output frequency for CLKoutX and CLKoutY.

Quick Start

Analog Delay+Divider.

CLKoutX in bypass mode.

values of 1 and 2 works in conjunction with control on this list #15, SYSREF_GBL_PD.

NOTE: Setting a register equal to 0 OR un-checking a register’s checkbox performs the same

action. Similarly, setting a register equal to 1 is the same as checking that register’s checkbox.

2.1.2 TICS Pro Tips

• Mousing over different controls will display some help prompt with the register address, data bit location/length, and a brief register description in the lower left Context help pane.

2.2 SYSREF Quick Start

The LMK0482x EVK allows for verification of the LMK0482x’s implementation of JESD 204B SYSREF functionality. To quickly setup and operate the SYSREF functions, refer to the following procedures.

2.2.1 Continuous SYSREF

1. On the Clock Outputs page, set SDCLKoutY_PD = 0 (where Y is the desired SDCLKout).

2. Set SDCLKoutY_MUX = 1 (Set to “SYSREF” for desired SDCLKout).

3. On the SYNC/SYSREF page, set SYSREF_PD and SYSREF_DDLY_PD = 0.

4. Set SYNC_DISX and SYNC_DISSYSREF = 0 (where X is the desired DCLKout).

5. Perform a SYNC event (toggle SYNC_POL on/off/on).

6. Set SYNC_DISX = 1 (for desired DCLKout’s) and SYNC_DISSYSREF = 1.

7. Set SYSREF_MUX = 3 (SYSREF Continuous).

8. Ensure SYSREF_CLR = 0 (On the right side, in the grey Other SYNC Controls box).

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In Figure 3 and Figure 4, the Blue trace is DCLKout6 at 245.76 MHz and the Green trace is SDCLKout7 (SYSREF) at 24.475 MHz. Figure 5 shows the configuration of the LMK0482xB outputs.

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Figure 3. Continuous SYSREF Output

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2.2.2 Pulsed SYSREF

1. On the Clock Outputs page, set SDCLKoutY_PD = 0 (where Y is the desired SDCLKout).

2. Set SDCLKoutY_MUX = 1 (Set to “SYSREF” for desired SDCLKout).

3. On the SYNC/SYSREF page, set SYSREF_PD and SYSREF_DDLY_PD = 0.

4. Set SYNC_DISX and SYNC_DISSYSREF = 0 (where X is the desired DCLKout).

5. Set SYSREF_PLSR_PD = 0.

6. Perform a SYNC event (toggle SYNC_POL on/off/on).

7. Set SYNC_DISX = 1 (for desired DCLKout’s) and SYNC_DISSYSREF = 1.

8. Set SYSREF_MUX = 2 (SYSREF Pulser).

9. Set SYSREF_PULSE_CNT = 1, 2, 4, or 8 as desired.

10. Perform a SYNC event (toggle SYNC_POL on/off/on).

11. Ensure SYSREF_CLR = 0 (On the right side, in the grey Other SYNC Controls box).

Quick Start

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Figure 4. Pulsed SYSREF Output

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Figure 5. Clock Outputs Page Setup for SYSREF Output on SDCLKout7

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3 PLL Loop Filters and Loop Parameters

In jitter cleaning applications that use a cascaded or dual PLL architecture, the first PLL’s purpose is to substitute the phase noise of a low-noise oscillator (VCXO or crystal resonator) for the phase noise of a “dirty” reference clock. The first PLL is typically configured with a narrow loop bandwidth to minimize the impact of the reference clock phase noise. The reference clock consequently serves only as a frequency reference rather than a phase reference.

The loop filters on the LMK048xx evaluation board are setup using the approach above. The loop filter for PLL1 has been configured for a narrow loop bandwidth (> 100 kHz). The specific loop bandwidth values depend on the phase noise performance of the oscillator mounted on the board. Table 2 and Table 3 contain the parameters for PLL1 and PLL2 for each oscillator option.

TI’s Clock Design Tool can be used to optimize PLL phase noise/jitter for given specifications. See:

http://www.ti.com/tool/clockdesigntool.

3.1 PLL1 Loop Filter

PLL Loop Filters and Loop Parameters

Table 2. PLL1 Loop Filter Parameters for Crystek 122.88 MHz VCXO

Phase Margin 50˚ Kφ (Charge Pump) 150 µA Loop Bandwidth 14 Hz Phase Detector Freq 1.024 MHz

Reference Clock Frequency 122.88 MHz Output Frequency 122.88 MHz

Loop Filter Components C1_A1 = 100 nF C2_A1 = 680 nF R2_A1 = 39 kΩ

(1)

Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing Kφ and N will change the loop bandwidth.

3.2 PLL2 Loop Filter

C1_A2 0.047 nF

C2_A2 3.9 nF C3 (internal) 0.01 nF C4 (internal) 0.01 nF

R2_A2 0.62 kΩ R3 (internal) 0.2 kΩ R4 (internal) 0.2 kΩ

Charge Pump Current, Kφ 3.2 mA

Phase Detector Frequency 122.88 MHz

Frequency 1966.08 2457.6 2457.6 2949.12 MHz

Kvco 15.3 8.9 21.9 17.4 MHz/V

N 16 20 20 24

Phase Margin 73 64 73 70 degrees

Loop Bandwidth 303 151 344 233 kHz

(1)

PLL Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing Kφ and N will change the loop bandwidth.

122.88 MHz VCXO PLL

VCO Gain 2.0 kHz/V

(To PLL 2)

Table 3. Integrated VCO PLL

LMK04826 LMK04828

VCO0 VCO1 VCO0 VCO1

(1)

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Default TICS Pro Modes for the LMK0482x

4 Default TICS Pro Modes for the LMK0482x

TICS Pro saves the state of the selected LMK0482x device when exiting the software. To ensure a common starting point, the following modes listed in Table 4 may be restored by clicking “Default configuration” and selecting the appropriate device configuration.

Table 4. Default TICS Pro Modes for the LMK0482x

Default TICS Pro Mode Device Mode CLKin Frequency OSCin Frequency

CLKin1 122.88 MHz, OSCin

122.88 MHz

Figure 6. Selecting a Default Mode for the LMK04828 Device

Dual PLL, Internal VCO 122.88 MHz 122.88 MHz

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5 Using TICS Pro to Program the LMK0482x

This section will demonstrate how to use TICS Pro. Making measurements with the LMK04828B device will serve as an example. For more information on using TICS Pro, refer to Appendix A. TICS Pro is available for download at http://www.ti.com/tool/ticspro-sw.

Another option is to use CodeLoader4. The tool page for CodeLoader4 is located at

http://www.ti.com/tool/codeloader/.

Before proceeding, be sure to follow the instructions in Section 2 to ensure proper connections. To program the LMK04826B, the procedure would be the same, but the LMK04826B would be selected as the device.

5.1 Start TICS Pro Application

Click “Start” → “Programs” → “Texas Instruments” → “TICS Pro”. The TICS Pro program is installed by default to the Texas Instruments application group.

5.2 Select Device

Click “Select Device” → “Clock Generator/ Jitter Cleaner (Dual Loop)” → “LMK0482x” → “LMK04828B” Once started, TICS Pro will load the last used device. To load a new device, click “Select Device” from the

menu bar, then select the subgroup “Clock Generator/ Jitter Cleaner (Dual Loop)”, then “LMNK0482x”, and finally the device to load. For this example, the LMK04828B is chosen. Selecting the device does cause the device to be programmed. However, it is advisable to press “Ctrl+L”to ensure programming.

Using TICS Pro to Program the LMK0482x

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5.3 Program/Load Device

Press “Ctrl+L” Alternatively, click “USB communications” → “Write All Registers” from the menu to program the device to

the current state of the newly loaded LMK04828 file. “Ctrl+L” is the accelerator key assigned to the “Write All Registers” option and is very convenient.

Once the device has been loaded, by default TICS Pro will automatically program changed registers, so it is not necessary to load the device again completely. It is possible to disable this functionality by ensuring there is no checkmark by the “Options” → “AutoUpdate”.

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Figure 7. Selecting the LMK04828B

Figure 8. Loading the Device

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Once the device has been initially loaded, TICS Pro will automatically program changed registers, so it is not necessary to reload the device upon subsequent changes in the device configuration. It is possible to disable this functionality by ensuring there is no checkmark by the “Options” → “AutoUpdate”

Because a default mode will be restored in the next step, this step isn’t really needed but is included to emphasize the importance of pressing “Ctrl+L” to load the device at least once after starting TICS Pro, restoring a mode, or restoring a saved setup using the File menu.

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Using TICS Pro to Program the LMK0482x

5.4 Restoring a Default Mode

Click “Default configuration” → “CLKin1 122,88 MHz, OSCin 122.88 MHz”; then Press “Ctrl+L”

Figure 9. Setting the Default Mode for LMK04828

For the purpose of this walkthrough, a default mode will be loaded to ensure a common starting point. This is important because when TICS Pro is closed, it remembers the last settings used for a particular device. Again, remember to press “Ctrl+L” as the first step after loading a default mode.

5.5 Visual Confirmation of Frequency Lock

After a default mode is restored and loaded, LED D4, and D5 must illuminate when PLL1 and PLL2 are locked to the reference clock applied to CLKin1. This assumes PLL1_LD_MUX = PLL1_DLD, PLL2_LD_MUX = PLL2_DLD and PLLX_LD_TYPE = Output (Push-Pull).

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5.6 Enable Clock Outputs

While the LMK0482x offers programmable clock output buffer formats, the evaluation board is shipped with pre-configured output terminations to match the default buffer type for each output.

To measure Phase noise at one of the clock outputs, for example DCLKout0:

1. Click on the Clock Outputs page,

2. Uncheck “CLKoutX_Y_PD” in the Clock Output box to enable the channel,

3. Set the following as needed: a. Digital Delay value. b. Clock Divider value (if “Bypass” is not selected as DCLKoutX_MUX). c. Analog Delay Value (if “Analog Delay and Divider” is selected as DCLKoutX_MUX).

Using TICS Pro to Program the LMK0482x

Figure 10. Setting Digital Delay, Clock Divider, Analog Delay and Output Format

4. Depending on the configured output type, the clock output SMAs can be interfaced to a test instrument

with a single-ended 50-Ω input as follows.

a. For LVDS:

i. A balun (like ADT2-1T or high quality Prodyn BIB-100G) is recommended for differential-to-

single-ended conversion.

b. For LVPECL:

I. A balun can be used, or II. One side of the LVPECL signal can be terminated with a 50-Ω load and the other side can be

run single-ended to the instrument.

c. For HSDS:

I. A balun (like ADT2-1T or high quality Prodyn BIB-100G) is recommended for differential-to-

single-ended conversion.

5. The phase noise may be measured with a spectrum analyzer or signal source analyzer.

TI’s Clock Design Tool can be used to calculate divider values to achieve desired clock output frequencies. See: http://www.ti.com/tool/clockdesigntool

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Evaluation Board Inputs and Outputs

6 Evaluation Board Inputs and Outputs

Table 5 contains descriptions of the inputs and outputs for the evaluation board. Unless otherwise noted,

the connectors described can be assumed to be populated by default. Additionally, some applicable TICS Pro programming controls are noted for convenience.

Table 5. Description of Evaluation Board Inputs and Outputs

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CONNECTOR NAME

Populated: DCLKout0, DCLKout0*, SDCLKout1, SDCLKout1*, DCLKout2, DCLKout2*, SDCLKout3, SDCLKout3*, DCLKout10, DCLKout10* SDCLKout11, SDCLKout11*

Populated: OSCout, OSCout*

Populated: J1

VccVCXO/Aux

SIGNAL TYPE,

INPUT/OUTPUT

Analog,

Output

Analog,

Output

Power,

Input

Power,

Input

Power,

Input

DESCRIPTION

Clock outputs with programmable output buffers. The output terminations by default on the evaluation board are shown below:

Clock Output Pair Default Board Termination

DCLKout0 240 Ω

SDCLKout1 240 Ω

DCLKout2 240Ω

SDCLKout3 240 Ω

DCLKout4 HSDS / LVDS

SDCLKout5 HSDS / LVDS

DCLKout6 HSDS / LVDS

SDCLKout7 HSDS / LVDS

DCLKout8 HSDS / LVDS SDCLKout9 HSDS / LVDS DCLKout10 HSDS / LVDS

SDCLKout11 HSDS / LVDS

DCLKout12 HSDS / LVDS

SDCLKout13 HSDS / LVDS

Each CLKout pair has a programmable LVDS, LVPECL, or HSDS buffer. The output buffer type can be selected in TICS Pro in the Clock Outputs page through the CLKoutX_TYPE control. All clock outputs are AC-coupled to allow safe testing with RF test equipment. All LVPECL clock outputs are terminated using 240 Ω emitter-resistors. If an output pair is programmed to LVCMOS, each output can be independently configured (normal, inverted, or off/tri-state).

Buffered outputs of OSCin port. The output terminations on the evaluation board are shown below.:

OSC Output Pair Default Board Termination

OSCout LVPECL

OSCout has a programmable LVDS, LVPECL, or LVCMOS output buffer. The OSCout buffer type can be selected in TICS Pro on the Clock Outputs page through the OSCout_FMT control. OSCout is AC-coupled to allow safe testing with RF test equipment. The OSCout output is terminated using 240 Ω emitter-resistors. If OSCout is programmed as LVCMOS, each output can be independently configured (normal, inverted, inverted, and off/tri-state). Best performance/EMI reduction is achieved by using a complementary output mode like Norm/Inv. It is NOT recommended to use Norm/Norm or Inv/Inv mode.

Main power supply input for the evaluation board. The LMK0482x contains internal voltage regulators for the VCO, PLL and other internal blocks. The clock outputs do not have an internal regulator, so a clean power supply with sufficient output current capability is required for optimal performance. On-board LDO regulators and 0 Ω resistor options provide flexibility to supply and route power to various devices. See the schematics in Appendix C for more details.

Alternative power supply input for the evaluation board using two unshielded wires (Vcc and GND). Apply power to either Vcc SMA or J1, but not both.

Optional Vcc input to power the VCXO circuit if separated voltage rails are needed. The VccVCXO/Aux input can power these circuits directly or supply the on-board LDO regulators. 0 Ω resistor options provide flexibility to route power.

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