Texas Instruments LMH0356 Datasheet

RETIMER / FIFO

VCO / PLL

SDI0

LOCK DETECT

SDO

CONTROL LOGIC

AUTO BYPASS

BYPASS/

O/P MUTE

RATE0 RATE1

XTAL IN/EXT CLK

XTAL OUT LOOP FILTER 1 LOOP FILTER 2

SCO_EN

SCO/SDO2

BYPASS

SDI0

SDO

CCO

SD/

CCO

SCO/SDO2

SDI1 SDI1

SDI2 SDI2

SDI3 SDI3

SEL0 SEL1

ENABLE

EQUALIZER

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Technical Documents

Tools & Software

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SNLS270L –AUGUST 2007–REVISED JANUARY 2016

LMH0356 3-Gbps HD/SD SDI Reclocker with 4:1 Input Mux and FR4 EQs

LMH0356

1 Features

• Supports SMPTE ST-424, ST-292, and ST-259 Serial Digital Video Standards

• Supports 270-Mbps, 1.483-Gbps, 1.485-Gbps,

2.967-Gbps, and 2.97-Gbps Serial Data Rate Operation

• Supports DVB-ASI at 270 Mbps

• Single 3.3-V Supply Operation

• 430-mW Typical Power Consumption

• Integrated 4:1 Multiplexed Input

• 0 to 30-inch FR4 Equalizer on Each Multiplexed Input

• Two Differential, Reclocked Outputs

• Choice of Second Reclocked Output or Recovered Clock Output

• Single 27-MHz External Crystal or Reference Clock Input

• Manual Rate Select Input

• SD/HD Operating Rate Indicator Output

• Lock Detect Indicator Output

• Output Mute Function for Data and Clock

• Auto/Manual Reclocker Bypass

• Power Saver Mode With Device Power-Down Control (10-mW Typical Power Consumption in Disabled State)

• Differential LVPECL-Compatible Serial Data Inputs and Outputs

• LVCMOS Control Inputs and Indicator Outputs

• 48-Pin WQFN or 40-Pin WQFN Package

• Industrial Temperature Range: –40°C to 85°C

• 48-Pin WQFN Version Footprint-Compatible with the LMH0056 and LMH0036

3 Description

The LMH0356 3-Gbps HD/SD SDI Reclocker with 4:1 Input Mux and FR4 EQs retimes serial digital video data conforming to the SMPTE ST-424, ST-292, and ST-259 standards. The LMH0356 operates at serial data rates of 270 Mbps, 1.483 Gbps, 1.485 Gbps,

2.967 Gbps, and 2.97 Gbps. The LMH0356 supports DVB-ASI operation at 270 Mbps. The LMH0356 includes an integrated 4:1 input multiplexer for selecting one of four input data streams for retiming. In addition, the four inputs of the LMH0356 each have an FR4 equalizer capable of equalizing 0 to 30 inches of FR4 trace length.

The LMH0356 automatically detects the incoming data rate and adjusts itself to retime the incoming data to suppress accumulated jitter. The LMH0356 recovers the serial data-rate clock and optionally provides it as an output. The LMH0356 has two differential serial data outputs; the second output may be selected as a low-jitter, data-rate clock output. Controls and indicators are: serial clock or second serial data output select, manual rate select input, SD/HD rate indicator output, lock detect output, auto/manual data bypass, output mute, and device enable. The serial data inputs, outputs, and serial clock outputs are differential LVPECL compatible. The CML serial data and serial clock outputs are suitable for driving 100-Ω differentially terminated networks. The control logic inputs and outputs are LVCMOS compatible.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)

LMH0356

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

WQFN (40) 5.00 mm x 5.00 mm WQFN (48) 7.00 mm x 7.00 mm

(1)

Functional Block Diagram

2 Applications

• SDTV/HDTV and 3-Gbps Serial Digital Video Interfaces for:

– Digital Video Routers and Switchers – Digital Video Processing and Editing

Equipment – DVB-ASI Equipment – Video Standards and Format Converters

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMH0356

SNLS270L –AUGUST 2007–REVISED JANUARY 2016

www.ti.com

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Description (continued)......................................... 3

6 Pin Configuration and Functions......................... 3

7 Specifications......................................................... 6

7.1 Absolute Maximum Ratings ..................................... 6

7.2 ESD Ratings.............................................................. 6

7.3 Recommended Operating Conditions....................... 6

7.4 Thermal Information.................................................. 6

7.5 DC Electrical Characteristics .................................... 7

7.6 AC Electrical Characteristics..................................... 8

7.7 AC Timing Requirements.......................................... 9

8 Detailed Description............................................ 10

8.1 Overview ................................................................. 10

8.2 Functional Block Diagram....................................... 10

8.3 Feature Description................................................. 11

8.4 Device Functional Modes ....................................... 14

9 Application and Implementation ........................ 15

9.1 Application Information............................................ 15

9.2 Typical Application ................................................. 15

10 Power Supply Recommendations ..................... 19

11 Layout................................................................... 20

11.1 Layout Guidelines ................................................. 20

11.2 Layout Example .................................................... 20

12 Device and Documentation Support................. 21

12.1 Community Resources.......................................... 21

12.2 Trademarks........................................................... 21

12.3 Electrostatic Discharge Caution............................ 21

12.4 Glossary................................................................ 21

13 Mechanical, Packaging, and Orderable

Information........................................................... 21

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision K (April 2013) to Revision L Page

• Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device

and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ............................. 1

Product Folder Links: LMH0356

LMH0356SQ

(top view)

SDI0

SCO/SDO2

XTAL IN/

EXT CLK

SDI1

ENABLE

SDI2

SDI3

13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37

SDO

BYPASS/

LF1

SEL1

SEL0

LF2

SCO_EN

OP MUTE

XTAL OUT

VEEV

SD/HD

RATE1

RATE0

AUTO BP

LMH0356

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SNLS270L –AUGUST 2007–REVISED JANUARY 2016

5 Description (continued)

The LMH0356 is powered from a single 3.3-V supply. Power dissipation is typically 430 mW. The device is available in two space-saving packages: a 7-mm x 7-mm, 48-pin WQFN and even more space-efficient 5-mm x 5-mm, 40-pin WQFN package.

6 Pin Configuration and Functions

RHS Package 48-Pin WQFN

Top View

The exposed die attach pad is the primary negative electrical terminal for this device. It must be connected to the negative power supply voltage.

Product Folder Links: LMH0356

LMH0356SQ-40

(top view)

SDI0

SCO/SDO2

XTAL IN/

EXT CLK

SDI1

ENABLE

SDI2

SDI3

11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32 31

SDO

BYPASS/

LF1

SEL1

SEL0

LF2

SCO_EN

OP MUTE

LOCK DET

SD/HD

RATE1

RATE0

AUTO BP

LMH0356

SNLS270L –AUGUST 2007–REVISED JANUARY 2016

www.ti.com

RSB Package 40-Pin WQFN

Top View

The exposed die attach pad is the primary negative electrical terminal for this device. It must be connected to the negative power supply voltage.

Pin Functions

NAME

BYPASS/ AUTO BYPASS

ENABLE 9 8 Device Enable. Powers down device when low. This pin has an internal pullup. LF1 43 35 Loop Filter. LF2 44 36 Loop Filter. LOCK DETECT 24 23 PLL Lock Detect output (active high). OUTPUT MUTE 16 15 Data and Clock Output Mute input. Mutes the output when low. This pin has an

WQFN 48 PIN

15 14 Bypass/Auto Bypass mode select. Bypasses reclocking when high. This pin has

WQFN 40 PIN

an internal pulldown.

internal pullup.

DESCRIPTION

RATE0 45 37 Data Rate select input. This pin has an internal pulldown. RATE1 46 38 Data Rate select input. This pin has an internal pulldown. SCO/SDO2 28 24 Serial Clock or Serial Data Output 2 Complement. SCO/SDO2 29 25 Serial Clock or Serial Data Output 2 True. SCO_EN 37 32 Serial Clock or Serial Data 2 Output select. Sets second output to output the

clock when high and the data when low. This pin has an internal pulldown.

SD/HD 36 31 Data Rate Range output. Output is high for SD and low for HD or 3G.

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SNLS270L –AUGUST 2007–REVISED JANUARY 2016

Pin Functions (continued)

NAME

WQFN 48 PIN

WQFN 40 PIN

SDI0 1 1 Data Input 0 True. SDI0 2 2 Data Input 0 Complement. SDI1 4 4 Data Input 1 True. SDI1 5 5 Data Input 1 Complement. SDI2 7 6 Data Input 2 True. SDI2 8 7 Data Input 2 Complement. SDI3 10 9 Data Input 3 True. SDI3 11 10 Data Input 3 Complement. SDO 32 27 Data Output Complement. SDO 33 28 Data Output True. SEL0 47 39 Data Input select input. This pin has an internal pulldown. SEL1 48 40 Data Input select input. This pin has an internal pulldown.

30, 31, 34,

35,

3, 6, 12, 14,

3, 11, 13, 26,

29, 30

Positive power supply input.

DAP, 13, 17,

23, 25, 26, 27, 38, 39,

19, 20, 21,

12, 17, 18,

20, 33, 34

Negative power supply input.

40, 41, 42 XTAL IN/EXT CLK 18 16 Crystal or External Oscillator input. XTAL OUT 22 19 Crystal Oscillator output. NC — 21, 22 No connect.

DESCRIPTION

LMH0356

Product Folder Links: LMH0356

LMH0356

SNLS270L –AUGUST 2007–REVISED JANUARY 2016

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

Supply voltage (VCC– VEE) 4 v Logic supply voltage VEE– 0.15 VCC+ 0.15 V

Logic input current (single input)

Vi = VEE– 0.15 V –5

Vi = VCC+ 0.15 V 5 Logic output voltage VEE– 0.15 VCC+ 0.15 V Logic output source/sink current –8 8 mA Serial data output sink current 24 mA Junction temperature (TJ) 125 °C Storage temperature (T

) –65 150 °C

stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001

(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible with the necessary precautions. Pins listed as ±8000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250-V CDM is possible with the necessary precautions. Pins listed as ±1250 V may actually have higher performance.

Charged-device model (CDM), per JEDEC specification JESD22-

(2)

C101 Machine model (MM) ±400

(1)

MIN MAX UNIT

VALUE UNIT

(1)

±8000 ±1250

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

Supply voltage 3.3 – 5% 3.3 + 5% V Logic input voltage V

Differential serial input voltage 800 – 10% 800 + 10% mV Serial data or clock output sink current 16 mA Operating free-air temperature –40 85 °C

7.4 Thermal Information

LMH0356

THERMAL METRIC

θJA

θJC(top)

θJC(bot)

Junction-to-ambient thermal resistance 28.3 31.2 °C/W Junction-to-case (top) thermal resistance 8.8 16.8 °C/W Junction-to-case (bottom) thermal resistance 1.3 1.2 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report (SPRA953).

(1)

UNITRHS (WQFN) RSB (WQFN)

48 PINS 40 PINS

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LMH0356

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SNLS270L –AUGUST 2007–REVISED JANUARY 2016

7.5 DC Electrical Characteristics

over supply voltage and recommended operating temperature ranges (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SDID

CMI

SDOD

SCOD

CMO

(1) Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are referenced to (2) Typical values are stated for: VCC= 3.3 V, TA= 25°C.

(3) This parameter is ensured by characterization over voltage and temperature limits.

Logic input voltage high level 2 V Logic input voltage low level V Logic input current high level VIH= V Logic input current low level VIL= V

Logic output voltage high level IOH= −2 mA 2 V Logic output voltage low level IOL= 2 mA VEE+ 0.6 V Serial input voltage, differential SDI Input common mode voltage V Serial data output voltage,

differential

Serial clock output voltage, differential

(3)

SDID

= 200 mV

(3)

SDO, SDO2 100-Ω differential load

SCO 100-Ω differential load, 2970 MHz

(3)

SCO 100-Ω differential load,

200 1600 mV

VEE+ 0.95 VCC− 0.2 V

620 750 880 mV

400 525 650 mV

1485 or 270 MHz

Output common mode voltage

Power supply current, 3.3-V supply, total

SDO, SCO 100-Ω differential load

VCC− V

2970 Mbps, device enabled 130 150 mA Device disabled

(ENABLE = 0)

VEE(equal to zero volts).

(1)(2)

0.8 V

47 65 µA

−18 −25 µA

750 mV

SDOD

3 mA

P-P

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LMH0356

SNLS270L –AUGUST 2007–REVISED JANUARY 2016

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7.6 AC Electrical Characteristics

over supply voltage and recommended operating temperature ranges (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TOL

JIT

TOL

JIT

TOL

JIT

TOL

JIT

TOL

JIT

TOL

JIT

LOOP

JIT

ALG

ODC

REF

TOL

(1) Typical values are stated for: VCC= 3.3 V, TA= 25°C. (2) Peak-to-peak amplitude with sinusoidal modulation per SMPTE RP 184-1996 paragraph 4.1. The test data signal shall be color bars. (3) This parameter is ensured by characterization over voltage and temperature limits. (4) Refer to A1 in Figure 1 of SMPTE RP 184-1996. (5) Refer to A2 in Figure 1 of SMPTE RP 184-1996. (6) PRBS 210– 1, input jitter = 31 ps (7) PRBS 210– 1, input jitter = 24 ps (8) PRBS 210– 1, input jitter = 22 ps

Serial data rate ST-259 270 Mbps Serial data rate ST-292 1483, 1485 Mbps Serial data rate ST-424 2967, 2970 Mbps Serial input jitter tolerance 270 Mbps Serial input jitter tolerance 270 Mbps Serial input jitter tolerance 1483 or 1485 Mbps Serial input jitter tolerance 1483 or 1485 Mbps Serial input jitter tolerance 2967 or 2970 Mbps Serial input jitter tolerance 2967 or 2970 Mbps

(2) (3) (5)

Serial data output jitter 270 Mbps Serial data output jitter 1483 or 1485 Mbps Serial data output jitter 2967 or 2970 Mbps

(2)(3)(4) (2)(3)(5)

(3)(6)

(2)(3)(4) (2)(3)(5) (2)(3)(4)

(3)(7) (3)(8)

>6 UI

>0.6 UI

>6 UI

>0.6 UI

>6 UI

>0.6 UI

270-Mbps, <0.1-dB Peaking

Loop bandwidth

1485-Mbps, <0.1-dB Peaking

2970 Mbps, <0.1-dB Peaking

Serial clock output

270-Mbps data rate

frequency Serial clock output

1483-Mbps data rate

frequency Serial clock output

1485-Mbps data rate

frequency Serial clock output

2967-Mbps data rate

frequency Serial clock output

2970-Mbps data rate

frequency Serial Clock Output Jitter 2 3 ps Serial clock output

alignment with respect to

See

(3)

40% 60%

data interval Serial clock output duty

cycle

See

(3)

45% 55%

Reference clock frequency

Reference clock frequency tolerance

P-P

(1)

P-P P-P P-P P-P P-P

P-P

0.01 0.03 UI

0.04 0.05 UI

0.08 0.09 UI

P-P P-P P-P

275 kHz

1.5 MHz

2.75 MHz

270 MHz

1483 MHz

1485 MHz

2967 MHz

2970 MHz

RMS

27 MHz

±50 ppm

Product Folder Links: LMH0356

SDI 270 MBPS DATANO DATA

1485 MBPS DATA 2970 MBPS DATA 270 MBPS DATA

ACQ

SDI 270 MBPS DATANO DATA

Lock Dete

SD/HD

NO DATA 1485 MBPS DATA NO DATA

Lock Dete

SD/HD

ACQ

www.ti.com

7.7 AC Timing Requirements

T tr, t tr, t tr, t tr, t tr, t tr, t

ACQ

f f f f f f

Acquisition time See Logic inputs rise/fall time 10%–90% 1.5 ns Input rise/fall time 20%–80%, 270 Mbps Input rise/fall time 20%–80%, 1483 or 1485 Mbps Input rise/fall time 20%–80%, 2967 or 2970 Mbps Logic outputs rise/fall time 10%–90% 1.5 ns Output rise/fall time 20%–80%

(1) Measured from first SDI transition until Lock Detect output goes high (true). (2) This specification is ensured by design. (3) RL= 100-Ω differential. (4) This parameter is ensured by characterization over voltage and temperature limits.

(1)

(2)

(2) (2)

(3) (4)

LMH0356

SNLS270L –AUGUST 2007–REVISED JANUARY 2016

MIN NOM MAX UNIT

15 ms

1500 ps

270 ps 135 ps

90 130 ps

= Acquisition Time, defined in AC Timing Requirements

ACQ

T1= Time from Lock Detect assertion or deassertion until SD/HD output is valid, typically 37 ns (one 27-MHz clock period)

T2= Time from SDI input change until Lock Detect deassertion, 1 ms maximum. SD/HD output is not valid during this time.

Figure 1. SDI, Lock Detect, and SD/HD Timing

Product Folder Links: LMH0356

RETIMER / FIFO

VCO / PLL

SDI0

LOCK DETECT

SDO

CONTROL LOGIC

AUTO BYPASS

BYPASS/

O/P MUTE

RATE0 RATE1

XTAL IN/EXT CLK

XTAL OUT

LOOP FILTER 1 LOOP FILTER 2

SCO_EN

SCO/SDO2

BYPASS

SDI0

SDO

CCO

SD/

CCO

SCO/SDO2

SDI1 SDI1

SDI2 SDI2

SDI3 SDI3

SEL0 SEL1

ENABLE

EQUALIZER

LMH0356

SNLS270L –AUGUST 2007–REVISED JANUARY 2016

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8 Detailed Description

8.1 Overview

The LMH0356 3-Gbps HD/SD SDI Reclocker with 4:1 Input Mux and FR4 EQs is used in many types of digital video signal processing equipment. Supported serial digital video standards are ST-259, ST-292, and ST-424. Corresponding serial data rates are 270 Mbps, 1.483 Gbps, 1.485 Gbps, 2.967 Gbps, and 2.97 Gbps. DVB-ASI data at 270 Mbps may also be retimed. The LMH0356 retimes the serial data stream to suppress accumulated jitter. It provides two low-jitter, differential, serial data outputs. The second output may be selected to output either serial data or a low-jitter serial data-rate clock. Controls and indicators are: serial clock or second serial data output select, manual rate select input, SD/HD rate output, lock detect output, auto/manual data bypass and output mute.

Serial data inputs are CML and LVPECL compatible. Serial data and clock outputs are differential CML and produce LVPECL compatible levels. The output buffer design can drive AC or DC-coupled, terminated 100-Ω differential loads. The differential output level is 750 mV inputs and outputs are LVCMOS compatible.

The device package is a 48-pin WQFN or a 40-pin WQFN. Both package options have an exposed die attach pad. The exposed die attach pad is electrically connected to device ground (VEE) and is the primary electrical terminal for the device. This terminal must be connected to the negative power supply or circuit ground.

8.2 Functional Block Diagram

into 100-Ω AC- or DC-coupled differential loads. Logic

P-P

Product Folder Links: LMH0356

+ 22 hidden pages

Texas Instruments LMH0356 Datasheet

1 Features

3 Description

2 Applications

Table of Contents

4 Revision History

5 Description (continued)

6 Pin Configuration and Functions

7 Specifications

7.1 Absolute Maximum Ratings

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

7.5 DC Electrical Characteristics

7.6 AC Electrical Characteristics

7.7 AC Timing Requirements

8 Detailed Description

8.1 Overview

8.2 Functional Block Diagram