Texas Instruments LMH0036 Datasheet

LMH0036

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SNLS254B –MARCH 2008–REVISED APRIL 2013

LMH0036 SD SDI Reclocker with 4:1 Input Multiplexer

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FEATURES

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• Supports SMPTE 259M (C) Serial Digital Video Standard

• Supports 270 Mbps Serial Data Rate Operation

• Supports DVB-ASI at 270 Mbps Equipment

• Single 3.3V Supply Operation – DVB-ASI Equipment

• 360 mW Typical Power Consumption – Video Standards and Format Converters

• Integrated 4:1 Multiplexed Input

• Two Differential, Reclocked Outputs

• Choice of Second Reclocked Output or LowJitter, Differential, Data-Rate Clock Output

• Single 27 MHz External Crystal or Reference Clock Input

• Lock Detect Indicator Output

• Output Mute Function for Data and Clock

• Auto/Manual Reclocker Bypass

• Differential LVPECL Compatible Serial Data Inputs and Outputs

• LVCMOS Control Inputs and Indicator Outputs

• 48-Pin WQFN Package

• Industrial Temperature Range: -40°C to +85°C

• Footprint Compatible with the LMH0056 and LMH0356

APPLICATIONS

• SDTV Serial Digital Video Interfaces for: – Digital Video Routers and Switchers – Digital Video Processing and Editing

DESCRIPTION

The LMH0036 SD SDI Reclocker with 4:1 Input Multiplexer retimes serial digital video data conforming to the SMPTE 259M (C) standard. The LMH0036 operates at the serial data rate of 270 Mbps, and also supports DVB-ASI operation at 270 Mbps. The LMH0036 includes an integrated 4:1 input multiplexer for selecting one of four input data streams for retiming.

The LMH0036 retimes the incoming data to suppress accumulated jitter. The LMH0036 recovers the serial data-rate clock and optionally provides it as an output. The LMH0036 has two differential serial data outputs; the second output may be selected as a lowjitter, data-rate clock output. Controls and indicators are: serial clock or second serial data output select, manual rate select input, SD indicator output, lock detect output, auto/manual data bypass, and output mute. The serial data inputs, outputs, and serial datarate clock outputs are differential LVPECL compatible. The CML serial data and serial data-rate clock outputs are suitable for driving 100Ω differentially terminated networks. The control logic inputs and outputs are LVCMOS compatible.

The LMH0036 is powered from a single 3.3V supply. Power dissipation is typically 360 mW. The device is housed in a 48-pin WQFN package.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

RETIMER/FIFO

VCO/PLL

SDI0

LOCK DETECT

SDO

CONTROL LOGIC

AUTO BYPASS

BYPASS/

O/P MUTE

50

XTAL IN/EXT CLK

XTAL OUT

LOOP FILTER 1 LOOP FILTER 2

SCO_EN

SCO/SDO2

BYPASS

SDI0

SDO

50

V

CCO

V

CCO

SCO/SDO2

SDI1 SDI1

SDI2 SDI2

SDI3 SDI3

SEL0 SEL1

SD

LMH0074 Equalizer

Crosspoint

LMH0036 Reclocker

LMH0001

Cable Driver

LMH0074 Equalizer

LMH0001

Cable Driver

LMH0001

Cable Driver

LMH0001

Cable Driver

Crosspoint

LMH0036

SNLS254B –MARCH 2008–REVISED APRIL 2013

Typical Application

Block Diagram

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LMH0036

(top view)

V

CC

SDI0

SCO/SDO2

V

CC

XTAL IN/

EXT CLK

V

EE

V

CC

SDI1

V

CC

SDI2

SDI3

2

3

4

5

6

7

8

9

10

11

12

13 14 15 16 17 18 19 20 21 22 23 24

36

35

34

33

32

31

30

29

28

27

26

25

48 47 46 45 44 43 42 41 40 39 38 37

SDO

V

EE

V

CC

V

EE

LF1

SEL1

SEL0

LF2

V

EE

SCO_EN

V

EE

V

CC

V

CC

V

EE

V

EE

V

CC

V

CC

O/P MUTE

XTAL OUT

VEEV

EE

V

EE

LOCK DET

V

EE

SD

RSVD

NC

V

EE

V

EE

V

EE

BYPASS/

AUTOBYPASS

LMH0036

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Connection Diagram

SNLS254B –MARCH 2008–REVISED APRIL 2013

The exposed die attach pad is the primary negative electrical terminal for this device. It must be connected to the negative power supply voltage.

See Package Number RHS0048A

Figure 1. 48-Pin WQFN

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SNLS254B –MARCH 2008–REVISED APRIL 2013

PIN DESCRIPTIONS

Pin Name Description

1 SDI0 Data Input 0 True. 2 SDI0 Data Input 0 Complement. 4 SDI1 Data Input 1 True. 5 SDI1 Data Input 1 Complement 7 SDI2 Data Input 2 True.

8 SDI2 Data Input 2 Complement. 10 SDI3 Data Input 3 True. 11 SDI3 Data Input 3 Complement.

15 BYPASS/AUTO BYPASS pulldown.

16 OUTPUT MUTE pullup. 18 XTAL IN/EXT CLK Crystal or External Oscillator input. 22 XTAL OUT Crystal Oscillator output. 24 LOCK DETECT PLL Lock Detect output (active high). 28 SCO/SDO2 Serial Clock or Serial Data Output 2 complement. 29 SCO/SDO2 Serial Clock or Serial Data Output 2 true. 32 SDO Data Output complement. 33 SDO Data Output true. 36 SD SD indicator output. Output is high when locked to 270 Mbps.

37 SCO_EN high and the data when low. This pin has an internal pulldown. 43 LF1 Loop Filter. 44 LF2 Loop Filter. 45 NC No Connect. Not bonded internally. 46 RSVD Reserved. Do not connect or connect to ground. 47 SEL0 Data Input select input. This pin has an internal pulldown. 48 SEL1 Data Input select input. This pin has an internal pulldown.

3, 6, 12, 14,

30, 31, 34, 35 V

DAP, 13, 17,

19, 20, 21, 23, 25, 26, 27, 38, 39,

40, 41, 42 V

CC

EE

Bypass/Auto Bypass mode select. Bypasses reclocking when high. This pin has an internal

Data and Clock Output Mute input. Mutes the output when low. This pin has an internal

Serial Clock or Serial Data 2 Output select. Sets second output to output the clock when

Positive power supply input.

Negative power supply input.

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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ABSOLUTE MAXIMUM RATINGS

(1)(2)

SNLS254B –MARCH 2008–REVISED APRIL 2013

Supply Voltage (VCC–VEE) 4.0V Logic Supply Voltage (Vi) VEE−0.15V to VCC+0.15V Logic Input Current (single input) Vi = VEE−0.15V −5 mA

Vi = VCC+0.15V +5 mA Logic Output Voltage (Vo) VEE−0.15V to VCC+0.15V Logic Output Source/Sink Current ±8 mA Serial Data Input Voltage (V Serial Data Output Sink Current (I

) VCCto VCC−2.0V

SDI

) 24 mA

SDO

Package Thermal Resistance θJA48-pin WQFN 26.1°C/W

θ

48-pin WQFN 1.9°C/W

JC

Storage Temp. Range −65°C to +150°C Junction Temperature +150°C Lead Temperature (Soldering 4 Sec) +260°C (Pb-free) ESD Rating (HBM) 8 kV ESD Rating (MM) 400V ESD Rating (CDM) 1250V

(1) “Absolute Maximum Ratings” are those parameter values beyond which the life and operation of the device cannot be ensured. The

stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values.

DC ELECTRICAL CHARACTERISTICS and AC ELECTRICAL CHARACTERISTICS specify acceptable device operating conditions.

(2) It is anticipated that this device will not be offered in a military qualified version. If Military/Aerospace specified devices are

required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.

RECOMMENDED OPERATING CONDITIONS

Supply Voltage (VCC–VEE) 3.3V ±5% Logic Input Voltage VEEto V Differential Serial Input Voltage 800 mV ±10% Serial Data or Clock Output Sink Current (ISO) 16 mA max. Operating Free Air Temperature (TA) −40°C to +85°C

DC ELECTRICAL CHARACTERISTICS

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.

Symbol Parameter Conditions Reference Min Typ Max Units

V V

V

SDID

V

SDOD

V

CMO

I

(1) Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are referenced to

VEE(equal to zero volts).

(2) Typical values are stated for: VCC= +3.3V, TA= +25°C.

Input Voltage High Level Logic level inputs 2 V

IH

Input Voltage Low Level V

IL

I

Input Current High Level VIH= V

IH

I

Input Current Low Level VIL= V

IL

Output Voltage High Level IOH= −2 mA All logic level 2 V

OH

Output Voltage Low Level IOL= +2 mA VEE+ 0.6 V

OL

CC

EE

outputs

Serial Input Voltage, SDI Differential

Input Common Mode V

CMI

Voltage

= 200 mV SDI

SDID

Serial Output Voltage, 100Ω differential load SDO, SCO Differential

Output Common Mode 100Ω differential load SDO, SCO V Voltage

Power Supply Current, 270 Mbps, NTSC color bar

CC

3.3V supply, Total pattern

(1)(2)

CC

EE

0.8 V

47 65 µA

−18 −25 µA

200 1600 mV

VEE+1.2 VCC−0.2 V

720 800 880 mV

−

CC

V

SDOD

109 mA

V

P-P

V

CC

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SNLS254B –MARCH 2008–REVISED APRIL 2013

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AC ELECTRICAL CHARACTERISTICS

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.

Symbol Parameter Conditions Reference Min Typ Max Units

BR

TOL

t

BW

F

t

T

tr, t tr, t tr, t tr, t

F

Serial Data Rate SMPTE 259M (C) SDI, SDO 270 Mbps

SD

Serial Input Jitter 270 Mbps

JIT

Tolerance Serial Input Jitter 270 Mbps

JIT

Tolerance Serial Data Output Jitter 270 Mbps

JIT

Loop Bandwidth 270 Mbps,

LOOP

Serial Clock Output 270 Mbps data rate SCO

CO

Frequency Serial Clock Output Jitter 2 3 ps

JIT

<0.1dB Peaking

(2)(3)(4)

(2)(3)(5)

(3)(6)

SDI

SDO 0.02 0.08 UI

Serial Clock Output SDO, SCO Alignment with respect to 40 60 % Data Interval

Serial Clock Output Duty SCO Cycle

Acquisition Time See

ACQ

Input rise/fall time 10%–90% Logic inputs 1.5 3 ns

f

Input rise/fall time 20%–80% SDI 1500 ps

f

Output rise/fall time 10%–90% Logic outputs 1.5 3 ns

f

Output rise/fall time 20%–80%

f

Reference Clock

REF

Frequency Ref. Clock Freq.

TOL

Tolerance

(7)(8)

(9)

SCO, SDO 90 130 ps

(1)

>6 UI

>0.6 UI

300 kHz

270 MHz

45 55 %

15 ms

27 MHz

±50 ppm

P-P

RMS

(1) Typical values are stated for: VCC= +3.3V, TA= +25°C. (2) Peak-to-peak amplitude with sinusoidal modulation per SMPTE RP 184-1996 paragraph 4.1. The test data signal shall be color bars. (3) This parameter is ensured by characterization over voltage and temperature limits. (4) Refer to “A1” in Figure 1 of SMPTE RP 184-1996. (5) Refer to “A2” in Figure 1 of SMPTE RP 184-1996. (6) Serial Data Output Jitter is total output jitter with 0.2UI (7) Specification is ensured by design.

input jitter.

P-P

(8) Measured from first SDI transition until Lock Detect (LD) output goes high (true). (9) RL= 100Ω differential.

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