TEXAS INSTRUMENTS LM3S2637 Technical data
PRELIMINARY
LM3S2637 Microcontroller
DATA SHEET
Copyright © 2007 Luminary Micro, Inc.DS-LM3S2637-1972
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Preliminary
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LM3S2637 Microcontroller
Table of Contents
About This Document .................................................................................................................... 19
Audience .............................................................................................................................................. 19
About This Manual ................................................................................................................................ 19
Related Documents ............................................................................................................................... 19
Documentation Conventions .................................................................................................................. 19
1 Architectural Overview ...................................................................................................... 21
1.1 Product Features ...................................................................................................................... 21
1.2 Target Applications .................................................................................................................... 26
1.3 High-Level Block Diagram ......................................................................................................... 26
1.4 Functional Overview .................................................................................................................. 27
1.4.1 ARM Cortex™-M3 ..................................................................................................................... 28
1.4.2 Motor Control Peripherals .......................................................................................................... 28
1.4.3 Analog Peripherals .................................................................................................................... 29
1.4.4 Serial Communications Peripherals ............................................................................................ 29
1.4.5 System Peripherals ................................................................................................................... 31
1.4.6 Memory Peripherals .................................................................................................................. 32
1.4.7 Additional Features ................................................................................................................... 32
1.4.8 Hardware Details ...................................................................................................................... 33
2 ARM Cortex-M3 Processor Core ...................................................................................... 34
2.1 Block Diagram .......................................................................................................................... 35
2.2 Functional Description ............................................................................................................... 35
2.2.1 Serial Wire and JTAG Debug ..................................................................................................... 35
2.2.2 Embedded Trace Macrocell (ETM) ............................................................................................. 36
2.2.3 Trace Port Interface Unit (TPIU) ................................................................................................. 36
2.2.4 ROM Table ............................................................................................................................... 36
2.2.5 Memory Protection Unit (MPU) ................................................................................................... 36
2.2.6 Nested Vectored Interrupt Controller (NVIC) ................................................................................ 36
3 Memory Map ....................................................................................................................... 40
4 Interrupts ............................................................................................................................ 42
5 JTAG Interface .................................................................................................................... 45
5.1 Block Diagram .......................................................................................................................... 46
5.2 Functional Description ............................................................................................................... 46
5.2.1 JTAG Interface Pins .................................................................................................................. 47
5.2.2 JTAG TAP Controller ................................................................................................................. 48
5.2.3 Shift Registers .......................................................................................................................... 49
5.2.4 Operational Considerations ........................................................................................................ 49
5.3 Initialization and Configuration ................................................................................................... 52
5.4 Register Descriptions ................................................................................................................ 52
5.4.1 Instruction Register (IR) ............................................................................................................. 52
5.4.2 Data Registers .......................................................................................................................... 54
6 System Control ................................................................................................................... 56
6.1 Functional Description ............................................................................................................... 56
6.1.1 Device Identification .................................................................................................................. 56
6.1.2 Reset Control ............................................................................................................................ 56
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6.1.3 Power Control ........................................................................................................................... 59
6.1.4 Clock Control ............................................................................................................................ 59
6.1.5 System Control ......................................................................................................................... 61
6.2 Initialization and Configuration ................................................................................................... 62
6.3 Register Map ............................................................................................................................ 62
6.4 Register Descriptions ................................................................................................................ 63
7 Hibernation Module .......................................................................................................... 115
7.1 Block Diagram ........................................................................................................................ 116
7.2 Functional Description ............................................................................................................. 116
7.2.1 Register Access Timing ........................................................................................................... 116
7.2.2 Clock Source .......................................................................................................................... 117
7.2.3 Battery Management ............................................................................................................... 117
7.2.4 Real-Time Clock ...................................................................................................................... 117
7.2.5 Non-Volatile Memory ............................................................................................................... 118
7.2.6 Power Control ......................................................................................................................... 118
7.2.7 Interrupts and Status ............................................................................................................... 118
7.3 Initialization and Configuration ................................................................................................. 119
7.3.1 Initialization ............................................................................................................................. 119
7.3.2 RTC Match Functionality (No Hibernation) ................................................................................ 119
7.3.3 RTC Match/Wake-Up from Hibernation ..................................................................................... 119
7.3.4 External Wake-Up from Hibernation .......................................................................................... 120
7.3.5 RTC/External Wake-Up from Hibernation .................................................................................. 120
7.4 Register Map .......................................................................................................................... 120
7.5 Register Descriptions .............................................................................................................. 121
8 Internal Memory ............................................................................................................... 134
8.1 Block Diagram ........................................................................................................................ 134
8.2 Functional Description ............................................................................................................. 134
8.2.1 SRAM Memory ........................................................................................................................ 134
8.2.2 Flash Memory ......................................................................................................................... 135
8.3 Flash Memory Initialization and Configuration ........................................................................... 136
8.3.1 Flash Programming ................................................................................................................. 136
8.3.2 Nonvolatile Register Programming ........................................................................................... 137
8.4 Register Map .......................................................................................................................... 137
8.5 Flash Register Descriptions (Flash Control Offset) ..................................................................... 138
8.6 Flash Register Descriptions (System Control Offset) .................................................................. 145
9 General-Purpose Input/Outputs (GPIOs) ....................................................................... 158
9.1 Functional Description ............................................................................................................. 158
9.1.1 Data Control ........................................................................................................................... 159
9.1.2 Interrupt Control ...................................................................................................................... 160
9.1.3 Mode Control .......................................................................................................................... 161
9.1.4 Commit Control ....................................................................................................................... 161
9.1.5 Pad Control ............................................................................................................................. 161
9.1.6 Identification ........................................................................................................................... 161
9.2 Initialization and Configuration ................................................................................................. 161
9.3 Register Map .......................................................................................................................... 163
9.4 Register Descriptions .............................................................................................................. 164
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10 General-Purpose Timers ................................................................................................. 199
10.1 Block Diagram ........................................................................................................................ 199
10.2 Functional Description ............................................................................................................. 200
10.2.1 GPTM Reset Conditions .......................................................................................................... 201
10.2.2 32-Bit Timer Operating Modes .................................................................................................. 201
10.2.3 16-Bit Timer Operating Modes .................................................................................................. 202
10.3 Initialization and Configuration ................................................................................................. 206
10.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 206
10.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 207
10.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 207
10.3.4 16-Bit Input Edge Count Mode ................................................................................................. 208
10.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 208
10.3.6 16-Bit PWM Mode ................................................................................................................... 209
10.4 Register Map .......................................................................................................................... 209
10.5 Register Descriptions .............................................................................................................. 210
11 Watchdog Timer ............................................................................................................... 235
11.1 Block Diagram ........................................................................................................................ 235
11.2 Functional Description ............................................................................................................. 235
11.3 Initialization and Configuration ................................................................................................. 236
11.4 Register Map .......................................................................................................................... 236
11.5 Register Descriptions .............................................................................................................. 237
12 Analog-to-Digital Converter (ADC) ................................................................................. 258
12.1 Block Diagram ........................................................................................................................ 259
12.2 Functional Description ............................................................................................................. 259
12.2.1 Sample Sequencers ................................................................................................................ 259
12.2.2 Module Control ........................................................................................................................ 260
12.2.3 Hardware Sample Averaging Circuit ......................................................................................... 261
12.2.4 Analog-to-Digital Converter ...................................................................................................... 261
12.2.5 Test Modes ............................................................................................................................. 261
12.2.6 Internal Temperature Sensor .................................................................................................... 261
12.3 Initialization and Configuration ................................................................................................. 262
12.3.1 Module Initialization ................................................................................................................. 262
12.3.2 Sample Sequencer Configuration ............................................................................................. 262
12.4 Register Map .......................................................................................................................... 263
12.5 Register Descriptions .............................................................................................................. 264
13 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 291
13.1 Block Diagram ........................................................................................................................ 292
13.2 Functional Description ............................................................................................................. 292
13.2.1 Transmit/Receive Logic ........................................................................................................... 292
13.2.2 Baud-Rate Generation ............................................................................................................. 293
13.2.3 Data Transmission .................................................................................................................. 294
13.2.4 Serial IR (SIR) ......................................................................................................................... 294
13.2.5 FIFO Operation ....................................................................................................................... 295
13.2.6 Interrupts ................................................................................................................................ 295
13.2.7 Loopback Operation ................................................................................................................ 296
13.2.8 IrDA SIR block ........................................................................................................................ 296
13.3 Initialization and Configuration ................................................................................................. 296
13.4 Register Map .......................................................................................................................... 297
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13.5 Register Descriptions .............................................................................................................. 298
14 Synchronous Serial Interface (SSI) ................................................................................ 332
14.1 Block Diagram ........................................................................................................................ 332
14.2 Functional Description ............................................................................................................. 332
14.2.1 Bit Rate Generation ................................................................................................................. 333
14.2.2 FIFO Operation ....................................................................................................................... 333
14.2.3 Interrupts ................................................................................................................................ 333
14.2.4 Frame Formats ....................................................................................................................... 334
14.3 Initialization and Configuration ................................................................................................. 341
14.4 Register Map .......................................................................................................................... 342
14.5 Register Descriptions .............................................................................................................. 343
15 Inter-Integrated Circuit (I2C) Interface ............................................................................ 369
15.1 Block Diagram ........................................................................................................................ 369
15.2 Functional Description ............................................................................................................. 369
15.2.1 I2C Bus Functional Overview .................................................................................................... 370
15.2.2 Available Speed Modes ........................................................................................................... 372
15.2.3 Interrupts ................................................................................................................................ 373
15.2.4 Loopback Operation ................................................................................................................ 373
15.2.5 Command Sequence Flow Charts ............................................................................................ 374
15.3 Initialization and Configuration ................................................................................................. 380
15.4 I2C Register Map ..................................................................................................................... 381
15.5 Register Descriptions (I2C Master) ........................................................................................... 382
15.6 Register Descriptions (I2C Slave) ............................................................................................. 395
16 Controller Area Network (CAN) Module ......................................................................... 404
16.1 Controller Area Network Overview ............................................................................................ 404
16.2 Controller Area Network Features ............................................................................................ 404
16.3 Controller Area Network Block Diagram .................................................................................... 405
16.4 Controller Area Network Functional Description ......................................................................... 406
16.4.1 Initialization ............................................................................................................................. 406
16.4.2 Operation ............................................................................................................................... 407
16.4.3 Transmitting Message Objects ................................................................................................. 407
16.4.4 Configuring a Transmit Message Object .................................................................................... 407
16.4.5 Updating a Transmit Message Object ....................................................................................... 408
16.4.6 Accepting Received Message Objects ...................................................................................... 408
16.4.7 Receiving a Data Frame .......................................................................................................... 409
16.4.8 Receiving a Remote Frame ...................................................................................................... 409
16.4.9 Receive/Transmit Priority ......................................................................................................... 409
16.4.10 Configuring a Receive Message Object .................................................................................... 409
16.4.11 Handling of Received Message Objects .................................................................................... 410
16.4.12 Handling of Interrupts .............................................................................................................. 410
16.4.13 Bit Timing Configuration Error Considerations ........................................................................... 411
16.4.14 Bit Time and Bit Rate ............................................................................................................... 411
16.4.15 Calculating the Bit Timing Parameters ...................................................................................... 413
16.5 Controller Area Network Register Map ...................................................................................... 415
16.6 Register Descriptions .............................................................................................................. 417
17 Analog Comparators ....................................................................................................... 445
17.1 Block Diagram ........................................................................................................................ 446
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17.2 Functional Description ............................................................................................................. 446
17.2.1 Internal Reference Programming .............................................................................................. 448
17.3 Initialization and Configuration ................................................................................................. 449
17.4 Register Map .......................................................................................................................... 449
17.5 Register Descriptions .............................................................................................................. 450
18 Pin Diagram ...................................................................................................................... 458
19 Signal Tables .................................................................................................................... 459
20 Operating Characteristics ............................................................................................... 472
21 Electrical Characteristics ................................................................................................ 473
21.1 DC Characteristics .................................................................................................................. 473
21.1.1 Maximum Ratings ................................................................................................................... 473
21.1.2 Recommended DC Operating Conditions .................................................................................. 473
21.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ............................................................ 474
21.1.4 Power Specifications ............................................................................................................... 474
21.1.5 Flash Memory Characteristics .................................................................................................. 476
21.2 AC Characteristics ................................................................................................................... 476
21.2.1 Load Conditions ...................................................................................................................... 476
21.2.2 Clocks .................................................................................................................................... 476
21.2.3 Analog-to-Digital Converter ...................................................................................................... 477
21.2.4 Analog Comparator ................................................................................................................. 478
21.2.5 I2C ......................................................................................................................................... 478
21.2.6 Hibernation Module ................................................................................................................. 479
21.2.7 Synchronous Serial Interface (SSI) ........................................................................................... 479
21.2.8 JTAG and Boundary Scan ........................................................................................................ 481
21.2.9 General-Purpose I/O ............................................................................................................... 482
21.2.10 Reset ..................................................................................................................................... 483
22 Package Information ........................................................................................................ 485
A Serial Flash Loader .......................................................................................................... 487
A.1 Serial Flash Loader ................................................................................................................. 487
A.2 Interfaces ............................................................................................................................... 487
A.2.1 UART ..................................................................................................................................... 487
A.2.2 SSI ......................................................................................................................................... 487
A.3 Packet Handling ...................................................................................................................... 488
A.3.1 Packet Format ........................................................................................................................ 488
A.3.2 Sending Packets ..................................................................................................................... 488
A.3.3 Receiving Packets ................................................................................................................... 488
A.4 Commands ............................................................................................................................. 489
A.4.1 COMMAND_PING (0X20) ........................................................................................................ 489
A.4.2 COMMAND_GET_STATUS (0x23) ........................................................................................... 489
A.4.3 COMMAND_DOWNLOAD (0x21) ............................................................................................. 489
A.4.4 COMMAND_SEND_DATA (0x24) ............................................................................................. 490
A.4.5 COMMAND_RUN (0x22) ......................................................................................................... 490
A.4.6 COMMAND_RESET (0x25) ..................................................................................................... 490
B Register Quick Reference ............................................................................................... 492
C Ordering and Contact Information ................................................................................. 509
C.1 Ordering Information ................................................................................................................ 509
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C.2 Kits ......................................................................................................................................... 509
C.3 Company Information .............................................................................................................. 509
C.4 Support Information ................................................................................................................. 510
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List of Figures
Figure 1-1. Stellaris®2000 Series High-Level Block Diagram ............................................................... 27
Figure 2-1. CPU Block Diagram ......................................................................................................... 35
Figure 2-2. TPIU Block Diagram ........................................................................................................ 36
Figure 5-1. JTAG Module Block Diagram ............................................................................................ 46
Figure 5-2. Test Access Port State Machine ....................................................................................... 49
Figure 5-3. IDCODE Register Format ................................................................................................. 54
Figure 5-4. BYPASS Register Format ................................................................................................ 55
Figure 5-5. Boundary Scan Register Format ....................................................................................... 55
Figure 6-1. External Circuitry to Extend Reset .................................................................................... 57
Figure 7-1. Hibernation Module Block Diagram ................................................................................. 116
Figure 8-1. Flash Block Diagram ...................................................................................................... 134
Figure 9-1. GPIO Port Block Diagram ............................................................................................... 159
Figure 9-2. GPIODATA Write Example ............................................................................................. 160
Figure 9-3. GPIODATA Read Example ............................................................................................. 160
Figure 10-1. GPTM Module Block Diagram ........................................................................................ 200
Figure 10-2. 16-Bit Input Edge Count Mode Example .......................................................................... 204
Figure 10-3. 16-Bit Input Edge Time Mode Example ........................................................................... 205
Figure 10-4. 16-Bit PWM Mode Example ............................................................................................ 206
Figure 11-1. WDT Module Block Diagram .......................................................................................... 235
Figure 12-1. ADC Module Block Diagram ........................................................................................... 259
Figure 12-2. Internal Temperature Sensor Characteristic ..................................................................... 262
Figure 13-1. UART Module Block Diagram ......................................................................................... 292
Figure 13-2. UART Character Frame ................................................................................................. 293
Figure 13-3. IrDA Data Modulation ..................................................................................................... 295
Figure 14-1. SSI Module Block Diagram ............................................................................................. 332
Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) .................................................... 334
Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 335
Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 336
Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 336
Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 337
Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 338
Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 338
Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 339
Figure 14-10. MICROWIRE Frame Format (Single Frame) .................................................................... 340
Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 341
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 341
Figure 15-1. I2C Block Diagram ......................................................................................................... 369
Figure 15-2. I2C Bus Configuration .................................................................................................... 370
Figure 15-3. START and STOP Conditions ......................................................................................... 370
Figure 15-4. Complete Data Transfer with a 7-Bit Address ................................................................... 371
Figure 15-5. R/S Bit in First Byte ........................................................................................................ 371
Figure 15-6. Data Validity During Bit Transfer on the I2C Bus ............................................................... 371
Figure 15-7. Master Single SEND ...................................................................................................... 374
Figure 15-8. Master Single RECEIVE ................................................................................................. 375
Figure 15-9. Master Burst SEND ....................................................................................................... 376
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Figure 15-10. Master Burst RECEIVE .................................................................................................. 377
Figure 15-11. Master Burst RECEIVE after Burst SEND ........................................................................ 378
Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 379
Figure 15-13. Slave Command Sequence ............................................................................................ 380
Figure 16-1. CAN Module Block Diagram ........................................................................................... 405
Figure 16-2. CAN Bit Time ................................................................................................................ 412
Figure 17-1. Analog Comparator Module Block Diagram ..................................................................... 446
Figure 17-2. Structure of Comparator Unit .......................................................................................... 447
Figure 17-3. Comparator Internal Reference Structure ........................................................................ 448
Figure 18-1. Pin Connection Diagram ................................................................................................ 458
Figure 21-1. Load Conditions ............................................................................................................ 476
Figure 21-2. I2C Timing ..................................................................................................................... 479
Figure 21-3. Hibernation Module Timing ............................................................................................. 479
Figure 21-4. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 480
Figure 21-5. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 480
Figure 21-6. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 481
Figure 21-7. JTAG Test Clock Input Timing ......................................................................................... 482
Figure 21-8. JTAG Test Access Port (TAP) Timing .............................................................................. 482
Figure 21-9. JTAG TRST Timing ........................................................................................................ 482
Figure 21-10. External Reset Timing (RST) .......................................................................................... 483
Figure 21-11. Power-On Reset Timing ................................................................................................. 484
Figure 21-12. Brown-Out Reset Timing ................................................................................................ 484
Figure 21-13. Software Reset Timing ................................................................................................... 484
Figure 21-14. Watchdog Reset Timing ................................................................................................. 484
Figure 22-1. 100-Pin LQFP Package .................................................................................................. 485
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LM3S2637 Microcontroller
List of Tables
Table 1. Documentation Conventions ............................................................................................ 19
Table 3-1. Memory Map ................................................................................................................... 40
Table 4-1. Exception Types .............................................................................................................. 42
Table 4-2. Interrupts ........................................................................................................................ 43
Table 5-1. JTAG Port Pins Reset State ............................................................................................. 47
Table 5-2. JTAG Instruction Register Commands ............................................................................... 52
Table 6-1. System Control Register Map ........................................................................................... 62
Table 7-1. Hibernation Module Register Map ................................................................................... 120
Table 8-1. Flash Protection Policy Combinations ............................................................................. 136
Table 8-2. Flash Resident Registers ............................................................................................... 137
Table 8-3. Flash Register Map ........................................................................................................ 137
Table 9-1. GPIO Pad Configuration Examples ................................................................................. 162
Table 9-2. GPIO Interrupt Configuration Example ............................................................................ 162
Table 9-3. GPIO Register Map ....................................................................................................... 163
Table 10-1. Available CCP Pins ........................................................................................................ 200
Table 10-2. 16-Bit Timer With Prescaler Configurations ..................................................................... 203
Table 10-3. Timers Register Map ...................................................................................................... 209
Table 11-1. Watchdog Timer Register Map ........................................................................................ 236
Table 12-1. Samples and FIFO Depth of Sequencers ........................................................................ 259
Table 12-2. ADC Register Map ......................................................................................................... 263
Table 13-1. UART Register Map ....................................................................................................... 297
Table 14-1. SSI Register Map .......................................................................................................... 342
Table 15-1. Examples of I2C Master Timer Period versus Speed Mode ............................................... 372
Table 15-2. Inter-Integrated Circuit (I2C) Interface Register Map ......................................................... 381
Table 15-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................ 386
Table 16-1. Transmit Message Object Bit Settings ............................................................................. 408
Table 16-2. Receive Message Object Bit Settings .............................................................................. 410
Table 16-3. CAN Protocol Ranges .................................................................................................... 412
Table 16-4. CAN Register Map ......................................................................................................... 415
Table 17-1. Comparator 0 Operating Modes ..................................................................................... 447
Table 17-2. Comparator 1 Operating Modes ..................................................................................... 447
Table 17-3. Comparator 2 Operating Modes ...................................................................................... 448
Table 17-4. Internal Reference Voltage and ACREFCTL Field Values ................................................. 448
Table 17-5. Analog Comparators Register Map ................................................................................. 450
Table 19-1. Signals by Pin Number ................................................................................................... 459
Table 19-2. Signals by Signal Name ................................................................................................. 463
Table 19-3. Signals by Function, Except for GPIO ............................................................................. 467
Table 19-4. GPIO Pins and Alternate Functions ................................................................................. 470
Table 20-1. Temperature Characteristics ........................................................................................... 472
Table 20-2. Thermal Characteristics ................................................................................................. 472
Table 21-1. Maximum Ratings .......................................................................................................... 473
Table 21-2. Recommended DC Operating Conditions ........................................................................ 473
Table 21-3. LDO Regulator Characteristics ....................................................................................... 474
Table 21-4. Detailed Power Specifications ........................................................................................ 475
Table 21-5. Flash Memory Characteristics ........................................................................................ 476
Table 21-6. Phase Locked Loop (PLL) Characteristics ....................................................................... 476
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Table 21-7. Clock Characteristics ..................................................................................................... 476
Table 21-8. Crystal Characteristics ................................................................................................... 477
Table 21-9. ADC Characteristics ....................................................................................................... 477
Table 21-10. Analog Comparator Characteristics ................................................................................. 478
Table 21-11. Analog Comparator Voltage Reference Characteristics .................................................... 478
Table 21-12. I2C Characteristics ......................................................................................................... 478
Table 21-13. Hibernation Module Characteristics ................................................................................. 479
Table 21-14. SSI Characteristics ........................................................................................................ 479
Table 21-15. JTAG Characteristics ..................................................................................................... 481
Table 21-16. GPIO Characteristics ..................................................................................................... 483
Table 21-17. Reset Characteristics ..................................................................................................... 483
Table C-1. Part Ordering Information ............................................................................................... 509
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LM3S2637 Microcontroller
List of Registers
System Control .............................................................................................................................. 56
Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 64
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 66
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 67
Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 68
Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 69
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 70
Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 71
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 72
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 76
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 77
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 79
Register 12: Device Identification 1 (DID1), offset 0x004 ....................................................................... 80
Register 13: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 82
Register 14: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 83
Register 15: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 85
Register 16: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 87
Register 17: Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 89
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 90
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 92
Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 94
Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 .................................... 96
Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 .................................. 99
Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 102
Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 105
Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 107
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 109
Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 111
Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 112
Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 114
Hibernation Module ..................................................................................................................... 115
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 122
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 123
Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 124
Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 125
Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 126
Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 128
Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 129
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 130
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 131
Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 132
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 133
Internal Memory ........................................................................................................................... 134
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 139
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 140
Preliminary
13November 30, 2007
Table of Contents
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 141
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 143
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 144
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 145
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 146
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 147
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 148
Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 149
Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 150
Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 151
Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 152
Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 153
Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 154
Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 155
Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 156
Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 157
General-Purpose Input/Outputs (GPIOs) ................................................................................... 158
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 165
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 166
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 167
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 168
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 169
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 170
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 171
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 172
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 173
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 174
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 176
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 177
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 178
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 179
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 180
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 181
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 182
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 183
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 184
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 185
Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 187
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 188
Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 189
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 190
Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 191
Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 192
Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 193
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 194
Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 195
Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 196
Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 197
Preliminary
November 30, 200714
LM3S2637 Microcontroller
Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 198
General-Purpose Timers ............................................................................................................. 199
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 211
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 212
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 214
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 216
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 219
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 221
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 222
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 223
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 225
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 226
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 227
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 228
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 229
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 230
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 231
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 232
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 233
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 234
Watchdog Timer ........................................................................................................................... 235
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 238
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 239
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 240
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 241
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 242
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 243
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 244
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 245
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 246
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 247
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 248
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 249
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 250
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 251
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 252
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 253
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 254
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 255
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 256
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 257
Analog-to-Digital Converter (ADC) ............................................................................................. 258
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 265
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 266
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 267
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 268
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 269
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 270
Preliminary
15November 30, 2007
Table of Contents
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 273
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 274
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 275
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 276
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 277
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 279
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 282
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 282
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 282
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 282
Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 283
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 283
Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 283
Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 283
Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 284
Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 284
Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 285
Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 285
Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 287
Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 288
Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 289
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 291
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 299
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 301
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 303
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 305
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 306
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 307
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 308
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 310
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 312
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 314
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 316
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 317
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 318
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 320
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 321
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 322
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 323
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 324
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 325
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 326
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 327
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 328
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 329
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 330
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 331
Preliminary
November 30, 200716
LM3S2637 Microcontroller
Synchronous Serial Interface (SSI) ............................................................................................ 332
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 344
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 346
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 348
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 349
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 351
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 352
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 354
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 355
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 356
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 357
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 358
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 359
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 360
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 361
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 362
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 363
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 364
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 365
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 366
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 367
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 368
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 369
Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 383
Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 384
Register 3: I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 388
Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 389
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 390
Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 391
Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 392
Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 393
Register 9: I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 394
Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 396
Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 397
Register 12: I2C Slave Data (I2CSDR), offset 0x008 ........................................................................... 399
Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 400
Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 401
Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 402
Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 403
Controller Area Network (CAN) Module ..................................................................................... 404
Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................. 418
Register 2: CAN Status (CANSTS), offset 0x004 ............................................................................... 420
Register 3: CAN Error Counter (CANERR), offset 0x008 ................................................................... 423
Register 4: CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 424
Register 5: CAN Interrupt (CANINT), offset 0x010 ............................................................................. 426
Register 6: CAN Test (CANTST), offset 0x014 .................................................................................. 427
Register 7: CAN Baud Rate Prescalar Extension (CANBRPE), offset 0x018 ....................................... 429
17November 30, 2007
Preliminary
Table of Contents
Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 430
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 430
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 431
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 431
Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 434
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 434
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 435
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 435
Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 436
Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 436
Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 437
Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 437
Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 438
Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 .................................................. 438
Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ................................................................. 440
Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................. 440
Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................. 440
Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................. 440
Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ................................................................. 440
Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ................................................................. 440
Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ................................................................. 440
Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ................................................................. 440
Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100 ................................................ 441
Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104 ................................................ 441
Register 32: CAN New Data 1 (CANNWDA1), offset 0x120 ................................................................. 442
Register 33: CAN New Data 2 (CANNWDA2), offset 0x124 ................................................................. 442
Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ..................................... 443
Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ..................................... 443
Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ....................................................... 444
Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ....................................................... 444
Analog Comparators ................................................................................................................... 445
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 451
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 452
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 453
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 454
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... 455
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40 ....................................................... 455
Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x60 ....................................................... 455
Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x24 ....................................................... 456
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x44 ....................................................... 456
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x64 ...................................................... 456
Preliminary
November 30, 200718
About This Document
This data sheet provides reference information for the LM3S2637 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following documents are referenced by the data sheet, and available on the documentation CD
or from the Luminary Micro web site at www.luminarymicro.com:
■
ARM® Cortex™-M3 Technical Reference Manual
LM3S2637 Microcontroller
■
ARM® CoreSight Technical Reference Manual
■
ARM® v7-M Architecture Application Level Reference Manual
The following related documents are also referenced:
■
IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the Luminary Micro web
site for additional documentation, including application notes and white papers.
Documentation Conventions
This document uses the conventions shown in Table 1 on page 19.
Table 1. Documentation Conventions
MeaningNotation
General Register Notation
REGISTER
offset 0xnnn
Register N
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
A single bit in a register.bit
Two or more consecutive and related bits.bit field
A hexadecimal increment to a register's address, relative to that module's base address as specified
in “Memory Map” on page 40.
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
Preliminary
19November 30, 2007
About This Document
reserved
yy:xx
Register Bit/Field
Types
R/W1C
W1C
Reset Value
Pin/Signal Notation
assert a signal
SIGNAL
SIGNAL
Numbers
X
0x
MeaningNotation
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
Software can read this field. The bit or field is cleared by hardware after reading the bit/field.RC
Software can read this field. Always write the chip reset value.RO
Software can read or write this field.R/W
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
Only a write by software is valid; a read of the register returns no meaningful data.WO
This value in the register bit diagram shows the bit/field value after any reset, unless noted.Register Bit/Field
Bit cleared to 0 on chip reset.0
Bit set to 1 on chip reset.1
Nondeterministic.-
Pin alternate function; a pin defaults to the signal without the brackets.[ ]
Refers to the physical connection on the package.pin
Refers to the electrical signal encoding of a pin.signal
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
Change the value of the signal from the logically True state to the logically False state.deassert a signal
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
Preliminary
November 30, 200720
1 Architectural Overview
The Luminary Micro Stellaris®family of microcontrollers—the first ARM® Cortex™-M3 based
controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller
applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to
legacy 8- and 16-bit devices, all in a package with a small footprint.
The Stellaris®family offers efficient performance and extensive integration, favorably positioning
the device into cost-conscious applications requiring significant control-processing and connectivity
capabilities. The Stellaris®LM3S1000 series extends the Stellaris®family with larger on-chip
memories, enhanced power management, and expanded I/O and control capabilities. The Stellaris
LM3S2000 series, designed for Controller Area Network (CAN) applications, extends the Stellaris
family with Bosch CAN networking technology, the golden standard in short-haul industrial networks.
The Stellaris®LM3S2000 series also marks the first integration of CAN capabilities with the
revolutionary Cortex-M3 core. The Stellaris®LM3S6000 series combines both a 10/100 Ethernet
Media Access Control (MAC) and Physical (PHY) layer, marking the first time that integrated
connectivity is available with an ARM Cortex-M3 MCU and the only integrated 10/100 Ethernet MAC
and PHY available in an ARM architecture MCU. The Stellaris®LM3S8000 series combines Bosch
Controller Area Network technology with both a 10/100 Ethernet Media Access Control (MAC) and
Physical (PHY) layer.
LM3S2637 Microcontroller
®
The LM3S2637 microcontroller is targeted for industrial applications, including remote monitoring,
electronic point-of-sale machines, test and measurement equipment, network appliances and
switches, factory automation, HVAC and building control, gaming equipment, motion control, medical
instrumentation, and fire and security.
For applications requiring extreme conservation of power, the LM3S2637 microcontroller features
a Battery-backed Hibernation module to efficiently power down the LM3S2637 to a low-power state
during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time
counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated
non-volatile memory, the Hibernation module positions the LM3S2637 microcontroller perfectly for
battery applications.
In addition, the LM3S2637 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S2637 microcontroller is code-compatible
to all members of the extensive Stellaris®family; providing flexibility to fit our customers' precise
needs.
Luminary Micro offers a complete solution to get to market quickly, with evaluation and development
boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong
support, sales, and distributor network.
1.1 Product Features
The LM3S2637 microcontroller includes the following product features:
■ 32-Bit RISC Performance
– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
applications
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21November 30, 2007
Architectural Overview
– System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
counter with a flexible control mechanism
– Thumb®-compatible Thumb-2-only instruction set processor core for high code density
– 50-MHz operation
– Hardware-division and single-cycle-multiplication
– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
– 32 interrupts with eight priority levels
– Memory protection unit (MPU), providing a privileged mode for protected operating system
functionality
– Unaligned data access, enabling data to be efficiently packed into memory
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
■ Internal Memory
– 128 KB single-cycle flash
• User-managed flash block protection on a 2-KB block basis
• User-managed flash data programming
• User-defined and managed flash-protection block
– 32 KB single-cycle SRAM
■ General-Purpose Timers
– Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers.
Each GPTM can be configured to operate independently:
• As a single 32-bit timer
• As one 32-bit Real-Time Clock (RTC) to event capture
• For Pulse Width Modulation (PWM)
• To trigger analog-to-digital conversions
– 32-bit Timer modes
• Programmable one-shot timer
• Programmable periodic timer
• Real-Time Clock when using an external 32.768-KHz clock as the input
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November 30, 200722
LM3S2637 Microcontroller
• User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU
Halt flag during debug
• ADC event trigger
– 16-bit Timer modes
• General-purpose timer function with an 8-bit prescaler
• Programmable one-shot timer
• Programmable periodic timer
• User-enabled stalling when the controller asserts CPU Halt flag during debug
• ADC event trigger
– 16-bit Input Capture modes
• Input edge count capture
• Input edge time capture
– 16-bit PWM mode
• Simple PWM mode with software-programmable output inversion of the PWM signal
■ ARM FiRM-compliant Watchdog Timer
– 32-bit down counter with a programmable load register
– Separate watchdog clock with an enable
– Programmable interrupt generation logic with interrupt masking
– Lock register protection from runaway software
– Reset generation logic with an enable/disable
– User-enabled stalling when the controller asserts the CPU Halt flag during debug
■ Controller Area Network (CAN)
– Supports CAN protocol version 2.0 part A/B
– Bit rates up to 1Mb/s
– 32 message objects, each with its own identifier mask
– Maskable interrupt
– Disable automatic retransmission mode for TTCAN
– Programmable loop-back mode for self-test operation
■ Synchronous Serial Interface (SSI)
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23November 30, 2007
Architectural Overview
– Master or slave operation
– Programmable clock bit rate and prescale
– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
– Programmable data frame size from 4 to 16 bits
– Internal loopback test mode for diagnostic/debug testing
■ UART
– Two fully programmable 16C550-type UARTs with IrDA support
– Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service
loading
– Programmable baud-rate generator with fractional divider
– Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
– FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
– Standard asynchronous communication bits for start, stop, and parity
– False-start-bit detection
– Line-break generation and detection
■ ADC
– Single- and differential-input configurations
– Four 10-bit channels (inputs) when used as single-ended inputs
– Sample rate of 500 thousand samples/second
– Flexible, configurable analog-to-digital conversion
– Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs
– Each sequence triggered by software or internal event (timers, analog comparators, or GPIO)
– On-chip temperature sensor
■ Analog Comparators
– Three independent integrated analog comparators
– Configurable for output to: drive an output pin, generate an interrupt, or initiate an ADC sample
sequence
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Preliminary
LM3S2637 Microcontroller
– Compare external pin input to external pin input or to internal programmable voltage reference
■ I2C
– Master and slave receive and transmit operation with transmission speed up to 100 Kbps in
Standard mode and 400 Kbps in Fast mode
– Interrupt generation
– Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
■ GPIOs
– 15-46 GPIOs, depending on configuration
– 5-V-tolerant input/outputs
– Programmable interrupt generation as either edge-triggered or level-sensitive
– Bit masking in both read and write operations through address lines
– Can initiate an ADC sample sequence
– Programmable control for GPIO pad configuration:
• Weak pull-up or pull-down resistors
• 2-mA, 4-mA, and 8-mA pad drive
• Slew rate control for the 8-mA drive
• Open drain enables
• Digital input enables
■ Power
– On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
– Hibernation module handles the power-up/down 3.3 V sequencing and control for the core
digital logic and analog circuits
– Low-power options on controller: Sleep and Deep-sleep modes
– Low-power options for peripherals: software controls shutdown of individual peripherals
– User-enabled LDO unregulated voltage detection and automatic reset
– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Flexible Reset Sources
– Power-on reset (POR)
– Reset pin assertion
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25November 30, 2007
Architectural Overview
– Brown-out (BOR) detector alerts to system power drops
– Software reset
– Watchdog timer reset
– Internal low drop-out (LDO) regulator output goes unregulated
■ Additional Features
– Six reset sources
– Programmable clock source control
– Clock gating to individual peripherals for power savings
– IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
– Debug access via JTAG and Serial Wire interfaces
– Full JTAG boundary scan
■ Industrial-range 100-pin RoHS-compliant LQFP package
1.2 Target Applications
■ Remote monitoring
■ Electronic point-of-sale (POS) machines
■ Test and measurement equipment
■ Network appliances and switches
■ Factory automation
■ HVAC and building control
■ Gaming equipment
■ Motion control
■ Medical instrumentation
■ Fire and security
■ Power and energy
■ Transportation
1.3 High-Level Block Diagram
Figure 1-1 on page 27 represents the full set of features in the Stellaris®2000 series of devices;
not all features may be available on the LM3S2637 microcontroller.
Preliminary
November 30, 200726
Figure 1-1. Stellaris®2000 Series High-Level Block Diagram
LM3S2637 Microcontroller
1.4 Functional Overview
The following sections provide an overview of the features of the LM3S2637 microcontroller. The
page number in parenthesis indicates where that feature is discussed in detail. Ordering and support
information can be found in “Ordering and Contact Information” on page 509.
27November 30, 2007
Preliminary
Architectural Overview
1.4.1 ARM Cortex™-M3
1.4.1.1 Processor Core (see page 34)
All members of the Stellaris®product family, including the LM3S2637 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for
a high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
“ARM Cortex-M3 Processor Core” on page 34 provides an overview of the ARM core; the core is
detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.1.2 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
1.4.1.3 Nested Vectored Interrupt Controller (NVIC)
The LM3S2637 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the
ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions
are handled in Handler Mode. The processor state is automatically stored to the stack on an
exception, and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry.
The processor supports tail-chaining, which enables back-to-back interrupts to be performed without
the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions
(system handlers) and 32 interrupts.
“Interrupts” on page 42 provides an overview of the NVIC controller and the interrupt map. Exceptions
and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.2 Motor Control Peripherals
To enhance motor control, the LM3S2637 controller features Pulse Width Modulation (PWM) outputs.
1.4.2.1 PWM
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
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Preliminary
On the LM3S2637, PWM motion control functionality can be achieved through:
■ The motion control features of the general-purpose timers using the CCP pins
CCP Pins (see page 205)
The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable
to support a simple PWM mode with a software-programmable output inversion of the PWM signal.
1.4.3 Analog Peripherals
To handle analog signals, the LM3S2637 microcontroller offers an Analog-to-Digital Converter
(ADC).
For support of analog signals, the LM3S2637 microcontroller offers three analog comparators.
1.4.3.1 ADC (see page 258)
An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number.
The LM3S2637 ADC module features 10-bit conversion resolution and supports four input channels,
plus an internal temperature sensor. Four buffered sample sequences allow rapid sampling of up
to eight analog input sources without controller intervention. Each sample sequence provides flexible
programming with fully configurable input source, trigger events, interrupt generation, and sequence
priority.
LM3S2637 Microcontroller
1.4.3.2 Analog Comparators (see page 445)
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
The LM3S2637 microcontroller provides three independent integrated analog comparators that can
be configured to drive an output or generate an interrupt or ADC event.
A comparator can compare a test voltage against any one of these voltages:
■ An individual external reference voltage
■ A shared single external reference voltage
■ A shared internal reference voltage
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts or triggers to the
ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering
logic is separate. This means, for example, that an interrupt can be generated on a rising edge and
the ADC triggered on a falling edge.
1.4.4 Serial Communications Peripherals
The LM3S2637 controller supports both asynchronous and synchronous serial communications
with:
■ Two fully programmable 16C550-type UARTs
■ One SSI module
■ One I2C module
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Preliminary
Architectural Overview
■ One CAN unit
1.4.4.1 UART (see page 291)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The LM3S2637 controller includes two fully programmable 16C550-type UARTs that support data
transfer speeds up to 460.8 Kbps. (Although similar in functionality to a 16C550 UART, it is not
register-compatible.) In addition, each UART is capable of supporting IrDA.
Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading.
The UART can generate individually masked interrupts from the RX, TX, modem status, and error
conditions. The module provides a single combined interrupt when any of the interrupts are asserted
and are unmasked.
1.4.4.2 SSI (see page 332)
Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface.
The LM3S2637 controller includes one SSI module that provides the functionality for synchronous
serial communications with peripheral devices, and can be configured to use the Freescale SPI,
MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also
configurable, and can be set between 4 and 16 bits, inclusive.
The SSI module performs serial-to-parallel conversion on data received from a peripheral device,
and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths
are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently.
The SSI module can be configured as either a master or slave device. As a slave device, the SSI
module can also be configured to disable its output, which allows a master device to be coupled
with multiple slave devices.
The SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
1.4.4.3 I2C (see page 369)
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL).
The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking
devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and
diagnostic purposes in product development and manufacture.
The LM3S2637 controller includes one I2C module that provides the ability to communicate to other
IC devices over an I2C bus. The I2C bus supports devices that can both transmit and receive (write
and read) data.
Devices on the I2C bus can be designated as either a master or a slave. The I2C module supports
both sending and receiving data as either a master or a slave, and also supports the simultaneous
operation as both a master and a slave. The four I2C modes are: Master Transmit, Master Receive,
Slave Transmit, and Slave Receive.
A Stellaris®I2C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps).
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