Texas Instruments JM38510-34102BEA, JM38510-34102B2A, JM38510-34102BFA, SN74F109D, SN74F109DR Datasheet

DUAL J-K

SN54F109, SN74F109

POSITIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SDFS047A – MARCH 1987 – REVISED OCT OBER 1993

• Package Options Include Plastic

Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs

description

These devices contain two independent J-K
positive-edge-triggered flip-flops. A low level at
the preset (PRE
resets the outputs regardless of the levels of the
other inputs. When PRE
(high), data at the J and K
setup-time requirements are transferred to the
outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse. Following the hold time interval, data
at the J and K
affecting the levels at the outputs. These versatile
flip-flops can perform as toggle flip-flops by
grounding K
perform as D-type flip-flops if J and K
together.

The SN54F109 is characterized for operation over
the full military temperature range of –55°C to
125°C. The SN74F109 is characterized for
operation from 0°C to 70°C.

) or clear (CLR) inputs sets or

and CLR are inactive

input meeting the

inputs may be changed without

and trying J high. They also can

are tied

SN54F109 ...J PACKAGE

SN74F109 ...D OR N PACKAGE

1CLR

1CLK
1PRE

1K

1CLK

NC

1PRE

1Q

NC – No internal connection

(TOP VIEW)

NC

NC

16
15
14
13
12
11
10

9

CC

V

2Q

VCC
2CLR
2J
2K
2CLK
2PRE
2Q
2Q

2CLR

18
17
16
15
14

2Q

1

1J

2

1K

3
4
5

1Q

6
7

1Q

GND

SN54F109 . . . FK PACKAGE

8

(TOP VIEW)

1J

1CLR

3212019

4
5
6
7
8

910111213

1Q

GND

2J
2K
NC
2CLK
2PRE

FUNCTION TABLE

INPUTS

PRE CLR CLK J K Q Q

L H X X X H L

H LXXXLH

LLXXXH
HH↑LLLH
HH↑H L Toggle
H H ↑ LHQ
HH↑HHHL
HHLXXQ

†

The output levels are not guaranteed to meet the minimum
levels for VOH. Furthermore, this configuration is nonstable;
that is, it will not persist when PRE
inactive (high) level.

OUTPUTS

†

H

Q

0

Q

0

or CLR returns to its

†

0

0

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1993, Texas Instruments Incorporated

2–1

SN54F109, SN74F109

UNIT

DUAL J-K

POSITIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SDFS047A – MARCH 1987 – REVISED OCT OBER 1993

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, J, and N packages.

†

1PRE

1J

1CLK

1K

1CLR

2PRE

2J

2CLK

2K

2CLR

5
2
4
3
1

11
14

12
13
15

S
1J

1K
R

C1

10

6

1Q

7

1Q

2Q

9

2Q

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V

Input current range –30 mA to 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high state –0.5 V to V

Current into any output in the low state 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range: SN54F109 –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –1.2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74F109 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

‡

CC

recommended operating conditions

V
V
V
I

IK

I

OH

I

OL

T

2–2

CC
IH
IL

A

Supply voltage 4.5 5 5.5 4.5 5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input clamp current –18 –18 mA
High-level output current –1 –1 mA
Low-level output current 20 20 mA
Operating free-air temperature –55 125 0 70 °C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54F109 SN74F109

MIN NOM MAX MIN NOM MAX

SN54F109, SN74F109

PARAMETER

TEST CONDITIONS

UNIT

V

V

I

V

V

V

mA

twPulse duration

ns

Set

CLK↑

su

thHold time, data after CLK↑

ns

(

)

(

)

(INPUT)

(OUTPUT)

CLK

Q

Q

ns

PRE or CLR

Q or Q

ns

DUAL J-K

POSITIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SDFS047A – MARCH 1987 – REVISED OCTOBER 1993

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

SN54F109 SN74F109

MIN TYP†MAX MIN TYP†MAX

V

IK

OH

V

OL

I

I

I

IH

IL

I

OS

I

CC

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.

NOTE 2: ICC is measured with J, K

J, K, CLK
PRE or CLR

‡

VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
VCC = 4.5 V, IOH = – 1 mA 2.5 3.4 2.5 3.4
VCC = 4.75 V, IOH = – 1 mA 2.7
VCC = 4.5 V, IOL = 20 mA 0.3 0.5 0.3 0.5 V
VCC = 5.5 V, VI = 7 V 0.1 0.1 mA
VCC = 5.5 V, VI = 2.7 V 20 20 µA

= 5.5 V,

CC

VCC = 5.5 V, VO = 0 –60 –150 –60 –150 mA
VCC = 5.5 V, See Note 2 11.7 17 11.7 17 mA

, CLK, and PRE grounded then with J, K, CLK, and CLR grounded.

= 0.5

I

– 0.6 – 0.6
– 1.8 – 1.8

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)

VCC = 5 V,

f

Clock frequency 0 100 0 70 0 90 MHz

clock

CLK high, PRE or CLR low 4 4 4
CLK low 5 5 5

t

su

§

Inactive-state setup time is also referred to as recovery time.

up time, data before

Setup time, inactive-state before CLK↑

High 3 3 3
Low 3 3 3

§

PRE or CLR to CLK 2 2 2
High 1 1 1
Low 1 1 1

TA = 25°C

′F74

MIN MAX MIN MAX MIN MAX

SN54F109 SN74F109

UNIT

ns

switching characteristics (see Note 3)

VCC = 5 V,
CL = 50 pF,

PARAMETER

f

max

t

PLH

t

PHL

t

PLH

t
¶
NOTE 3: Load circuits and waveforms are shown in Section 1.

PHL

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

FROM
INPUT

TO

OUTPUT

or

RL = 500 Ω,
TA = 25°C

′F109 SN54F109 SN74F109

MIN TYP MAX MIN MAX MIN MAX

100 150 70 90 MHz

3 4.9 7 3 9 3 8

3.6 5.8 8 3.6 10.5 3.6 9.2

2.4 4.8 7 2.4 9 2.4 8

2.7 6.6 9 2.7 11.5 2.7 10.5

VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500Ω,
TA = MIN to MAX

¶

UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2–3

SN54F109, SN74F109
DUAL J-K

POSITIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SDFS047A – MARCH 1987 – REVISED OCT OBER 1993

2–4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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