Texas Instruments INA209AIPW, INA209 Datasheet

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INA209

Critical DAC+

Critical DAC -

CMP

Filter

OverlimitRegister

WarningRegister

PowerRegister

CurrentRegister

I C

Interface

VoltageRegister

ConvertGND GPIO

IN+VIN-

(SupplyVoltage)

Critical

Overlimit

Warning

Alert

Data

CLK

CMP

ADC

High-Side Measurement, Bi-Directional Current/Power Monitor

with I2C™ Interface

FEATURES DESCRIPTION

• SENSES BUS VOLTAGES FROM 0V TO +26V

• REPORTS CURRENT, VOLTAGE, AND

POWER; STORES PEAKS

• TRIPLE WATCHDOG LIMITS:

– Lower Warning with Delay – Upper Over-limit, No Delay – Fast Analog Critical

• HIGH ACCURACY: 1% MAX OVER TEMP

APPLICATIONS

• SERVERS

• TELECOM EQUIPMENT

• AUTOMOTIVE The INA209 also includes an analog-to-digital

• POWER MANAGEMENT

• BATTERY CHARGERS

• WELDING EQUIPMENT

• POWER SUPPLIES

• TEST EQUIPMENT

The INA209 is a high-side current shunt and power monitor with an I2C interface. The INA209 monitors both shunt drop and shunt bus voltage. A programmable calibration value, combined with an internal multiplier, enables direct readouts in amperes. An additional multiplying register calculates power in watts. The INA209 features two separate, onboard watchdog capabilities: a warning comparator and an over-limit comparator. The warning comparator is useful for monitoring lower warning limits and incorporates a user-defined delay. The over-limit comparator assists with monitoring upper limits that could require immediate system shutdown.

converter (ADC) comparator and a programmable digital-to-analog converter (DAC) that combine to provide the fastest possible responses to current overload conditions.

The INA209 can be used together with hot swap controllers that already use a current sense resistor. The INA209 full-scale range can be selected to be either within the hot-swap controller sense limits, or wide enough to include them.

INA209

SBOS403 – JUNE 2007

I2C is a trademark of NXP Semiconductors. All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

The INA209 senses across shunts on buses that can vary from 0V to 26V. The device uses a single +3V to +5.5V supply, drawing a maximum of 1.5mA of supply current. It is specified for operation from –25 ° C to +85 ° C.

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INA209

SBOS403 – JUNE 2007

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

(1)

PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING

INA209 TSSOP-16 PW INA209A

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com .

ABSOLUTE MAXIMUM RATINGS

(1)

Over operating free-air temperature range (unless otherwise noted).

INA209 UNIT

Supply Voltage, V Analog Inputs,

, V

IN+

IN–

Differential (V

) – (V

IN+

(2)

)

IN–

Common-Mode –0.3 to +26 V Open-Drain Digital Outputs GND – 0.3 to +6 V GPIO, Convert Pins GND – 0.3 to VS+ 0.3 V Input Current Into Any Pin 5 mA Open-Drain Digital Output Current 10 mA Operating Temperature –40 to +125 ° C Storage Temperature –40 to +150 ° C Junction Temperature +150 ° C

Human Body Model 2000 V ESD Ratings Charged-Device Model 1000 V

Machine Model (MM) 150 V

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.

(2) V

and V

IN+

+26V.

may have a differential voltage of –26V to +26V; however, the voltage at these pins must not exceed the range –0.3V to

IN–

6 V

–26 to +26 V

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SBOS403 – JUNE 2007

INA209

ELECTRICAL CHARACTERISTICS: V

Boldface limits apply over the specified temperature range, TA= –25 ° C to +85 ° C.

At TA= +25 ° C, V

INPUT

Full-Scale Current Sense (Input) Voltage Range PGA = ÷ 1 0 ± 40 mV

Bus Voltage (Input Voltage) Range

Common-Mode Rejection CMRR V Offset Voltage, RTI

vs Temperature 0.1 µ V/ ° C

vs Power Supply PSRR VS= 3V to 5.5V 10 µ V/V

Current Sense Gain Error ± 40 m%

vs Temperature 10 ppm/ ° C

Input Impedance Active Mode

Pin 20 µ A

IN+

Pin 20 || 320 µ A || k Ω

IN–

Input Leakage Power-Down Mode

Pin 0.1 ± 0.5 µ A

IN+

Pin 0.1 ± 0.5 µ A

IN–

DC ACCURACY

ADC Basic Resolution 12 Bits 1 LSB Step Size

Shunt Voltage 10 µ V Bus Voltage 4 mV

Current Measurement Error ± 0.2 ± 0.5 %

over Temperature ± 1 %

Bus Voltage Measurement Error ± 0.2 ± 0.5 %

over Temperature ± 1 %

Differential Nonlinearity ± 0.1 LSB Critical DAC Full-Scale Range 255 mV Critical DAC Accuracy ± 0.5 ± 1 % Critical DAC Resolution 8 Bits Critical DAC 1 LSB Step Size 1 mV Critical DAC Comparator Offset ± 0.3 ± 1.6 mV Critical DAC Comparator Hysteresis Critical DAC Comparator Delay 5 µ s

= 12V, V

IN+

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(3)

= (V

SENSE

(2)

(4)

– V

IN+

= +3.3V

) = 32mV, PGA = ÷ 1, and BRNG

IN–

IN+

(1)

= 1, unless otherwise noted.

INA209

PGA = ÷ 2 0 ± 80 mV PGA = ÷ 4 0 ± 160 mV PGA = ÷ 8 0 ± 320 mV BRNG = 1 0 32 V BRNG = 0 0 16 V

= 0V to 26V 100 120 dB PGA = ÷ 1 ± 10 ± 100 µ V PGA = ÷ 2 ± 20 ± 125 µ V PGA = ÷ 4 ± 30 ± 150 µ V PGA = ÷ 8 ± 40 ± 200 µ V

(4)

See

(1) BRNG is bit 13 of the Configuration Register. (2) This parameter only expresses the full-scale range of the ADC scaling. In no event should more than 26V be applied to this device. (3) Referred-to-input (RTI). (4) User-programmable. See the Critical Comparator and Register sections.

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INA209

SBOS403 – JUNE 2007

ELECTRICAL CHARACTERISTICS: V

= +3.3V (continued)

Boldface limits apply over the specified temperature range, TA= –25 ° C to +85 ° C.

At TA= +25 ° C, V

ADC TIMING

ADC Conversion Time 12-Bit 532 586 µ s

Minimum Convert Input Low Time 4 µ s

SMBus

SMBus Timeout

DIGITAL INPUTS (Convert, GPIO and SDA as Input, SCL, A0, A1)

Input Capacitance Leakage 3 pF Input Current 0 ≤ VIN≤ V Input Logic Levels:

Hysteresis 500 mV

DIGITAL OUTPUTS

GPIO Pin Output Low I GPIO Pin Output High I

OPEN-DRAIN DIGITAL OUTPUTS (Critical, Over-Limit, Warning, Alert, SDA)

Logic '0' Output Level I High-Level Output Leakage Current V

POWER SUPPLY

Operating Supply Range +3 +5.5 V Quiescent Current 1 1.5 mA Quiescent Current, Power-Down Mode 6 15 µ A Power-On Reset Threshold 2 V

TEMPERATURE RANGE

Specified Temperature Range –25 +85 ° C Operating Temperature Range –40 +125 ° C Thermal Resistance θ

TSSOP-16 +150 ° C/W

= 12V, V

IN+

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(5)

= (V

– V

SENSE

IN+

) = 32mV, PGA = ÷ 1, and BRNG = 1, unless otherwise noted.

IN–

11-Bit 276 304 µ s 10-Bit 148 163 µ s

9-Bit 84 93 µ s

0.7 (VS) 6 V –0.3 0.3 (VS) V

= 3mA 0.15 0.4 V

SINK

= 3mA VS– 0.4 VS– 0.15 V

SOURCE

= 3mA 0.15 0.4 V

SINK

= V

OUT

INA209

28 35 ms

0.1 1 µ A

(5) SMBus timeout in the INA209 resets the interface any time SCL is low for over 28ms.

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SMBusAlert

SDA

SCL

GND

S+

Warning

IN+

IN-

Convert

GND

S+

GPIO

Critical

Overlimit

SBOS403 – JUNE 2007

PIN CONFIGURATIONS

INA209

Top View

PIN DESCRIPTIONS

PIN NO. NAME DESCRIPTION

1 V 2 V

IN+ IN–

3 Convert Used to trigger conversions in triggered mode. In triggered mode, this pin should normally be high and

4 GND Connect together with pin 11 to ground. 5 V

S+

6 GPIO General-purpose, user-programmable input/output. Totem-pole output. Connect to ground or supply if

7 Critical Open-drain critical watchdog output (filter set in Critical DAC– Register). Default condition is disabled;

8 Overlimit Open-drain over-limit watchdog output. Default condition is disabled; active-low; transparent

9 Warning Open-drain warning watchdog output (delay set in Critical DAC– Register). Default condition is

10 V

S+

11 GND Connect together with pin 4 to ground. 12 SCL Serial bus clock line. 13 SDA Serial bus data line. 14 A0 Address pin. Table 1 shows pin settings and corresponding addresses. 15 A1 Address pin. Table 1 shows pin settings and corresponding addresses. 16 SMBus Alert Open-drain SMBus alert output. Controlled in SMBus Alert Mask Register. Default is disabled.

Positive differential shunt voltage. Connect to positive side of shunt resistor. Negative differential shunt voltage. Connect to negative side of shunt resistor. Bus voltage is

measured from this pin to ground.

taken low to initiate conversion. It may be returned high after 4 µ s. If held low, the ADC converts each time a triggered mode command is written via the I2C bus. If not used, this line should be tied high.

Connect together with pin 10 to supply, 3V to 5.5V.

not used. Default condition is as an input.

active-low; transparent (non-latched).

(non-latched).

disabled; active-low; transparent (non-latched). Connect together with pin 5 to supply, 3V to 5.5V.

INA209

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-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

100

10k 100k

Gain(dB)

InputFrequency(Hz)

100

-20

-40

-60

-80

-100

-40

-25

25 50

75 100

Offset( V)m

Temperature( C)°

125

160mVRange

320mVRange

80mVRange

40mVRange

100

-20

-40

-60

-80

-100

-40

-25

25 50

75 100

GainError(m%)

Temperature( C)°

125

320mVRange

160mVRange

80mVRange

40mVRange

-40

-25

25 50

75 100

Offset(mV)

Temperature( C)°

125

32VRange

16VRange

-5

-10

-15

-20

-0.4

-0.3

-0.2

-0.1 0

0.1 0.2 0.3

INL(

V)m

InputVoltage(V)

0.4

100

-20

-40

-60

-80

-100

-40

-25

25 50

75 100

GainError(m%)

Temperature( C)°

125

32VRange

16VRange

INA209

SBOS403 – JUNE 2007

At TA= +25 ° C, V

TYPICAL CHARACTERISTICS

= 12V, V

IN+

FREQUENCY RESPONSE ADC SHUNT OFFSET vs TEMPERATURE

Figure 1. Figure 2.

= (V

– V

SENSE

IN+

) = 32mV, PGA = ÷ 1, and BRNG = 1, unless otherwise noted.

IN–

ADC SHUNT GAIN ERROR vs TEMPERATURE ADC BUS VOLTAGE OFFSET vs TEMPERATURE

Figure 3. Figure 4.

ADC BUS GAIN ERROR vs TEMPERATURE INTEGRAL NONLINEARITY vs INPUT VOLTAGE

Figure 5. Figure 6.

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1.0

0.8

0.6

0.4

0.2

-0.2

-0.4

-0.6

-0.8

-1.0

-40

-25

25 50

75 100

Offset(mV)

Temperature( C)°

125

CriticalComparator -

CriticalComparator+

1.0

0.8

0.6

0.4

0.2

-0.2

-0.4

-0.6

-0.8

-1.0

-40

-25

25 50

75 100

Full-ScaleError(mV)

Temperature( C)°

125

CriticalComparator -

CriticalComparator+

2.0

1.5

1.0

0.5

-0.5

-1.0

-1.5

15 20

InputCurrents(mA)

V Voltage(V)

IN-

VS+=5V

V 5VS+=

VS+=3V

V 3VS+=

1.2

1.0

0.8

0.6

0.4

0.2

-40

-25

25 50

75 100

(mA)

Temperature( C)°

125

V =5V

V =3V

-40

-25

125

I ( A)m

Temperature( C)°

V =5V

V =3V

50 75 100

1.4

1.2

1.0

0.8

0.6

0.4

0.2

10k

100k

10M

SCLFrequency(Hz)

V =5V

V =S3V

At TA= +25 ° C, V

IN+

= 12V, V

TYPICAL CHARACTERISTICS (continued)

= (V

SENSE

– V

IN+

) = 32mV, PGA = ÷ 1, and BRNG = 1, unless otherwise noted.

IN–

INA209

SBOS403 – JUNE 2007

CRITICAL COMPARATOR OFFSET vs TEMPERATURE TEMPERATURE

Figure 7. Figure 8.

INPUT CURRENTS WITH LARGE DIFFERENTIAL

VOLTAGES

at 12V, Sweep of V

IN+

) ACTIVE IQvs TEMPERATURE

IN–

CRITICAL COMPARATOR FULL-SCALE ERROR vs

Figure 9. Figure 10.

SHUTDOWN IQvs TEMPERATURE ACTIVE IQvs I2C FREQUENCY

Figure 11. Figure 12.

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400

350

300

250

200

150

100

10k

100k

10M

I ( A)

SCLFrequency(Hz)

V =5V

V =3V

INA209

SBOS403 – JUNE 2007

At TA= +25 ° C, V

IN+

= 12V, V

TYPICAL CHARACTERISTICS (continued)

= (V

SENSE

– V

IN+

) = 32mV, PGA = ÷ 1, and BRNG = 1, unless otherwise noted.

IN–

SHUTDOWN IQvs I2C FREQUENCY

Figure 13.

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FUNCTIONAL BLOCK DIAGRAM

ADC

DAC

ShuntVoltage

Channel

BusV

oltage

Channel

PGA

(InConfigurationRegister)

ShuntVoltage

(1)

DataRegisters

Full-ScaleCalibration

(2)

Current

(1)

BusVoltage

(1)

Power

(1)

ShuntV

oltage Peak-

(2)

ShuntV

oltage+Peak

(2)

Peak-HoldRegisters

BusV

oltage

MinimumPeak

(2)

BusVoltage

MaximumPeak

(2)

PowerPeak

(2)

CMP

ShuntV

oltage Warning-

(2)

ShuntV

oltage+Warning

(2)

BusVoltageUnder-

VoltageWarning

(2)

ProgrammableDelay

(setin

CriticalDAC Register)-

Latchand

Polarity

BusV

oltageOver

VoltageWarning

(2)

PowerW

arning

(2)

BusUnder-Voltage Over-limit

(2)

BusOver-Voltage Over-limit

(2)

Power Over-limit

(2)

Enable/Disable

inSMBus/Enable

arning

(Open-Drain)

Latchand

Polarity

Enable/Disable

inSMBus/Enable

Over-limit

(Open-Drain)

WarningOutputDefault:

· Disabled

· ActiveLow

· Transparent(notlatched)

ProgrammableDelay

(setin

CriticalDAC Register)-

Latchand

Polarity

Enable/Disable

inSMBus/Enable

Critical

(Open-Drain)

CriticalOutputDefault:

· Disabled

· ActiveLow

· Transparent(notlatched)

WarningRegistersandOutput

OverlimitOutputDefault:

Disabled

· ActiveLow

· Transparent(notlatched)

OverlimitRegistersandOutput

CriticalDAC+

(2)

DAC

CriticalDAC-

(2)

CriticalDACHysteresis

NOTE:DashedlineindicatestheflagisintheStatusRegister

(1)Read-only.

(2)Read/Write.

INA209

SBOS403 – JUNE 2007

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Figure 14.

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PowerRegister

CurrentRegister

VoltageRegister

OverlimitRegister WarningRegister

I C

Interface

GND

Supply

Voltage

IN-

IN+

Warning

Overlimit

CMP

Filter

Critical

Convert

Data

CLK

Alert

GPIO

Critical

DAC+

Critical

DAC-

Supply

Load

Current

Shunt

3.3VSupply

CriticalOutput

OverlimitOutput

WarningOutput

Data(SDA)

Clock(SCL)

0.1 F

BYPASS

CMP

INA209

SBOS403 – JUNE 2007

APPLICATION INFORMATION

The INA209 is a digital current-shunt monitor with an To address a specific device, the master initiates a I2C and SMBus-compatible interface. It provides START condition by pulling the data signal line digital current, voltage, and power readings (SDA) from a HIGH to a LOW logic level while SCL necessary for accurate decision-making in is HIGH. All slaves on the bus shift in the slave precisely-controlled systems. Programmable address byte on the rising edge of SCL, with the last registers allow flexible configuration for setting bit indicating whether a read or write operation is warning limits, measurement resolution, and intended. During the ninth clock pulse, the slave continuous-versus-triggered operation. Detailed being addressed responds to the master by register information appears at the end of this data generating an Acknowledge and pulling SDA LOW. sheet, beginning with Table 2 . See the Functional

Block Diagram for a block diagram of the INA209.

The INA209 offers compatability with I2C and SMBus data transfer, SDA must remain stable while SCL is interfaces. The I2C and SMBus protocols are HIGH. Any change in SDA while SCL is HIGH is essentially compatible with each other. I2C will be interpreted as a START or STOP condition. used throughout this document, with SMBus being specified only when a difference between the two systems is being addressed. Two bi-directional lines, SCL and SDA, connect the INA209 to the bus. Both SCL and SDA are open-drain connections. Figure 15 shows a typical application circuit.

Data transfer is then initiated and eight bits of data are sent, followed by an Acknowledge bit. During

Once all data have been transferred, the master generates a STOP condition, indicated by pulling SDA from LOW to HIGH while SCL is HIGH. The INA209 includes a 28ms timeout on its interface to prevent locking up an SMBus.

BUS OVERVIEW

The device that initiates the transfer is called a

master, and the devices controlled by the master are slaves. The bus must be controlled by a master

device that generates the serial clock (SCL), controls the bus access, and generates START and STOP conditions.

Figure 15. Typical Application Circuit

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INA209

SBOS403 – JUNE 2007

Serial Bus Address WRITING TO/READING FROM THE INA209

To communicate with the INA209, the master must Accessing a particular register on the INA209 is first address slave devices via a slave address byte. accomplished by writing the appropriate value to the The slave address byte consists of seven address register pointer. Refer to Table 2 for a complete list bits, and a direction bit indicating the intent of of registers and corresponding addresses. The value executing a read or write operation. for the register pointer as shown in Figure 19 is the

The INA209 has two address pins, A0 and A1.

Table 1 describes the pin logic levels for each of the

16 possible addresses. The state of pins A0 and A1 is sampled on every bus communication and should Writing to a register begins with the first byte be set before any activity on the interface occurs. transmitted by the master. This byte is the slave The address pins are read at the start of each address, with the R/ W bit LOW. The INA209 then communication event. acknowledges receipt of a valid address. The next

Table 1. INA209 Address Pins and register to which data will be written. This register

Slave Addresses

A1 A0 ADDRESS

GND GND 1000000 GND V GND SDA 1000010 GND SCL 1000011

S+

SDA GND 1001000 SDA V SDA SDA 1001010 SDA SCL 1001011 SCL GND 1001100 SCL V SCL SDA 1001110 SCL SCL 1001111

S+

GND 1000100

S+

SDA 1000110

SCL 1000111

S+

1000001

1000101

1001001

1001101

Serial Interface

The INA209 operates only as a slave device on the I2C bus and SMBus. Connections to the bus are made via the open-drain I/O lines SDA and SCL. The SDA and SCL pins feature integrated spike suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The INA209 supports the transmission protocol for fast (1kHz to 400kHz) and high-speed (1kHz to 3.4MHz) modes. All data bytes are transmitted most significant byte first.

first byte transferred after the slave address byte with the R/ W bit LOW. Every write operation to the INA209 requires a value for the register pointer.

byte transmitted by the master is the address of the address value updates the register pointer to the

desired register. The next two bytes are written to the register addressed by the register pointer. The INA209 acknowledges receipt of each data byte. The master may terminate data transfer by generating a START or STOP condition.

When reading from the INA209, the last value stored in the register pointer by a write operation determines which register is read during a read operation. To change the register pointer for a read operation, a new value must be written to the register pointer. This write is accomplished by issuing a slave address byte with the R/ W bit LOW, followed by the register pointer byte. No additional data are required. The master then generates a START condition and sends the slave address byte with the R/ W bit HIGH to initiate the read command. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the register pointer. This byte is followed by an Acknowledge from the master; then the slave transmits the least significant byte. The master acknowledges receipt of the data byte. The master may terminate data transfer by generating a Not-Acknowledge after receiving any data byte, or generating a START or STOP condition. If repeated reads from the same register are desired, it is not necessary to continually send the register pointer bytes; the INA209 retains the register pointer value until it is changed by the next write operation.

Figure 16 and Figure 17 show read and write

operation timing diagrams. Note that register bytes are sent most-significant byte first, followed by the least significant byte. Figure 18 shows the timing diagram for the SMBus Alert operation. Figure 19 illustrates a typical register pointer configuration.

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Frame1Two-WireSlaveAddressByte

(1)

Frame2DataMSByte

(2)

StartBy

Master

ACKBy

INA209

ACKBy

Master

From

INA209

1 9 1

SDA

SCL

0 0 A3 R/W

D15 D14 D13 D12 D11 D10 D9 D8

A2 A1 A0

Frame3DataLSByte

(2)

StopNoACKBy

(3)

Master

From

INA209

D7 D6 D5 D4 D3 D2 D1 D0

NOTES:(1)ThevalueoftheSlaveAddressByteisdeterminedbythesettingsoftheA0andA1pins.

RefertoT

able1.

(2)Readdataisfromthelastregisterpointerlocation.Ifanewregisterisdesired,theregister

pointermustbeupdated.SeeFigure19.

(3)ACKbyMastercanalsobesent.

Frame1Two-WireSlaveAddressByte

(1)

Frame2RegisterPointerByte

StartBy

Master

ACKBy

INA209

ACKBy

INA209

1 9 1

ACKBy

INA209

D15 D14 D13 D12 D11 D10 D9 D8

SDA

SCL

1 0 0 A3 A2

A1 A0 R/W P7 P6 P5 P4 P3 P2 P1 P0

NOTE(1):ThevalueoftheSlaveAddressByteisdeterminedbythesettingsoftheA0andA1pins.RefertoTable1.

Frame4DataLSByteFrame3DataMSByte

ACKBy

INA209

StopBy

Master

D7 D6 D5 D4 D3 D2 D1 D0

INA209

SBOS403 – JUNE 2007

Figure 16. Timing Diagram for Write Word Format

Figure 17. Timing Diagram for Read Word Format

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Frame1SMBusALERTResponseAddressByte Frame2SlaveAddressByte

(1)

StartBy

Master

ACKBy

INA209

From

INA209

NACKBy

Master

StopBy

Master

1 9 1

SDA

SCL

ALERT

0 0 0 1 1 0 0 R/W

1 0 0 A3 A2 A1 A0 0

NOTE(1):ThevalueoftheSlaveAddressByteisdeterminedbythesettingsoftheA0andA1pins.RefertoTable1.

Frame1Two-WireSlaveAddressByte

(1)

Frame2RegisterPointerByte

StartBy

Master

ACKBy

INA209

ACKBy

INA209

1 9 1 9

SDA

SCL

0 0 A3 A2 A1 A0 R/W P7 P6 P5 P4 P3 P2 P1 P0 Stop

NOTE(1):ThevalueoftheSlaveAddressByteisdeterminedbythesettingsoftheA0andA1pins.RefertoTable1.

Figure 18. Timing Diagram for SMBus ALERT

INA209

SBOS403 – JUNE 2007

Figure 19. Typical Register Pointer Set

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