Texas Instruments GTLP User Manual

GTLP Evaluation Module
(EVM)

User’s Guide

June 2001 Standard Linear & Logic

Printed in U.S.A.
0601

SCEA023

GTLP Evaluation Module (EVM)

User’s Guide

SCEA023

June 2001

Printed on Recycled Paper

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products
or to discontinue any product or service without notice, and advise customers to obtain the latest
version of relevant information to verify , before placing orders, that information being relied on
is current and complete. All products are sold subject to the terms and conditions of sale supplied
at the time of order acknowledgment, including those pertaining to warranty , patent infringement,
and limitation of liability .

TI warrants performance of its products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty . T esting and other quality control techniques are utilized
to the extent TI deems necessary to support this warranty . Specific testing of all parameters of
each device is not necessarily performed, except those mandated by government requirements.

Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and

operating safeguards must be provided by the customer to minimize inherent or procedural
hazards.

TI assumes no liability for applications assistance or customer product design. TI does not
warrant or represent that any license, either express or implied, is granted under any patent right,
copyright, mask work right, or other intellectual property right of TI covering or relating to any
combination, machine, or process in which such products or services might be or are used. TI’s
publication of information regarding any third party’ s products or services does not constitute TI’s
approval, license, warranty or endorsement thereof.

Reproduction of information in TI data books or data sheets is permissible only if reproduction
is without alteration and is accompanied by all associated warranties, conditions, limitations and
notices. Representation or reproduction of this information with alteration voids all warranties
provided for an associated TI product or service, is an unfair and deceptive business practice,
and TI is not responsible nor liable for any such use.

Resale of TI’s products or services with statements different from or beyond the parameters
stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service, is an unfair and deceptive business practice, and TI is not
responsible nor liable for any such use.

Also see: Standard Terms and Conditions of Sale for Semiconductor Products.
www.ti.com/sc/docs/stdterms.htm

Mailing Address:

Texas Instruments
Post Office Box 655303
Dallas, Texas 75265

Copyright  2001, Texas Instruments Incorporated

About This Manual

Use this manual to set up and use the GTLP evaluation module (EVM) for the
SN74GTLPH1655 and other GTLP devices.

How to Use This Manual

This document contains the following chapters:

-

-

-

-

Preface

Read This First

Chapter 1 – Introduction
Chapter 2 – GTLP EVM Board Typical Test and Setup Configuration
Chapter 3 – Oscilloscope Operation
Chapter 4 – Waveform Measurement and Interpretation

-

Chapter 5 – Troubleshooting

-

Appendix A – Bill of Materials, Schematics, Board Layouts, and
Suggested Specifications

iii

Information About Cautions and Warnings

Information About Cautions and Warnings

This book may contain cautions and warnings.

This is an example of a caution statement.
A caution statement describes a situation that could potentially

damage your software or equipment.

This is an example of a warning statement.
A warning statement describes a situation that could potentially

cause harm to you

The information in a caution or a warning is provided for your protection.
Please read each caution and warning carefully.

.

FCC Warning

Trademarks

iv

This equipment is intended for use in a laboratory test environment only. It
generates, uses, and can radiate radio frequency energy and has not been
tested for compliance with the limits of computing devices pursuant to subpart
J of part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other
environments may cause interference with radio communications, in which
case, users, at their own expense, will be required to take whatever measures
may be required to correct this interference.

TI-OPC is a trademark of Texas Instruments.
Trademarks are the property of their respective owners.

Contents

Contents

1 Introduction 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 GTLP EVM Overview 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 GTLP EVM Kit Contents 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 GTLP EVM Kit Availability 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 GTLP EVM Board Typical Test and Setup Configuration 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 GTLP EVM Case 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Top Tray 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Backplane Board 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Connectors 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Power Supply 2-1 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Clock Crystals 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 Termination Cards 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8 Bottom Compartment 2-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9 Measurement Equipment 2-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.10 Clock Cards 2-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11 Driver Cards 2-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.1 Single-Bit Selection 2-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.2 Edge-Rate Control 2-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.3 Source-Synchronous Clock/System-Clock Selection 2-25. . . . . . . . . . . . . . . . . . . .

2.12 Receiver Cards 2-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.13 Backplane Setup 2-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.13.1 Insertion of Clock Cards 2-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.13.2 Insertion of Clock Crystals 2-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.13.3 Insertion of Termination Cards 2-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.13.4 Insertion of Driver and Receiver Cards 2-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Oscilloscope Operation 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Oscilloscope Setup 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Measurements 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vContents

Contents

4 Waveform Measurement and Interpretation 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and

Driver Card (D1) Latch Clock (Ch2) 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and

Driver Card (D1) Group 1 GTLP Data Out (Ch2) 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and

Receiver Card (R2) Group 1 GTLP Data In (Ch2) 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4 Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and

Receiver Card (R2) Group 1 LVTTL Data Out (Ch2) 4-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5 Timing Relationship of Receiver Card (R2) Group 1 GTLP Data In (Ch1) and

Receiver Card (R20) Group 1 GTLP Data In (Ch2) 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6 Monitored Waveforms 4-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Troubleshooting 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 Spare Parts 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 Replacing 5-A Fuse F2 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 Replacing 2.5-A Fuse F1 5-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4 Damage to the Daughter Cards 5-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A Bill of Materials, Schematics, Board Layouts, and Suggested Specifications A-1. . . . . . . . .

A.1 GTLP EVM Bill of Materials A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.2 Board Layouts and Schematics A-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi

Figures

Figures

2–1 GTLP EVM Case 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 GTLP EVM Top Tray 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 GTLP EVM Backplane Board 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–4 GTLP EVM Backplane Block Diagram 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–5 AMP Z-PACK 2-mm, 110-Pin, Hard-Metric (HM) Male Connector 2-8. . . . . . . . . . . . . . . . . .

2–6 AMP Pin Lengths 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–7 AMP Single-Line-Model Data Sheet 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–8 Power Supply (Left) and Backplane Connection (Right) 2-11. . . . . . . . . . . . . . . . . . . . . . . . . . .

2–9 1.5-V V

2–10 Power-Supply LED Indicators 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–11 Clock Crystal on Card (Left) and Stored in Tube (Right) 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . .

2–12 Clock Crystal With Leads in Position for Storage 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–13 Termination Card Location (Left) and Close-Up View (Right) 2-15. . . . . . . . . . . . . . . . . . . . . . .

2–14 Termination-Card Storage 2-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–15 Oscilloscope and Backplane Daughter-Card Storage Area 2-17. . . . . . . . . . . . . . . . . . . . . . . .

2–16 Tektronix THS730A O-Scope 2-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–17 GTLP EVM Clock Card 2-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–18 GTLP EVM Driver Daughter Card 2-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–19 Bit Selection for Normal Data Pattern (Left), Signal Held Low (Center), or

Signal Held High (Right) 2-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–20 ERC Bit-Selection Jumper Set for Slow (Left) or Fast (Right) Rate 2-24. . . . . . . . . . . . . . . . . .

2–21 JB2 Set to Source-Synchronous Clock (Left) or System-Clock (Right) Operation 2-25. . . . .

2–22 GTLP EVM Monitored Receiver Card 2-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–23 AMP Z-PACK, 2-mm, 55-Pin, HM Male (Left) and

Female (Right) Clock-Card Connectors 2-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–24 Connector Premate (Left), Mating (Center), and Mated (Right) 2-30. . . . . . . . . . . . . . . . . . . . .

2–25 Clock Card Properly (Left) and Improperly (Right) Inserted 2-30. . . . . . . . . . . . . . . . . . . . . . . .

2–26 Clock Crystal Removal (Left) and Insertion (Right) 2-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–27 Termination-Card Keying 2-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–28 Slot 1 (Left) and Slot 20 (Right) Termination Cards on the Backplane 2-32. . . . . . . . . . . . . . .

2–29 Driver and Receiver Connector Keying 2-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–30 Close-up View of Connector Keying 2-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–31 Proper Connector Mating Sequence (Left to Right) 2-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–32 Connectors Properly Mated 2-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Linear Regulator 2-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TT

viiContents

Figures

3–1 Tektronix O-Scope Front (Left) and Top (Right) 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 O-Scope Probe Monitor-Point Adapters 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–3 Simple Test-Measurement 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4 Turn on O-Scope (Left) and Select Channel (Right) 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–5 O-Scope Display 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–6 Timing Adjustment 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–7 Voltage Adjustment 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–8 Trigger Adjustment 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–1 Case 1: D1 Data Pattern (Ch1) and D1 Latch Clock (Ch2) 4-2. . . . . . . . . . . . . . . . . . . . . . . . . .

4–2 Case 2: D1 Data Pattern (Ch1) and D1 Group 1 GTLP Data Out (Ch2) 4-3. . . . . . . . . . . . . . .

4–3 Case 3: D1 Data Pattern (Ch1) and R2 Group 1 GTLP Data In (Ch2) 4-4. . . . . . . . . . . . . . . .

4–4 Case 4: D1 Data Pattern (Ch1) and R2 Group 1 LVTTL Data Out (Ch2) 4-5. . . . . . . . . . . . . .

4–5 Case 5: R2 Group 1 GTLP Data In (Ch1) and R20 Group 1 GTLP Data In (Ch2) 4-6. . . . . .

4–6 GTLP Backplane Waveforms at 23-MHz Clock Frequency 4-7. . . . . . . . . . . . . . . . . . . . . . . . . .

4–7 GTLP Monitor Test-Point Waveforms at 23-MHz Clock Frequency 4-7. . . . . . . . . . . . . . . . . . .

5–1 Spare Fuses and Jumpers 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–2 Fuse F2 (Left) and Removal Procedure (Right) 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–3 Fuse F1 5-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A–1 Backplane Layout, Front Side A-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A–2 Backplane Layout, Back Side A-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A–3 Driver-Card and Receiver-Card Connector Pinout A-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A–4 Backplane Schematic A-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A–5 Driver-Card Layout A-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A–6 Driver-Card Schematic A-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A–7 Unmonitored-Receiver Card Layout A-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A–8 Monitored-Receiver Card Layout A-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A–9 Receiver-Card Schematic A-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A–10 Clock-Card Layout A-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A–11 Clock-Card Schematic A-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A–12 Resistor-Termination-Card Layout A-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A–13 Standard-Termination-Card Schematic A-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

viii

Tables

Tables

2–1 GTLP EVM Group Assignment 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 GTLP EVM Backplane Eight-Layer Stackup 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 GTLP EVM Group 1, Bits 1 Through 8 Trace Impedance 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . .

2–4 Termination-Card Stackup 2-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–5 Clock-Card Stackup 2-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–6 Driver-Card Stackup 2-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–7 Receiver-Card Stackup 2-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ixContents

Tables

x

Chapter 1

Introduction

The Texas Instruments (TI) GTLP evaluation module (EVM) board is used to
evaluate the SN74GTLPH1655 in multipoint data-transmission applications in
a heavily loaded backplane.

The GTLP EVM is a 17.9-in., 20-slot, 0.94-in.-pitch, 8-layer PC backplane
board that provides a total of 48 parallel data lines divided into 6 groups of 8
bits staggered into various lengths. The EVM also includes a 1-bit clock along
the length of the backplane showing source-synchronous transfer mode. This
board allows the designer to connect 50-Ω unloaded parallel buses to the
transmitter and receiver connectors in a backplane configuration.

New-design backplane-driver selection criteria are based on drive capability ,
live-insertion capability, data throughput, noise margin, backward
compatibility, and bus configuration. The purpose of the GTLP EVM is to
demonstrate the performance of the TI GTLP product portfolio in a
best-in-class high-performance backplane. The backplane enables users to
observe the effects of different kinds of terminations, changing load conditions
due to different spacing and count of daughter cards, and various frequencies,
as well as the benefit of source-synchronous clock over system-synchronous
clock operations. The backplane also can be used to observe the advantages
of edge-rate control and TI-OPC overshoot-protection circuitry, and show
the performance of TI GTLP devices vs alternate-source devices under
different loading conditions.

Topic Page

1.1 GTLP EVM Overview 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 GTLP EVM Kit Contents 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 GTLP EVM Kit Availability 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1

GTLP EVM Overview

1.1 GTLP EVM Overview

The EVM can be used to evaluate device parameters, while acting as a guide
for high-speed board layout. Because GTLP operates over a wide range of
frequencies, designers must optimize their designs for the frequency of
interest. Additionally , designers can use buried transmission lines and provide
additional noise attenuation and EMI suppression to optimize their
end product.

The board layout is designed and optimized to support high-speed operation
up to 100 MHz. Thus, understanding impedance control and transmission-line
effects are crucial when designing high-speed boards.

Some of the advanced features offered by this board include:

-

The backplane printed circuit board (PCB) is designed for high-speed
signal integrity, while the daughter card is designed with integral
measurement points for easily measuring signal integrity.

-

Subminiature A connectors (SMA) as specified by MIL-C-39012 coaxial
connector specification and parallel fixtures easily are connected to test
equipment.

-

The first bit of each group of input/output signals is accessible for rapid
prototyping.

1-2

1.2 GTLP EVM Kit Contents

This EVM kit comprises the following major parts, components of which are
listed in Appendix A.1, GTLP EVM Bill of Materials:

-

GTLP EVM kit documentation (this document, SCEA023)

-

Backplane

-

Clock driver card

-

Termination card

-

Monitored receiver card

-

Monitored driver card

-

Unmonitored receiver card

GTLP EVM Kit Contents

1-3Introduction

GTLP EVM Kit Availability

1.3 GTLP EVM Kit Availability

The GTLP EVM kit is not available for resale, but can be obtained and used
for short periods of time by contacting the GTLP team at [e-mail].
There are six locations worldwide where GTLP EVMs can be obtained:
Europe, China, Korea, Japan, and the Americas (2).

1-4

Chapter 2

GTLP EVM Board

Typical Test and Setup Configuration

This chapter describes the GTLP EVM setup and the configurations used to
evaluate the SN74GTLPH1655 transceiver . These configurations can be used
to evaluate different transceivers that will be available in the future.

Topic Page

2.1 GTLP EVM Case 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Top Tray 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Backplane Board 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Connectors 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Power Supply 2-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Clock Crystals 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 Termination Cards 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8 Bottom Compartment 2-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9 Measurement Equipment 2-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.10 Clock Cards 2-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11 Driver Cards 2-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.12 Receiver Cards 2-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.13 Backplane Setup 2-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-1

GTLP EVM Case

2.1 GTLP EVM Case

The EVM is stored and transported in a sturdy plastic case with rollers and
extensible handle (see Figure 2–1). The handle locks in position and can be
extended or retracted by pressing the release on the underside of the handle.

Figure 2–1. GTLP EVM Case

The case is suitable for air transportation and has the combination lock set at

394. To lock the case, rotate one or more of the dials from the opening
combination.

2-2

2.2 Top Tray

The top tray fits snuggly in the GTLP EVM case (see Figure 2–2) and holds
the backplane board, power supply , extra clock crystals, and extra termination
cards in place. The tray is electrostatic protective foam that holds the
backplane board during demonstrations.

Figure 2–2. GTLP EVM Top Tray

Top Tray

2-3 GTLP EVM Board Typical Test and Setup Configuration

Backplane Board

2.3 Backplane Board

The backplane board (see Figure 2–3) is typical of backplanes used in
commercial applications, and consists of 20 slots with 0.94-in. pitch and
48 data bits, and 1 clock bit on stripline transmission lines.

Figure 2–3. GTLP EVM Backplane Board

This backplane board is constructed uniquely of six groups of eight data bits
each to study the effect of different backplane lengths and driver/receiver
placements. Group 1 consists of all 20 slots, but subsequent groups move to
the left (see Figure 2–4) and have a reduced number of slots, as listed in
Table 2–1.

2-4

Backplane Board

Figure 2–4. GTLP EVM Backplane Block Diagram

Backplane Overview

Slot 1

Slot 2

Slot 3

Slot 4

Slot 5

Slot 6

Slot 7

Slot 8

Slot 9

X X

Clock Generator

X = Termination Card on Back of Connector

Slot 10

Slot 11

Slot 12

Slot 13

Slot 14

Slot 15

Slot 16

Slot 17

Slot 18

Slot 19

Slot 20

Table 2–1. GTLP EVM Group Assignment

Group 6 Group 5 Group 4 Group 3 Group 2 Group 1

2 slots 4 slots 8 slots 12 slots 16 slots 20 slots
P1-1 to P1-2 P1-1 to P1-4 P1-1 to P1-8 P1-1 to P1-12 P1-1 to P1-16 P1-1 to P1-20

A single GTLP clock line that runs from P1-1 to P1-20 is used in the
source-synchronous transfer mode.

The GTLP clock and the data lines from groups 2 through 6 have fixed,
on-board, 25-Ω termination resistors. Group 1 data lines terminate on plug-in
cards on the back of the backplane board at P1-1B and P1-20B. This provides
a way to vary the termination resistance or demonstrate other termination
techniques.

The design also uses a system clock that is generated on the clock-driver
board plugged into P3. This system clock is distributed to all 20 slots
simultaneously and is used as the system master timing in the system-clock
mode. Using a separate card for clock generation and distribution is not an
industry standard, but it provides flexibility in using this demonstration board.

2-5 GTLP EVM Board Typical Test and Setup Configuration

Backplane Board

A logic selection line (MODESEL) connects P1-1 through P1-20. The driver
card uses this line to select between source-synchronous and system-clock
operation. The demonstration board is an eight-layer board with separate V
and ground planes. The backplane board stackup is shown in Table 2–2.
Embedded microstrip nominal line width is 0.006 in., dielectric material is
Nelco N4000-13 with a dielectric constant (50% resin contents) of

3.80 @ 100 MHz.

Table 2–2. GTLP EVM Backplane Eight-Layer Stackup

CC

Trace Name Use Layer

Top Regulator power/

bypass capacitor/
termination

Internal signal 2 Clock distribution/

signal

Ground plane Ground plane 3 1

Internal signal 3 Data signal 4 1

Internal signal 4 Data signal 5 1

V

CC

V

CC

1 0.5

2 1

6 1

Copper
Weight
(oz)

Physical
Representation

Dielectric
Height
(in.)

0.004 B stage

0.004 Core

0.004 B stage

0.058 Core

0.004 B stage

0.004 Core

Dielectric
Name

Internal signal 5 Data signal 7 1

Bottom Termination 8 0.5

2-6

0.004 B stage

Backplane Board

Targeted, nominal, unloaded line impedance was 50 Ω, but, based on
post-manufacturing testing, was not consistent. Results for Group 1, bits 1
through 8 are shown in T able 2–3. The backplane natural trace impedance (Z
is calculated and is a best estimate. The backplane trace impedance with only
the connector pins attached (i.e., all cards removed) (Z

′) and the backplane

o

trace impedance in a fully loaded backplane (i.e., 20 cards inserted) (Z
measured.

Table 2–3. GTLP EVM Group 1, Bits 1 Through 8 Trace Impedance

Group 1 Trace D1 D2 D3 D4 D5 D6 D7 D8
Natural Trace Impedance

Zo (Ω) 91 47.5 47 47 48 47.5 83 47.5
tpd (ps/in.) 165 140 138 139 141 148 147 142
C

(pF/in.) 1.81 2.95 2.94 2.96 2.94 3.12 1.77 2.99

o

Trace Impedance With Only Connectors

Zo′ (Ω) 62.7 37.5 37 36.3 37.1 37.9 58.5 36.8

′′) are

o

)

o

tpd′ (ps/in.) 240 177 175 180 183 185 208 183

Trace Impedance Under Full Load

Zo′′ (Ω) 26.6 17.7 17.9 17.5 17.9 18 24.8 17.7
tpd′′ (ps/in.) 564 377 362 373 377 390 493 382

Note the difference in fully loaded trace impedance between trace bit 1 and
bit 7 (D1 and D7) and the other traces. Using the lower natural trace
impedance offers the advantage of a smaller t

and shorter flight time, but at

pd

the expense of terminating with a lower-value termination resistor and the
subsequent increase in power consumption. TI offers both medium-drive
(50 mA) and high-drive (100 mA) GTLP devices that allow designers to match
the device with backplane loading. The termination resistor (R

) should

TT

match the fully loaded trace impedance (i.e., Zo′′) of the backplane for optimal
signal integrity.

2-7 GTLP EVM Board Typical Test and Setup Configuration

Connectors

2.4 Connectors

An AMP Z-P ACK  2-mm, 110-pin, hard-metric (HM) male connector is used
in slots 1 through 20 (see Figure 2–5) .

Figure 2–5. AMP Z-PACK 2-mm, 110-Pin, Hard-Metric (HM) Male Connector

Five pins are used on the backplane, with three different lengths on the
backplane daughter-card side. Pins A, B, and C are used for data/VCC,
BIAS V

, and GND, respectively. C-length pins are in the center, and

CC

A-length pins are in two rows on either side. The daughter-card connectors
P1-1 through P1-20 use these three levels of pin height for power sequencing.
The ground pins make contact first, followed by a pin for BIAS V
other connections are made. There is only one B-length pin because BIAS V

, then all

CC

CC

can be distributed to all four GTLP devices on the board. The pin lengths of
pins K and T are identical to those of pins A and C on the card side, but they
protrude through the backplane board, providing connection to the termination
cards that are on the reverse side.

Initial testing revealed that this pin configuration was unacceptable for actual
operation because the BIAS V

circuitry was disabled before all I/O pins were

CC

connected. Any tilt on the card caused VCC to be connected first. Some slots
in selected EVMs have been modified, so that BIAS V

and GND are

CC

C length, data signal is B length, and VCC is A length, to allow proper operation
of the BIAS V

precharge circuitry.

CC

Various AMP pin lengths, including pins A, B, C, K, and T, are shown in
Figure 2–6, and the single-line-model data sheet is shown in Figure 2–7.

2-8

Figure 2–6. AMP Pin Lengths

Connectors

* X, U, V are used only for cross-connect applications. Not all versions are tooled.

2-9 GTLP EVM Board Typical Test and Setup Configuration

Connectors

Figure 2–7. AMP Single-Line-Model Data Sheet

2-10

2.5 Power Supply

The power supply (see Figure 2–8) is a universal power supply that accepts
100 V to 240 V , 50/60-Hz ac and uses any wall plug that connects to the IEC
320 two-connector universal socket with the US/Canada Edison plug. An
alternate supply cord with a different wall plug must be procured locally, if
required.

The power-supply output is 24-Vdc at 2.1 A, which is fed to the backplane
board using the 5.5-mm plug to J5 (see Figure 2–8), and connects through a

2.5-A slow-blow fuse (F1). Power should not be applied to the backplane board
until the cards have been inserted during the initial setup because the clock
card is not hot insertable. The termination, daughter cards, and clock crystals
are live insertable and can be inserted and removed to change position/values
during testing without disconnecting the power supply.

Figure 2–8. Power Supply (Left) and Backplane Connection (Right)

Power Supply

The 24-Vdc is reduced to 5 V, 1 A by the Lambda PM10-24S05 switching
regulator (Figure 2–8 background) and to 3.3 V, 7.5 A by the Lambda
PM30-24503 switching regulator (Figure 2–8 foreground) for V
and the linear regulator. The 3.3 V is supplied to all connectors through a 5-A
fuse (F2). The 5 V also is applied to all connectors. Originally , F2 was specified
as a 3.5-A fuse, but, at 100-MHz operation, current exceeds this value, so 5-A
fuses are necessary.

, BIAS VCC,

CC

2-11 GTLP EVM Board Typical Test and Setup Configuration