Texas Instruments GC4014 Datasheet

SLWS132

GC4014

QUAD RECEIVER CHIP

DATASHEET

April 27, 1999

Rev 0.5

This datasheet contains information which may be changed at any time without notice.

GC4014 QUAD RECEIVER CHIP DATA SHEET REV 0.5

REVISION HISTORY

Revision Date Description

0.0 1 Dec. 1997 Original

0.1 14 Jan 1998 Page iii, added mask revision table to list of tables
Pages 8, last line, added non-symmetry mode errata
Page 10, footnote, changed “1 milliseconds” to “10 microseconds”.
Page 11, modified Figure 10 (c)
Page 12, first line Section 3.7, changed “output” to “input”.
Page 18, address 1, bit 6, added non-symmetry errata
Page 19, address 4, bits 4-7, corrected bit assignments
Pages 20-21, corrected address numbering for blanking and flush registers
Page 22, address 12, bits 0,1, changed “12 LSBs” to “14 LSBs”.
Page 24, address 16, added mask revision table.
Throughout, corrected table and figure reference

0.2 21 Jan 1998 Page 30, Changed data setup time from 4 to 2 ns.
Page 8, 18 Non-symmetry mode works for parts marked with all mask codes
except 55532B
Page 24, Changed Table 5 to add mask code 55532C
Page 28, Table 7 min and max recommended Vcc changed to 3.1 to 3.5 volts.
Page 28, Table 7 max junction temperature changed to 125C.

0.3 5 Feb 1998 Page 38, Changed 800 to 8000 in Table 17.
Page 38, Changed E5 to EA in note 1, Table 16.
Page 37, Checksum for test4 changed to D2.

0.4 23 Apr 1999 Page 38, Changed CS to CE in the control interface timing description, Table 10
Pages 9,19, Changed GAIN equation from
Page 28, Table 7, Changed max Vup voltage to 5.5v.
Page 39, New gain application note.
Pages 5, 25, Positive frequency to downconvert.
Pages 36, 37, changed 26 -> 2A for address 00
Page 29, Table 9, changed V
Page 29, Table 9, changed I
Page 30, F

0.5 27 Apr 1999 Pages 9,19,33,35,39, changed gain equation G/64 -> G/32

0.6 Pages 6, 38 changed 55 to 56 in gain equations.

changed to 64MHz, clock to output changed to 20ns.

CK

for CK, CK2X to 2.4V from 2.0V.

IH

to +/- 4mA from 2.0mA

OH/L

“NARROW*1.97”

to

“NARROW*0.97 + 1"

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CONTACTING GRAYCHIP

CORPORATE OFFICES:

GRAYCHIP, Inc.
2185 Park Blvd.
Palo Alto, CA 94306

PHONE:

[phone]

FAX:

[phone]

WEB PAGE:

www.graychip.com

E-MAIL:

[e-mail]
[e-mail]

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GC4014 QUAD RECEIVER CHIP DATA SHEET REV 0.5

1.0 KEY FEATURES .........................................................................................................................1

2.0 BLOCK DIAGRAM .....................................................................................................................1

3.0 FUNCTIONAL DESCRIPTION ...................................................................................................2

3.1 CONTROL INTERFACE ....................................................................................................................... 2

3.2 INPUT FORMAT ................................................................................................................................... 3

3.3 THE DOWN CONVERTERS ................................................................................................................ 4

3.4 FINAL GAIN ADJUSTMENT ................................................................................................................ 9

3.5 SUMMATION MODES ......................................................................................................................... 9

3.6 OUTPUT MODES ............................................................................................................................... 10

3.7 CLOCKING ......................................................................................................................................... 12

3.8 POWER DOWN MODES ................................................................................................................... 12

3.9 SYNCHRONIZATION ......................................................................................................................... 12

3.10 DATA LATENCY ................................................................................................................................ 13

3.11 DIAGNOSTICS ................................................................................................................................... 13

4.0 PACKAGING .............................................................................................................................14

5.0 CONTROL REGISTERS............................................................................................................16

5.1 SYNC MODE REGISTER ................................................................................................................... 17

5.2 DECIMATION MODE REGISTER....................................................................................................... 18

5.3 CIC DECIMATION REGISTERS......................................................................................................... 18

5.4 SCALE CONTROL REGISTER........................................................................................................... 19

5.5 CHANNEL GAIN REGISTER.............................................................................................................. 19

5.6 OUTPUT FORMAT REGISTER.......................................................................................................... 20

5.7 OUTPUT MODE REGISTER............................................................................................................... 20

5.8 BLANKING CONTROL REGISTER ....................................................................................................20

5.9 CHANNEL FLUSH CONTROL REGISTER......................................................................................... 21

5.10 COUNTER MODE REGISTERS......................................................................................................... 21

5.11 TEST MODE REGISTER.................................................................................................................... 22

5.12 PAGE MAP REGISTER ...................................................................................................................... 22

5.13 STATUS CONTROL REGISTER ........................................................................................................ 23

5.14 CHECKSUM REGISTER..................................................................................................................... 23

5.15 CHANNEL OUTPUT PAGE (PAGE = 0)............................................................................................. 24

5.16 KEEPALIVE STATUS PAGE (PAGE = 1)........................................................................................... 24

5.17 CHANNEL CONTROL PAGES (PAGES 4, 5, 6, 7)............................................................................. 25

5.18 COEFFICIENT STORAGE PAGES (PAGES 8, 9, 10 and 11)............................................................ 27

6.0 SPECIFICATIONS.....................................................................................................................28

6.1 ABSOLUTE MAXIMUM RATINGS...................................................................................................... 28

6.2 RECOMMENDED OPERATING CONDITIONS.................................................................................. 28

6.3 THERMAL CHARACTERISTICS ........................................................................................................ 28

6.4 DC CHARACTERISTICS .................................................................................................................... 29

6.5 AC CHARACTERISTICS..................................................................................................................... 30

7.0 APPLICATION NOTES..............................................................................................................31

7.1 POWER AND GROUND CONNECTIONS.......................................................................................... 31

7.2 STATIC SENSITIVE DEVICE.............................................................................................................. 31

7.3 SYNCHRONIZING MULTIPLE GC4014 CHIPS ................................................................................. 31

7.4 THERMAL MANAGEMENT................................................................................................................. 31

7.5 GSM APPLICATION............................................................................................................................ 32

7.6 DAMPS APPLICATION....................................................................................................................... 34

7.7 DIAGNOSTICS.................................................................................................................................... 36

7.8 OUTPUT TEST CONFIGURATION ....................................................................................................38

7.9 OPTIMAL GAIN SETTINGS................................................................................................................ 39

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LIST OF FIGURES

Figure 1: GC4014 Block Diagram ..................................................................................................................1

Figure 2: Control I/O Timing...........................................................................................................................3

Figure 3: The Down Converter Channel.........................................................................................................4

Figure 4: NCO Circuit.....................................................................................................................................5

Figure 5: Example NCO Spurs.......................................................................................................................5

Figure 6: NCO Peak Spur Scan Plot..............................................................................................................6

Figure 7: Four Stage CIC Decimate by N Filter..............................................................................................6

Figure 8: Combined CFIR and CIC Frequency Response.............................................................................7

Figure 9: Overall CIC-CFIR-PFIR Response .................................................................................................8

Figure 10: Serial Output Formats...................................................................................................................11

Figure 11: Overall Frequency Response for GSM.........................................................................................32

Figure 12: Overall Frequency Response for DAMPS.....................................................................................34

LIST OF TABLES

Table 1: Output Summation Modes ..............................................................................................................9

Table 2: TDM Modes...................................................................................................................................10

Table 3: Latency..........................................................................................................................................13

Table 4: Sync Modes ..................................................................................................................................17

Table 5: Mask Revision History...................................................................................................................24

Table 6: Absolute Maximum Ratings ..........................................................................................................28

Table 7: Recommended Operating Conditions...........................................................................................28

Table 8: Thermal Data ................................................................................................................................28

Table 9: DC Operating Conditions..............................................................................................................29

Table 10: AC Characteristics (-40 To +85C Ambient, unless noted)............................................................30

Table 11: GSM Configuration........................................................................................................................33

Table 12: DAMPS Configuration...................................................................................................................35

Table 13: Diagnostic Test 1 Configuration....................................................................................................36

Table 14: Diagnostic Test 2 Configuration....................................................................................................36

Table 15: Diagnostic Test 3 Configuration....................................................................................................37

Table 16: Diagnostic Test 4 Configuration....................................................................................................37

Table 17: Output Test Configuration.............................................................................................................38

Table 18: Test Output Sequence..................................................................................................................38

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1.0

KEY FEATURES

• Input rates up to 64 MSPS

• Four real input down-convert channels or
Two complex input downconvert channels

• Independent tuning frequencies

• Independent phase/gain controls

• 4 by 4 14 bit Input Crossbar switch or
3 by 4 16 bit Input Crossbar switch

• Decimation factors of

16 to 32,768 in the real output mode
32 to 65,536 in the complex output mode

• Zero padding for lower decimation factors

• Outputs can be either:

bit serial,
nibble serial (link port)
or memory mapped

• Output summing for beamforming

• 8 to 16 bit output samples

• 0.02 Hz tuning resolution

GC4014 DATASHEET

• 0.14 dB gain resolution

• Less than 0.05 dB peak to peak passband
ripple

• Greater than 100 dB far image rejection

• Greater than 95 dB spur free dynamic range

• User programmable 63 tap output filter

• Nyquist filtering for QPSK or QAM symbol
data

• Meets GSM, AMPS and DAMPS Cellular
specifications

• Microprocessor interface for control, output,
and diagnostics

• Built in diagnostics

• Microprocessor interface will accept either

3.3 or 5 volt input levels

• 250 mW per channel at 50 MHz, 3.3 volts

• 100 pin thin QFP package

2.0 BLOCK DIAGRAM

A block diagram illustrating the major functions of the chip is shown in Figure 1.

DIAGNOSTICS

BANDWIDTH

FILTER SELECT
DECIMATE BY 8

FORMAT

A[0:4]

C[0:7]

CK

CE

WR

RD

SI

CLOCK DOUBLING

AND

DISTRIBUTION CIRCUIT

CONTROL INTERFACE

AND FILTER

COEFFICIENT RAMS

SYNC COUNTER

AND

DIAGNOSTIC TEST

GENERATOR

SO

SELECT

A

IN

(14 BITS)

(16 bit input mode uses the DIN pins for the LSB’s of inputs AIN, BIN, and CIN)

SINE/

COSINE

PHASE

TUNING

FREQUENCY

GENERATOR

OFFSET

DECIMATE

BY 8 TO 16K

FILTER

TWO STAGE

DECIMATE
BY 4OR 8

FILTER

OUTPUT
FORMAT

AND GAIN

GAIN GAIN

A

OUT

(BIT SERIAL)

B

IN

(14 BITS)

DECIMATE

BY 8 TO 16K

FILTER

TWO STAGE

DECIMATE
BY 4OR 8

FILTER

OUTPUT
FORMAT

AND GAIN

OUTPUT SUM AND MULTIPLEX

B

OUT

(BIT SERIAL)

CROSSBAR SWITCH

SINE/

COSINE

GENERATOR

PHASE

TUNING

OFFSET

FREQUENCY

C

IN

(14 BITS)

SINE/

COSINE

DECIMATE

BY 8 TO 16K

FILTER

TWO STAGE

DECIMATE
BY 4OR 8

FILTER

OUTPUT
FORMAT

AND GAIN

GAIN GAIN

C

OUT

(BIT SERIAL)

GENERATOR

PHASE

TUNING

FREQUENCY

OFFSET

D

IN

(14 BITS)

DECIMATE

BY 8 TO 16K

FILTER

TWO STAGE

DECIMATE
BY 4OR 8

FILTER

OUTPUT
FORMAT

AND GAIN

D

OUT

(BIT SERIAL)

SINE/

COSINE

GENERATOR

PHASE

TUNING

OFFSET

FREQUENCY

ACKNOWLEDGE

READY

BIT-CLOCK

FRAME SYNC

Figure 1. GC4014 Block Diagram

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GC4014 QUAD RECEIVER CHIP DATA SHEET REV 0.6

3.0

accepts a real sample rate up to 62.5 MHz, down converts a selected carrier frequency to zero, decimates the signal
rate by a programmable factor ranging from 16 to 32768 (32 to 65,536 for complex outputs), and optionally sums it
with other down converted samples. The chip outputs the four down-converted signals, or their sum. The chip
contains a user programmable output filter which can be used to arbitrarily shape the received data’s spectrum. This
filter can be used as a Nyquist receive filter for digital data transmission.

out of band rejection. Each down-convert circuit accepts 16 bit inputs and produces 16 bit outputs (bit serial). The
frequencies and phase offsets of the four sine/cosine sequence generators can be independently specified, as can
the gain of each circuit. The down converters share the same bandwidth, filter coefficients and input formats. A
special mode allows the downconverters to support GSM and DAMPS blocker requirements (see Sections 7.5 and

FUNCTIONAL DESCRIPTION

The GC4014 quad receive chip contains four identical down-conversion circuits. Each down-convert circuit

Two down-converter paths can be merged to be used as a single complex input down-conversion circuit.
The down-converters are designed to maintain over 95 dB of spur free dynamic range and over 100 dB of

7.6).
On chip diagnostic circuits are provided to simplify system debug and maintenance.
The chip receives configuration and control information over a microprocessor compatible bus consisting of

an 8 bit data I/O port, a 5 bit address port, a chip enable strobe, a read strobe and a write strobe. The chip’s control
registers (8 bits each) are memory mapped into the 5 bit address space of the control port.

Section 7.5 Describes a typical application, including control register values and the proper sequence of

operations required to use the chip.

3.1 CONTROL INTERFACE

The chip is configured by writing control information into sixty four control registers within the chip. The

contents of these control registers and how to use them are described in Section 5. The registers are written to or
read from using the C[0:7] , A[0:4] , CE , RD and WR pins. Each control register has been assigned a unique address
within the chip. This interface is designed to allow the GC4014 to appear to an external processor as a memory
mapped peripheral (the pin RD is equivalent to a memory chip’s OE pin).

An external processor (a microprocessor, computer, or DSP chip) can write into a register by setting A[0:4]

to the desired register address, selecting the chip using the CE pin, setting C[0:7] to the desired value and then
pulsing WR low. The data will be written into the selected register when both WR and CE are low and will be held
when either signal goes high.

To read from a control register the processor must set A[0:4] to the desired address, select the chip with

the CE pin, and then set RD low. The chip will then drive C[0:7] with the contents of the selected register. After the

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RD

processor has read the value from C[0:7] it should set RD and CE high. The C[0:7] pins are turned off (high
impedance) whenever CE or RD are high or when WR is low. The chip will only drive these pins when both CE and

are low and WR is high.

One can also ground the RD pin and use the WR pin as a read/write direction control and use the CE pin

as a control I/O strobe. Figure 2 shows timing diagrams illustrating both I/O modes.

CE
WR

RD

A[0-5]

C[0-7]

CE
WR

RD

A[0-5]

C[0-7]

CE
WR

A[0-5]

C[0-7]

t

CSU

t

CSU

t

CSU

t

CSU

t

CSU

t

CDLY

READ CYCLE- NORMAL MODE

t

CSPW

WRITE CYCLE- NORMAL MODE

t

CDLY

READ CYCLE- RD HELD LOW

t

CHD

t

CHD

t

CHD

t

CZ

t

CZ

t

CE
WR

A[0-5]

C[0-7]

t

CSU

WRITE CYCLE- RD

CSPW

HELD LOW

t

CHD

Figure 2. Control I/O Timing

The setup, hold and pulse width requirements for control read or write operations are given in

Section 6.0.

The C , A , WR , RD and CE pins will accept either 5 volt or 3.3 volt input levels. A separate power supply

voltage pin ( V

) is provided on the chip to enable this feature.

UP

3.2 INPUT FORMAT

Both 14 bit and 16 bit input formats are accepted. In the 14 bit mode the inputs are 14 bit samples from four

different sources. In the 16 bit mode, the inputs are 16 bit samples from three different sources. In either case, a
crossbar switch allows the user to route any input to any down-converter channel. The input samples are normally
clocked into the chip at the clock rate, i.e., the input sample rate is equal to the clock rate. Input rates lower than the
clock rate can be accepted by using the zero pad mode. The zero pad mode will insert up to 15 zeroes between

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T

each input sample, allowing input data rates down to 1/16th the clock rate. Zero padding also lowers the effective
decimation ratio. For example, the minimum decimation is normally factor of 32. If the input data rate is 5 MSPS and
the chip can be clocked at 40 MHz, then the zero pad function can be used to pad the 5 MSPS input data up by a
factor of 8 to 40 MSPS. The minimum decimation of 32, once the zero padding is done, becomes a minimum
decimation of 4 relative to the original 5 MSPS data.

3.3 THE DOWN CONVERTERS

Each down converter uses an NCO and mixer to quadrature down convert a signal to baseband and then

uses a 4 stage CIC1 filter and a two-stage decimate by 4 or 8 filter to lowpass filter and to isolate the desired signal.
A block diagram of each filter is shown below:

SCALE and

BIG_SCALE

IN

SHIFT DOWN

N

8 TO 16K

CIC FILTER

DECIMATE BY

COARSE

GAIN

COARSE

NARROW

CFIR FILTER

DECIMATE BY 2

FILTER_SELEC

REAL

DEC_BY_4

2 OR 4

PFIR FILTER

DECIMATE BY

G

GAIN

FINAL

I

TO

OUTPUT

FORMATTER

Q

TUNING

FREQUENCY

PHASE

OFFSET

NCO

Figure 3. The Down Converter Channel

The CIC filter reduces the sample rate by a programmable factor ranging from 8 to 16,384. The CIC outputs

are followed by a coarse gain stage and then followed by a two stage decimate by 4 or 8 filter. The coarse gain
circuit allows the user to boost the gain of weak signals up to 42 dB in 6 dB steps. The first stage of the two stage
filter is a compensating 21 tap decimate by 2 filter (CFIR) with a choice of two sets of fixed tap weights. The first set
is designed to be flat from -0.5FS to +0.5FS, where FS is the output sample rate, and to reject out of band energy by
at least 80dB. The second set has a narrower output passband (-0.25FS to +0.25FS), but more out of band rejection.
The second set is ideal for systems such as GSM, which require more far band rejection (>97 dB), but with relaxed
adjacent band rejection. The second stage is a 63 tap decimate by 2 or 4 programmable filter (PFIR) with either
internal or user supplied tap weights. The internal filter is designed to be flat from -0.4FS to +0.4FS of the output
sample rate and to reject out of band energy by at least 85 dB. The user can also design and download their own
final filter to customize the channel’s spectral response. Typical uses of the programmable filter include matched
(root-raised cosine) filtering, or filtering to generate oversampled outputs with greater out of band rejection. The 63
tap symmetrical filter is downloaded into the chip as 32 words, 16 bits each. The programmable PFIR coefficients
must be used to bandlimit the output in the decimate by 4 mode.

1. Hogenauer, Eugene B., An Economical Class of Digital Filters for Decimation and Interpolation, IEEE transactions on Acoustics,
Speech and Signal Processing, April 1981.

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The PFIR will also, if desired, convert the complex output data to real. The complex to real conversion also

doubles the output sample rate so that the PFIR decimation is 1 or 2 in the real mode.

The PFIR filter is followed by a gain and output format circuit. The gain circuit allows the user to add an

additional 18 dB of gain in 0.14 dB steps. The output format circuit can also delete every other sample without
filtering. Anti-aliasing filtering must have already been performed (in the second stage filter). This is useful to achieve
deeper far-band rejection since the stopband performance of the CIC filter is a function of the decimation that follows
it.

3.3.1 The Numerically Controlled Oscillator (NCO)

The tuning frequency of each down converter is specified as a 32 bit word and the phase offset is specified

as a 16 bit word. The NCOs can be synchronized with NCOs on other chips. This allows multiple down converter
outputs to be coherently combined, each with a unique phase and amplitude. A block diagram of the NCO circuit is
shown in Figure 4.

GENERATOR

16 BITS

18 MSBs

DITHER

5 BITS

14 MSBs

SINE/COSINE

LOOKUP

TABLE

15 BITS

SINE/COSINE

OUT

FREQUENCY

WORD

32 BITS

32 BITS

PHASE

OFFSET

Figure 4. NCO Circuit

The tuning frequency is set to FREQ according to the formula FREQ = 232F/FCK, where F is the desired

tuning frequency and FCK is the chip’s clock rate. The 16 bit phase offset setting is PHASE = 2

the desired phase in radians ranging between 0 and 2π. Note that a positive tuning frequency is used to

downconvert the signal. A negative tuning frequency can be used to upconvert the negative image of a real signal
(inverting the spectrum).

The NCO’s spur level is reduced to below -92 dBc through the use of phase dithering. The spectrums in

Figure 5 show the NCO spurs for an example tuning frequency before and after dithering has been turned on. Notice
that the spur level decreases from -82 dB to -105 dB.

16

P/2π, where P is

-82 dB

(a) Before Dithering

-105 dB

(b) After Dithering

Figure 5. Example NCO Spurs

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Figure 6 shows the maximum spur levels as the tuning frequency is scanned over a portion of the frequency

range with the peak hold function of the spectrum analyzer turned on. Notice that the peak spur level is -82 dB before
dithering and is between -92 and -102 after dithering has been turned on.

-82 dB

-102 dB

-92 dB

(a) Before Dithering (b) After Dithering

Figure 6. NCO Peak Spur Scan Plot

The worst case NCO spurs at -92 dB, such as the one shown in figure 6(b), are due to a few frequencies

that are related to the sampling frequency by small rational numbers (for example FREQ = 3/16 * Fck). In these
cases the rounding errors in the sine/cosine lookup table repeat in a regular fashion, thereby concentrating the error
power into a single frequency, rather than spreading it across the spectrum. These worst case spurs can be
eliminated by selecting an initial phase that minimizes the errors or by changing the tuning frequency by a small
amount (50 Hz). All spurs can be made to fall below -96 dB with the selection of a proper initial phase or tuning
frequency.

3.3.2 Four Stage CIC Filter

The mixer outputs are decimated by a factor of N in a four stage CIC filter, where N is any integer between

8 and 16,384. The programmable decimation allows the chip’s usable output bandwidth to range from less than a
kilo-Hertz to 1.5 MHz when the input rate (which is equal to the chip’s clock rate) is 62.5 MHz. A block diagram of
the CIC filter is shown in Figure 7.

DATA

IN

16 BITS

CIC_SCALE

UPPER
24 BITS

OF N

DECIMATE

CLOCKED AT FULL RATE CLOCKED AT 1/N RATE

BY FACTOR

24 BITS

DATA

OUT

Figure 7. Four Stage CIC Decimate by N Filter

The CIC filter has a gain equal to N4 which must be compensated for in the “CIC_SCALE” circuit shown in

Figure 7. This circuit has a gain equal to 2
ranges from 0 to 7. The gain of the CIC circuit is equal to: . The user must select

(SCALE+6*BIG_SCALE-56)

GAIN N42

, where SCALE ranges from 0 to 5 and BIG_SCALE

SCALE 6 BIG_SCALE 56–×+()

=

values for SCALE and BIG_SCALE such that GAIN is less than one, i.e., SCALE and BIG_SCALE must be selected
such that: . Overflows due to improper gain settings will go undetected if this

SCALE 6 BIG_SCALE×+()56 4log2N–()≤

relationship is violated. For example, if N is equal to 8, then this restriction means that BIG_SCALE and SCALE

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should be less than or equal to 7 and 2 respectively. The BIG_SCALE and SCALE settings are common to all
channels.

3.3.3 Coarse Channel Gain

The gain of each channel can be boosted up to 42 dB by shifting the output of the CIC filter up by 0 to 7 bits

prior to rounding it to 16 bits. The coarse gain is: , where COARSE ranges from 0 to 7. Overflows
in the coarse gain circuit are saturated to plus or minus full scale. The coarse gain is used to increase the gain of
an individual signal after the input bandwidth of the downconverter has been reduced by a factor of N in the CIC
filter. If the signal power across the input bandwidth is relatively flat, as is the case in most frequency division
multiplexed (FDM) systems, then one would want to boost the signal power out of the CIC filter by a factor of

GAIN 2

=

COARSE

GAIN N=

Section 3.4 can boost the overall gain by up to 24 more dB.

. Each channel can be given its own coarse gain setting. Note that the final gain stage described in

3.3.4 The Compensating Decimate By Two Filter (CFIR)

The CIC/Coarse gain outputs are filtered by two stages of filtering. The first stage is a 21 tap decimate by

2 filter with two sets of fixed coefficients. The first set of coefficients is used in the normal mode to give a passband
which is flat (0.01 dB ripple) over 100% of the final output bandwidth and which has 85 dB of out of band rejection.
The filter also compensates for the droop associated with the CIC programmable decimation filter. The filter is
symmetric with the following taps:

29, -85, -308, -56, 1068, 1405, -2056, -6009, 1303, 21121, 32703

The narrow set of coefficients are intended for applications that need deeper stop bands or need

oversampled outputs. These requirement are common in cellular systems where out of band rejection requirements
can exceed 100 dB. The filter coefficients for the narrow mode are:

-98, -679, -2016, -3234, -2537, 850, 6053, 12060, 18230, 23239, 25212

The combined frequency response of the CIC and CFIR filter for both modes is shown below:

(a) Normal Mode (b) Narrow Mode

Figure 8. Combined CFIR and CIC Frequency Response

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The dashed vertical line in the plots shows the output Nyquist rate for the chip when the PFIR is in the

decimate by 2 mode. The narrow mode filter introduces a gain of 1.97 (5.9 dB).

3.3.5 The Programmable Final Filter (PFIR)

The second stage decimate by two or four filter uses either internal ROM based coefficients, or externally

downloaded filter coefficients. The internal 80% bandwidth filter has 80 dB of out of band image rejection and 0.03
dB peak to peak passband ripple. The internal filter is a 63 tap symmetric filter. The 32 unique coefficients are:

-14, -20, 19, 73, 43, -70, -82, 84, 171, -49, -269, -34, 374, 192, -449,

-430, 460, 751, -357, -1144, 81, 1581, 443, -2026, -1337, 2437, 2886,

-2770, -6127, 2987, 20544, 29647

Figure 9(a) shows the overall response for the internal PFIR when the CFIR is in the normal mode. Figure

9(b) shows the overall response when the CFIR is in the narrow mode. Note that the peaks in the stop band at 3.5
times the output sample rate will, after decimation, fold into the transition band from 0.4 to 0.5 of the output sample
rate. This out of band power, if necessary, can be filtered out by either using a custom PFIR filter with a narrower
passband, or by post-filtering.

An overall response using custom coefficients suitable to meet the stringent GSM Cellular requirements is

shown in Figure 9(c). See Sections 7.5 and 7.6 for more details on GSM and DAMPS configurations.

Peaks fold into

transition band

(a) Normal CFIR Mode (b) Narrow CFIR Mode

Peaks fold into

transition band

(c) GSM Coefficients

Figure 9. Overall CIC-CFIR-PFIR Response

The externally downloaded coefficients can be used to tailor the spectral response to the user’s needs. For

example, it can be programmed as a Nyquist (typically a root-raised-cosine) filter for matched filtering digital data.
The user downloaded filter coefficients are 16 bit 2’s complement numbers. Unity gain will be achieved through the
filter if the sum of the 63 coefficients is equal to 65536. If the sum is not 65536, then the PFIR will introduce a gain
equal to (sum of coefficients)/65536.

The 63 coefficients are identified as coefficients h0 through h62, where h31 is the center tap. The coefficients

are assumed to be symmetric, so only the first 32 coefficients (h0 through h31) are loaded into the chip. A
non-symmetric mode allows the user to download a 32 tap non-symmetric filter as taps h0 through h31. ERRATA:
The non-symmetry mode does not work properly for parts marked with mask code 55532B, Contact GRAYCHIP for
details.

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This document contains information which may be changed at any time without notice

GC4014 QUAD RECEIVER CHIP DATA SHEET REV 0.6

3.3.6 Real Mode

The PFIR will output either complex or real data. Complex data is output at a rate equal to FCK/(4N) or

FCK/(8N) in the decimate by 4 mode. If the output samples are real, then the filter translates the output spectrum up
by multiplying the filtered data by the complex sequence +1, -j, -1, +j, …, and then outputting the real part at a rate
equal to FCK/2N. The real output mode can be used to create double sided signals out of single sideband data. The
real outputs are packed into complex words for output. The first sample of a real pair is put into the I-half and the
second is put into the Q-half. Note that the decimate by 4 mode is invalid in the real mode.

3.4 FINAL GAIN ADJUSTMENT

The final gain of each channel is adjusted by multiplying each output sample by G/32, where G is a 10bit

2’s complement gain word. Since G can range between -512 and +511, the gain adjustment will range from -16.0

to +15.98. Setting G to zero clears the channel. This provides a final gain adjustment range from -∞ to +24 dB in

approximately 0.28 dB steps. A different gain can be specified for each channel. Note that the overall gain of the
chip is also a function of the amount of decimation programmed into the chip (N), the scale circuit setting in the CIC
filter, the coarse gain setting, the narrow mode in the CFIR, and the sum of the PFIR coefficients. The overall gain
is shown below where the first term in braces is fixed for all four channels and must be less than or equal to unity.
The terms in square brackets can be different for each channel. NARROW is “1” in the narrow CFIR mode, “0”
otherwise. See Section 7.9 for a discussion on properly setting the chip’s gain.

GAIN N42

{} 2

SCALE 6 BIG_SCALE× 56–+()

COARSE

[]1.0 NARROW 0.97×+{}

PFIR_SUM

------------------ -

{}

65536

G

----- -

[]=

32

3.5 SUMMATION MODES

The chip can be programmed to output the four individual channels, the sum of pairs of channels, or the

sum of all four channels.These modes are used to process four real input signals, two complex input signals, or one
beamformed signal. When processing two complex input signals, the I inputs are put in channels A and C, and the
Q inputs are put in channels B and D. The summation mode then adds channels A and B together and channels C
and D together.

Summation is disabled in Sum Mode 0. In Sum Mode 1 the channel A output is replaced by the sum of

channels A and B, the channel B output is replaced by the sum of channels C and D, and the channel C and D
outputs are left alone. In Sum Mode 2 the channel A output becomes the sum of all four channels and channels B,
C and D are left alone. These modes are summarized in the following table:

Table 1: Output Summation Modes

CHANNEL OUTPUT

SUM MODE

OUT

A

CH

0
1
2

CHA + CHB + CHC + CH

A

CHA + CH

B

D

OUT

B

CH

B

CHC + CH

CH

B

OUT

C

CH

C

D

CH
CH

C

C

OUT

CH
CH
CH

D

D

D

D

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This document contains information which may be changed at any time without notice