Datasheet EV2050, BQ2050SN-D119TR, BQ2050SN-D119 Datasheet (Texas Instruments)

1

Features

➤

Conservative and repeatable
measurement of available capac

­ity in Lithium Ion rechargeable
batteries

➤

Designed for battery pack inte

­gration

-

120µA typical operating
current

-

Small size enables imple­mentations in as little as

1

2

square inch of PCB

➤

Integrate within a system or as a
stand-alone device

-

Display capacity via single­wire serial communication
port or direct drive of LEDs

➤ Measurements compensated for

current and temperature

➤ Self-discharge compensation us-

ing internal temperature sensor

➤ 16-pin narrow SOIC

General Description

The bq2050 Lithium Ion Power
Gauge™ IC is intended for battery­pack or in-system installation to
maintain an accurate record of
available battery capacity. The IC
monitors a voltage drop across a
sense resistor connected in series
between the negative battery termi

­nal and ground to determine
charge and discharge activity of
the battery. Compensations for bat

­tery temperature and rate of charge
or discharge are applied to the
charge, discharge, and self-discharge
calculations to provide available ca

­pacity information across a wide
range of operating conditions. Bat

­tery capacity is automatically recali

­brated, or “learned,” in the course of
a discharge cycle from full to empty.

Nominal available capacity may be
directly indicated using a five­segment LED display. These seg­ments are used to graphically indi­cate available capacity. The bq2050

supports a simple single-line bidi

­rectional serial link to an external
processor (common ground). The
bq2050 outputs battery information
in response to external commands
over the serial link.

The bq2050 may operate directly
from one cell (V

BAT

> 3V). With the

REF output and an external transis

­tor, a simple, inexpensive regulator
can be built for systems with more
than one series cell.

Internal registers include available
capacity, temperature, scaled avail

­able energy, battery ID, battery
status, and programming pin set

­tings. To support subassembly test

­ing, the outputs may also be con

­trolled. The external processor may
also overwrite some of the bq2050
power gauge data registers.

LCOM LED common output

SEG

1

/PROG1LED segment 1/

program 1 input

SEG

2

/PROG2LED segment 2/

program 2 input

SEG

3

/PROG3LED segment 3/

program 3 input

SEG

4

/PROG4LED segment 4/

program 4 input

SEG

5

/PROG5LED segment 5/

program 5 input

PROG

6

Program 6 input

1

PN205001.eps

16-Pin Narrow SOIC

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

V

CC

REF

N/C

DQ

RBI

SB

DISP

SR

LCOM

SEG1/PROG

1

SEG2/PROG

2

SEG3/PROG

3

SEG4/PROG

4

SEG5/PROG

5

PROG

6

V

SS

REF Voltage reference output

N/C No connect

DQ Serial communications

input/output

RBI Register backup input

SB Battery sense input

DISP

Display control input

SR Sense resistor input

V

CC

3.0–6.5V

V

SS

System ground

Pin Connections Pin Names

bq2050

9/96 C

Lithium Ion Power Gauge™ IC

Pin Descriptions

LCOM

LED common output

Open-drain output switches V

CC

to source

current for the LEDs. The switch is off dur

­ing initialization to allow reading of the soft
pull-up or pull-down program resistors.
LCOM is also high impedance when the dis

­play is off.

SEG

1

–

SEG

5

LED display segment outputs (dual func

­tion with PROG

1

–PROG6)

Each output may activate an LED to sink
the current sourced from LCOM.

PROG

1

–

PROG

2

Programmed full count selection inputs
(dual function with SEG

1

–SEG2)

These three-level input pins define the pro

­grammed full count (PFC) thresholds de

­scribed in Table 2.

PROG

3

–

PROG

4

Power gauge rate selection inputs (dual
function with SEG

3

–SEG4)

These three-level input pins define the scale
factor described in Table 2.

PROG

5

Self-discharge rate selection (dual func­tion with SEG

5

)

This three-level input pin defines the
selfdischarge and battery compensation fac­tors as shown in Table 1.

PROG

6

Capacity initialization selection

This three-level pin defines the battery state
of charge at reset as shown in Table 1.

N/C

No connect

SR

Sense resistor input

The voltage drop (V

SR

) across the sense re

-

sistor R

S

is monitored and integrated over

time to interpret charge and discharge activ

-

ity. The SR input is tied between the nega

-

tive terminal of the battery and the sense re

-

sistor. V

SR<VSS

indicates discharge, and V

SR

>VSSindicates charge. The effective voltage
drop, V

SRO

, as seen by the bq2050 is VSR+

V

OS

.

DISP

Display control input

DISP

high disables the LED display. DISP
tied to VCCallows PROGXto connect directly
to V

CC

or VSSinstead of through a pull-up or

pull-down resistor. DISP

floating allows the
LED display to be active during charge.
DISP

low activates the display. See Table 1.

SB

Secondary battery input

This input monitors the battery cell voltage
potential through a high-impedance resis­tive divider network for end-of-discharge
voltage (EDV) thresholds, and battery re­moved.

RBI

Register backup input

This pin is used to provide backup potential to
the bq2050 registers during periods when
V

CC

≤ 3V. A storage capacitor or a battery

can be connected to RBI.

DQ

Serial I/O pin

This is an open-drain bidirectional pin.

REF

Voltage reference output for regulator

REF provides a voltage reference output for
an optional micro-regulator.

V

CC

Supply voltage input

V

SS

Ground

2

bq2050

Functional Description

General Operation

The bq2050 determines battery capacity by monitor

­ing the amount of current input to or removed from a
rechargeable battery. The bq2050 measures dis

­charge and charge currents, measures battery volt

­age, estimates self-discharge, monitors the battery
for low battery voltage thresholds, and compensates
for temperature and charge/discharge rates. The cur

­rent measurement is made by monitoring the voltage
across a small-value series sense resistor between the
negative battery terminal and ground. The estimate of
scaled available energy is made using the remaining
average battery voltage during the discharge cycle
and the remaining nominal available charge. The

scaled available energy measurement is corrected for
the environmental and operating conditions.

Figure 1 shows a typical battery pack application of the
bq2050 using the LED display capability as a charge­state indicator. The bq2050 is configured to display ca

­pacity in relative display mode. The relative display
mode uses the last measured discharge capacity of the
battery as the battery “full” reference. A push-button
display feature is available for momentarily enabling
the LED display.

The bq2050 monitors the charge and discharge currents
as a voltage across a sense resistor (see R

S

in Figure 1).
A filter between the negative battery terminal and the
SR pin may be required if the rate of change of the bat

-

tery current is too great.

3

bq2050

FG205001.eps

PROG

6

SEG5/PROG

5

SEG4/PROG

4

SEG3/PROG

3

SEG2/PROG

2

SEG1/PROG

1

SR

DISP

SB

V

CC

REF

bq2050

Power Gauge IC

LCOM

V

SS

RBI

DQ

V

CC

C1

0.1 F

Q1
ZVNL110A

R

1

R

S

RB

1

RB

2

Load

Charger

Indicates optional.

Directly connect to VCC across 1 cell (V

BAT

> 3V).

Otherwise, R1, C1, and Q1 are needed for regulation of > 1 cell.

Programming resistors (6 max.) and ESD-protection diodes are not shown.

R-C on SR may be required, application-specific.

A series Zener may be used to limit discharge current at low voltages
in desi

g

ns using 3 or more cells.

V

CC

C2

1M

PSTAT

Figure 1. Battery Pack Application Diagram—LED Display

Voltage Thresholds

In conjunction with monitoring VSRfor charge/discharge
currents, the bq2050 monitors the battery potential
through the SB pin. The voltage is determined through
a resistor-divider network per the following equation:

RB1
RB2

2N=−1

where N is the number of cells, RB1 is connected to the
positive battery terminal, and RB2 is connected to the
negative battery terminal. The single-cell battery volt

­age is monitored for the end-of-discharge voltage (EDV).
EDV threshold levels are used to determine when the
battery has reached an “empty” state.

Two EDV thresholds for the bq2050 are programmable
with the default values fixed at:

EDV1 (early warning) = 1.52V

EDVF (empty) = 1.47V

If V

SB

is below either of the two EDV thresholds, the as

­sociated flag is latched and remains latched, independ­ent of V

SB

, until the next valid charge. The VSBvalue is

also available over the serial port.

During discharge and charge, the bq2050 monitors V

SR

for various thresholds used to compensate the charge
and discharge rates. Refer to the count compensation
section for details. EDV monitoring is disabled if the
discharge rate is greater than 2C (typical) and resumes

1

2

second after the rate falls below 2C.

RBI Input

The RBI input pin is intended to be used with a storage ca

­pacitor or external supply to provide backup potential to the
internal bq2050 registers when V

CC

drops below 3.0V. V

CC

is output on RBI when VCCis above 3.0V. A diode is re

­quired to isolate the external supply.

Reset

The bq2050 can be reset either by removing VCCand
grounding the RBI pin for 15 seconds or by writing 0x80
to register 0x39.

Temperature

The bq2050 internally determines the temperature in
10°C steps centered from approximately -35°C to +85°C.
The temperature steps are used to adapt charge and dis

­charge rate compensations, self-discharge counting, and
available charge display translation. The temperature
range is available over the serial port in 10°C incre

­ments as shown in the following table:

Layout Considerations

The bq2050 measures the voltage differential between
the SR and V

SS

pins. VOS(the offset voltage at the SR
pin) is greatly affected by PC board layout. For optimal
results, the PC board layout should follow the strict rule
of a single-point ground return. Sharing high-current
ground with small signal ground causes undesirable
noise on the small signal nodes. Additionally:

n

The capacitors (C1 and C2) should be placed as
close as possible to the V

CC

and SB pins,

respectively, and their paths to V

SS

should be as
short as possible. A high-quality ceramic capacitor
of 0.1µf is recommended for V

CC

.

n

The sense resistor capacitor should be placed as close
as possible to the SR pin.

n

The sense resistor (RS) should be as close as possible to
the bq2050.

4

bq2050

TMP (hex) Temperature Range

0x < -30°C

1x -30°C to -20°C

2x -20°C to -10°C

3x -10°C to 0°C

4x 0°C to 10°C

5x 10°C to 20°C

6x 20°C to 30°C

7x 30°C to 40°C

8x 40°C to 50°C

9x 50°C to 60°C

Ax 60°C to 70°C

Bx 70°C to 80°C

Cx > 80°C

Gas Gauge Operation

The operational overview diagram in Figure 2 illustrates
the operation of the bq2050. The bq2050 accumulates a
measure of charge and discharge currents, as well as an
estimation of self-discharge. Charge and discharge cur

­rents are temperature and rate compensated, whereas
self-discharge is only temperature compensated.

The main counter, Nominal Available Capacity (NAC),
represents the available battery capacity at any given
time. Battery charging increments the NAC register,
while battery discharging and self-discharge decrement
the NAC register and increment the DCR (Discharge
Count Register).

The Discharge Count Register (DCR) is used to update
the Last Measured Discharge (LMD) register only if a
complete battery discharge from full to empty occurs
without any partial battery charges. Therefore, the
bq2050 adapts its capacity determination based on the
actual conditions of discharge.

The battery's initial capacity is equal to the Pro

­grammed Full Count (PFC) shown in Table 2. Until
LMD is updated, NAC counts up to but not beyond this
threshold during subsequent charges. This approach al

­lows the gas gauge to be charger-independent and com

­patible with any type of charge regime.

1. Last Measured Discharge (LMD) or learned

battery capacity:

LMD is the last measured discharge capacity of the
battery. On initialization (application of V

CC

or bat

-

tery replacement), LMD = PFC. During subsequent
discharges, the LMD is updated with the latest
measured capacity in the Discharge Count Register
(DCR) representing a discharge from full to below
EDV1. A qualified discharge is necessary for a capac

-

ity transfer from the DCR to the LMD register. The
LMD also serves as the 100% reference threshold
used by the relative display mode.

5

bq2050

FG205002.eps

Rate and

Temperature

Compensation

Temperature

Compensation

Charge
Current

Discharge

Current

Self-Discharge

Timer

Temperature

Translation

Nominal

Available

Charge

(NAC)

Last

Measured

Discharged

(LMD)

Discharge

Count

Register

(DCR)

<

Qualified

Transfer

+

Rate and

Temperature

Compensation

Rate and

Temperature

Compensation

Temperature Step,
Other Data

+

--

+

Inputs

Main Counters

and Capacity

Reference (LMD)

Outputs

Serial

Port

Compensated
Available Charge
LED Display, etc.

Figure 2. Operational Overview

2. Programmed Full Count (PFC) or initial bat

-

tery capacity:

The initial LMD and gas gauge rate values are pro

-

grammed by using PROG

1

–PROG4. The bq2050 is
configured for a given application by selecting a
PFC value from Table 2. The correct PFC may be
determined by multiplying the rated battery capac

-

ity in mAh by the sense resistor value:

Battery capacity (mAh)*sense resistor (Ω) =

PFC (mVh)

Selecting a PFC slightly less than the rated capac

­ity provides a conservative capacity reference until
the bq2050 “learns” a new capacity reference.

Example: Selecting a PFC Value

Given:

Sense resistor = 0.05

Ω

Number of cells = 2
Capacity = 1000mAh, Li-Ion battery, coke-anode
Current range = 50mA to 1A
Relative display mode
Serial port only
Self-discharge =

NAC

512

per day @ 25°C
Voltage drop over sense resistor = 2.5mV to 50mV
Nominal discharge voltage = 3.6V

Therefore:

1000mAh*0.05Ω= 50mVh

6

bq2050

PROG

x

Pro-

grammed

Full

Count

(PFC)

PROG

4

= L PROG4= Z

Units

1 2 PROG3 = H PROG3 = Z PROG3 = L PROG3 = H PROG3 = Z PROG3 = L

-- -

SCALE =

1/80

SCALE =

1/160

SCALE =

1/320

SCALE =

1/640

SCALE =

1/1280

SCALE =

1/2560

mVh/
count

H H 49152 614 307 154 76.8 38.4 19.2 mVh

H Z 45056 563 282 141 70.4 35.2 17.6 mVh

H L 40960 512 256 128 64.0 32.0 16.0 mVh

Z H 36864 461 230 115 57.6 28.8 14.4 mVh

Z Z 33792 422 211 106 53.0 26.4 13.2 mVh

Z L 30720 384 192 96.0 48.0 24.0 12.0 mVh

L H 27648 346 173 86.4 43.2 21.6 10.8 mVh

L Z 25600 320 160 80.0 40.0 20.0 10.0 mVh

L L 22528 282 141 70.4 35.2 17.6 8.8 mVh

VSR equivalent to 2

counts/sec. (nom.)

90 45 22.5 11.25 5.6 2.8 mV

Table 2. bq2050 Programmed Full Count mVh Selections

Pin

Connection

PROG5Compensation/

Self-Discharge

PROG

6

NAC on Reset

DISP

Display State

H Table 4/Disabled PFC LEDs disabled

Z Table 4/

NAC

512

0 LEDs on when charging

L Table 3/

NAC

512

0 LEDs on for 4 sec.

Note: PROG5and PROG6states are independent.

Table 1. bq2050 Programming

Select:

PFC = 30720 counts or 48mVh
PROG

1

= float

PROG

2

= low

PROG

3

= high

PROG

4

= float

PROG

5

= float

PROG

6

= float

The initial full battery capacity is 48mVh (960mAh)
until the bq2050 “learns” a new capacity with a
qualified discharge from full to EDV1.

3. Nominal Available Capacity (NAC):

NAC counts up during charge to a maximum value
of LMD and down during discharge and self-dis

­charge to 0. NAC is reset to 0 on initialization and on
the first valid charge following discharge to EDV1. To
prevent overstatement of charge during periods of
overcharge, NAC stops incrementing when NAC =
LMD.

4. Discharge Count Register (DCR):

The DCR counts up during discharge independent of
NAC and could continue increasing after NAC has
decremented to 0. Prior to NAC = 0 (empty battery),
both discharge and self-discharge increment the
DCR. After NAC = 0, only discharge increments the
DCR. The DCR resets to 0 when NAC = LMD. The
DCR does not roll over but stops counting when it
reaches FFFFh.

The DCR value becomes the new LMD value on the
first charge after a valid discharge to V

EDV1

if:

No valid charge initiations (charges greater than
256 NAC counts, where V

SRO>VSRQ

) occurred dur

­ing the period between NAC = LMD and EDV1 de

­tected.

The self-discharge count is not more than 4096
counts (8% to 18% of PFC, specific percentage
threshold determined by PFC).

The temperature is≥0°C when the EDV1 level is
reached during discharge.

The valid discharge flag (VDQ) indicates whether
the present discharge is valid for LMD update.

5. Scaled Available Energy (SAE):

SAE is useful in determining the available energy
within the battery, and may provide a more useful
capacity reference in battery chemistries with
sloped voltage profiles during discharge. SAE may
be converted to a mWh value using the following
formula:

E(mWh) =

(* *SAEH SAEL)256 +

24.)∗∗+

∗

SCALE (R R

RR

B1 B2

SB2

where RB1,RB2and RSare resistor values in ohms.
SCALE is the selected scale from Table 2. SAEH
and SAEL are digital values read via DQ.

6. Compensated Available Capacity (CAC)

CAC counts similar to NAC, but contains the avail

­able capacity compensated for discharge rate and
temperature.

Charge Counting

Charge activity is detected based on a positive voltage
on the V

SR

input. If charge activity is detected, the

bq2050 increments NAC at a rate proportional to V

SR

and,

if enabled, activates an LED display. Charge actions in

-

crement the NAC after compensation for temperature.

The bq2050 determines charge activity sustained at a
continuous rate equivalent to V

SRO>VSRQ

. A valid
charge equates to sustained charge activity greater
than 256 NAC counts. Once a valid charge is detected,
charge counting continues until V

SRO(VSR+VOS

) falls

below V

SRQ

.V

SRQ

is 210µV, and is described in the

Digital Magnitude Filter section.

Discharge Counting

Discharge activity is detected based on a negative voltage
on the V

SR

input. All discharge counts where V

SRO<VSRD

cause the NAC register to decrement and the DCR to
increment. V

SRD

is -200µV, and is described in the

Digital Magnitude Filter section.

Self-Discharge Estimation

The bq2050 continuously decrements NAC and increments
DCR for self-discharge based on time and temperature. The
self-discharge count rate is programmed to be a nominal

1

512

*

NAC per day or disabled. This is the rate for a bat

­tery whose temperature is between 20°–30°C. The NAC
register cannot be decremented below 0.

Count Compensations

Discharge Compensation

Corrections for the rate of discharge, temperature, and anode
type are made by adjusting an internal compensation factor.
This factor is based on the measured rate of discharge of the
battery. Tables 3A and 3B outline the correction factor typi

­cally used for graphite anode Li-Ion batteries, and Tables 4A
and 4B outline the factors typically used for coke anode
Li-Ion batteries. The compensation factor is applied to
CAC and is based on discharge rate and temperature.

7

bq2050

Charge Compensation

The bq2050 applies the following temperature compen

­sation to NAC during charge:

This compensation applies to both types of Li-Ion cells.

Self-Discharge Compensation

The self-discharge compensation is programmed for a
nominal rate of

1

512

*

NAC per day. This is the rate for a
battery within the 20°C–30°C temperature range. This
rate varies across 8 ranges from < 10°C to > 70°C, chang

­ing with each higher temperature (approximately 10°C).
See Table 5 below:

Self-discharge may be disabled by connecting PROG

5

=H.

Digital Magnitude Filter

The bq2050 has a digital filter to eliminate charge and dis

­charge counting below a set threshold. The bq2050 setting
is 200µV for V

SRD

and 210µV for V

SRQ

.

8

bq2050

Temperature Range

Typical Rate

PROG

5

= Z or L

< 10°C

NAC

2048

10–20°C

NAC

1024

20–30°C

NAC

512

30–40°C

NAC

256

40–50°C

NAC

128

50–60°C

NAC

64

60–70°C

NAC

32

> 70°C

NAC

16

Table 5. Self-Discharge Compensation

Approximate

Discharge Rate

Discharge

Compensation

Factor Efficiency

<

0.5C 1.00 100%

≥

0.5C 1.05 95%

Table 3A. Graphite Anode

Temperature

Temperature

Compensation

Factor Efficiency

≥

10°C 1.00 100%

0°C to 10°C 1.10 90%

-10°C to 0°C 1.35 74%

≤

-10°C 2.50 40%

Table 3B. Graphite Anode

Approximate

Discharge Rate

Discharge

Compensation

Factor Efficiency

<

0.5C 1.00 100%

≥

0.5C 1.15 86%

Table 4A. Coke Anode

Temperature

Temperature

Compensation

Factor Efficiency

≥

10°C 1.00 100%

0°C to 10°C 1.25 80%

-10°C to 0°C 2.00 50%

≤

-10°C 8.00 12%

Table 4B. Coke Anode

Temperature

Temperature

Compensation

Factor Efficiency

<

10°C 0.95 95%

≥

10°C 1.00 100%

Error Summary

Capacity Inaccurate

The LMD is susceptible to error on initialization or if no
updates occur. On initialization, the LMD value in

­cludes the error between the programmed full capacity
and the actual capacity. This error is present until a
valid discharge occurs and LMD is updated (see the
DCR description on page 7). The other cause of LMD er

­ror is battery wear-out. As the battery ages, the meas

­ured capacity must be adjusted to account for changes in
actual battery capacity.

A Capacity Inaccurate counter (CPI) is maintained and
incremented each time a valid charge occurs (qualified
by NAC; see the CPI register description) and is reset
whenever LMD is updated from the DCR. The counter
does not wrap around but stops counting at 255. The ca­pacity inaccurate flag (CI) is set if LMD has not been up­dated following 64 valid charges.

Current-Sensing Error

Table 5 illustrates the current-sensing error as a func

­tion of V

SRO

. A digital filter eliminates charge and dis

­charge counts to the NAC register when V

SRO

is between

V

SRQ

and V

SRD

.

Communicating With the bq2050

The bq2050 includes a simple single-pin (DQ plus re

­turn) serial data interface. A host processor uses the in

­terface to access various bq2050 registers. Battery char

­acteristics may be easily monitored by adding a single
contact to the battery pack. The open-drain DQ pin on
the bq2050 should be pulled up by the host system, or may
be left floating if the serial interface is not used.

The interface uses a command-based protocol, where the
host processor sends a command byte to the bq2050.
The command directs the bq2050 to either store the next
eight bits of data received to a register specified by the
command byte or output the eight bits of data specified
by the command byte.

The communication protocol is asynchronous return-to­one. Command and data bytes consist of a stream of

eight bits that have a maximum transmission rate of
333 bits/sec. The least-significant bit of a command or
data byte is transmitted first. The protocol is simple
enough that it can be implemented by most host proces

­sors using either polled or interrupt processing. Data
input from the bq2050 may be sampled using the pulse­width capture timers available on some microcontrol

­lers.

If a communication error occurs, e.g. t

CYCB

> 6ms, the
bq2050 should be sent a BREAK to reinitiate the serial
interface. A BREAK is detected when the DQ pin is
driven to a logic-low state for a time, t

B

or greater. The
DQ pin should then be returned to its normal ready­high logic state for a time, t

BR

. The bq2050 is now ready

to receive a command from the host processor.

The return-to-one data bit frame consists of three dis­tinct sections. The first section is used to start the
transmission by either the host or the bq2050 taking the
DQ pin to a logic-low state for a period, t

STRH,B

. The
next section is the actual data transmission, where the
data should be valid by a period, t

DSU

, after the negative
edge used to start communication. The data should be
held for a period, t

DV

, to allow the host or bq2050 to

sample the data bit.

The final section is used to stop the transmission by re

-

turning the DQ pin to a logic-high state by at least a pe

-

riod, t

SSU

, after the negative edge used to start commu

­nication. The final logic-high state should be held until
a period, t

SV

, to allow time to ensure that the bit trans

­mission was stopped properly. The timings for data and
break communication are given in the serial communi

­cation timing specification and illustration sections.

Communication with the bq2050 is always performed with
the least-significant bit being transmitted first. Figure 3
shows an example of a communication sequence to read
the bq2050 NAC register.

9

bq2050

Symbol Parameter Typical Maximum Units Notes

INL

Integrated non-linearity
error

±

2

±

4

%

Add 0.1% per °C above or below 25°C
and 1% per volt above or below 4.25V.

INR

Integrated non­repeatability error

±

1

±

2

%

Measurement repeatability given
similar operating conditions.

Table 6. bq2050 Current-Sensing Errors

bq2050 Registers

The bq2050 command and status registers are listed in
Table 7 and described below.

Command Register (CMDR)

The write-only CMDR register is accessed when eight
valid command bits have been received by the bq2050.
The CMDR register contains two fields:

n

W/R bit

n

Command address

The W/R

bit of the command register is used to select whether

the received command is for a read or a write function.

The W/R

values are:

CMDR Bits

7654 3 2 1 0

W/R

- -- - - - -

Where W/R is:

0 The bq2050 outputs the requested register con

-

tents specified by the address portion of CMDR.

1 The following eight bits should be written

to the register specified by the address por

-

tion of CMDR.

The lower seven-bit field of CMDR contains the address
portion of the register to be accessed. Attempts to write
to invalid addresses are ignored.

Primary Status Flags Register (FLGS1)

The read-only FLGS1 register (address=01h) contains
the primary bq2050 flags.

The charge status flag (CHGS) is asserted when a
valid charge rate is detected. Charge rate is deemed
valid when V

SRO>VSRQ

.AV

SRO

of less than V

SRQ

or

discharge activity clears CHGS.

The CHGS values are:

Where CHGS is:

0 Either discharge activity detected or V

SRO

<

V

SRQ

1V

SRO>VSRQ

The battery replaced flag (BRP) is asserted whenever
the bq2050 is reset either by application of V

CC

or by a
serial port command. BRP is reset when either a valid
charge action increments NAC to be equal to LMD, or a
valid charge action is detected after the EDV1 flag is as

-

serted. BRP = 1 signifies that the device has been reset.

The BRP values are:

Where BRP is:

0 Battery is charged until NAC = LMD or dis

-

charged until the EDV1 flag is asserted

1 bq2050 is reset

10

FLGS1 Bits

76543 2 1 0

CHGS - -- - - - -

CMDR Bits

765 4 3 2 1 0

- AD6 AD5 AD4 AD3 AD2 AD1

AD0

(LSB)

TD205002.eps

DQ

Break 0 0 0 0 0 0 1 0 1 0 0 1

Written by Host to bq2050

CMDR = 03h

Received by Host to bq2050

NAC = 65h

LSB MSB LSB MSB

1110

Figure 3. Typical Communication With the bq2050

bq2050

FLGS1 Bits

76543 2 1 0

- BRP - - - - - -

11

Symbol

Register Name

Loc.

(hex)

Read/

Write

Control Field

7(MSB) 6 5 4 3 2 1 0(LSB)

CMDR Command register 00h Write W/R

AD6 AD5 AD4 AD3 AD2 AD1 AD0

FLGS1

Primary status flags
register

01h Read CHGS BRP n/u CI VDQ n/u EDV1 EDVF

TMP Temperature register 02h Read TMP3 TMP2 TMP1 TMP0 GG3 GG2 GG1 GG0

NACH

Nominal available ca

-

pacity high byte reg

-

ister

03h R/W NACH7 NACH6 NACH5 NACH4 NACH3 NACH2 NACH1 NACH0

NACL

Nominal available
capacity low byte
register

17h Read NACL7 NACL6 NACL5 NACL4 NACL3 NACL2 NACL1 NACL0

BATID

Battery
identification
register

04h R/W BATID7 BATID6 BATID5 BATID4 BATID3 BATID2 BATID1 BATID0

LMD

Last measured dis

-

charge register

05h R/W LMD7 LMD6 LMD5 LMD4 LMD3 LMD2 LMD1 LMD0

FLGS2

Secondary status
flags register

06h Read n/u DR2 DR1 DR0 n/u n/u n/u OVLD

PPD

Program pin pull­down register

07h Read n/u n/u PPD6 PPD5 PPD4 PPD3 PPD2 PPD1

PPU

Program pin pull-up
register

08h Read n/u n/u PPU6 PPU5 PPU4 PPU3 PPU2 PPU1

CPI

Capacity
inaccurate count reg­ister

09h Read CPI7 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 CPI0

VSB

Battery voltage
register

0Bh Read VSB7 VSB6 VSB5 VSB4 VSB3 VSB2 VSB1 VSB0

VTS

End-of-discharge thresh

-

old select register

0Ch R/W VTS7 VTS6 VTS5 VTS4 VTS3 VTS2 VTS1 VTS0

CACH

Compensated avail

­able capacity high byte
register

0Dh Read CACH7 CACH6 CACH5 CACH4 CACH3 CACH2 CACH1 CACH0

CACL

Compensated
available capacity low
byte register

0Eh Read CACL7 CACL6 CACL5 CACL4 CACL3 CACL2 CACL1 CACL0

SAEH

Scaled available

energy high byte reg

-

ister

0Fh Read SAEH7 SAEH6 SAEH5 SAEH4 SAEH3 SAEH2 SAEH1 SAEH0

SAEL

Scaled available

energy low byte regis

-

ter

10h Read SAEL7 SAEL6 SAEL5 SAEL4 SAEL3 SAEL2 SAEL1 SAEL0

RST Reset register 39h Write RST 0 0 0 0 0 0 0

Note: n/u = not used

Table 7. bq2050 Command and Status Registers

bq2050

The capacity inaccurate flag (CI) is used to warn the
user that the battery has been charged a substantial
number of times since LMD has been updated. The CI
flag is asserted on the 64th charge after the last LMD
update or when the bq2050 is reset. The flag is cleared
after an LMD update.

The CI values are:

Where CI is:

0 When LMD is updated with a valid full dis

-

charge

1 After the 64th valid charge action with no

LMD updates or the bq2050 is reset

The valid discharge flag (VDQ) is asserted when the
bq2050 is discharged from NAC=LMD. The flag remains
set until either LMD is updated or one of three actions
that can clear VDQ occurs:

n

The self-discharge count register (SDCR) has
exceeded the maximum acceptable value (4096
counts) for an LMD update.

n

A valid charge action sustained at V

SRO

> V

SRQ

for at

least 256 NAC counts.

n

The EDV1 flag was set at a temperature below 0°C

The VDQ values are:

Where VDQ is:

0 SDCR≥4096, subsequent valid charge ac

­tion detected, or EDV1 is asserted with the
temperature less than 0°C

1 On first discharge after NAC = LMD

The first end-of-discharge warning flag (EDV1)
warns the user that the battery is almost empty. The
first segment pin, SEG

1

, is modulated at a 4Hz rate if
the display is enabled once EDV1 is asserted, which
should warn the user that loss of battery power is immi

­nent. The EDV1 flag is latched until a valid charge has
been detected. The EDV1 threshold is externally con

­trolled via the VTS register (see Voltage Threshold Reg

­ister on this page).

The EDV1 values are:

Where EDV1 is:

0 Valid charge action detected, V

SB

≥

V

TS

1VSB<VTSproviding that the discharge rate is

<2C

The final end-of-discharge warning flag (EDVF) flag
is used to warn that battery power is at a failure condi

­tion. All segment drivers are turned off. The EDVF flag
is latched until a valid charge has been detected. The
EDVF threshold is set 50mV below the EDV1 threshold.

The EDVF values are:

Where EDVF is:

0 Valid charge action detected, V

SB

≥

(V

TS

-

50mV)

1V

SB

< (VTS- 50mV) providing the discharge

rate is < 2C

Temperature Register (TMP)

The read-only TMP register (address=02h) contains the
battery temperature.

The bq2050 contains an internal temperature sensor.
The temperature is used to set charge and discharge ef

­ficiency factors as well as to adjust the self-discharge co

­efficient. The temperature register contents may be
translated as shown in Table 7.

The bq2050 calculates the gas gauge bits, GG3-GG0 as a
function of CACH and LMD. The results of the calculation
give available capacity in

1

16

increments from 0 to

15

16

.

12

bq2050

FLGS1 Bits

76543 2 1 0

---CI- - - -

FLGS1 Bits

76543 2 1 0

- - - - VDQ - - -

FLGS1 Bits

7654 3 2 1 0

- - - - - - EDV1 -

FLGS1 Bits

7654 3 2 1 0

---- - - -EDVF

TMP Temperature Bits

76543210

TMP4 TMP3 TMP2 TMP1 - - - -

Nominal Available Charge Registers
(NACH/NACL)

The read/write NACH high-byte register (address=03h) and
the read-only NACL low-byte register (address=17h) are
the main gas gauging register for the bq2050. The NAC
registers are incremented during charge actions and decre

­mented during discharge and self-discharge actions. The
correction factors for charge/discharge efficiency are applied
automatically to NAC. NACH and NACL are set to 0 dur

­ing a bq2050 reset.

Writing to the NAC registers affects the available charge

counts and, therefore, affects the bq2050 gas gauge opera

­tion. Do not write the NAC registers to a value greater than
LMD.

Battery Identification Register (BATID)

The read/write BATID register (address=04h) is avail

­able for use by the system to determine the type of bat

­tery pack. The BATID contents are retained as long as
V

CC

is greater than 2V. The contents of BATID have no

effect on the operation of the bq2050. There is no de

­fault setting for this register.

Last Measured Discharge Register (LMD)

LMD is a read/write register (address=05h) that the
bq2050 uses as a measured full reference. The bq2050
adjusts LMD based on the measured discharge capacity
of the battery from full to empty. In this way the bq2050
updates the capacity of the battery. LMD is set to PFC
during a bq2050 reset.

Secondary Status Flags Register (FLGS2)

The read-only FLGS2 register (address=06h) contains
the secondary bq2050 flags.

The discharge rate flags, DR2–0, are bits 6–4.

They are used to determine the current discharge re­gime as follows:

The overload flag (OVLD) is asserted when a discharge
rate in excess of 2C is detected. OVLD remains asserted
as long as the condition persists and is cleared 0.5 sec

-

onds after the rate drops below 2C. The overload condi

-

tion is used to stop sampling of the battery terminal char

-

acteristics for end-of-discharge determination.

Program Pin Pull-Down Register (PPD)

The read-only PPD register (address=07h) contains some
of the programming pin information for the bq2050. The
segment drivers, SEG

1–6

, have a corresponding PPD regis

-

ter location, PPD

1–6

. A given location is set if a pull-down
resistor has been detected on its corresponding segment
driver. For example, if SEG

1

and SEG4have pull-down

resistors, the contents of PPD are xx001001.

Program Pin Pull-Up Register (PPU)

The read-only PPU register (address=08h) contains the rest
of the programming pin information for the bq2050. The
segment drivers, SEG

1–6

, have a corresponding PPU regis

-

ter location, PPU

1–6

. A given location is set if a pull-up re

-

sistor has been detected on its corresponding segment

13

bq2050

TMP3 TMP2 TMP1 TMP0 Temperature

0000 T < -30°C

0001-30°C < T < -20°C

0010-20°C < T < -10°C

0011-10°C < T < 0°C

01000°C < T < 10°C

010110°C < T < 20°C

011020°C < T < 30°C

011130°C < T < 40°C

100040°C < T < 50°C

100150°C < T < 60°C

101060°C < T < 70°C

101170°C < T < 80°C

1100 T > 80°C

Table 7. Temperature Register

FLGS2 Bits

7 6 5 4 3210

- DR2 DR1 DR0 - - -

DR2 DR1 DR0 Discharge Rate

0 0 0 DRATE<0.5C
0 0 1 0.5C≤DRATE<2C
0 1 0 DRATE≥2C (OVLD = 1)

FLGS2 Bits

76543 2 1 0

- - - - - - - OVLD

TMPGG Gas Gauge Bits

76 5 4 321 0

- - - - GG3 GG2 GG1 GG0

driver. For example, if SEG3and SEG6have pull-up resis

-

tors, the contents of PPU are xx100100.

Capacity Inaccurate Count Register (CPI)

The read-only CPI register (address=09h) is used to in

­dicate the number of times a battery has been charged
without an LMD update. Because the capacity of a re

­chargeable battery varies with age and operating condi

­tions, the bq2050 adapts to the changing capacity over
time. A complete discharge from full (NAC=LMD) to
empty (EDV1=1) is required to perform an LMD update
assuming there have been no intervening valid charges,
the temperature is greater than or equal to 0°C, and the
self-discharge counter is less than 4096 counts.

The CPI register is incremented every time a valid
charge is detected. When NAC > 0.94*LMD, however,
the CPI register increments on the first valid charge;
CPI does not increment again for a valid charge until
NAC < 0.94*LMC. This prevents continuous trickle
charging from incrementing CPI if self-discharge decre­ments NAC. The CPI register increments to 255 with­out rolling over. When the contents of CPI are incre­mented to 64, the capacity inaccurate flag, CI, is as­serted in the FLGS1 register. The CPI register is reset
whenever an update of the LMD register is performed,
and the CI flag is also cleared.

Battery Voltage Register (VSB)

The read-only battery voltage register is used to read the
single-cell battery voltage on the SB pin. The VSB regis

­ter (address = 0Bh) is updated approximately once per sec

­ond with the present value of the battery voltage. V

SB

=

2.4V*(VSB/256).

Voltage Threshold Register (VTS)

The end-of-discharge threshold voltages (EDV1 and
EDVF) can be set using the VTS register (address =
0Ch). The read/write VTS register sets the EDV1 trip
point. EDVF is set 50mV below EDV1. The default
value in the VTS register is A2h, representing EDV1 =

1.52V and EDVF = 1.47V. EDV1 = 2.4V*(VTS/256).

Compensated Available Charge Registers
(CACH/CACL)

The read-only CACH high-byte register (address = 0Dh)
and the read-only CACL low-byte register (address =
0Eh) represent the available charge compensated for
discharge rate and temperature. CACH and CACL use
piece-wise corrections as outlined in Tables 3A, 3B, 4A,
and 4B, and will vary as conditions change. The NAC
and LMD registers are not affected by the discharge
rate and temperature.

Scaled Available Energy Registers
(SAEH/SAEL)

The read-only SAEH high-byte register (address = 0Fh)
and the read only SAEL low-byte register (address =
10h) are used to scale battery voltage and CAC to a
value which can be translated to watt-hours remaining
under the present conditions. SAEL and SAEH may be
converted to mWh using the formula on page 7.

Reset Register (RST)

The reset register (address = 39h) enables a software­controlled reset of the device. By writing the RST regis­ter contents from 00h to 80h, a bq2050 reset is per­formed. Setting any bit other than the most-significant

bit of the RST register is not allowed and results in im

-

proper operation of the bq2050.

Resetting the bq2050 sets the following:

n

LMD = PFC

n

CPI, VDQ, NACH, and NACL = 0

n

CI and BRP = 1

Note: Self-discharge is disabled when PROG

5

=H.

Display

The bq2050 can directly display capacity information
using low-power LEDs. If LEDs are used, the program
pins should be resistively tied to V

CC

or VSSfor a pro

-

gram high or program low, respectively.

The bq2050 displays the battery charge state in relative
mode. In relative mode, the battery charge is represented
as a percentage of the LMD. Each LED segment repre

-

sents 20% of the LMD.

The capacity display is also adjusted for the present bat

­tery temperature. The temperature adjustment reflects
the available capacity at a given temperature but does

14

bq2050

VTS Register Bits

76543210

VTS7 VTS6 VTS5 VTS4 VTS3 VTS2 VTS1 VTS0

VSB Register Bits

76543210

VSB7 VSB6 VSB5 VSB4 VSB3 VSB2 VSB1 VSB0

PPD/PPU Bits

76543210

- - PPU

6

PPU5PPU4PPU3PPU2PPU

1

- - PPD6PPD5PPD4PPD3PPD2PPD

1

not affect the NAC register. The temperature adjust

-

ments are detailed in the CACH and CACL register de

-

scriptions.

When DISP

is tied to VCC, the SEG

1–5

outputs are inac

-

tive. When DISP

is left floating, the display becomes ac

­tive whenever the bq2050 detects a charge in progress
V

SRO>VSRQ

. When pulled low, the segment outputs be

­come active for a period of four seconds,±0.5 seconds.

The segment outputs are modulated as two banks, with
segments 1, 3, and 5 alternating with segments 2 and 4.
The segment outputs are modulated at approximately
100Hz with each segment bank active for 30% of the pe

­riod.

SEG

1

blinks at a 4Hz rate whenever VSBhas been de

-

tected to be below V

EDV1

(EDV1 = 1), indicating a low-

battery condition. V

SB

below V

EDVF

(EDVF = 1) disables

the display output.

Microregulator

The bq2050 can operate directly from one cell. A micro

­power source for the bq2050 can be inexpensively built
using the FET and an external resistor to accommodate
a greater number of cells; see Figure 1.

15

bq2050

16

bq2050

DC Voltage Thresholds (T

A

= T

OPR

; V = 3.0 to 6.5V)

Symbol Parameter Minimum Typical Maximum Unit Notes

V

EDVF

Final empty warning 1.44 1.47 1.50 V SB

V

EDV1

First empty warning 1.49 1.52 1.55 V SB

V

SRO

SR sense range -300 - 2000 mV SR, VSR+ V

OS

V

SRQ

Valid charge 210 - -

µ

VVSR+ VOS(see note)

V

SRD

Valid discharge - - -200

µ

VVSR+ VOS(see note)

V

MCV

Maximum single-cell voltage 2.20 2.25 2.30 V SB

Note: VOSis affected by PC board layout. Proper layout guidelines should be followed for optimal performance.

See “Layout Considerations.”

Absolute Maximum Ratings

Symbol Parameter Minimum Maximum Unit Notes

V

CC

Relative to V

SS

-0.3 7.0 V

All other pins Relative to V

SS

-0.3 7.0 V

REF Relative to V

SS

-0.3 8.5 V Current limited by R1 (see Figure 1)

V

SR

Relative to V

SS

-0.3 7.0 V

Minimum 100Ωseries resistor should
be used to protect SR in case of a
shorted battery (see the bq2050 appli

-

cation note for details).

T

OPR

Operating tempera

-

ture

0 70 °C Commercial

-40 85 °C Industrial

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation

should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to con

-

ditions beyond the operational limits for extended periods of time may affect device reliability.

17

bq2050

DC Electrical Characteristics (T

A

= T

OPR

)

Symbol Parameter Minimum Typical Maximum Unit Notes

V

CC

Supply voltage 3.0 4.25 6.5 V

V

CC

excursion from < 2.0V to

≥

3.0V initializes the unit.

V

OS

Offset referred to V

SR

-

±50 ±150 µV

DISP

= V

CC

V

REF

Reference at 25°C 5.7 6.0 6.3 V I

REF

= 5µA

Reference at -40°C to +85°C 4.5 - 7.5 V I

REF

= 5µA

R

REF

Reference input impedance 2.0 5.0 - MΩV

REF

= 3V

I

CC

Normal operation

- 90 135

µ

AV

CC

= 3.0V, DQ = 0

- 120 180

µ

AV

CC

= 4.25V, DQ = 0

- 170 250

µ

AV

CC

= 6.5V, DQ = 0

V

SB

Battery input 0 - V

CC

V

R

SBmax

SB input impedance 10 - - MΩ0 < VSB< V

CC

I

DISP

DISP input leakage - - 5

µ

AV

DISP

= V

SS

I

LCOM

LCOM input leakage -0.2 - 0.2

µ

A DISP = V

CC

I

RBI

RBI data retention current - - 100 nA V

RBI

> VCC< 3V

R

DQ

Internal pulldown 500 - - K

Ω

V

SR

Sense resistor input -0.3 - 2.0 V

V

SR<VSS

= discharge;

V

SR

> VSS= charge

R

SR

SR input impedance 10 - - MΩ-200mV < VSR< V

CC

V

IH

Logic input high VCC- 0.2 - - V PROG1–PROG

6

V

IL

Logic input low - - VSS+ 0.2 V PROG1–PROG

6

V

IZ

Logic input Z float - float V PROG1–PROG

6

V

OLSL

SEGXoutput low, low V

CC

- 0.1 - V

V

CC

= 3V, I

OLS

≤

1.75mA

SEG

1

–SEG

5

V

OLSH

SEGXoutput low, high V

CC

- 0.4 - V

V

CC

= 6.5V, I

OLS

≤

11.0mA

SEG

1

–SEG

5

V

OHLCL

LCOM output high, low V

CC

VCC- 0.3 - - V VCC= 3V, I

OHLCOM

= -5.25mA

V

OHLCH

LCOM output high, high V

CC

VCC- 0.6 - - V VCC= 6.5V, I

OHLCOM

= -33.0mA

I

IH

PROG

1-6

input high current - 1.2 -

µ

AV

PROG

= VCC/2

I

IL

PROG

1-6

input low current - 1.2 -

µ

AV

PROG

= VCC/2

I

OHLCOM

LCOM source current -33 - - mA At V

OHLCH

= VCC- 0.6V

I

OLS

SEG

1-5

sink current - - 11.0 mA At V

OLSH

= 0.4V

I

OL

Open-drain sink current - - 5.0 mA

At V

OL

= VSS+ 0.3V

DQ

V

OL

Open-drain output low - - 0.5 V I

OL

≤

5mA, DQ

V

IHDQ

DQ input high 2.5 - - V DQ

V

ILDQ

DQ input low - - 0.8 V DQ

R

PROG

Soft pull-up or pull-down resis

-

tor value (for programming)

- - 200

K

Ω

PROG

1

–PROG

6

R

FLOAT

Float state external impedance - 5 - MΩPROG1–PROG

6

Note: All voltages relative to VSS.

18

bq2050

Serial Communication Timing Specification (T

A

=T

OPR

)

Symbol Parameter Minimum Typical Maximum Unit Notes

t

CYCH

Cycle time, host to bq2050 3 - - ms See note

t

CYCB

Cycle time, bq2050 to host 3 - 6 ms

t

STRH

Start hold, host to bq2050 5 - - ns

t

STRB

Start hold, bq2050 to host 500 - -

µ

s

t

DSU

Data setup - - 750

µ

s

t

DH

Data hold 750 - -

µ

s

t

DV

Data valid 1.50 - - ms

t

SSU

Stop setup - - 2.25 ms

t

SH

Stop hold 700 - -

µ

s

t

SV

Stop valid 2.95 - - ms

t

B

Break 3 - - ms

t

BR

Break recovery 1 - - ms

Notes: The open-drain DQ pin should be pulled to at least VCCby the host system for proper DQ operation.

DQ may be left floating if the serial interface is not used.

TD201002.eps

DQ

(R/W "1")

t

STRH

t

STRB

t

DSU

t

DH

t

DV

t

SV

t

SSU

t

SH

t

CYCH, tCYCB, tB

t

BR

DQ

(R/W "0")

DQ

(BREAK)

Serial Communication Timing

19

bq2050

16-Pin SOIC Narrow (SN)

A

A1

.004

C

B

e

D

E

H

L

16-Pin SN(0.150" SOIC

)

Dimension

Inches Millimeters

Min. Max. Min. Max.

A 0.060 0.070 1.52 1.78

A1 0.004 0.010 0.10 0.25

B 0.013 0.020 0.33 0.51

C 0.007 0.010 0.18 0.25

D 0.385 0.400 9.78 10.16

E 0.150 0.160 3.81 4.06

e 0.045 0.055 1.14 1.40

H 0.225 0.245 5.72 6.22

L 0.015 0.035 0.38 0.89

Data Sheet Revision History

Change No. Page No. Description Nature of Change

1 4 Changed reset procedure Was: Reset by issuing command over serial port

Is: Reset by removing V

CC

and grounding RBI for

15 s.
1 11, 14 Deleted reset register
2 16 Changed values V

EDVF

: Min. was 1.45; Max. was 1.49

Min. now is 1.44; Max. now is 1.50

V

EDV1

: Min. was 1.50; Min. now is 1.49

2 17 Changed values V

CC

: Min. was 2.5; Min. now is 3.0
2 4, 11, 13, 14 Reinserted reset register
2 9 Maximum offset V

OS

: Max. was 150

Max. now is 180

Notes: Change 1 = June 1995 B changes from Dec. 1994.

Change 2 = Sept. 1996 C changes from June 1995 B.

20

bq2050

Ordering Information

bq2050

Package Option:

SN = 16-pin narrow SOIC

Device:

bq2040 Gas Gauge IC With SMB Interface

Temperature Range:

blank = Commercial (-20 to +70°C)
N = Industrial (-40 to +85°C)*

* Contact factory for availability.

17919 Waterview Parkway

Dallas, Texas 75252

Fax: [phone]

Tel: [phone]

www.benchmarq.com or www.unitrode.com

Copyright © 1996, Unitrode Corporation All rights reserved. No part of this data sheet may be reproduced in any
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ucts without notice.

Unitrode assumes no responsibility for use of any products or circuitry described within. No license for use of intel

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lectual property (patents, copyrights, or other rights) owned by Unitrode or other parties is granted or implied.

Unitrode does not authorize the use of its components in life-support systems where failure or malfunction may
cause injury to the user. If Unitrode components are used in life-support systems, the user assumes all responsibili

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ties and indemnifies Unitrode from all liability or damages.

Benchmarq is a registered trademark of Unitrode Corporation. Printed in U.S.A.

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