Texas Instruments EV2014X, EV2014, BQ2014SN-D120TR, BQ2014SN-D120 Datasheet

1

Features

➤

Conservative and repeatable
measurement of available charge
in rechargeable batteries

➤

Charge control output operates an
external charge controller such as
the bq2004 Fast Charge IC

➤

Designed for battery pack inte

-

gration

-

120µA typical standby current

➤

Display capacity via single-wire
serial communication port or di

-

rect drive of LEDs

➤

Measurements compensated for
current and temperature

➤ Self-discharge compensation using

internal temperature sensor

➤ User-selectable end-of-discharge

threshold

➤ Battery voltage, nominal avail-

able charge, temperature, etc.
available over serial port

➤

16-pin narrow SOIC

General Description

The bq2014 Gas Gauge IC is in

­tended for battery-pack or in-system
installation to maintain an accurate
record of available battery charge.
The IC monitors the voltage drop
across a sense resistor connected in
series between the negative battery
terminal and ground to determine
charge and discharge activity of the
battery.

Self-discharge of NiMH and NiCd
batteries is estimated based on an
internal timer and temperature sen

­sor. Compensations for battery tem

­perature and rate of charge or dis

­charge are applied to the charge, dis

­charge, and self-discharge calcula­tions to provide available charge in­formation across a wide range of op­erating conditions. Battery capacity
is automatically recalibrated, or
“learned,” in the course of a dis­charge cycle from full to empty.

The bq2014 includes a charge con­trol output that controls an external
Fast Charge IC such as the bq2004.

Nominal Available Charge (NAC)
may be directly indicated using a
five-segment LED display.

The bq2014 supports a simple single­line bidirectional serial link to an ex

­ternal processor (with a common
ground). The bq2014 outputs battery
information in response to external
commands over the serial link.

Internal registers include available
charge, temperature, capacity, bat

­tery voltage, battery ID, battery
status, and programming pin set

­tings. To support subassembly test

­ing, the outputs may also be con

­trolled. The external processor may
also overwrite some of the bq2014
gas gauge data registers.

The bq2014 may operate directly
from three or four cells. With the
REF output and an external transis­tor, a simple, inexpensive regulator
can be built to provide V

CC

across a

greater number of cells.

LCOM LED common output

SEG

1

/PROG1LED segment 1/

program 1 input

SEG

2

/PROG2LED segment 2/

program 2 input

SEG

3

/PROG3LED segment 3/

program 3 input

SEG

4

/PROG4LED segment 4/

program 4 input

SEG

5

/PROG5LED segment 5/

program 5 input

DONE Fast charge complete

1

PN201401.eps

16-Pin Narrow SOIC

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

LCOM

SEG1/PROG

1

SEG2/PROG

2

SEG3/PROG

3

SEG4/PROG

4

SEG5/PROG

5

DONE

V

SS

V

CC

REF

CHG

DQ

EMPTY

SB

DISP

SR

REF Voltage reference output

CHG Charge control output

DQ Serial communications

input/output

EMPTY Empty battery indicator

output

SB Battery sense input

DISP

Display control input

SR Sense resistor input

V

CC

3.0–6.5V

V

SS

System ground

12/95 C

Pin Connections Pin Names

bq2014

Gas Gauge IC with External Charge Control

Pin Descriptions

LCOM

LED common output

Open-drain output switches V

CC

to source

current for the LEDs. The switch is off dur

­ing initialization to allow reading of the soft
pull-up or pull-down programming resistors.
LCOM is also in a high impedance state
when the display is off.

SEG

1

–

SEG

5

LED display segment outputs (dual func

­tion with PROG

1

—PROG5)

Each output may activate an LED to sink
the current sourced from LCOM.

PROG

1

–

PROG

5

Programmed full count selection imputs
(dual function with SEG

1

—SEG5)

These three-level input pins define the pro

-

grammed full count (PFC) thresholds de

-

scribed in Table 2.

PROG

3

–

PROG

4

Gas gauge rate selection inputs (dual
function with SEG

3

—SEG4)

These three-level input pins define the pro­grammed full count (PFC) thresholds de­scribed in Table 2.

PROG

5

Self-discharge rate selection (dual func­tion with SEG

5

)

This three-level input pin defines the self­discharge compensation rate shown in Ta­ble 1.

CHG

Charge control output

This open-drain output becomes active high
when charging is allowed.

DONE

Fast charge complete

This input is used to communicate the
status of an external charge controller such
as the bq2004 Fast Charge IC. Note: This
pin must be pulled down to V

SS

using a

200KΩ resistor.

SR

Sense resistor input

The voltage drop (V

SR

) across the sense re

-

sistor R

S

is monitored and integrated over

time to interpret charge and discharge activ

­ity. The SR input is tied to the high side of
the sense resistor. V

SR<VSS

indicates dis

­charge, and V

SR>VSS

indicates charge. The

effective voltage drop V

SRO

, as seen by the

bq2014, is V

SR+VOS

(see Table 5).

DISP

Display control input

DISP

high disables the LED display. DISP

tied to VCCallows PROGXto connect di

­rectly to V

CC

or VSSinstead of through a

pull-up or pull-down reistor. DISP

floating
allows the LED display to be active during
a valid charge or during discharge if the
NAC register is updated at a rate equiva

-

lent to V

SRO

≤ -4mV. DISP low activates

the display. See Table 1.

SB

Secondary battery input

This input monitors the single-cell voltage
potential through a high-impedance resis­tive divider network for the end-of-discharge
voltage (EDV) thresholds,maximum charge
voltage (MCV), and battery removed.

EMPTY

Battery empty output

This open-drain output becomes high­impedance on detection of a valid final end­of-discharge voltage (V

EDVF

) and is low fol

-

lowing the next application of a valid charge.

DQ

Serial I/O pin

This is an open-drain bidirectional pin.

REF

Voltage reference output for regulator

REF provides a voltage reference output for
an optional micro-regulator.

V

CC

Supply voltage input

V

SS

Ground

2

bq2014

Functional Description

General Operation

The bq2014 determines battery capacity by monitoring
the amount of charge input to or removed from a re

­chargeable battery. The bq2014 measures discharge and
charge currents, estimates self-discharge, monitors the
battery for low-battery voltage thresholds, and compen

­sates for temperature and charge/discharge rates. The
charge measurement is made by monitoring the voltage
across a small-value series sense resistor between the
battery’s negative terminal and ground. The available
battery charge is determined by monitoring this voltage
over time and correcting the measurement for the envi

­ronmental and operating conditions.

Figure 1 shows a typical battery pack application of the
bq2014 using the LED display capability as a charge­state indicator. The bq2014 is configured to display ca

­pacity in a relative display mode. The relative display
mode uses the last measured discharge capacity of the
battery as the battery “full” reference. The LED seg

­ments output a percentage of the available charge based
on NAC and LMD. A push-button display feature is
available for momentarily enabling the LED display.

The bq2014 monitors the charge and discharge currents
as a voltage across a sense resistor (see R

S

in Figure 1).
A filter between the negative battery terminal and the
SR pin is required.

3

bq2014

Figure 1. Battery Pack Application Diagram—LED Display,

Voltage Thresholds

In conjunction with monitoring VSRfor charge/discharge
currents, the bq2014 monitors the single-cell battery po

-

tential through the SB pin. The single-cell voltage po

­tential is determined through a resistor/divider network
per the following equation:

R
R

N

2
3

1=−

where N is the number of cells, R2 is connected to the
positive battery terminal, and R3 is connected to the
negative battery terminal. The single-cell battery volt

­age is monitored for the end-of-discharge voltage (EDV)
and for maximum cell voltage (MCV). EDV threshold
levels are used to determine when the battery has
reached an “empty” state, and the MCV threshold is used
for fault detection during charging.

Two EDV thresholds for the bq2014 are programmable
with the default values fixed at:

EDV1 (early warning) = 1.05V

EDVF (empty) = 0.95V

If V

SB

is below either of the two EDV thresholds, the as­sociated flag is latched and remains latched, independ­ent of V

SB

, until the next valid charge (as defined in the

section entitled “Gas Gauge Operation”). The V

SB

value

is also available over the serial port.

During discharge and charge, the bq2014 monitors V

SR

for various thresholds. These thresholds are used to
compensate the charge and discharge rates. Refer to the
count compensation section for details. EDV monitoring
is disabled if V

SR

≤ -250mV typical and resumes ½ sec

-

ond after V

SR

> -250mV.

EMPTY Output

The EMPTY output switches to high impedance when
V

SB<VEDF

and remains latched until a valid charge oc

-

curs.

Reset

The bq2014 recognizes a valid battery whenever VSBis
greater than 0.1V typical. V

SB

rising from below 0.25V

or falling from above 2.25V (V

MCV

) resets the device. Re

­set can also be accomplished with a command over the
serial port as described in the Reset Register section.

Temperature

The bq2014 internally determines the temperature in
10°C steps centered from -35°C to +85°C. The tempera

­ture steps are used to adapt charge and discharge rate

compensations, self-discharge counting, and available
charge display translation. The temperature range is
available over the serial port in 10°C increments as
shown below:

Layout Considerations

The bq2014 measures the voltage differential between
the SR and V

SS

pins. VOS(the offset voltage at the SR
pin) is greatly affected by PC board layout. For optimal
results, the PC board layout should follow the strict rule
of a single-point ground return. Sharing high-current
ground with small signal ground causes undesirable
noise on the small signal nodes. Additionally:

n

The capacitors (C2 and C3) should be placed as close as
possible to the SB and V

CC

pins, respectively, and their

paths to V

SS

should be as short as possible. A
high-quality ceramic capacitor of 0.1µf is recommended
for V

CC

.

n

The sense resistor (R1, C1) should be placed as close
as possible to the SR pin.

n

The sense resistor (R16) should be as close as
possible to the bq2014.

4

bq2014

TMPGG (hex) Temperature Range

0x < -30°C

1x -30°C to -20°C

2x -20°C to -10°C

3x -10°C to 0°C

4x 0°C to 10°C

5x 10°C to 20°C

6x 20°C to 30°C

7x 30°C to 40°C

8x 40°C to 50°C

9x 50°C to 60°C

Ax 60°C to 70°C

Bx 70°C to 80°C

Cx > 80°C

Gas Gauge Operation

The operational overview diagram in Figure 2 illustrates
the operation of the bq2014. The bq2014 accumulates a
measure of charge and discharge currents, as well as an
estimation of self-discharge. Charge and discharge cur

­rents are temperature and rate compensated, whereas
self-discharge is only temperature compensated.

The main counter, Nominal Available Charge (NAC),
represents the available battery capacity at any given
time. Battery charging increments the NAC register,
while battery discharging and self-discharge decrement
the NAC register and increment the DCR (Discharge
Count Register).

The Discharge Count Register (DCR) is used to update
the Last Measured Discharge (LMD) register only if a
complete battery discharge from full to empty occurs
without any partial battery charges. Therefore, the
bq2014 adapts its capacity determination based on the
actual conditions of discharge.

The battery's initial capacity is equal to the Pro

­grammed Full Count (PFC) shown in Table 2. Until
LMD is updated, NAC counts up to but not beyond this
threshold during subsequent charges. This approach al­lows the gas gauge to be charger-independent and com­patible with any type of charge regime.

Many actions in the bq2014 are triggered by detection of
a “valid charge.” NAC is stored in an asynchronous, 2­byte counter; the lower byte is NACL and the upper byte
is NACH. A valid charge has occurred anytime the

charge lasts long enough to cause an increment in
NACH. Small increments of charging are not consid

­ered “valid” if they result in counts in NACL but do not
generate a roll-over (carry) that increments NACH.
NACL is reset anytime the counter direction changes
from down to up, so the number of counts required to
cause a roll-over and a valid charge is always 256. The
counter may be incrementing by 2, 4, 8, or more counts
per increment, however, depending on the scaling fac

­tors selected. Therefore, a valid charge may be consti

­tuted by a smaller number of counter increments.

1. Last Measured Discharge (LMD) or

learned battery capacity:

LMD is the last measured discharge capacity of the
battery. On initialization (application of V

CC

or bat

-

tery replacement), LMD = PFC. During subsequent
discharges, the LMD is updated with the latest
measured capacity in the Discharge Count Register
(DCR) representing a discharge from full to below
EDV1. A qualified discharge is necessary for a ca

-

pacity transfer from the DCR to the LMD register.
The LMD also serves as the 100% reference thresh

-

old used by the relative display mode.

2. Programmed Full Count (PFC) or initial

battery capacity:

The initial LMD and gas gauge rate values are pro­grammed by using PROG

1

—PROG4. The bq2014 is
configured for a given application by selecting a
PFC value from Table 2. The correct PFC may be

5

bq2014

FG201002.eps

Rate and

Temperature

Compensation

Temperature

Compensation

Charge
Current

Discharge

Current

Self-Discharge

Timer

Temperature

Translation

Nominal

Available

Charge

(NAC)

Last

Measured

Discharged

(LMD)

Discharge

Count

Register

(DCR)

<

Qualified
Transfer

+

Rate and

Temperature

Compensation

Rate and

Temperature

Compensation

Temperature Step,
Other Data

+

--

+

Inputs

Main Counters

and Capacity

Reference (LMD)

Outputs

Serial

Port

Chip-Controlled

Available Charge

LED Display

Figure 2. Operational Overview

determined by multiplying the rated battery capac

-

ity in mAh by the sense resistor value:

Battery capacity (mAh)*sense resistor (Ω) =

PFC (mVh)

Selecting a PFC slightly less than the rated capac

­ity for absolute mode provides capacity above the
full reference for much of the battery's life.

Example: Selecting a PFC Value

Given:

Sense resistor = 0.1Ω
Number of cells = 6
Capacity = 2200mAh, NiCd battery
Current range = 50mA to 2A

Relative display mode
Serial port only
Self-discharge =

C

64

Voltage drop over sense resistor = 5mV to 400mV

Therefore:

2200mAh ∗ 0.1Ω= 220mVh

Select:

PFC = 33792 counts or 211mVh
PROG

1

= float

PROG

2

= float

PROG

3

= float

PROG

4

= low

PROG

5

= float

DONE = low

6

bq2014

PROG

x

Programmed

Full

Count

(PFC)

PROG

4

= L PROG4= Z

Units

1 2 PROG3 = H PROG3 = Z PROG3 = L PROG3 = H PROG3 = Z PROG3 = L

-- -

Scale =

1/80

Scale =

1/160

Scale =

1/320

Scale =

1/640

Scale =

1/1280

Scale =

1/2560

mVh/
count

H H 49152 614 307 154 76.8 38.4 19.2 mVh

H Z 45056 563 282 141 70.4 35.2 17.6 mVh

H L 40960 512 256 128 64.0 32.0 16.0 mVh

Z H 36864 461 230 115 57.6 28.8 14.4 mVh

Z Z 33792 422 211 106 53.0 26.4 13.2 mVh

Z L 30720 384 192 96.0 48.0 24.0 12.0 mVh

L H 27648 346 173 86.4 43.2 21.6 10.8 mVh

L Z 25600 320 160 80.0 40.0 20.0 10.0 mVh

L L 22528 282 141 70.4 35.2 17.6 8.8 mVh

VSR equivalent to 2

counts/s (nom.)

90 45 22.5 11.25 5.6 2.8 mV

Table 2. bq2014 Programmed Full Count mVh Selections

Pin Connection PROG5Self-Discharge Rate DISP Display State

H Disabled LED disabled

Z

NAC

64

LED enabled on discharge when

V

SRO

< -4mV or during a valid charge

L

NAC

47

LED on

Table 1. bq2014 Programming

The initial full battery capacity is 211mVh
(2110mAh) until the bq2014 “learns” a new capacity
with a qualified discharge from full to EDV1.

3. Nominal Available Charge (NAC):

NAC counts up during charge to a maximum value
of LMD and down during discharge and self­discharge to 0. NAC is reset to 0 on initialization
and on the first valid charge after EDV = 1. To pre

­vent overstatement of charge during periods of over

­charge, NAC stops incrementing when NAC = LMD.

4. Discharge Count Register (DCR):

The DCR counts up during discharge independent
of NAC and could continue increasing after NAC
has decremented to 0 until V

SB

< EDV1. Prior to
NAC = 0 (empty battery), both discharge and self­discharge increment the DCR. After NAC = 0, only
discharge increments the DCR. The DCR resets to
0 when NAC = LMD. The DCR does not roll over
but stops counting when it reaches FFFFh.

The DCR value becomes the new LMD value on the
first charge after a valid discharge to V

EDV1

if:

n

No valid charges have occurred during the peri­od between NAC = LMD and EDV1 detected.

n The self-discharge count is not more than 4096

counts (8% to 18% of PFC, specific percentage
threshold determined by PFC).

n

The temperature is ≥ 0°C when the EDV1 level
is reached during discharge.

The valid discharge flag (VDQ) indicates whether
the present discharge is valid for LMD update.

Charge Counting

Charge activity is detected based on a positive voltage
on the V

SR

input. The bq2014 determines charge activ

-

ity sustained at a continuous rate equivalent to V

SRO

(VSR+VOS)>V

SRQ

. Once a valid charge is detected,

charge counting continues until V

SRO

falls below V

SRQ

.

V

SRQ

is a programmable threshold (as described in the
Digital Magnitude Filter section) and has a default
value of 375µV. If charge activity is detected, the bq2014
increments the NAC at a rate proportional to V

SRO

.If
enabled, the bq2014 then activates an LED display.
Charge actions increment the NAC after compensation
for charge rate and temperature.

Charge Control

Charge control is provided by the CHG output. This out

­put is asserted continuously when NAC > 0.94 ∗ LMD.
CHG is also asserted when a valid charge is detected
(CHGS in the FLGS1 register is also set). CHG is low
when NAC < 0.94 ∗ LMD and there is no valid charge ac

­tivity.

DONE Input

When the bq2014 detects a valid charge complete with
an active-high signal on the DONE input, NAC is set to
LMD for

NAC

64

(NiCd) self-discharge setting. NAC is set

to 94% of LMD (if NAC is below 94%) for

NAC

47

(NiMH)

self-discharge setting. VDQ is set along with DONE.

Discharge Counting

All discharge counts where V

SRO<VSRD

cause the NAC
register to decrement and the DCR to increment if
EDV1 = 0. Exceeding the fast discharge threshold
(FDQ) if the rate is equivalent to V

SRO

< -4mV activates
the display, if enabled. The display becomes inactive af­ter V

SRO

rises above -4mV. V

SRD

is a programmable
threshold as described in the Digital Magnitude Fil­ter section. The default value for V

SRD

is -300µV.

Self-Discharge Estimation

The bq2014 continuously decrements NAC and incre­ments DCR for self-discharge based on time and tempera­ture. The self-discharge count rate is programmed to be a
nominal

1

64

*

NAC or

1

47

∗

NAC per day or disabled as se-

lected by PROG

5

. This is the rate for a battery whose
temperature is between 20°C–30°C. The NAC register
cannot be decremented below 0.

Count Compensations

The bq2014 determines fast charge when the NAC up

­dates at a rate of ≥ 2 counts/sec. Charge and discharge
activity is compensated for temperature and charge/dis

­charge rate before updating the NAC and/or DCR. Self­discharge estimation is compensated for temperature
before updating the NAC or DCR.

Charge Compensation

Two charge efficiency compensation factors are used for
trickle charge and fast charge. Fast charge is defined as
a rate of charge resulting in ≥ 2 NAC counts/sec (≥ 0.15C
to 0.32C depending on PFC selections; see Table 2). The
compensation defaults to the fast charge factor until the
actual charge rate is determined.

7

bq2014

Temperature adapts the charge rate compensation fac

­tors over three ranges between nominal, warm, and hot
temperatures. The compensation factors are shown below.

Discharge Compensation

Corrections for the rate of discharge are made by adjust

­ing an internal discharge compensation factor. The dis

­charge factor is based on the dynamically measured V

SR

.

The compensation factors during discharge are:

Temperature compensation during discharge also takes place.
At lower temperatures, the compensation factor increases by

0.05 for each 10°C temperature range below 10°C.

Comp. factor = 1.00 + (0.05*N)

Where N = number of 10°C steps below 10°C and

-150mV < V

SR

<0.

For example:

T > 10°C: Nominal compensation, N = 0

0°C<T<10°C: N = 1 (i.e.,1.00 becomes 1.05)

-10°C<T<0°C: N = 2 (i.e., 1.00 becomes 1.10)

-20°C<T<-10°C: N = 3 (i.e., 1.00 becomes 1.15)

-20°C<T<-30°C: N = 4 (i.e., 1.00 becomes 1.20)

Self-Discharge Compensation

The self-discharge compensation is programmed for a
nominal rate of

1

64

*

NAC per day,

1

47

∗ NAC per day, or

disabled. This is the rate for a battery within the
20°C–30°C temperature range (TMPGG = 6x). This rate
varies across 8 ranges from <10°C to >70°C, doubling
with each higher temperature step (10°C). See Table 3

Digital Magnitude Filter

The bq2014 has a programmable digital filter to elimi

-

nate charge and discharge counting below a set thresh

-

old. The default setting is -0.30mV for V

SRD

and

+0.38mV for V

SRQ

. The proper digital filter setting can
be calculated using the following equation. Table 4
shows typical digital filter settings.

V

SRD

(mV) =

−45

DMF

V

SRQ

(MV) = -125 ∗ V

SRD

Error Summary

Capacity Inaccurate

The LMD is susceptible to error on initialization or if no up

­dates occur. On initialization, the LMD value includes the
error between the programmed full capacity and the actual
capacity. This error is present until a valid discharge oc

­curs and LMD is updated (see the DCR description on page

7). The other cause of LMD error is battery wear-out. As
the battery ages, the measured capacity must be adjusted
to account for changes in actual battery capacity.

A Capacity Inaccurate counter (CPI) is maintained and
incremented each time a valid charge occurs (qualified
by NAC; see the CPI register description) and is reset

8

bq2014

Approximate

V

SR

Threshold

Discharge

Compensa

-

tion Factor Efficiency

V

SR

> -150 mV 1.00 100%

V

SR

< -150 mV 1.05 95%

Charge

Temperature

Trickle Charge
Compensation

Fast Charge

Compensation

< 40°C 0.80 0.95

> 40°C 0.75 0.90

Temperature

Step

Typical Rate

PROG

5

= Z PROG5= L

< 10°C

NAC

256

NAC

188

10–20°C

NAC

128

NAC

94

20–30°C

NAC

64

NAC

47

30–40°C

NAC

32

NAC

23 5.

40–50°C

NAC

16

NAC

11 8.

50–60°C

NAC

8

NAC

588.

60–70°C

NAC

4

NAC

294.

> 70°C

NAC

2

NAC

147.

Table 3. Self-Discharge Compensation

DMF

DMF
Hex.

V

SRD

(mV)

V

SRQ

(mV)

75 4B -0.60 0.75

100 64 -0.45 0.56

150 (default) 96 -0.30 0.38

175 AF -0.26 0.32
200 C8 -0.23 0.28

Table 4. Typical Digital Filter Settings

whenever LMD is updated from the DCR. The counter
does not wrap around but stops counting at 255. The ca

-

pacity inaccurate flag (CI) is set if LMD has not been up

-

dated following 64 valid charges.

Current-Sensing Error

Table 5 illustrates the current-sensing error as a func

-

tion of V

SR

. A digital filter eliminates charge and

discharge counts to the NAC register when V

SRO(VSR

+

V

OS

) is between V

SRQ

and V

SRD

.

Communicating With the bq2014

The bq2014 includes a simple single-pin (DQ plus re­turn) serial data interface. A host processor uses the in­terface to access various bq2014 registers. Battery char­acteristics may be easily monitored by adding a single
contact to the battery pack. The open-drain DQ pin on
the bq2014 should be pulled up by the host system, or may
be left floating if the serial interface is not used.

The interface uses a command-based protocol, where the
host processor sends a command byte to the bq2014.
The command directs the bq2014 to either store the next
eight bits of data received to a register specified by the
command byte or output the eight bits of data specified
by the command byte.

The communication protocol is asynchronous return-to­one. Command and data bytes consist of a stream of eight
bits that have a maximum transmission rate of 333
bits/sec. The least-significant bit of a command or data
byte is transmitted first. The protocol is simple enough
that it can be implemented by most host processors using

either polled or interrupt processing. Data input from the
bq2014 may be sampled using the pulse-width capture
timers available on some microcontrollers.

Communication is normally initiated by the host proces

­sor sending a BREAK command to the bq2014. A
BREAK is detected when the DQ pin is driven to a
logic-low state for a time, t

B

or greater. The DQ pin
should then be returned to its normal ready-high logic
state for a time, t

BR

. The bq2014 is now ready to receive

a command from the host processor.

The return-to-one data bit frame consists of three distinct
sections. The first section is used to start the transmission
by either the host or the bq2014 taking the DQ pin to a
logic-low state for a period, t

STRH,B

. The next section is the
actual data transmission, where the data should be valid by
a period, t

DSU

, after the negative edge used to start commu-

nication. The data should be held for a period, t

DV

, to allow

the host or bq2014 to sample the data bit.

The final section is used to stop the transmission by return­ing the DQ pin to a logic-high state by at least a period,
t

SSU

, after the negative edge used to start communication.

The final logic-high state should be held until a period, t

SV

,
to allow time to ensure that the bit transmission was
stopped properly. The timings for data and break commu

­nication are given in the serial communication timing
specification and illustration sections.

Communication with the bq2014 is always performed
with the least-significant bit being transmitted first.
Figure 3 shows an example of a communication se

­quence to read the bq2014 NAC register.

9

bq2014

TD201401.eps

DQ

Break 0 0 0 0 0 0 1 0 1 0 0 1

Written by Host to bq2014

CMDR = 03h

Received by Host to bq2014

NAC = 65h

LSB MSB LSB MSB

1110

Figure 3. Typical Communication With the bq2014

Symbol Parameter Typical Maximum Units Notes

INL

Integrated non-linearity
error

±

2

±

4

%

Add 0.1% per °C above or below 25°C
and 1% per volt above or below 4.25V.

INR

Integrated non­repeatability error

±

1

±

2

%

Measurement repeatability given
similar operating conditions.

Table 5. Current-Sensing Error as a Function of V

SR

bq2014 Registers

The bq2014 command and status registers are listed in
Table 6 and described below.

Command Register (CMDR)

The write-only CMDR register is accessed when eight
valid command bits have been received by the bq2014.
The CMDR register contains two fields:

n

W/R bit

n

Command address

The W/R

bit of the command register is used to select
whether the received command is for a read or a write
function.

The W/R

values are:

Where W/R

is:

0 The bq2014 outputs the requested register

contents specified by the address portion of
CMDR.

1 The following eight bits should be written

to the register specified by the address por­tion of CMDR.

The lower seven-bit field of CMDR contains the address
portion of the register to be accessed. Attempts to write
to invalid addresses are ignored.

Primary Status Flags Register (FLGS1)

The read-only FLGS1 register (address=01h) contains
the primary bq2014 flags.

The charge status flag (CHGS) is asserted when a
valid charge rate is detected. Charge rate is deemed
valid when V

SRO>VSRQ

.AV

SRO

of less than V

SRQ

or

discharge activity clears CHGS.

The CHGS values are:

Where CHGS is:

0 Either discharge activity detected or V

SRO

<

V

SRQ

1V

SRO

> V

SRQ

The battery replaced flag (BRP) is asserted whenever
the potential on the SB pin (relative to V

SS

), VSB, falls
from above the maximum cell voltage, MCV (2.25V), or
rises above 0.1V. The BRP flag is also set when the
bq2014 is reset (see the RST register description). BRP
is reset when either a valid charge action increments
NAC to be equal to LMD, or a valid charge action is de

­tected after the EDV1 flag is asserted. BRP = 1 signifies
that the device has been reset.

The BRP values are:

Where BRP is:

0 Battery is charged until NAC = LMD or dis-

charged until the EDV1 flag is asserted

1V

SB

dropping from above MCV, VSBrising
from below 0.1V, or a serial port initiated
reset has occurred

The battery removed flag (BRM) is asserted whenever
the potential on the SB pin (relative to V

SS

) rises above
MCV or falls below 0.1V. The BRM flag is asserted until
the condition causing BRM is removed. Because of sig

­nal filtering, 30 seconds may have to transpire for BRM
to react to battery insertion or removal.

The BRM values are:

Where BRM is:

0 0.1V < V

SB

< 2.25V

1 0.1V > V

SB

or VSB> 2.25V

The capacity inaccurate flag (CI) is used to warn the
user that the battery has been charged a substantial
number of times since LMD has been updated. The CI
flag is asserted on the 64th charge after the last LMD
update or when the bq2014 is reset. The flag is cleared
after an LMD update.

10

bq2014

FLGS1 Bits

7654 3 2 1 0

CHGS - -- - - - -

FLGS1 Bits

7654 3 2 1 0

- BRP - - - - - -

CMDR Bits

765 4 3 2 1 0

- AD6 AD5 AD4 AD3 AD2 AD1

AD0

(LSB)

CMDR Bits

7654 3 2 1 0

W/R

- -- - - - -

FLGS1 Bits

7654 3 2 1 0

- - BRM - - - - -

11

bq2014

Symbol

Register

Name

Loc.

(hex)

Read/

Write

Control Field

7(MSB) 6543210(LSB)

CMDR

Command
register

00h Write W/R

AD6 AD5 AD4 AD3 AD2 AD1 AD0

FLGS1

Primary
status flags
register

01h Read CHGS BRP BRM CI VDQ n/u EDV1 EDVF

TMPGG

Temperature
and gas gauge
register

02h Read TMP3 TMP2 TMP1 TMP0 GG3 GG2 GG1 GG0

NACH

Nominal
available
charge high
byte register

03h R/W NACH7 NACH6 NACH5 NACH4 NACH3 NACH2 NACH1 NACH0

NACL

Nominal
available
charge low
byte register

17h Read NACL7 NACL6 NACL5 NACL4 NACL3 NACL2 NACL1 NACL0

BATID

Battery
identification
register

04h R/W BATID7 BATID6 BATID5 BATID4 BATID3 BATID2 BATID1 BATID0

LMD

Last meas­ured dis­charge regis­ter

05h R/W LMD7 LMD6 LMD5 LMD4 LMD3 LMD2 LMD1 LMD0

FLGS2

Secondary
status flags
register

06h Read CR DR2 DR1 DR0 n/u n/u n/u OVLD

PPD

Program pin
pull-down
register

07h Read n/u n/u PPD6 PPD5 PPD4 PPD3 PPD2 PPD1

PPU

Program pin
pull-up regis

-

ter

08h Read n/u n/u PPU6 PPU5 PPU4 PPU3 PPU2 PPU1

CPI

Capacity
inaccurate
count register

09h Read CPI7 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 CPI0

DMF

Digital mag

­nitude filter
register

0Ah R/W DMF7 DMF6 DMF5 DMF4 DMF3 DMF2 DMF1 DMF0

VSB

Battery
voltage

0Bh Read VSB7 VSB6 VSB5 VSB4 VSB3 VSB2 VSB1 VSB0

VTS

End-of­discharge
threshold se

-

lect

0Ch R/W VTS7 VTS6 VTS5 VTS4 VTS3 VTS2 VTS1 VTS0

RST Reset register 39h Write RST 0000000

Note: n/u = not used

Table 6. bq2014 Command and Status Registers

The CI values are:

Where CI is:

0 When LMD is updated with a valid full dis

-

charge

1 After the 64th valid charge action with no

LMD updates or when the device is reset

The valid discharge flag (VDQ) is asserted when the
bq2014 is discharged from NAC = LMD or DONE is
valid. The flag remains set until either LMD is updated
or one of three actions that can clear VDQ occurs:

n

The self-discharge count register (SDCR) has
exceeded the maximum acceptable value (4096
counts) for an LMD update.

n

A valid charge action sustained at V

SRO

> V

SRQ

for at

least 256 NAC counts.

n

The EDV flag was set at a temperature below 0°C

The VDQ values are:

Where VDQ is:

0 SDCR≥4096, subsequent valid charge ac

­tion detected, or EDV1 is asserted with the
temperature less than 0°C

1 On first discharge after NAC = LMD or

DONE is valid

The first end-of-discharge warning flag (EDV1)
warns the user that the battery is almost empty. The
first segment pin, SEG

1

, is modulated at a 4Hz rate if
the display is enabled once EDV1 is asserted, which
should warn the user that loss of battery power is immi

­nent. The EDV1 flag is latched until a valid charge has
been detected. The EDV1 threshold is externally con

­trolled via the VTS register (see Voltage Threshold Reg

­ister on this page).

The EDV1 values are:

Where EDV1 is:

0 Valid charge action detected,V

SB

≥ V

TS

1VSB< VTSproviding that OVLD=0 (see

FLGS2 register description)

The final end-of-discharge warning flag (EDVF) flag
is used to warn that battery power is at a failure condi

­tion. All segment drivers are turned off. The EDVF flag
is latched until a valid charge has been detected. The
EMPTY pin is also forced to a high-impedance state on
assertion of EDVF. The host system may pull EMPTY
high, which may be used to disable circuitry to prevent
deep-discharge of the battery. The EDVF threshold is
set 100mV below the EDV1 threshold.

The EDVF values are:

Where EDVF is:

0 Valid charge action detected,

V

SB

≥ VTS- 100mV

1V

SB<VTS

- 100mV providing that OVLD=0

(see FLGS2 register description)

Voltage Threshold Register (VTS)

The end-of-discharge threshold voltages (EDV1 and
EDVF) can be set using the VTS register (address=0ch).
The read/write VTS register sets the EDV1 trip point.
EDVF is set 100mV below EDV1. The default value in
the VTS register is 70h, representing EDV1 = 1.05V and
EDVF = 0.95V. EDV1 = 2.4V ∗ (VTS/256).

Battery Voltage Register (VSB)

The read-only battery voltage register is used to read
the single-cell battery voltage on the SB pin. The VSB
register is updated approximately once per second with
the present value of the battery voltage.
V

SB

= 2.4V ∗ (VSB/256)

12

bq2014

VSB Register Bits

76543210

VSB7 VSB6 VSB5 VSB4 VSB3 VSB2 VSB1 VSB0

FLGS1 Bits

7654 3 2 1 0

- - - - VDQ - - -

FLGS1 Bits

765 4 3 2 1 0

- - - - - - EDV1 -

FLGS1 Bits

7654 3 2 1 0

---CI- - - -

FLGS1 Bits

765 4 3 2 1 0

--- - - - -EDVF

VTS Register Bits

76543210

VTS7 VTS6 VTS5 VTS4 VTS3 VTS2 VTS1 VTS0

Temperature and Gas Gauge Register
(TMPGG)

The read-only TMPGG register (address=02h) contains
two data fields. The first field contains the battery tem

­perature. The second field contains the available charge
from the battery.

The bq2014 contains an internal temperature sensor.
The temperature is used to set charge and discharge ef

­ficiency factors as well as to adjust the self-discharge co

­efficient. The temperature register contents may be
translated as shown in Table 7.

The bq2014 calculates the available charge as a function
of NAC, temperature, and LMD. The results of the cal

­culation are available via the display port or the gas
gauge field of the TMPGG register. The register is used
to give available capacity in

1

16

increments from 0 to

15

16

.

The gas gauge display and the gas gauge portion of the
TMPGG register are adjusted for cold temperature de­pendencies. A piece-wise correction is performed as fol

­lows:

The adjustment between > 0°C and -20°C < T < 0°C has a
10°C hysteresis.

Nominal Available Charge Register
(NACH/NACL)

The read/write NACH register (address=03h) and the
read-only NACL low-byte register (address=17h) are the
main gas gauging registers for the bq2014. The NAC
registers are incremented during charge actions and
decremented during discharge and self-discharge ac

­tions. The correction factors for charge/discharge effi

­ciency are applied automatically to NAC.

On reset, NACH and NACL are cleared to 0. When the
bq2014 detects a charge, NACL resets to 0. NACH and
NACL are reset to 0 on the first valid charge after V

SB

=

EDV1. Writing to the NAC registers affects the available

charge counts and, therefore, affects the bq2014 gas
gauge operation. Do not write the NAC registers to a
value greater than LMD.

Battery Identification Register (BATID)

The read/write BATID register (address=04h) is avail­able for use by the system to determine the type of bat

­tery pack. The BATID contents are retained as long as
V

CC

is greater than 2V. The contents of BATID have no

effect on the operation of the bq2014. There is no de

­fault setting for this register.

Last Measured Discharge Register (LMD)

LMD is a read/write register (address=05h) that the
bq2014 uses as a measured full reference. The bq2014
adjusts LMD based on the measured discharge capacity
of the battery from full to empty. In this way the bq2014
updates the capacity of the battery. LMD is set to PFC
during a bq2014 reset.

Secondary Status Flags Register (FLGS2)

The read-only FLGS2 register (address=06h) contains
the secondary bq2014 flags.

The charge rate flag (CR) is used to denote the fast
charge regime. Fast charge is assumed whenever a
charge action is initiated. The CR flag remains asserted
if the charge rate does not fall below 2 counts/sec.

13

Temperature Available Capacity Calculation

> 0°C NAC / “Full Reference”

-20°C < T < 0°C 0.75*NAC / “Full Reference”

< -20°C 0.5*NAC / “Full Reference”

TMP3 TMP2 TMP1 TMP0 Temperature

0000 T < -30°C

0001-30°C < T < -20°C

0010-20°C < T < -10°C

0011-10°C < T < 0°C

01000°C < T < 10°C

010110°C < T < 20°C

011020°C < T < 30°C

011130°C < T < 40°C

100040°C < T < 50°C

100150°C < T < 60°C

101060°C < T < 70°C

101170°C < T < 80°C

1100 T > 80°C

Table 7. Temperature Register Translation

TMPGG Gas Gauge Bits

765 4 3 2 1 0

- - - - GG3 GG2 GG1 GG0

TMPGG Temperature Bits

7 6 5 4 3210

TMP3 TMP2 TMP1 TMP0 - - -

bq2014

The CR values are:

Where CR is:

0 When charge rate falls below 2 counts/sec

1 When charge rate is above 2 counts/sec

The fast charge regime efficiency factors are used when
CR = 1. When CR = 0, the trickle charge efficiency fac

­tors are used. The time to change CR varies due to the
user-selectable count rates.

The discharge rate flags, DR2–0, are bits 6–4.

They are used to determine the current discharge re­gime as follows:

The overload flag (OVLD) is asserted when a discharge
overload is detected, V

SR

< -250mV. OVLD remains as-

serted as long as the condition persists and is cleared af

­ter V

SR

> -150mV. The overload condition is used to stop
sampling of the battery terminal characteristics for
end-of-discharge determination when excessive dis

-

charges occur.

DR2–0 and OVLD are set based on the measurement of the
voltage at the SR pin relative to V

SS

. The rate at which

this measurement is made varies with device activity.

Program Pin Pull-Down Register (PPD)

The read-only PPD register (address=07h) contains some
of the programming pin information for the bq2014. The
segment drivers, SEG

1–5

and DONE, have corresponding

PPD register locations, PPD

1–6

. A given location is set if a
pull-down resistor has been detected on its corresponding
segment driver. For example, if SEG

1

and SEG4have

pull-down resistors, the contents of PPD are xx101001.
(Note: DONE must be pulled down for proper operation.)

Program Pin Pull-Up Register (PPU)

The read-only PPU register (address=08h) contains the
rest of the programming pin information for the bq2014.
The segment drivers, SEG

1–5

and DONE, have corre

-

sponding PPU register locations, PPU

1–6

. A given loca

­tion is set if a pull-up resistor has been detected on its
corresponding segment driver. For example, if SEG

3

and
DONE have pull-up resistors, the contents of PPU are
xx100100.

Capacity Inaccurate Count Register (CPI)

The read-only CPI register (address=09h) is used to in­dicate the number of times a battery has been charged
without an LMD update. Because the capacity of a re­chargeable battery varies with age and operating condi­tions, the bq2014 adapts to the changing capacity over
time. A complete discharge from full (NAC=LMD) to
empty (EDV1=1) is required to perform an LMD update
assuming there have been no intervening valid charges,
the temperature is greater than or equal to 0°C, and the
self-discharge counter is less than 4096 counts.

The CPI register is incremented every time a valid
charge is detected. When NAC > 0.94 ∗ LMD, however,
the CPI register increments on the first valid charge;
CPI does not increment again for a valid charge until
NAC < 0.94 ∗ LMD. This prevents continuous trickle
charging from incrementing CPI if self-discharge decre

-

ments NAC. The CPI register increments to 255 with

-

out rolling over. When the contents of CPI are incre

-

mented to 64, the capacity inaccurate flag, CI, is as

­serted in the FLGS1 register. The CPI register is reset
whenever an update of the LMD register is performed,
and the CI flag is also cleared.

Digital Magnitude Filter (DMF)

The read-write DMF register (address=0Ah) provides
the system with a means to change the default settings
of the digital magnitude filter. By writing different val

­ues into this register, the limits of V

SRD

and V

SRQ

can be

adjusted.

Note: Care should be taken when writing to this regis

­ter. A V

SRD

and V

SRQ

below the specified VOSmay ad

­versely affect the accuracy of the bq2014. Refer to Table
4 for recommended settings for the DMF register.

14

bq2014

FLGS2 Bits

76543 2 1 0

- - - - - - - OVLD

PPD/PPU Bits

87654321

- - PPU

6

PPU5PPU4PPU3PPU2PPU

1

- - PPD6PPD5PPD4PPD3PPD2PPD

1

FLGS2 Bits

7 6 5 4 3210

- DR2 DR1 DR0 - - -

DR2 DR1 DR0 VSR(V)

000 V

SR

> -150mV

001 V

SR

< -150mV

FLGS2 Bits

76543 2 1 0

CR - - - - - - -

Reset Register (RST)

The reset register (address=39h) provides the means to
perform a software-controlled reset of the device. By
writing the RST register contents from 00h to 80h, a
bq2014 reset is performed. Setting any bit other than

the most-significant bit of the RST register is not al

-

lowed, and results in improper operation of the bq2014.

Resetting the bq2014 sets the following:

n

LMD = PFC

n

CPI, VDQ, NAC, and NACL = 0

n

CI and BRP = 1

Note: Self-discharge is disabled when PROG

5

=H.

Display

The bq2014 can directly display capacity information us

­ing low-power LEDs. If LEDs are used, the program
pins should be resistively tied to V

CC

or VSSfor a pro

­gram high or program low, respectively..

The bq2014 displays the battery charge state in relative
mode. In relative mode, the battery charge is repre­sented as a percentage of the LMD. Each LED segment
represents 20% of the LMD.

The capacity display is also adjusted for the present bat­tery temperature. The temperature adjustment reflects
the available capacity at a given temperature but does
not affect the NAC register. The temperature adjust­ments are detailed in the TMPGG register description.

When DISP

is tied to VCC, the SEG

1–5

outputs are inac

-

tive. Note: DISP

must be tied to VCCif the LEDs

are not used. When DISP

is left floating, the display

becomes active whenever the NAC registers are count

-

ing at a rate equivalent to V

SRO

< -4mV or charge cur

-

rent is detected, V

SRO>VSRQ

. When pulled low, the seg

­ment outputs become active immediately. A capacitor
tied to DISP

allows the display to remain active for a
short period of time after activation by a push-button
switch.

The segment outputs are modulated as two banks of
three, with segments 1, 3, and 5 alternating with seg

­ments 2 and 4. The segment outputs are modulated at
approximately 100Hz, with each segment bank active
for 30% of the period.

SEG

1

blinks at a 4Hz rate whenever VSBhas been de

­tected to be below V

EDV1

(EDV1 = 1), indicating a low-

battery condition. V

SB

below V

EDVF

(EDVF = 1) disables

the display output.

Microregulator

The bq2014 can operate directly from 3 or 4 cells. To facili­tate the power supply requirements of the bq2014, an REF
output is provided to regulate an external low-threshold n­FET. A micropower source for the bq2014 can be inexpen­sively built using the FET and an external resistor; see
Figure 1.

15

bq2014

16

bq2014

Absolute Maximum Ratings

Symbol Parameter Minimum Maximum Unit Notes

V

CC

Relative to V

SS

-0.3 7.0 V

All other pins Relative to V

SS

-0.3 7.0 V

REF Relative to V

SS

-0.3 8.5 V Current limited by R1 (see Figure 1)

V

SR

Relative to V

SS

-0.3 7.0 V

Minimum 100Ωseries resistor should
be used to protect SR in case of a
shorted battery (see the bq2014 appli

-

cation note for details).

T

OPR

Operating tempera

-

ture

0 70 °C Commercial

-40 85 °C Industrial

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional opera

-

tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Expo

-

sure to conditions beyond the operational limits for extended periods of time may affect device reliability.

DC Voltage Thresholds (T

A

= T

OPR

; V = 3.0 to 6.5V)

Symbol Parameter Minimum Typical Maximum Unit Notes

V

EDVF

Final empty warning, default 0.92 0.95 0.98 V SB

V

EDV1

First empty warning, default 1.02 1.05 1.08 V SB

V

SR1

Discharge compensation threshold -120 -150 -180 mV SR

V

SRO

SR sense range -300 - 2000 mV SR

V

OVLD

Overload threshold -220 -250 -280 mV SR

V

SRQ

Valid charge 375 - -

µ

VVSR+ VOS(see note 1)

V

SRD

Valid discharge - - -300

µ

VVSR+ VOS(see note 1)

V

MCV

Maximum single-cell voltage 2.20 2.25 2.30 V SB

V

BR

Battery removed/replaced

- 0.1 0.25 V SB pulled low

2.20 2.25 2.30 V SB pulled high

Notes: 1. Default value; value set in DMF register. VOSis affected by PC board layout. Proper layout guide

lines should be followed for optimal performance.

2. To ensure correct threshold determination and proper operation, V

CC

> VSB+ 1.5V

17

bq2014

DC Electrical Characteristics (T

A

= T

OPR

)

Symbol Parameter Minimum Typical Maximum Unit Notes

V

CC

Supply voltage 3.0 4.25 6.5 V

V

CC

excursion from < 2.0V to

≥

3.0V initializes the unit.

V

OS

Offset referred to V

SR

-

±50 ±150 µV

DISP

= V

CC

V

REF

Reference at 25°C 5.7 6.0 6.3 V I

REF

= 5µA

Reference at -40°C to +85°C 4.5 - 7.5 V I

REF

= 5µA

R

REF

Reference input impedance 2.0 5.0 - MΩV

REF

= 3V

I

CC

Normal operation

- 90 135

µ

AV

CC

= 3.0V

- 120 180

µ

AV

CC

= 4.25V

- 170 250

µ

AV

CC

= 6.5V

V

SB

Battery input - - 2.4 V

R

SBmax

SB input impedance 10 - - MΩ0 < VSB< V

CC

I

DISP

DISP input leakage - - 5

µ

AV

DISP

= V

SS

I

LCOM

LCOM input leakage -0.2 - 0.2

µ

A DISP = V

CC

R

DQ

Internal pulldown 500 - - K

Ω

V

SR

Sense resistor input -0.3 - 2.0 V

V

SR<VSS

= discharge;

V

SR

> VSS= charge

R

SR

SR input impedance 10 - - MΩ-200mV < VSR< V

CC

V

IH

Logic input high VCC- 0.2 - - V PROG1–PROG

5

V

IL

Logic input low - - VSS+ 0.2 V PROG1–PROG5; note 2

V

IZ

Logic input Z float - float V PROG1–PROG

5

V

OLSL

SEGXoutput low, low V

CC

- 0.1 - V

V

CC

= 3V, I

OLS

≤

1.75mA

SEG

1

–SEG

5

V

OLSH

SEGXoutput low, high V

CC

- 0.4 - V

V

CC

= 6.5V, I

OLS

≤

11.0mA

SEG

1

–SEG

5

V

OHLCL

LCOM output high, low V

CC

VCC- 0.3 - - V VCC= 3V, I

OHLCOM

= -5.25mA

V

OHLCH

LCOM output high, high V

CC

VCC- 0.6 - - V VCC= 6.5V, I

OHLCOM

= -33.0mA

I

IH

PROG

1-5

input high current - 1.2 -

µ

AV

PROG

= VCC/2

I

IL

PROG

1-5

input low current - 1.2 -

µ

AV

PROG

= VCC/2

I

OHLCOM

LCOM source current -33 - - mA At V

OHLCH

= VCC- 0.6V

I

OLS

SEGXsink current - - 11.0 mA At V

OLSH

= 0.4V

I

OL

Open-drain sink current - - 5.0 mA

At V

OL

= VSS+ 0.3V

DQ, EMPTY, CHG

V

OL

Open-drain output low - - 0.5 V I

OL

≤

5mA, DQ, EMPTY

V

IHDQ

DQ input high 2.5 - - V DQ

V

ILDQ

DQ input low - - 0.8 V DQ

R

PROG

Soft pull-up or pull-down resis

-

tor value (for programming)

- - 200

K

Ω

PROG

1

–PROG

5

R

FLOAT

Float state external impedance - 5 - MΩPROG1–PROG

5

Notes: 1. All voltages relative to VSS.

2. DONE must be pulled low for proper operation.

18

bq2014

Serial Communication Timing Specification

Symbol Parameter Minimum Typical Maximum Unit Notes

t

CYCH

Cycle time, host to bq2014 3 - - ms See note

t

CYCB

Cycle time, bq2014 to host 3 - 6 ms

t

STRH

Start hold, host to bq2014 5 - - ns

t

STRB

Start hold, bq2014 to host 500 - -

µ

s

t

DSU

Data setup - - 750

µ

s

t

DH

Data hold 750 - -

µ

s

t

DV

Data valid 1.50 - - ms

t

SSU

Stop setup - - 2.25 ms

t

SH

Stop hold 700 - -

µ

s

t

SV

Stop valid 2.95 - - ms

t

B

Break 3 - - ms

t

BR

Break recovery 1 - - ms

Note: The open-drain DQ pin should be pulled to at least VCCby the host system for proper DQ operation.

DQ may be left floating if the serial interface is not used.

TD201002.eps

DQ

(R/W "1")

t

STRH

t

STRB

t

DSU

t

DH

t

DV

t

SV

t

SSU

t

SH

t

CYCH, tCYCB, tB

t

BR

DQ

(R/W "0")

DQ

(BREAK)

Serial Communication Timing Illustration

19

bq2014

16-Pin SOIC Narrow (SN)

16-Pin SN(SOIC Narrow

)

Dimension Minimum Maximum

A 0.060 0.070

A1 0.004 0.010

B 0.013 0.020
C 0.007 0.010

D 0.385 0.400

E 0.150 0.160
e 0.045 0.055

H 0.225 0.245

L 0.015 0.035

All dimensions are in inches.

A

A1

.004

C

B

e

D

E

H

L

ChangeNo. Page No. Description Nature of Change

1 1, 3, 5, 6, 7, 13, 15 Changed display mode Relative display mode only

1 1, 17 DONE pin Removed PROG

6

1 2, 17 DONE pin Added: DONE pin must be pulled to V

SS

with a 200KΩresistor

1 6 Table 1 Removed PROG

6

1 7 DONE input Was: NAC is set to 90%...

Is: NAC is set to 94%...

1 8, Table 3 PROG

5

= Z Was: PROG5= Z or H

Is: PROG

5

= Z

2 8 Temperature Compen

-

sation table

Replaced

2 6 Table 2 Added V

SR

definition

2 6 Valid charge definition Added definition

2 14 Overload flag Was: 0.5sec. after V

SR

> -250mV

Is: after V

SR

= -150mV

Notes: Change 1 = Dec. 1994 B “Final” changes from Aug. 1994 A “Preliminary.”

Change 2 = Dec. 1995 C from Dec. 1994 B.

Data Sheet Revision History

20

bq2014

Ordering Information

bq2014

Package Option:

SN = 16-pin narrow SOIC

Device:

bq2014 Gas Gauge IC

Temperature Range:

blank = Commercial (0 to +70°C)
N = Industrial (-40 to +85°C)*

* Contact factory for availability.

Copyright © 1995, Unitrode Corporation. All rights reserved. No part of this data sheet may be reproduced in any
form or means, without express permission from Unitrode. Unitrode reserves the right to make changes in its prod

-

ucts without notice.

Unitrode assumes no responsibility for use of any products or circuitry described within. No license for use of intel

-

lectual property (patents, copyrights, or other rights) owned by Unitrode or other parties is granted or implied.

Unitrode does not authorize the use of its components in life-support systems where failure or malfunction may
cause injury to the user. If Unitrode components are used in life-support systems, the user assumes all responsibili

-

ties and indemnifies Unitrode from all liability or damages.

Benchmarq is a registered trademark of Unitrode Corporation Printed in U.S.A.

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Dallas, Texas 75252

Fax: [phone]

Tel: [phone]

www.benchmarq.com or www.unitrode.com

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